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sim: profile: fix bucketing with 64-bit targets
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
68ed2854
MF		 12021-01-11 Mike Frysinger <vapier@gentoo.org>
2
3 * config.in, configure: Regenerate.
4 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
5 and strings.h include.
6
50df264d
MF		 72021-01-09 Mike Frysinger <vapier@gentoo.org>
8
9 * configure: Regenerate.
10
bf470982
MF		 112021-01-09 Mike Frysinger <vapier@gentoo.org>
12
13 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
14 * configure: Regenerate.
15
46f900c0
MF		 162021-01-08 Mike Frysinger <vapier@gentoo.org>
17
18 * configure: Regenerate.
19
dfb856ba
MF		 202021-01-04 Mike Frysinger <vapier@gentoo.org>
21
22 * configure: Regenerate.
23
382bc56b
PK		 242020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
25
26 * sim-main.c: Include <stdlib.h>.
27
ad9675dd
PK		 282020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
29
30 * cp1.c: Include <stdlib.h>.
31
f693213d
SM		 322020-07-29 Simon Marchi <simon.marchi@efficios.com>
33
34 * configure: Re-generate.
35
5c887dd5
JB		 362017-09-06 John Baldwin <jhb@FreeBSD.org>
37
38 * configure: Regenerate.
39
91588b3a
MF		 402016-11-11 Mike Frysinger <vapier@gentoo.org>
41
6cb2202b 42 PR sim/20808
91588b3a
MF		 43 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
44 and SD to sd.
45
e04659e8
MF		 462016-11-11 Mike Frysinger <vapier@gentoo.org>
47
6cb2202b 48 PR sim/20809
e04659e8
MF		 49 * mips.igen (check_u64): Enable for `r3900'.
50
1554f758
MF		 512016-02-05 Mike Frysinger <vapier@gentoo.org>
52
53 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
54 STATE_PROG_BFD (sd).
55 * configure: Regenerate.
56
3d304f48
AB		 572016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
58 Maciej W. Rozycki <macro@imgtec.com>
59
60 PR sim/19441
61 * micromips.igen (delayslot_micromips): Enable for `micromips32',
62 `micromips64' and `micromipsdsp' only.
63 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
64 (do_micromips_jalr, do_micromips_jal): Likewise.
65 (compute_movep_src_reg): Likewise.
66 (compute_andi16_imm): Likewise.
67 (convert_fmt_micromips): Likewise.
68 (convert_fmt_micromips_cvt_d): Likewise.
69 (convert_fmt_micromips_cvt_s): Likewise.
70 (FMT_MICROMIPS): Likewise.
71 (FMT_MICROMIPS_CVT_D): Likewise.
72 (FMT_MICROMIPS_CVT_S): Likewise.
73
b36d953b
MF		 742016-01-12 Mike Frysinger <vapier@gentoo.org>
75
76 * interp.c: Include elf-bfd.h.
77 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
78 ELFCLASS32.
79
ce39bd38
MF		 802016-01-10 Mike Frysinger <vapier@gentoo.org>
81
82 * config.in, configure: Regenerate.
83
99d8e879
MF		 842016-01-10 Mike Frysinger <vapier@gentoo.org>
85
86 * configure: Regenerate.
87
35656e95
MF		 882016-01-10 Mike Frysinger <vapier@gentoo.org>
89
90 * configure: Regenerate.
91
16f7876d
MF		 922016-01-10 Mike Frysinger <vapier@gentoo.org>
93
94 * configure: Regenerate.
95
e19418e0
MF		 962016-01-10 Mike Frysinger <vapier@gentoo.org>
97
98 * configure: Regenerate.
99
6d90347b
MF		 1002016-01-10 Mike Frysinger <vapier@gentoo.org>
101
102 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
103 * configure: Regenerate.
104
347fe5bb
MF		 1052016-01-10 Mike Frysinger <vapier@gentoo.org>
106
107 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
108 * configure: Regenerate.
109
22be3fbe
MF		 1102016-01-10 Mike Frysinger <vapier@gentoo.org>
111
112 * configure: Regenerate.
113
0dc73ef7
MF		 1142016-01-10 Mike Frysinger <vapier@gentoo.org>
115
116 * configure: Regenerate.
117
936df756
MF		 1182016-01-09 Mike Frysinger <vapier@gentoo.org>
119
120 * config.in, configure: Regenerate.
121
2e3d4f4d
MF		 1222016-01-06 Mike Frysinger <vapier@gentoo.org>
123
124 * interp.c (sim_open): Mark argv const.
125 (sim_create_inferior): Mark argv and env const.
126
9bbf6f91
MF		 1272016-01-04 Mike Frysinger <vapier@gentoo.org>
128
129 * configure: Regenerate.
130
77cf2ef5
MF		 1312016-01-03 Mike Frysinger <vapier@gentoo.org>
132
133 * interp.c (sim_open): Update sim_parse_args comment.
134
0cb8d851
MF		 1352016-01-03 Mike Frysinger <vapier@gentoo.org>
136
137 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
138 * configure: Regenerate.
139
1ac72f06
MF		 1402016-01-02 Mike Frysinger <vapier@gentoo.org>
141
142 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
143 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
144 * configure: Regenerate.
145 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
146
d47f5b30
MF		 1472016-01-02 Mike Frysinger <vapier@gentoo.org>
148
149 * dv-tx3904cpu.c (CPU, SD): Delete.
150
e1211e55
MF		 1512015-12-30 Mike Frysinger <vapier@gentoo.org>
152
153 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
154 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
155 (sim_store_register): Rename to ...
156 (mips_reg_store): ... this. Delete local cpu var.
157 Update sim_io_eprintf calls.
158 (sim_fetch_register): Rename to ...
159 (mips_reg_fetch): ... this. Delete local cpu var.
160 Update sim_io_eprintf calls.
161
5e744ef8
MF		 1622015-12-27 Mike Frysinger <vapier@gentoo.org>
163
164 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
165
1b393626
MF		 1662015-12-26 Mike Frysinger <vapier@gentoo.org>
167
168 * config.in, configure: Regenerate.
169
26f8bf63
MF		 1702015-12-26 Mike Frysinger <vapier@gentoo.org>
171
172 * interp.c (sim_write, sim_read): Delete.
173 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
174 (load_word): Likewise.
175 * micromips.igen (cache): Likewise.
176 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
177 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
178 do_store_left, do_store_right, do_load_double, do_store_double):
179 Likewise.
180 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
181 (do_prefx): Likewise.
182 * sim-main.c (address_translation, prefetch): Delete.
183 (ifetch32, ifetch16): Delete call to AddressTranslation and set
184 paddr=vaddr.
185 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
186 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
187 (LoadMemory, StoreMemory): Delete CCA arg.
188
ef04e371
MF		 1892015-12-24 Mike Frysinger <vapier@gentoo.org>
190
191 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
192 * configure: Regenerated.
193
cb379ede
MF		 1942015-12-24 Mike Frysinger <vapier@gentoo.org>
195
196 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
197 * tconfig.h: Delete.
198
26936211
MF		 1992015-12-24 Mike Frysinger <vapier@gentoo.org>
200
201 * tconfig.h (SIM_HANDLES_LMA): Delete.
202
84e8e361
MF		 2032015-12-24 Mike Frysinger <vapier@gentoo.org>
204
205 * sim-main.h (WITH_WATCHPOINTS): Delete.
206
3cabaf66
MF		 2072015-12-24 Mike Frysinger <vapier@gentoo.org>
208
209 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
210
8abe6c66
MF		 2112015-12-24 Mike Frysinger <vapier@gentoo.org>
212
213 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
214
1d19cae7
DV		 2152015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
216
217 * micromips.igen (process_isa_mode): Fix left shift of negative
218 value.
219
cdf850e9
MF		 2202015-11-17 Mike Frysinger <vapier@gentoo.org>
221
222 * sim-main.h (WITH_MODULO_MEMORY): Delete.
223
797eee42
MF		 2242015-11-15 Mike Frysinger <vapier@gentoo.org>
225
226 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
227
6e4f085c
MF		 2282015-11-14 Mike Frysinger <vapier@gentoo.org>
229
230 * interp.c (sim_close): Rename to ...
231 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
232 sim_io_shutdown.
233 * sim-main.h (mips_sim_close): Declare.
234 (SIM_CLOSE_HOOK): Define.
235
8e394ffc
AB		 2362015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
237 Ali Lown <ali.lown@imgtec.com>
238
239 * Makefile.in (tmp-micromips): New rule.
240 (tmp-mach-multi): Add support for micromips.
241 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
242 that works for both mips64 and micromips64.
243 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
244 micromips32.
245 Add build support for micromips.
246 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
247 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
248 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
249 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
250 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
251 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
252 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
253 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
254 Refactored instruction code to use these functions.
255 * dsp2.igen: Refactored instruction code to use the new functions.
256 * interp.c (decode_coproc): Refactored to work with any instruction
257 encoding.
258 (isa_mode): New variable
259 (RSVD_INSTRUCTION): Changed to 0x00000039.
260 * m16.igen (BREAK16): Refactored instruction to use do_break16.
261 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
262 * micromips.dc: New file.
263 * micromips.igen: New file.
264 * micromips16.dc: New file.
265 * micromipsdsp.igen: New file.
266 * micromipsrun.c: New file.
267 * mips.igen (do_swc1): Changed to work with any instruction encoding.
268 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
269 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
270 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
271 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
272 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
273 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
274 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
275 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
276 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
277 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
278 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
279 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
280 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
281 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
282 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
283 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
284 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
285 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
286 instructions.
287 Refactored instruction code to use these functions.
288 (RSVD): Changed to use new reserved instruction.
289 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
290 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
291 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
292 do_store_double): Added micromips32 and micromips64 models.
293 Added include for micromips.igen and micromipsdsp.igen
294 Add micromips32 and micromips64 models.
295 (DecodeCoproc): Updated to use new macro definition.
296 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
297 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
298 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
299 Refactored instruction code to use these functions.
300 * sim-main.h (CP0_operation): New enum.
301 (DecodeCoproc): Updated macro.
302 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
303 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
304 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
305 ISA_MODE_MICROMIPS): New defines.
306 (sim_state): Add isa_mode field.
307
8d0978fb
MF		 3082015-06-23 Mike Frysinger <vapier@gentoo.org>
309
310 * configure: Regenerate.
311
306f4178
MF		 3122015-06-12 Mike Frysinger <vapier@gentoo.org>
313
314 * configure.ac: Change configure.in to configure.ac.
315 * configure: Regenerate.
316
a3487082
MF		 3172015-06-12 Mike Frysinger <vapier@gentoo.org>
318
319 * configure: Regenerate.
320
29bc024d
MF		 3212015-06-12 Mike Frysinger <vapier@gentoo.org>
322
323 * interp.c [TRACE]: Delete.
324 (TRACE): Change to WITH_TRACE_ANY_P.
325 [!WITH_TRACE_ANY_P] (open_trace): Define.
326 (mips_option_handler, open_trace, sim_close, dotrace):
327 Change defined(TRACE) to WITH_TRACE_ANY_P.
328 (sim_open): Delete TRACE ifdef check.
329 * sim-main.c (load_memory): Delete TRACE ifdef check.
330 (store_memory): Likewise.
331 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
332 [!WITH_TRACE_ANY_P] (dotrace): Define.
333
3ebe2863
MF		 3342015-04-18 Mike Frysinger <vapier@gentoo.org>
335
336 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
337 comments.
338
20bca71d
MF		 3392015-04-18 Mike Frysinger <vapier@gentoo.org>
340
341 * sim-main.h (SIM_CPU): Delete.
342
7e83aa92
MF		 3432015-04-18 Mike Frysinger <vapier@gentoo.org>
344
345 * sim-main.h (sim_cia): Delete.
346
034685f9
MF		 3472015-04-17 Mike Frysinger <vapier@gentoo.org>
348
349 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
350 PU_PC_GET.
351 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
352 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
353 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
354 CIA_SET to CPU_PC_SET.
355 * sim-main.h (CIA_GET, CIA_SET): Delete.
356
78e9aa70
MF		 3572015-04-15 Mike Frysinger <vapier@gentoo.org>
358
359 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
360 * sim-main.h (STATE_CPU): Delete.
361
bf12d44e
MF		 3622015-04-13 Mike Frysinger <vapier@gentoo.org>
363
364 * configure: Regenerate.
365
7bebb329
MF		 3662015-04-13 Mike Frysinger <vapier@gentoo.org>
367
368 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
369 * interp.c (mips_pc_get, mips_pc_set): New functions.
370 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
371 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
372 (sim_pc_get): Delete.
373 * sim-main.h (SIM_CPU): Define.
374 (struct sim_state): Change cpu to an array of pointers.
375 (STATE_CPU): Drop &.
376
8ac57fbd
MF		 3772015-04-13 Mike Frysinger <vapier@gentoo.org>
378
379 * interp.c (mips_option_handler, open_trace, sim_close,
380 sim_write, sim_read, sim_store_register, sim_fetch_register,
381 sim_create_inferior, pr_addr, pr_uword64): Convert old style
382 prototypes.
383 (sim_open): Convert old style prototype. Change casts with
384 sim_write to unsigned char *.
385 (fetch_str): Change null to unsigned char, and change cast to
386 unsigned char *.
387 (sim_monitor): Change c & ch to unsigned char. Change cast to
388 unsigned char *.
389
e787f858
MF		 3902015-04-12 Mike Frysinger <vapier@gentoo.org>
391
392 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
393
122bbfb5
MF		 3942015-04-06 Mike Frysinger <vapier@gentoo.org>
395
396 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
397
0fe84f3f
MF		 3982015-04-01 Mike Frysinger <vapier@gentoo.org>
399
400 * tconfig.h (SIM_HAVE_PROFILE): Delete.
401
aadc9410
MF		 4022015-03-31 Mike Frysinger <vapier@gentoo.org>
403
404 * config.in, configure: Regenerate.
405
05f53ed6
MF		 4062015-03-24 Mike Frysinger <vapier@gentoo.org>
407
408 * interp.c (sim_pc_get): New function.
409
c0931f26
MF		 4102015-03-24 Mike Frysinger <vapier@gentoo.org>
411
412 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
413 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
414
30452bbe
MF		 4152015-03-24 Mike Frysinger <vapier@gentoo.org>
416
417 * configure: Regenerate.
418
64dd13df
MF		 4192015-03-23 Mike Frysinger <vapier@gentoo.org>
420
421 * configure: Regenerate.
422
49cd1634
MF		 4232015-03-23 Mike Frysinger <vapier@gentoo.org>
424
425 * configure: Regenerate.
426 * configure.ac (mips_extra_objs): Delete.
427 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
428 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
429
3649cb06
MF		 4302015-03-23 Mike Frysinger <vapier@gentoo.org>
431
432 * configure: Regenerate.
433 * configure.ac: Delete sim_hw checks for dv-sockser.
434
ae7d0cac
MF		 4352015-03-16 Mike Frysinger <vapier@gentoo.org>
436
437 * config.in, configure: Regenerate.
438 * tconfig.in: Rename file ...
439 * tconfig.h: ... here.
440
8406bb59
MF		 4412015-03-15 Mike Frysinger <vapier@gentoo.org>
442
443 * tconfig.in: Delete includes.
444 [HAVE_DV_SOCKSER]: Delete.
445
465fb143
MF		 4462015-03-14 Mike Frysinger <vapier@gentoo.org>
447
448 * Makefile.in (SIM_RUN_OBJS): Delete.
449
5cddc23a
MF		 4502015-03-14 Mike Frysinger <vapier@gentoo.org>
451
452 * configure.ac (AC_CHECK_HEADERS): Delete.
453 * aclocal.m4, configure: Regenerate.
454
2974be62
AM		 4552014-08-19 Alan Modra <amodra@gmail.com>
456
457 * configure: Regenerate.
458
faa743bb
RM		 4592014-08-15 Roland McGrath <mcgrathr@google.com>
460
461 * configure: Regenerate.
462 * config.in: Regenerate.
463
1a8a700e
MF		 4642014-03-04 Mike Frysinger <vapier@gentoo.org>
465
466 * configure: Regenerate.
467
bf3d9781
AM		 4682013-09-23 Alan Modra <amodra@gmail.com>
469
470 * configure: Regenerate.
471
31e6ad7d
MF		 4722013-06-03 Mike Frysinger <vapier@gentoo.org>
473
474 * aclocal.m4, configure: Regenerate.
475
d3685d60
TT		 4762013-05-10 Freddie Chopin <freddie_chopin@op.pl>
477
478 * configure: Rebuild.
479
1517bd27
MF		 4802013-03-26 Mike Frysinger <vapier@gentoo.org>
481
482 * configure: Regenerate.
483
3be31516
JS		 4842013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
485
486 * configure.ac: Address use of dv-sockser.o.
487 * tconfig.in: Conditionalize use of dv_sockser_install.
488 * configure: Regenerated.
489 * config.in: Regenerated.
490
37cb8f8e
SE		 4912012-10-04 Chao-ying Fu <fu@mips.com>
492 Steve Ellcey <sellcey@mips.com>
493
494 * mips/mips3264r2.igen (rdhwr): New.
495
87c8644f
JS		 4962012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
497
498 * configure.ac: Always link against dv-sockser.o.
499 * configure: Regenerate.
500
5f3ef9d0
JB		 5012012-06-15 Joel Brobecker <brobecker@adacore.com>
502
503 * config.in, configure: Regenerate.
504
a6ff997c
NC		 5052012-05-18 Nick Clifton <nickc@redhat.com>
506
507 PR 14072
508 * interp.c: Include config.h before system header files.
509
2232061b
MF		 5102012-03-24 Mike Frysinger <vapier@gentoo.org>
511
512 * aclocal.m4, config.in, configure: Regenerate.
513
db2e4d67
MF		 5142011-12-03 Mike Frysinger <vapier@gentoo.org>
515
516 * aclocal.m4: New file.
517 * configure: Regenerate.
518
4399a56b
MF		 5192011-10-19 Mike Frysinger <vapier@gentoo.org>
520
521 * configure: Regenerate after common/acinclude.m4 update.
522
9c082ca8
MF		 5232011-10-17 Mike Frysinger <vapier@gentoo.org>
524
525 * configure.ac: Change include to common/acinclude.m4.
526
6ffe910a
MF		 5272011-10-17 Mike Frysinger <vapier@gentoo.org>
528
529 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
530 call. Replace common.m4 include with SIM_AC_COMMON.
531 * configure: Regenerate.
532
31b28250
HPN		 5332011-07-08 Hans-Peter Nilsson <hp@axis.com>
534
3faa01e3
HPN		 535 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
536 $(SIM_EXTRA_DEPS).
537 (tmp-mach-multi): Exit early when igen fails.
31b28250 538
2419798b
MF		 5392011-07-05 Mike Frysinger <vapier@gentoo.org>
540
541 * interp.c (sim_do_command): Delete.
542
d79fe0d6
MF		 5432011-02-14 Mike Frysinger <vapier@gentoo.org>
544
545 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
546 (tx3904sio_fifo_reset): Likewise.
547 * interp.c (sim_monitor): Likewise.
548
5558e7e6
MF		 5492010-04-14 Mike Frysinger <vapier@gentoo.org>
550
551 * interp.c (sim_write): Add const to buffer arg.
552
35aafff4
JB		 5532010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
554
555 * interp.c: Don't include sysdep.h
556
3725885a
RW		 5572010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
558
559 * configure: Regenerate.
560
d6416cdc
RW		 5612009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
562
81ecdfbb
RW		 563 * config.in: Regenerate.
564 * configure: Likewise.
565
d6416cdc
RW		 566 * configure: Regenerate.
567
b5bd9624
HPN		 5682008-07-11 Hans-Peter Nilsson <hp@axis.com>
569
570 * configure: Regenerate to track ../common/common.m4 changes.
571 * config.in: Ditto.
572
6efef468 5732008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 574 Daniel Jacobowitz <dan@codesourcery.com>
575 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 576
577 * configure: Regenerate.
578
60dc88db
RS		 5792007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
580
581 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
582 that unconditionally allows fmt_ps.
583 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
584 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
585 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
586 filter from 64,f to 32,f.
587 (PREFX): Change filter from 64 to 32.
588 (LDXC1, LUXC1): Provide separate mips32r2 implementations
589 that use do_load_double instead of do_load. Make both LUXC1
590 versions unpredictable if SizeFGR () != 64.
591 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
592 instead of do_store. Remove unused variable. Make both SUXC1
593 versions unpredictable if SizeFGR () != 64.
594
599ca73e
RS		 5952007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
596
597 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
598 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
599 shifts for that case.
600
2525df03
NC		 6012007-09-04 Nick Clifton <nickc@redhat.com>
602
603 * interp.c (options enum): Add OPTION_INFO_MEMORY.
604 (display_mem_info): New static variable.
605 (mips_option_handler): Handle OPTION_INFO_MEMORY.
606 (mips_options): Add info-memory and memory-info.
607 (sim_open): After processing the command line and board
608 specification, check display_mem_info. If it is set then
609 call the real handler for the --memory-info command line
610 switch.
611
35ee6e1e
JB		 6122007-08-24 Joel Brobecker <brobecker@adacore.com>
613
614 * configure.ac: Change license of multi-run.c to GPL version 3.
615 * configure: Regenerate.
616
d5fb0879
RS		 6172007-06-28 Richard Sandiford <richard@codesourcery.com>
618
619 * configure.ac, configure: Revert last patch.
620
2a2ce21b
RS		 6212007-06-26 Richard Sandiford <richard@codesourcery.com>
622
623 * configure.ac (sim_mipsisa3264_configs): New variable.
624 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
625 every configuration support all four targets, using the triplet to
626 determine the default.
627 * configure: Regenerate.
628
efdcccc9
RS		 6292007-06-25 Richard Sandiford <richard@codesourcery.com>
630
0a7692b2 631 * Makefile.in (m16run.o): New rule.
efdcccc9 632
f532a356
TS		 6332007-05-15 Thiemo Seufer <ths@mips.com>
634
635 * mips3264r2.igen (DSHD): Fix compile warning.
636
bfe9c90b
TS		 6372007-05-14 Thiemo Seufer <ths@mips.com>
638
639 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
640 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
641 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
642 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
643 for mips32r2.
644
53f4826b
TS		 6452007-03-01 Thiemo Seufer <ths@mips.com>
646
647 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
648 and mips64.
649
8bf3ddc8
TS		 6502007-02-20 Thiemo Seufer <ths@mips.com>
651
652 * dsp.igen: Update copyright notice.
653 * dsp2.igen: Fix copyright notice.
654
8b082fb1 6552007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 656 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 657
658 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
659 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
660 Add dsp2 to sim_igen_machine.
661 * configure: Regenerate.
662 * dsp.igen (do_ph_op): Add MUL support when op = 2.
663 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
664 (mulq_rs.ph): Use do_ph_mulq.
665 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
666 * mips.igen: Add dsp2 model and include dsp2.igen.
667 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
668 for *mips32r2, *mips64r2, *dsp.
669 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
670 for *mips32r2, *mips64r2, *dsp2.
671 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
672
b1004875 6732007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 674 Nigel Stephens <nigel@mips.com>
b1004875
TS		 675
676 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
677 jumps with hazard barrier.
678
f8df4c77 6792007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 680 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 681
682 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
683 after each call to sim_io_write.
684
b1004875 6852007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 686 Nigel Stephens <nigel@mips.com>
b1004875
TS		 687
688 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
689 supported by this simulator.
07802d98
TS		 690 (decode_coproc): Recognise additional CP0 Config registers
691 correctly.
692
14fb6c5a 6932007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 694 Nigel Stephens <nigel@mips.com>
695 David Ung <davidu@mips.com>
14fb6c5a
TS		 696
697 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
698 uninterpreted formats. If fmt is one of the uninterpreted types
699 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
700 fmt_word, and fmt_uninterpreted_64 like fmt_long.
701 (store_fpr): When writing an invalid odd register, set the
702 matching even register to fmt_unknown, not the following register.
703 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
704 the the memory window at offset 0 set by --memory-size command
705 line option.
706 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
707 point register.
708 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
709 register.
710 (sim_monitor): When returning the memory size to the MIPS
711 application, use the value in STATE_MEM_SIZE, not an arbitrary
712 hardcoded value.
713 (cop_lw): Don' mess around with FPR_STATE, just pass
714 fmt_uninterpreted_32 to StoreFPR.
715 (cop_sw): Similarly.
716 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
717 (cop_sd): Similarly.
718 * mips.igen (not_word_value): Single version for mips32, mips64
719 and mips16.
720
c8847145 7212007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 722 Nigel Stephens <nigel@mips.com>
c8847145
TS		 723
724 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
725 MBytes.
726
4b5d35ee
TS		 7272007-02-17 Thiemo Seufer <ths@mips.com>
728
729 * configure.ac (mips*-sde-elf*): Move in front of generic machine
730 configuration.
731 * configure: Regenerate.
732
3669427c
TS		 7332007-02-17 Thiemo Seufer <ths@mips.com>
734
735 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
736 Add mdmx to sim_igen_machine.
737 (mipsisa64*-*-*): Likewise. Remove dsp.
738 (mipsisa32*-*-*): Remove dsp.
739 * configure: Regenerate.
740
109ad085
TS		 7412007-02-13 Thiemo Seufer <ths@mips.com>
742
743 * configure.ac: Add mips*-sde-elf* target.
744 * configure: Regenerate.
745
921d7ad3
HPN		 7462006-12-21 Hans-Peter Nilsson <hp@axis.com>
747
748 * acconfig.h: Remove.
749 * config.in, configure: Regenerate.
750
02f97da7
TS		 7512006-11-07 Thiemo Seufer <ths@mips.com>
752
753 * dsp.igen (do_w_op): Fix compiler warning.
754
2d2733fc 7552006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 756 David Ung <davidu@mips.com>
2d2733fc
TS		 757
758 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
759 sim_igen_machine.
760 * configure: Regenerate.
761 * mips.igen (model): Add smartmips.
762 (MADDU): Increment ACX if carry.
763 (do_mult): Clear ACX.
764 (ROR,RORV): Add smartmips.
72f4393d 765 (include): Include smartmips.igen.
2d2733fc
TS		 766 * sim-main.h (ACX): Set to REGISTERS[89].
767 * smartmips.igen: New file.
768
d85c3a10 7692006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 770 David Ung <davidu@mips.com>
d85c3a10
TS		 771
772 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
773 mips3264r2.igen. Add missing dependency rules.
774 * m16e.igen: Support for mips16e save/restore instructions.
775
e85e3205
RE		 7762006-06-13 Richard Earnshaw <rearnsha@arm.com>
777
778 * configure: Regenerated.
779
2f0122dc
DJ		 7802006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
781
782 * configure: Regenerated.
783
20e95c23
DJ		 7842006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
785
786 * configure: Regenerated.
787
69088b17
CF		 7882006-05-15 Chao-ying Fu <fu@mips.com>
789
790 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
791
0275de4e
NC		 7922006-04-18 Nick Clifton <nickc@redhat.com>
793
794 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
795 statement.
796
b3a3ffef
HPN		 7972006-03-29 Hans-Peter Nilsson <hp@axis.com>
798
799 * configure: Regenerate.
800
40a5538e
CF		 8012005-12-14 Chao-ying Fu <fu@mips.com>
802
803 * Makefile.in (SIM_OBJS): Add dsp.o.
804 (dsp.o): New dependency.
805 (IGEN_INCLUDE): Add dsp.igen.
806 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
807 mipsisa64*-*-*): Add dsp to sim_igen_machine.
808 * configure: Regenerate.
809 * mips.igen: Add dsp model and include dsp.igen.
810 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
811 because these instructions are extended in DSP ASE.
812 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
813 adding 6 DSP accumulator registers and 1 DSP control register.
814 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
815 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
816 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
817 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
818 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
819 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
820 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
821 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
822 DSPCR_CCOND_SMASK): New define.
823 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
824 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
825
21d14896
ILT		 8262005-07-08 Ian Lance Taylor <ian@airs.com>
827
828 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
829
b16d63da 8302005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 831 Nigel Stephens <nigel@mips.com>
832
833 * mips.igen: New mips16e model and include m16e.igen.
834 (check_u64): Add mips16e tag.
835 * m16e.igen: New file for MIPS16e instructions.
836 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
837 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
838 models.
839 * configure: Regenerate.
b16d63da 840
e70cb6cd 8412005-05-26 David Ung <davidu@mips.com>
72f4393d 842
e70cb6cd
CD		 843 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
844 tags to all instructions which are applicable to the new ISAs.
845 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
846 vr.igen.
847 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 848 instructions.
e70cb6cd
CD		 849 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
850 to mips.igen.
851 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
852 * configure: Regenerate.
72f4393d 853
2b193c4a
MK		 8542005-03-23 Mark Kettenis <kettenis@gnu.org>
855
856 * configure: Regenerate.
857
35695fd6
AC		 8582005-01-14 Andrew Cagney <cagney@gnu.org>
859
860 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
861 explicit call to AC_CONFIG_HEADER.
862 * configure: Regenerate.
863
f0569246
AC		 8642005-01-12 Andrew Cagney <cagney@gnu.org>
865
866 * configure.ac: Update to use ../common/common.m4.
867 * configure: Re-generate.
868
38f48d72
AC		 8692005-01-11 Andrew Cagney <cagney@localhost.localdomain>
870
871 * configure: Regenerated to track ../common/aclocal.m4 changes.
872
b7026657
AC		 8732005-01-07 Andrew Cagney <cagney@gnu.org>
874
875 * configure.ac: Rename configure.in, require autoconf 2.59.
876 * configure: Re-generate.
877
379832de
HPN		 8782004-12-08 Hans-Peter Nilsson <hp@axis.com>
879
880 * configure: Regenerate for ../common/aclocal.m4 update.
881
cd62154c 8822004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 883
cd62154c
AC		 884 Committed by Andrew Cagney.
885 * m16.igen (CMP, CMPI): Fix assembler.
886
e5da76ec
CD		 8872004-08-18 Chris Demetriou <cgd@broadcom.com>
888
889 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
890 * configure: Regenerate.
891
139181c8
CD		 8922004-06-25 Chris Demetriou <cgd@broadcom.com>
893
894 * configure.in (sim_m16_machine): Include mipsIII.
895 * configure: Regenerate.
896
1a27f959
CD		 8972004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
898
72f4393d 899 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 900 from COP0_BADVADDR.
901 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
902
5dbb7b5a
CD		 9032004-04-10 Chris Demetriou <cgd@broadcom.com>
904
905 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
906
14234056
CD		 9072004-04-09 Chris Demetriou <cgd@broadcom.com>
908
909 * mips.igen (check_fmt): Remove.
910 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
911 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
912 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
913 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
914 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
915 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
916 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
917 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
918 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
919 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
920
c6f9085c
CD		 9212004-04-09 Chris Demetriou <cgd@broadcom.com>
922
923 * sb1.igen (check_sbx): New function.
924 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
925
11d66e66 9262004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 927 Richard Sandiford <rsandifo@redhat.com>
928
929 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
930 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
931 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
932 separate implementations for mipsIV and mipsV. Use new macros to
933 determine whether the restrictions apply.
934
b3208fb8
CD		 9352004-01-19 Chris Demetriou <cgd@broadcom.com>
936
937 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
938 (check_mult_hilo): Improve comments.
939 (check_div_hilo): Likewise. Also, fork off a new version
940 to handle mips32/mips64 (since there are no hazards to check
941 in MIPS32/MIPS64).
942
9a1d84fb
CD		 9432003-06-17 Richard Sandiford <rsandifo@redhat.com>
944
945 * mips.igen (do_dmultx): Fix check for negative operands.
946
ae451ac6
ILT		 9472003-05-16 Ian Lance Taylor <ian@airs.com>
948
949 * Makefile.in (SHELL): Make sure this is defined.
950 (various): Use $(SHELL) whenever we invoke move-if-change.
951
dd69d292
CD		 9522003-05-03 Chris Demetriou <cgd@broadcom.com>
953
954 * cp1.c: Tweak attribution slightly.
955 * cp1.h: Likewise.
956 * mdmx.c: Likewise.
957 * mdmx.igen: Likewise.
958 * mips3d.igen: Likewise.
959 * sb1.igen: Likewise.
960
bcd0068e
CD		 9612003-04-15 Richard Sandiford <rsandifo@redhat.com>
962
963 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
964 unsigned operands.
965
6b4a8935
AC		 9662003-02-27 Andrew Cagney <cagney@redhat.com>
967
601da316
AC		 968 * interp.c (sim_open): Rename _bfd to bfd.
969 (sim_create_inferior): Ditto.
6b4a8935 970
d29e330f
CD		 9712003-01-14 Chris Demetriou <cgd@broadcom.com>
972
973 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
974
a2353a08
CD		 9752003-01-14 Chris Demetriou <cgd@broadcom.com>
976
977 * mips.igen (EI, DI): Remove.
978
80551777
CD		 9792003-01-05 Richard Sandiford <rsandifo@redhat.com>
980
981 * Makefile.in (tmp-run-multi): Fix mips16 filter.
982
4c54fc26
CD		 9832003-01-04 Richard Sandiford <rsandifo@redhat.com>
984 Andrew Cagney <ac131313@redhat.com>
985 Gavin Romig-Koch <gavin@redhat.com>
986 Graydon Hoare <graydon@redhat.com>
987 Aldy Hernandez <aldyh@redhat.com>
988 Dave Brolley <brolley@redhat.com>
989 Chris Demetriou <cgd@broadcom.com>
990
991 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
992 (sim_mach_default): New variable.
993 (mips64vr-*-*, mips64vrel-*-*): New configurations.
994 Add a new simulator generator, MULTI.
995 * configure: Regenerate.
996 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
997 (multi-run.o): New dependency.
998 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
999 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1000 (tmp-multi): Combine them.
1001 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1002 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1003 (distclean-extra): New rule.
1004 * sim-main.h: Include bfd.h.
1005 (MIPS_MACH): New macro.
1006 * mips.igen (vr4120, vr5400, vr5500): New models.
1007 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1008 * vr.igen: Replace with new version.
1009
e6c674b8
CD		 10102003-01-04 Chris Demetriou <cgd@broadcom.com>
1011
1012 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1013 * configure: Regenerate.
1014
28f50ac8
CD		 10152002-12-31 Chris Demetriou <cgd@broadcom.com>
1016
1017 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1018 * mips.igen: Remove all invocations of check_branch_bug and
1019 mark_branch_bug.
1020
5071ffe6
CD		 10212002-12-16 Chris Demetriou <cgd@broadcom.com>
1022
72f4393d 1023 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1024
06e7837e
CD		 10252002-07-30 Chris Demetriou <cgd@broadcom.com>
1026
1027 * mips.igen (do_load_double, do_store_double): New functions.
1028 (LDC1, SDC1): Rename to...
1029 (LDC1b, SDC1b): respectively.
1030 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1031
2265c243
MS		 10322002-07-29 Michael Snyder <msnyder@redhat.com>
1033
1034 * cp1.c (fp_recip2): Modify initialization expression so that
1035 GCC will recognize it as constant.
1036
a2f8b4f3
CD		 10372002-06-18 Chris Demetriou <cgd@broadcom.com>
1038
1039 * mdmx.c (SD_): Delete.
1040 (Unpredictable): Re-define, for now, to directly invoke
1041 unpredictable_action().
1042 (mdmx_acc_op): Fix error in .ob immediate handling.
1043
b4b6c939
AC		 10442002-06-18 Andrew Cagney <cagney@redhat.com>
1045
1046 * interp.c (sim_firmware_command): Initialize `address'.
1047
c8cca39f
AC		 10482002-06-16 Andrew Cagney <ac131313@redhat.com>
1049
1050 * configure: Regenerated to track ../common/aclocal.m4 changes.
1051
e7e81181 10522002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1053 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1054
1055 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1056 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1057 * mips.igen: Include mips3d.igen.
1058 (mips3d): New model name for MIPS-3D ASE instructions.
1059 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1060 instructions.
e7e81181
CD		 1061 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1062 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1063 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1064 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1065 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1066 (RSquareRoot1, RSquareRoot2): New macros.
1067 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1068 (fp_rsqrt2): New functions.
1069 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1070 * configure: Regenerate.
1071
3a2b820e 10722002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1073 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1074
1075 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1076 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1077 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1078 (convert): Note that this function is not used for paired-single
1079 format conversions.
1080 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1081 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1082 (check_fmt_p): Enable paired-single support.
1083 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1084 (PUU.PS): New instructions.
1085 (CVT.S.fmt): Don't use this instruction for paired-single format
1086 destinations.
1087 * sim-main.h (FP_formats): New value 'fmt_ps.'
1088 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1089 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1090
d18ea9c2
CD		 10912002-06-12 Chris Demetriou <cgd@broadcom.com>
1092
1093 * mips.igen: Fix formatting of function calls in
1094 many FP operations.
1095
95fd5cee
CD		 10962002-06-12 Chris Demetriou <cgd@broadcom.com>
1097
1098 * mips.igen (MOVN, MOVZ): Trace result.
1099 (TNEI): Print "tnei" as the opcode name in traces.
1100 (CEIL.W): Add disassembly string for traces.
1101 (RSQRT.fmt): Make location of disassembly string consistent
1102 with other instructions.
1103
4f0d55ae
CD		 11042002-06-12 Chris Demetriou <cgd@broadcom.com>
1105
1106 * mips.igen (X): Delete unused function.
1107
3c25f8c7
AC		 11082002-06-08 Andrew Cagney <cagney@redhat.com>
1109
1110 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1111
f3c08b7e 11122002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1113 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1114
1115 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1116 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1117 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1118 (fp_nmsub): New prototypes.
1119 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1120 (NegMultiplySub): New defines.
1121 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1122 (MADD.D, MADD.S): Replace with...
1123 (MADD.fmt): New instruction.
1124 (MSUB.D, MSUB.S): Replace with...
1125 (MSUB.fmt): New instruction.
1126 (NMADD.D, NMADD.S): Replace with...
1127 (NMADD.fmt): New instruction.
1128 (NMSUB.D, MSUB.S): Replace with...
1129 (NMSUB.fmt): New instruction.
1130
52714ff9 11312002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1132 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1133
1134 * cp1.c: Fix more comment spelling and formatting.
1135 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1136 (denorm_mode): New function.
1137 (fpu_unary, fpu_binary): Round results after operation, collect
1138 status from rounding operations, and update the FCSR.
1139 (convert): Collect status from integer conversions and rounding
1140 operations, and update the FCSR. Adjust NaN values that result
1141 from conversions. Convert to use sim_io_eprintf rather than
1142 fprintf, and remove some debugging code.
1143 * cp1.h (fenr_FS): New define.
1144
577d8c4b
CD		 11452002-06-07 Chris Demetriou <cgd@broadcom.com>
1146
1147 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1148 rounding mode to sim FP rounding mode flag conversion code into...
1149 (rounding_mode): New function.
1150
196496ed
CD		 11512002-06-07 Chris Demetriou <cgd@broadcom.com>
1152
1153 * cp1.c: Clean up formatting of a few comments.
1154 (value_fpr): Reformat switch statement.
1155
cfe9ea23 11562002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1157 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1158
1159 * cp1.h: New file.
1160 * sim-main.h: Include cp1.h.
1161 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1162 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1163 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1164 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1165 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1166 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1167 * cp1.c: Don't include sim-fpu.h; already included by
1168 sim-main.h. Clean up formatting of some comments.
1169 (NaN, Equal, Less): Remove.
1170 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1171 (fp_cmp): New functions.
1172 * mips.igen (do_c_cond_fmt): Remove.
1173 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1174 Compare. Add result tracing.
1175 (CxC1): Remove, replace with...
1176 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1177 (DMxC1): Remove, replace with...
1178 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1179 (MxC1): Remove, replace with...
1180 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1181
ee7254b0
CD		 11822002-06-04 Chris Demetriou <cgd@broadcom.com>
1183
1184 * sim-main.h (FGRIDX): Remove, replace all uses with...
1185 (FGR_BASE): New macro.
1186 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1187 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1188 (NR_FGR, FGR): Likewise.
1189 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1190 * mips.igen: Likewise.
1191
d3eb724f
CD		 11922002-06-04 Chris Demetriou <cgd@broadcom.com>
1193
1194 * cp1.c: Add an FSF Copyright notice to this file.
1195
ba46ddd0 11962002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1197 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1198
1199 * cp1.c (Infinity): Remove.
1200 * sim-main.h (Infinity): Likewise.
1201
1202 * cp1.c (fp_unary, fp_binary): New functions.
1203 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1204 (fp_sqrt): New functions, implemented in terms of the above.
1205 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1206 (Recip, SquareRoot): Remove (replaced by functions above).
1207 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1208 (fp_recip, fp_sqrt): New prototypes.
1209 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1210 (Recip, SquareRoot): Replace prototypes with #defines which
1211 invoke the functions above.
72f4393d 1212
18d8a52d
CD		 12132002-06-03 Chris Demetriou <cgd@broadcom.com>
1214
1215 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1216 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1217 file, remove PARAMS from prototypes.
1218 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1219 simulator state arguments.
1220 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1221 pass simulator state arguments.
1222 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1223 (store_fpr, convert): Remove 'sd' argument.
1224 (value_fpr): Likewise. Convert to use 'SD' instead.
1225
0f154cbd
CD		 12262002-06-03 Chris Demetriou <cgd@broadcom.com>
1227
1228 * cp1.c (Min, Max): Remove #if 0'd functions.
1229 * sim-main.h (Min, Max): Remove.
1230
e80fc152
CD		 12312002-06-03 Chris Demetriou <cgd@broadcom.com>
1232
1233 * cp1.c: fix formatting of switch case and default labels.
1234 * interp.c: Likewise.
1235 * sim-main.c: Likewise.
1236
bad673a9
CD		 12372002-06-03 Chris Demetriou <cgd@broadcom.com>
1238
1239 * cp1.c: Clean up comments which describe FP formats.
1240 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1241
7cbea089 12422002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1243 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1244
1245 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1246 Broadcom SiByte SB-1 processor configurations.
1247 * configure: Regenerate.
1248 * sb1.igen: New file.
1249 * mips.igen: Include sb1.igen.
1250 (sb1): New model.
1251 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1252 * mdmx.igen: Add "sb1" model to all appropriate functions and
1253 instructions.
1254 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1255 (ob_func, ob_acc): Reference the above.
1256 (qh_acc): Adjust to keep the same size as ob_acc.
1257 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1258 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1259
909daa82
CD		 12602002-06-03 Chris Demetriou <cgd@broadcom.com>
1261
1262 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1263
f4f1b9f1 12642002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1265 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1266
1267 * mips.igen (mdmx): New (pseudo-)model.
1268 * mdmx.c, mdmx.igen: New files.
1269 * Makefile.in (SIM_OBJS): Add mdmx.o.
1270 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1271 New typedefs.
1272 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1273 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1274 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1275 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1276 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1277 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1278 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1279 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1280 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1281 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1282 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1283 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1284 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1285 (qh_fmtsel): New macros.
1286 (_sim_cpu): New member "acc".
1287 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1288 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1289
5accf1ff
CD		 12902002-05-01 Chris Demetriou <cgd@broadcom.com>
1291
1292 * interp.c: Use 'deprecated' rather than 'depreciated.'
1293 * sim-main.h: Likewise.
1294
402586aa
CD		 12952002-05-01 Chris Demetriou <cgd@broadcom.com>
1296
1297 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1298 which wouldn't compile anyway.
1299 * sim-main.h (unpredictable_action): New function prototype.
1300 (Unpredictable): Define to call igen function unpredictable().
1301 (NotWordValue): New macro to call igen function not_word_value().
1302 (UndefinedResult): Remove.
1303 * interp.c (undefined_result): Remove.
1304 (unpredictable_action): New function.
1305 * mips.igen (not_word_value, unpredictable): New functions.
1306 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1307 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1308 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1309 NotWordValue() to check for unpredictable inputs, then
1310 Unpredictable() to handle them.
1311
c9b9995a
CD		 13122002-02-24 Chris Demetriou <cgd@broadcom.com>
1313
1314 * mips.igen: Fix formatting of calls to Unpredictable().
1315
e1015982
AC		 13162002-04-20 Andrew Cagney <ac131313@redhat.com>
1317
1318 * interp.c (sim_open): Revert previous change.
1319
b882a66b
AO		 13202002-04-18 Alexandre Oliva <aoliva@redhat.com>
1321
1322 * interp.c (sim_open): Disable chunk of code that wrote code in
1323 vector table entries.
1324
c429b7dd
CD		 13252002-03-19 Chris Demetriou <cgd@broadcom.com>
1326
1327 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1328 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1329 unused definitions.
1330
37d146fa
CD		 13312002-03-19 Chris Demetriou <cgd@broadcom.com>
1332
1333 * cp1.c: Fix many formatting issues.
1334
07892c0b
CD		 13352002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1336
1337 * cp1.c (fpu_format_name): New function to replace...
1338 (DOFMT): This. Delete, and update all callers.
1339 (fpu_rounding_mode_name): New function to replace...
1340 (RMMODE): This. Delete, and update all callers.
1341
487f79b7
CD		 13422002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1343
1344 * interp.c: Move FPU support routines from here to...
1345 * cp1.c: Here. New file.
1346 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1347 (cp1.o): New target.
1348
1e799e28
CD		 13492002-03-12 Chris Demetriou <cgd@broadcom.com>
1350
1351 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1352 * mips.igen (mips32, mips64): New models, add to all instructions
1353 and functions as appropriate.
1354 (loadstore_ea, check_u64): New variant for model mips64.
1355 (check_fmt_p): New variant for models mipsV and mips64, remove
1356 mipsV model marking fro other variant.
1357 (SLL) Rename to...
1358 (SLLa) this.
1359 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1360 for mips32 and mips64.
1361 (DCLO, DCLZ): New instructions for mips64.
1362
82f728db
CD		 13632002-03-07 Chris Demetriou <cgd@broadcom.com>
1364
1365 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1366 immediate or code as a hex value with the "%#lx" format.
1367 (ANDI): Likewise, and fix printed instruction name.
1368
b96e7ef1
CD		 13692002-03-05 Chris Demetriou <cgd@broadcom.com>
1370
1371 * sim-main.h (UndefinedResult, Unpredictable): New macros
1372 which currently do nothing.
1373
d35d4f70
CD		 13742002-03-05 Chris Demetriou <cgd@broadcom.com>
1375
1376 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1377 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1378 (status_CU3): New definitions.
1379
1380 * sim-main.h (ExceptionCause): Add new values for MIPS32
1381 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1382 for DebugBreakPoint and NMIReset to note their status in
1383 MIPS32 and MIPS64.
1384 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1385 (SignalExceptionCacheErr): New exception macros.
1386
3ad6f714
CD		 13872002-03-05 Chris Demetriou <cgd@broadcom.com>
1388
1389 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1390 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1391 is always enabled.
1392 (SignalExceptionCoProcessorUnusable): Take as argument the
1393 unusable coprocessor number.
1394
86b77b47
CD		 13952002-03-05 Chris Demetriou <cgd@broadcom.com>
1396
1397 * mips.igen: Fix formatting of all SignalException calls.
1398
97a88e93 13992002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1400
1401 * sim-main.h (SIGNEXTEND): Remove.
1402
97a88e93 14032002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1404
1405 * mips.igen: Remove gencode comment from top of file, fix
1406 spelling in another comment.
1407
97a88e93 14082002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1409
1410 * mips.igen (check_fmt, check_fmt_p): New functions to check
1411 whether specific floating point formats are usable.
1412 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1413 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1414 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1415 Use the new functions.
1416 (do_c_cond_fmt): Remove format checks...
1417 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1418
97a88e93 14192002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1420
1421 * mips.igen: Fix formatting of check_fpu calls.
1422
41774c9d
CD		 14232002-03-03 Chris Demetriou <cgd@broadcom.com>
1424
1425 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1426
4a0bd876
CD		 14272002-03-03 Chris Demetriou <cgd@broadcom.com>
1428
1429 * mips.igen: Remove whitespace at end of lines.
1430
09297648
CD		 14312002-03-02 Chris Demetriou <cgd@broadcom.com>
1432
1433 * mips.igen (loadstore_ea): New function to do effective
1434 address calculations.
1435 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1436 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1437 CACHE): Use loadstore_ea to do effective address computations.
1438
043b7057
CD		 14392002-03-02 Chris Demetriou <cgd@broadcom.com>
1440
1441 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1442 * mips.igen (LL, CxC1, MxC1): Likewise.
1443
c1e8ada4
CD		 14442002-03-02 Chris Demetriou <cgd@broadcom.com>
1445
1446 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1447 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1448 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1449 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1450 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1451 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1452 Don't split opcode fields by hand, use the opcode field values
1453 provided by igen.
1454
3e1dca16
CD		 14552002-03-01 Chris Demetriou <cgd@broadcom.com>
1456
1457 * mips.igen (do_divu): Fix spacing.
1458
1459 * mips.igen (do_dsllv): Move to be right before DSLLV,
1460 to match the rest of the do_<shift> functions.
1461
fff8d27d
CD		 14622002-03-01 Chris Demetriou <cgd@broadcom.com>
1463
1464 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1465 DSRL32, do_dsrlv): Trace inputs and results.
1466
0d3e762b
CD		 14672002-03-01 Chris Demetriou <cgd@broadcom.com>
1468
1469 * mips.igen (CACHE): Provide instruction-printing string.
1470
1471 * interp.c (signal_exception): Comment tokens after #endif.
1472
eb5fcf93
CD		 14732002-02-28 Chris Demetriou <cgd@broadcom.com>
1474
1475 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1476 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1477 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1478 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1479 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1480 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1481 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1482 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1483
bb22bd7d
CD		 14842002-02-28 Chris Demetriou <cgd@broadcom.com>
1485
1486 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1487 instruction-printing string.
1488 (LWU): Use '64' as the filter flag.
1489
91a177cf
CD		 14902002-02-28 Chris Demetriou <cgd@broadcom.com>
1491
1492 * mips.igen (SDXC1): Fix instruction-printing string.
1493
387f484a
CD		 14942002-02-28 Chris Demetriou <cgd@broadcom.com>
1495
1496 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1497 filter flags "32,f".
1498
3d81f391
CD		 14992002-02-27 Chris Demetriou <cgd@broadcom.com>
1500
1501 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1502 as the filter flag.
1503
af5107af
CD		 15042002-02-27 Chris Demetriou <cgd@broadcom.com>
1505
1506 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1507 add a comma) so that it more closely match the MIPS ISA
1508 documentation opcode partitioning.
1509 (PREF): Put useful names on opcode fields, and include
1510 instruction-printing string.
1511
ca971540
CD		 15122002-02-27 Chris Demetriou <cgd@broadcom.com>
1513
1514 * mips.igen (check_u64): New function which in the future will
1515 check whether 64-bit instructions are usable and signal an
1516 exception if not. Currently a no-op.
1517 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1518 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1519 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1520 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1521
1522 * mips.igen (check_fpu): New function which in the future will
1523 check whether FPU instructions are usable and signal an exception
1524 if not. Currently a no-op.
1525 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1526 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1527 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1528 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1529 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1530 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1531 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1532 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1533
1c47a468
CD		 15342002-02-27 Chris Demetriou <cgd@broadcom.com>
1535
1536 * mips.igen (do_load_left, do_load_right): Move to be immediately
1537 following do_load.
1538 (do_store_left, do_store_right): Move to be immediately following
1539 do_store.
1540
603a98e7
CD		 15412002-02-27 Chris Demetriou <cgd@broadcom.com>
1542
1543 * mips.igen (mipsV): New model name. Also, add it to
1544 all instructions and functions where it is appropriate.
1545
c5d00cc7
CD		 15462002-02-18 Chris Demetriou <cgd@broadcom.com>
1547
1548 * mips.igen: For all functions and instructions, list model
1549 names that support that instruction one per line.
1550
074e9cb8
CD		 15512002-02-11 Chris Demetriou <cgd@broadcom.com>
1552
1553 * mips.igen: Add some additional comments about supported
1554 models, and about which instructions go where.
1555 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1556 order as is used in the rest of the file.
1557
9805e229
CD		 15582002-02-11 Chris Demetriou <cgd@broadcom.com>
1559
1560 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1561 indicating that ALU32_END or ALU64_END are there to check
1562 for overflow.
1563 (DADD): Likewise, but also remove previous comment about
1564 overflow checking.
1565
f701dad2
CD		 15662002-02-10 Chris Demetriou <cgd@broadcom.com>
1567
1568 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1569 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1570 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1571 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1572 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1573 fields (i.e., add and move commas) so that they more closely
1574 match the MIPS ISA documentation opcode partitioning.
1575
15762002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1577
72f4393d
L		 1578 * mips.igen (ADDI): Print immediate value.
1579 (BREAK): Print code.
1580 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1581 (SLL): Print "nop" specially, and don't run the code
1582 that does the shift for the "nop" case.
20ae0098 1583
9e52972e
FF		 15842001-11-17 Fred Fish <fnf@redhat.com>
1585
1586 * sim-main.h (float_operation): Move enum declaration outside
1587 of _sim_cpu struct declaration.
1588
c0efbca4
JB		 15892001-04-12 Jim Blandy <jimb@redhat.com>
1590
1591 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1592 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1593 set of the FCSR.
1594 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1595 PENDING_FILL, and you can get the intended effect gracefully by
1596 calling PENDING_SCHED directly.
1597
fb891446
BE		 15982001-02-23 Ben Elliston <bje@redhat.com>
1599
1600 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1601 already defined elsewhere.
1602
8030f857
BE		 16032001-02-19 Ben Elliston <bje@redhat.com>
1604
1605 * sim-main.h (sim_monitor): Return an int.
1606 * interp.c (sim_monitor): Add return values.
1607 (signal_exception): Handle error conditions from sim_monitor.
1608
56b48a7a
CD		 16092001-02-08 Ben Elliston <bje@redhat.com>
1610
1611 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1612 (store_memory): Likewise, pass cia to sim_core_write*.
1613
d3ee60d9
FCE		 16142000-10-19 Frank Ch. Eigler <fche@redhat.com>
1615
1616 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1617 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1618
071da002
AC		 1619Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1622 * Makefile.in: Don't delete *.igen when cleaning directory.
1623
a28c02cd
AC		 1624Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * m16.igen (break): Call SignalException not sim_engine_halt.
1627
80ee11fa
AC		 1628Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 From Jason Eckhardt:
1631 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1632
673388c0
AC		 1633Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1634
1635 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1636
4c0deff4
NC		 16372000-05-24 Michael Hayes <mhayes@cygnus.com>
1638
1639 * mips.igen (do_dmultx): Fix typo.
1640
eb2d80b4
AC		 1641Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * configure: Regenerated to track ../common/aclocal.m4 changes.
1644
dd37a34b
AC		 1645Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1648
4c0deff4
NC		 16492000-04-12 Frank Ch. Eigler <fche@redhat.com>
1650
1651 * sim-main.h (GPR_CLEAR): Define macro.
1652
e30db738
AC		 1653Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * interp.c (decode_coproc): Output long using %lx and not %s.
1656
cb7450ea
FCE		 16572000-03-21 Frank Ch. Eigler <fche@redhat.com>
1658
1659 * interp.c (sim_open): Sort & extend dummy memory regions for
1660 --board=jmr3904 for eCos.
1661
a3027dd7
FCE		 16622000-03-02 Frank Ch. Eigler <fche@redhat.com>
1663
1664 * configure: Regenerated.
1665
1666Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1667
1668 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1669 calls, conditional on the simulator being in verbose mode.
1670
dfcd3bfb
JM		 1671Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1672
1673 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1674 cache don't get ReservedInstruction traps.
1675
c2d11a7d
JM		 16761999-11-29 Mark Salter <msalter@cygnus.com>
1677
1678 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1679 to clear status bits in sdisr register. This is how the hardware works.
1680
1681 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1682 being used by cygmon.
1683
4ce44c66
JM		 16841999-11-11 Andrew Haley <aph@cygnus.com>
1685
1686 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1687 instructions.
1688
cff3e48b
JM		 1689Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1690
1691 * mips.igen (MULT): Correct previous mis-applied patch.
1692
d4f3574e
SS		 1693Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1694
1695 * mips.igen (delayslot32): Handle sequence like
1696 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1697 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1698 (MULT): Actually pass the third register...
1699
17001999-09-03 Mark Salter <msalter@cygnus.com>
1701
1702 * interp.c (sim_open): Added more memory aliases for additional
1703 hardware being touched by cygmon on jmr3904 board.
1704
1705Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1708
a0b3c4fd
JM		 1709Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1710
1711 * interp.c (sim_store_register): Handle case where client - GDB -
1712 specifies that a 4 byte register is 8 bytes in size.
1713 (sim_fetch_register): Ditto.
72f4393d 1714
adf40b2e
JM		 17151999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1716
1717 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1718 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1719 (idt_monitor_base): Base address for IDT monitor traps.
1720 (pmon_monitor_base): Ditto for PMON.
1721 (lsipmon_monitor_base): Ditto for LSI PMON.
1722 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1723 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1724 (sim_firmware_command): New function.
1725 (mips_option_handler): Call it for OPTION_FIRMWARE.
1726 (sim_open): Allocate memory for idt_monitor region. If "--board"
1727 option was given, add no monitor by default. Add BREAK hooks only if
1728 monitors are also there.
72f4393d 1729
43e526b9
JM		 1730Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1731
1732 * interp.c (sim_monitor): Flush output before reading input.
1733
1734Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * tconfig.in (SIM_HANDLES_LMA): Always define.
1737
1738Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1739
1740 From Mark Salter <msalter@cygnus.com>:
1741 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1742 (sim_open): Add setup for BSP board.
1743
9846de1b
JM		 1744Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1747 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1748 them as unimplemented.
1749
cd0fc7c3
SS		 17501999-05-08 Felix Lee <flee@cygnus.com>
1751
1752 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1753
7a292a7a
SS		 17541999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1755
1756 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1757
1758Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1759
1760 * configure.in: Any mips64vr5*-*-* target should have
1761 -DTARGET_ENABLE_FR=1.
1762 (default_endian): Any mips64vr*el-*-* target should default to
1763 LITTLE_ENDIAN.
1764 * configure: Re-generate.
1765
17661999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1767
1768 * mips.igen (ldl): Extend from _16_, not 32.
1769
1770Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1771
1772 * interp.c (sim_store_register): Force registers written to by GDB
1773 into an un-interpreted state.
1774
c906108c
SS		 17751999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1776
1777 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1778 CPU, start periodic background I/O polls.
72f4393d 1779 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1780
17811998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1782
1783 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1784
c906108c
SS		 1785Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1786
1787 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1788 case statement.
1789
17901998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1791
1792 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1793 (load_word): Call SIM_CORE_SIGNAL hook on error.
1794 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1795 starting. For exception dispatching, pass PC instead of NULL_CIA.
1796 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1797 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1798 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1799 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1800 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1801 * mips.igen (*): Replace memory-related SignalException* calls
1802 with references to SIM_CORE_SIGNAL hook.
72f4393d 1803
c906108c
SS		 1804 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1805 fix.
1806 * sim-main.c (*): Minor warning cleanups.
72f4393d 1807
c906108c
SS		 18081998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1809
1810 * m16.igen (DADDIU5): Correct type-o.
1811
1812Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1813
1814 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1815 variables.
1816
1817Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1818
1819 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1820 to include path.
1821 (interp.o): Add dependency on itable.h
1822 (oengine.c, gencode): Delete remaining references.
1823 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1824
c906108c 18251998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1826
c906108c
SS		 1827 * vr4run.c: New.
1828 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1829 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1830 tmp-run-hack) : New.
1831 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1832 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1833 Drop the "64" qualifier to get the HACK generator working.
1834 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1835 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1836 qualifier to get the hack generator working.
1837 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1838 (DSLL): Use do_dsll.
1839 (DSLLV): Use do_dsllv.
1840 (DSRA): Use do_dsra.
1841 (DSRL): Use do_dsrl.
1842 (DSRLV): Use do_dsrlv.
1843 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1844 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1845 get the HACK generator working.
1846 (MACC) Rename to get the HACK generator working.
1847 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1848
c906108c
SS		 18491998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1850
1851 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1852 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1853
c906108c
SS		 18541998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1855
1856 * mips/interp.c (DEBUG): Cleanups.
1857
18581998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1859
1860 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1861 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1862
c906108c
SS		 18631998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1864
1865 * interp.c (sim_close): Uninstall modules.
1866
1867Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * sim-main.h, interp.c (sim_monitor): Change to global
1870 function.
1871
1872Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873
1874 * configure.in (vr4100): Only include vr4100 instructions in
1875 simulator.
1876 * configure: Re-generate.
1877 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1878
1879Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1882 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1883 true alternative.
1884
1885 * configure.in (sim_default_gen, sim_use_gen): Replace with
1886 sim_gen.
1887 (--enable-sim-igen): Delete config option. Always using IGEN.
1888 * configure: Re-generate.
72f4393d 1889
c906108c
SS		 1890 * Makefile.in (gencode): Kill, kill, kill.
1891 * gencode.c: Ditto.
72f4393d 1892
c906108c
SS		 1893Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1896 bit mips16 igen simulator.
1897 * configure: Re-generate.
1898
1899 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1900 as part of vr4100 ISA.
1901 * vr.igen: Mark all instructions as 64 bit only.
1902
1903Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1906 Pacify GCC.
1907
1908Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1911 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1912 * configure: Re-generate.
1913
1914 * m16.igen (BREAK): Define breakpoint instruction.
1915 (JALX32): Mark instruction as mips16 and not r3900.
1916 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1917
1918 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1919
1920Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1921
1922 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1923 insn as a debug breakpoint.
1924
1925 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1926 pending.slot_size.
1927 (PENDING_SCHED): Clean up trace statement.
1928 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1929 (PENDING_FILL): Delay write by only one cycle.
1930 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1931
1932 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1933 of pending writes.
1934 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1935 32 & 64.
1936 (pending_tick): Move incrementing of index to FOR statement.
1937 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1938
c906108c
SS		 1939 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1940 build simulator.
1941 * configure: Re-generate.
72f4393d 1942
c906108c
SS		 1943 * interp.c (sim_engine_run OLD): Delete explicit call to
1944 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1945
c906108c
SS		 1946Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1947
1948 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1949 interrupt level number to match changed SignalExceptionInterrupt
1950 macro.
1951
1952Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1953
1954 * interp.c: #include "itable.h" if WITH_IGEN.
1955 (get_insn_name): New function.
1956 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1957 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1958
1959Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1960
1961 * configure: Rebuilt to inhale new common/aclocal.m4.
1962
1963Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1964
1965 * dv-tx3904sio.c: Include sim-assert.h.
1966
1967Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1968
1969 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1970 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1971 Reorganize target-specific sim-hardware checks.
1972 * configure: rebuilt.
1973 * interp.c (sim_open): For tx39 target boards, set
1974 OPERATING_ENVIRONMENT, add tx3904sio devices.
1975 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1976 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1977
c906108c
SS		 1978 * dv-tx3904irc.c: Compiler warning clean-up.
1979 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1980 frequent hw-trace messages.
1981
1982Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1985
1986Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1989
1990 * vr.igen: New file.
1991 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1992 * mips.igen: Define vr4100 model. Include vr.igen.
1993Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1994
1995 * mips.igen (check_mf_hilo): Correct check.
1996
1997Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * sim-main.h (interrupt_event): Add prototype.
2000
2001 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2002 register_ptr, register_value.
2003 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2004
2005 * sim-main.h (tracefh): Make extern.
2006
2007Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2008
2009 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2010 Reduce unnecessarily high timer event frequency.
c906108c 2011 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2012
c906108c
SS		 2013Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2014
2015 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2016 to allay warnings.
2017 (interrupt_event): Made non-static.
72f4393d 2018
c906108c
SS		 2019 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2020 interchange of configuration values for external vs. internal
2021 clock dividers.
72f4393d 2022
c906108c
SS		 2023Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2024
72f4393d 2025 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2026 simulator-reserved break instructions.
2027 * gencode.c (build_instruction): Ditto.
2028 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2029 reserved instructions now use exception vector, rather
c906108c
SS		 2030 than halting sim.
2031 * sim-main.h: Moved magic constants to here.
2032
2033Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2034
2035 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2036 register upon non-zero interrupt event level, clear upon zero
2037 event value.
2038 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2039 by passing zero event value.
2040 (*_io_{read,write}_buffer): Endianness fixes.
2041 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2042 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2043
2044 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2045 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2046
c906108c
SS		 2047Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2048
72f4393d 2049 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2050 and BigEndianCPU.
2051
2052Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2053
2054 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2055 parts.
2056 * configure: Update.
2057
2058Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2059
2060 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2061 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2062 * configure.in: Include tx3904tmr in hw_device list.
2063 * configure: Rebuilt.
2064 * interp.c (sim_open): Instantiate three timer instances.
2065 Fix address typo of tx3904irc instance.
2066
2067Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2068
2069 * interp.c (signal_exception): SystemCall exception now uses
2070 the exception vector.
2071
2072Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2073
2074 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2075 to allay warnings.
2076
2077Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2080
2081Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2084
2085 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2086 sim-main.h. Declare a struct hw_descriptor instead of struct
2087 hw_device_descriptor.
2088
2089Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2092 right bits and then re-align left hand bytes to correct byte
2093 lanes. Fix incorrect computation in do_store_left when loading
2094 bytes from second word.
2095
2096Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2097
2098 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2099 * interp.c (sim_open): Only create a device tree when HW is
2100 enabled.
2101
2102 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2103 * interp.c (signal_exception): Ditto.
2104
2105Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2106
2107 * gencode.c: Mark BEGEZALL as LIKELY.
2108
2109Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2112 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2113
c906108c
SS		 2114Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2115
2116 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2117 modules. Recognize TX39 target with "mips*tx39" pattern.
2118 * configure: Rebuilt.
2119 * sim-main.h (*): Added many macros defining bits in
2120 TX39 control registers.
2121 (SignalInterrupt): Send actual PC instead of NULL.
2122 (SignalNMIReset): New exception type.
2123 * interp.c (board): New variable for future use to identify
2124 a particular board being simulated.
2125 (mips_option_handler,mips_options): Added "--board" option.
2126 (interrupt_event): Send actual PC.
2127 (sim_open): Make memory layout conditional on board setting.
2128 (signal_exception): Initial implementation of hardware interrupt
2129 handling. Accept another break instruction variant for simulator
2130 exit.
2131 (decode_coproc): Implement RFE instruction for TX39.
2132 (mips.igen): Decode RFE instruction as such.
2133 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2134 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2135 bbegin to implement memory map.
2136 * dv-tx3904cpu.c: New file.
2137 * dv-tx3904irc.c: New file.
2138
2139Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2140
2141 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2142
2143Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2144
2145 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2146 with calls to check_div_hilo.
2147
2148Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2149
2150 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2151 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2152 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2153 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2154 with calls to check_mult_hilo.
2155 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2156 with calls to check_div_hilo.
2157
2158Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2159
2160 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2161 Document a replacement.
2162
2163Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2164
2165 * interp.c (sim_monitor): Make mon_printf work.
2166
2167Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2168
2169 * sim-main.h (INSN_NAME): New arg `cpu'.
2170
2171Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2172
72f4393d 2173 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2174
2175Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2176
2177 * configure: Regenerated to track ../common/aclocal.m4 changes.
2178 * config.in: Ditto.
2179
2180Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2181
2182 * acconfig.h: New file.
2183 * configure.in: Reverted change of Apr 24; use sinclude again.
2184
2185Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2186
2187 * configure: Regenerated to track ../common/aclocal.m4 changes.
2188 * config.in: Ditto.
2189
2190Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2191
2192 * configure.in: Don't call sinclude.
2193
2194Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2195
2196 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2197
2198Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * mips.igen (ERET): Implement.
2201
2202 * interp.c (decode_coproc): Return sign-extended EPC.
2203
2204 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2205
2206 * interp.c (signal_exception): Do not ignore Trap.
2207 (signal_exception): On TRAP, restart at exception address.
2208 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2209 (signal_exception): Update.
2210 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2211 so that TRAP instructions are caught.
2212
2213Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2214
2215 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2216 contains HI/LO access history.
2217 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2218 (HIACCESS, LOACCESS): Delete, replace with
2219 (HIHISTORY, LOHISTORY): New macros.
2220 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2221
c906108c
SS		 2222 * gencode.c (build_instruction): Do not generate checks for
2223 correct HI/LO register usage.
2224
2225 * interp.c (old_engine_run): Delete checks for correct HI/LO
2226 register usage.
2227
2228 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2229 check_mf_cycles): New functions.
2230 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2231 do_divu, domultx, do_mult, do_multu): Use.
2232
2233 * tx.igen ("madd", "maddu"): Use.
72f4393d 2234
c906108c
SS		 2235Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * mips.igen (DSRAV): Use function do_dsrav.
2238 (SRAV): Use new function do_srav.
2239
2240 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2241 (B): Sign extend 11 bit immediate.
2242 (EXT-B*): Shift 16 bit immediate left by 1.
2243 (ADDIU*): Don't sign extend immediate value.
2244
2245Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2248
2249 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2250 functions.
2251
2252 * mips.igen (delayslot32, nullify_next_insn): New functions.
2253 (m16.igen): Always include.
2254 (do_*): Add more tracing.
2255
2256 * m16.igen (delayslot16): Add NIA argument, could be called by a
2257 32 bit MIPS16 instruction.
72f4393d 2258
c906108c
SS		 2259 * interp.c (ifetch16): Move function from here.
2260 * sim-main.c (ifetch16): To here.
72f4393d 2261
c906108c
SS		 2262 * sim-main.c (ifetch16, ifetch32): Update to match current
2263 implementations of LH, LW.
2264 (signal_exception): Don't print out incorrect hex value of illegal
2265 instruction.
2266
2267Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2270 instruction.
2271
2272 * m16.igen: Implement MIPS16 instructions.
72f4393d 2273
c906108c
SS		 2274 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2275 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2276 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2277 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2278 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2279 bodies of corresponding code from 32 bit insn to these. Also used
2280 by MIPS16 versions of functions.
72f4393d 2281
c906108c
SS		 2282 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2283 (IMEM16): Drop NR argument from macro.
2284
2285Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * Makefile.in (SIM_OBJS): Add sim-main.o.
2288
2289 * sim-main.h (address_translation, load_memory, store_memory,
2290 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2291 as INLINE_SIM_MAIN.
2292 (pr_addr, pr_uword64): Declare.
2293 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2294
c906108c
SS		 2295 * interp.c (address_translation, load_memory, store_memory,
2296 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2297 from here.
2298 * sim-main.c: To here. Fix compilation problems.
72f4393d 2299
c906108c
SS		 2300 * configure.in: Enable inlining.
2301 * configure: Re-config.
2302
2303Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * configure: Regenerated to track ../common/aclocal.m4 changes.
2306
2307Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * mips.igen: Include tx.igen.
2310 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2311 * tx.igen: New file, contains MADD and MADDU.
2312
2313 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2314 the hardwired constant `7'.
2315 (store_memory): Ditto.
2316 (LOADDRMASK): Move definition to sim-main.h.
2317
2318 mips.igen (MTC0): Enable for r3900.
2319 (ADDU): Add trace.
2320
2321 mips.igen (do_load_byte): Delete.
2322 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2323 do_store_right): New functions.
2324 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2325
2326 configure.in: Let the tx39 use igen again.
2327 configure: Update.
72f4393d 2328
c906108c
SS		 2329Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2332 not an address sized quantity. Return zero for cache sizes.
2333
2334Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * mips.igen (r3900): r3900 does not support 64 bit integer
2337 operations.
2338
2339Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2340
2341 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2342 than igen one.
2343 * configure : Rebuild.
72f4393d 2344
c906108c
SS		 2345Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * configure: Regenerated to track ../common/aclocal.m4 changes.
2348
2349Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2352
2353Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2354
2355 * configure: Regenerated to track ../common/aclocal.m4 changes.
2356 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2357
2358Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2359
2360 * configure: Regenerated to track ../common/aclocal.m4 changes.
2361
2362Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * interp.c (Max, Min): Comment out functions. Not yet used.
2365
2366Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2367
2368 * configure: Regenerated to track ../common/aclocal.m4 changes.
2369
2370Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2371
2372 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2373 configurable settings for stand-alone simulator.
72f4393d 2374
c906108c 2375 * configure.in: Added X11 search, just in case.
72f4393d 2376
c906108c
SS		 2377 * configure: Regenerated.
2378
2379Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * interp.c (sim_write, sim_read, load_memory, store_memory):
2382 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2383
2384Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2385
2386 * sim-main.h (GETFCC): Return an unsigned value.
2387
2388Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2389
2390 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2391 (DADD): Result destination is RD not RT.
2392
2393Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2394
2395 * sim-main.h (HIACCESS, LOACCESS): Always define.
2396
2397 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2398
2399 * interp.c (sim_info): Delete.
2400
2401Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2402
2403 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2404 (mips_option_handler): New argument `cpu'.
2405 (sim_open): Update call to sim_add_option_table.
2406
2407Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2408
2409 * mips.igen (CxC1): Add tracing.
2410
2411Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * sim-main.h (Max, Min): Declare.
2414
2415 * interp.c (Max, Min): New functions.
2416
2417 * mips.igen (BC1): Add tracing.
72f4393d 2418
c906108c 2419Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2420
c906108c 2421 * interp.c Added memory map for stack in vr4100
72f4393d 2422
c906108c
SS		 2423Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2424
2425 * interp.c (load_memory): Add missing "break"'s.
2426
2427Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2428
2429 * interp.c (sim_store_register, sim_fetch_register): Pass in
2430 length parameter. Return -1.
2431
2432Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2433
2434 * interp.c: Added hardware init hook, fixed warnings.
2435
2436Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2439
2440Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * interp.c (ifetch16): New function.
2443
2444 * sim-main.h (IMEM32): Rename IMEM.
2445 (IMEM16_IMMED): Define.
2446 (IMEM16): Define.
2447 (DELAY_SLOT): Update.
72f4393d 2448
c906108c 2449 * m16run.c (sim_engine_run): New file.
72f4393d 2450
c906108c
SS		 2451 * m16.igen: All instructions except LB.
2452 (LB): Call do_load_byte.
2453 * mips.igen (do_load_byte): New function.
2454 (LB): Call do_load_byte.
2455
2456 * mips.igen: Move spec for insn bit size and high bit from here.
2457 * Makefile.in (tmp-igen, tmp-m16): To here.
2458
2459 * m16.dc: New file, decode mips16 instructions.
2460
2461 * Makefile.in (SIM_NO_ALL): Define.
2462 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2463
2464Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2465
2466 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2467 point unit to 32 bit registers.
2468 * configure: Re-generate.
2469
2470Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2471
2472 * configure.in (sim_use_gen): Make IGEN the default simulator
2473 generator for generic 32 and 64 bit mips targets.
2474 * configure: Re-generate.
2475
2476Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2477
2478 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2479 bitsize.
2480
2481 * interp.c (sim_fetch_register, sim_store_register): Read/write
2482 FGR from correct location.
2483 (sim_open): Set size of FGR's according to
2484 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2485
c906108c
SS		 2486 * sim-main.h (FGR): Store floating point registers in a separate
2487 array.
2488
2489Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2490
2491 * configure: Regenerated to track ../common/aclocal.m4 changes.
2492
2493Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2496
2497 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2498
2499 * interp.c (pending_tick): New function. Deliver pending writes.
2500
2501 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2502 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2503 it can handle mixed sized quantites and single bits.
72f4393d 2504
c906108c
SS		 2505Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2506
2507 * interp.c (oengine.h): Do not include when building with IGEN.
2508 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2509 (sim_info): Ditto for PROCESSOR_64BIT.
2510 (sim_monitor): Replace ut_reg with unsigned_word.
2511 (*): Ditto for t_reg.
2512 (LOADDRMASK): Define.
2513 (sim_open): Remove defunct check that host FP is IEEE compliant,
2514 using software to emulate floating point.
2515 (value_fpr, ...): Always compile, was conditional on HASFPU.
2516
2517Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2518
2519 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2520 size.
2521
2522 * interp.c (SD, CPU): Define.
2523 (mips_option_handler): Set flags in each CPU.
2524 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2525 (sim_close): Do not clear STATE, deleted anyway.
2526 (sim_write, sim_read): Assume CPU zero's vm should be used for
2527 data transfers.
2528 (sim_create_inferior): Set the PC for all processors.
2529 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2530 argument.
2531 (mips16_entry): Pass correct nr of args to store_word, load_word.
2532 (ColdReset): Cold reset all cpu's.
2533 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2534 (sim_monitor, load_memory, store_memory, signal_exception): Use
2535 `CPU' instead of STATE_CPU.
2536
2537
2538 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2539 SD or CPU_.
72f4393d 2540
c906108c
SS		 2541 * sim-main.h (signal_exception): Add sim_cpu arg.
2542 (SignalException*): Pass both SD and CPU to signal_exception.
2543 * interp.c (signal_exception): Update.
72f4393d 2544
c906108c
SS		 2545 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2546 Ditto
2547 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2548 address_translation): Ditto
2549 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2550
c906108c
SS		 2551Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2552
2553 * configure: Regenerated to track ../common/aclocal.m4 changes.
2554
2555Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2556
2557 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2558
72f4393d 2559 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2560
2561 * sim-main.h (CPU_CIA): Delete.
2562 (SET_CIA, GET_CIA): Define
2563
2564Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2565
2566 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2567 regiser.
2568
2569 * configure.in (default_endian): Configure a big-endian simulator
2570 by default.
2571 * configure: Re-generate.
72f4393d 2572
c906108c
SS		 2573Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2574
2575 * configure: Regenerated to track ../common/aclocal.m4 changes.
2576
2577Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2578
2579 * interp.c (sim_monitor): Handle Densan monitor outbyte
2580 and inbyte functions.
2581
25821997-12-29 Felix Lee <flee@cygnus.com>
2583
2584 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2585
2586Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2587
2588 * Makefile.in (tmp-igen): Arrange for $zero to always be
2589 reset to zero after every instruction.
2590
2591Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * configure: Regenerated to track ../common/aclocal.m4 changes.
2594 * config.in: Ditto.
2595
2596Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2597
2598 * mips.igen (MSUB): Fix to work like MADD.
2599 * gencode.c (MSUB): Similarly.
2600
2601Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2602
2603 * configure: Regenerated to track ../common/aclocal.m4 changes.
2604
2605Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2606
2607 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2608
2609Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2610
2611 * sim-main.h (sim-fpu.h): Include.
2612
2613 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2614 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2615 using host independant sim_fpu module.
2616
2617Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618
2619 * interp.c (signal_exception): Report internal errors with SIGABRT
2620 not SIGQUIT.
2621
2622 * sim-main.h (C0_CONFIG): New register.
2623 (signal.h): No longer include.
2624
2625 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2626
2627Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2628
2629 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2630
2631Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * mips.igen: Tag vr5000 instructions.
2634 (ANDI): Was missing mipsIV model, fix assembler syntax.
2635 (do_c_cond_fmt): New function.
2636 (C.cond.fmt): Handle mips I-III which do not support CC field
2637 separatly.
2638 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2639 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2640 in IV3.2 spec.
2641 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2642 vr5000 which saves LO in a GPR separatly.
72f4393d 2643
c906108c
SS		 2644 * configure.in (enable-sim-igen): For vr5000, select vr5000
2645 specific instructions.
2646 * configure: Re-generate.
72f4393d 2647
c906108c
SS		 2648Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649
2650 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2651
2652 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2653 fmt_uninterpreted_64 bit cases to switch. Convert to
2654 fmt_formatted,
2655
2656 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2657
2658 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2659 as specified in IV3.2 spec.
2660 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2661
2662Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2663
2664 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2665 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2666 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2667 PENDING_FILL versions of instructions. Simplify.
2668 (X): New function.
2669 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2670 instructions.
2671 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2672 a signed value.
2673 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2674
c906108c
SS		 2675 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2676 global.
2677 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2678
2679Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * gencode.c (build_mips16_operands): Replace IPC with cia.
2682
2683 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2684 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2685 IPC to `cia'.
2686 (UndefinedResult): Replace function with macro/function
2687 combination.
2688 (sim_engine_run): Don't save PC in IPC.
2689
2690 * sim-main.h (IPC): Delete.
2691
2692
2693 * interp.c (signal_exception, store_word, load_word,
2694 address_translation, load_memory, store_memory, cache_op,
2695 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2696 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2697 current instruction address - cia - argument.
2698 (sim_read, sim_write): Call address_translation directly.
2699 (sim_engine_run): Rename variable vaddr to cia.
2700 (signal_exception): Pass cia to sim_monitor
72f4393d 2701
c906108c
SS		 2702 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2703 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2704 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2705
2706 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2707 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2708 SIM_ASSERT.
72f4393d 2709
c906108c
SS		 2710 * interp.c (signal_exception): Pass restart address to
2711 sim_engine_restart.
2712
2713 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2714 idecode.o): Add dependency.
2715
2716 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2717 Delete definitions
2718 (DELAY_SLOT): Update NIA not PC with branch address.
2719 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2720
2721 * mips.igen: Use CIA not PC in branch calculations.
2722 (illegal): Call SignalException.
2723 (BEQ, ADDIU): Fix assembler.
2724
2725Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2726
2727 * m16.igen (JALX): Was missing.
2728
2729 * configure.in (enable-sim-igen): New configuration option.
2730 * configure: Re-generate.
72f4393d 2731
c906108c
SS		 2732 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2733
2734 * interp.c (load_memory, store_memory): Delete parameter RAW.
2735 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2736 bypassing {load,store}_memory.
2737
2738 * sim-main.h (ByteSwapMem): Delete definition.
2739
2740 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2741
2742 * interp.c (sim_do_command, sim_commands): Delete mips specific
2743 commands. Handled by module sim-options.
72f4393d 2744
c906108c
SS		 2745 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2746 (WITH_MODULO_MEMORY): Define.
2747
2748 * interp.c (sim_info): Delete code printing memory size.
2749
2750 * interp.c (mips_size): Nee sim_size, delete function.
2751 (power2): Delete.
2752 (monitor, monitor_base, monitor_size): Delete global variables.
2753 (sim_open, sim_close): Delete code creating monitor and other
2754 memory regions. Use sim-memopts module, via sim_do_commandf, to
2755 manage memory regions.
2756 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2757
c906108c
SS		 2758 * interp.c (address_translation): Delete all memory map code
2759 except line forcing 32 bit addresses.
2760
2761Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2762
2763 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2764 trace options.
2765
2766 * interp.c (logfh, logfile): Delete globals.
2767 (sim_open, sim_close): Delete code opening & closing log file.
2768 (mips_option_handler): Delete -l and -n options.
2769 (OPTION mips_options): Ditto.
2770
2771 * interp.c (OPTION mips_options): Rename option trace to dinero.
2772 (mips_option_handler): Update.
2773
2774Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775
2776 * interp.c (fetch_str): New function.
2777 (sim_monitor): Rewrite using sim_read & sim_write.
2778 (sim_open): Check magic number.
2779 (sim_open): Write monitor vectors into memory using sim_write.
2780 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2781 (sim_read, sim_write): Simplify - transfer data one byte at a
2782 time.
2783 (load_memory, store_memory): Clarify meaning of parameter RAW.
2784
2785 * sim-main.h (isHOST): Defete definition.
2786 (isTARGET): Mark as depreciated.
2787 (address_translation): Delete parameter HOST.
2788
2789 * interp.c (address_translation): Delete parameter HOST.
2790
2791Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2792
72f4393d 2793 * mips.igen:
c906108c
SS		 2794
2795 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2796 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2797
2798Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2799
2800 * mips.igen: Add model filter field to records.
2801
2802Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2805
c906108c
SS		 2806 interp.c (sim_engine_run): Do not compile function sim_engine_run
2807 when WITH_IGEN == 1.
2808
2809 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2810 target architecture.
2811
2812 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2813 igen. Replace with configuration variables sim_igen_flags /
2814 sim_m16_flags.
2815
2816 * m16.igen: New file. Copy mips16 insns here.
2817 * mips.igen: From here.
2818
2819Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2820
2821 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2822 to top.
2823 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2824
2825Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2826
2827 * gencode.c (build_instruction): Follow sim_write's lead in using
2828 BigEndianMem instead of !ByteSwapMem.
2829
2830Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2831
2832 * configure.in (sim_gen): Dependent on target, select type of
2833 generator. Always select old style generator.
2834
2835 configure: Re-generate.
2836
2837 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2838 targets.
2839 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2840 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2841 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2842 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2843 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2844
c906108c
SS		 2845Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2846
2847 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2848
2849 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2850 CURRENT_FLOATING_POINT instead.
2851
2852 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2853 (address_translation): Raise exception InstructionFetch when
2854 translation fails and isINSTRUCTION.
72f4393d 2855
c906108c
SS		 2856 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2857 sim_engine_run): Change type of of vaddr and paddr to
2858 address_word.
2859 (address_translation, prefetch, load_memory, store_memory,
2860 cache_op): Change type of vAddr and pAddr to address_word.
2861
2862 * gencode.c (build_instruction): Change type of vaddr and paddr to
2863 address_word.
2864
2865Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866
2867 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2868 macro to obtain result of ALU op.
2869
2870Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871
2872 * interp.c (sim_info): Call profile_print.
2873
2874Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2877
2878 * sim-main.h (WITH_PROFILE): Do not define, defined in
2879 common/sim-config.h. Use sim-profile module.
2880 (simPROFILE): Delete defintion.
2881
2882 * interp.c (PROFILE): Delete definition.
2883 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2884 (sim_close): Delete code writing profile histogram.
2885 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2886 Delete.
2887 (sim_engine_run): Delete code profiling the PC.
2888
2889Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2890
2891 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2892
2893 * interp.c (sim_monitor): Make register pointers of type
2894 unsigned_word*.
2895
2896 * sim-main.h: Make registers of type unsigned_word not
2897 signed_word.
2898
2899Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2900
2901 * interp.c (sync_operation): Rename from SyncOperation, make
2902 global, add SD argument.
2903 (prefetch): Rename from Prefetch, make global, add SD argument.
2904 (decode_coproc): Make global.
2905
2906 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2907
2908 * gencode.c (build_instruction): Generate DecodeCoproc not
2909 decode_coproc calls.
2910
2911 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2912 (SizeFGR): Move to sim-main.h
2913 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2914 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2915 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2916 sim-main.h.
2917 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2918 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2919 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2920 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2921 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2922 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2923
c906108c
SS		 2924 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2925 exception.
2926 (sim-alu.h): Include.
2927 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2928 (sim_cia): Typedef to instruction_address.
72f4393d 2929
c906108c
SS		 2930Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * Makefile.in (interp.o): Rename generated file engine.c to
2933 oengine.c.
72f4393d 2934
c906108c 2935 * interp.c: Update.
72f4393d 2936
c906108c
SS		 2937Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2938
2939 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2940
c906108c
SS		 2941Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2942
2943 * gencode.c (build_instruction): For "FPSQRT", output correct
2944 number of arguments to Recip.
72f4393d 2945
c906108c
SS		 2946Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2947
2948 * Makefile.in (interp.o): Depends on sim-main.h
2949
2950 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2951
2952 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2953 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2954 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2955 STATE, DSSTATE): Define
2956 (GPR, FGRIDX, ..): Define.
2957
2958 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2959 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2960 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2961
c906108c 2962 * interp.c: Update names to match defines from sim-main.h
72f4393d 2963
c906108c
SS		 2964Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * interp.c (sim_monitor): Add SD argument.
2967 (sim_warning): Delete. Replace calls with calls to
2968 sim_io_eprintf.
2969 (sim_error): Delete. Replace calls with sim_io_error.
2970 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2971 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2972 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2973 argument.
2974 (mips_size): Rename from sim_size. Add SD argument.
2975
2976 * interp.c (simulator): Delete global variable.
2977 (callback): Delete global variable.
2978 (mips_option_handler, sim_open, sim_write, sim_read,
2979 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2980 sim_size,sim_monitor): Use sim_io_* not callback->*.
2981 (sim_open): ZALLOC simulator struct.
2982 (PROFILE): Do not define.
2983
2984Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2985
2986 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2987 support.h with corresponding code.
2988
2989 * sim-main.h (word64, uword64), support.h: Move definition to
2990 sim-main.h.
2991 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2992
2993 * support.h: Delete
2994 * Makefile.in: Update dependencies
2995 * interp.c: Do not include.
72f4393d 2996
c906108c
SS		 2997Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998
2999 * interp.c (address_translation, load_memory, store_memory,
3000 cache_op): Rename to from AddressTranslation et.al., make global,
3001 add SD argument
72f4393d 3002
c906108c
SS		 3003 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3004 CacheOp): Define.
72f4393d 3005
c906108c
SS		 3006 * interp.c (SignalException): Rename to signal_exception, make
3007 global.
3008
3009 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3010
c906108c
SS		 3011 * sim-main.h (SignalException, SignalExceptionInterrupt,
3012 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3013 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3014 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3015 Define.
72f4393d 3016
c906108c 3017 * interp.c, support.h: Use.
72f4393d 3018
c906108c
SS		 3019Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3020
3021 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3022 to value_fpr / store_fpr. Add SD argument.
3023 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3024 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3025
3026 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3027
c906108c
SS		 3028Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3029
3030 * interp.c (sim_engine_run): Check consistency between configure
3031 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3032 and HASFPU.
3033
3034 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3035 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3036 (mips_endian): Configure WITH_TARGET_ENDIAN.
3037 * configure: Update.
3038
3039Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * configure: Regenerated to track ../common/aclocal.m4 changes.
3042
3043Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3044
3045 * configure: Regenerated.
3046
3047Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3048
3049 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3050
3051Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3052
3053 * gencode.c (print_igen_insn_models): Assume certain architectures
3054 include all mips* instructions.
3055 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3056 instruction.
3057
3058 * Makefile.in (tmp.igen): Add target. Generate igen input from
3059 gencode file.
3060
3061 * gencode.c (FEATURE_IGEN): Define.
3062 (main): Add --igen option. Generate output in igen format.
3063 (process_instructions): Format output according to igen option.
3064 (print_igen_insn_format): New function.
3065 (print_igen_insn_models): New function.
3066 (process_instructions): Only issue warnings and ignore
3067 instructions when no FEATURE_IGEN.
3068
3069Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3070
3071 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3072 MIPS targets.
3073
3074Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3075
3076 * configure: Regenerated to track ../common/aclocal.m4 changes.
3077
3078Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3081 SIM_RESERVED_BITS): Delete, moved to common.
3082 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3083
c906108c
SS		 3084Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3085
3086 * configure.in: Configure non-strict memory alignment.
3087 * configure: Regenerated to track ../common/aclocal.m4 changes.
3088
3089Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3090
3091 * configure: Regenerated to track ../common/aclocal.m4 changes.
3092
3093Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3094
3095 * gencode.c (SDBBP,DERET): Added (3900) insns.
3096 (RFE): Turn on for 3900.
3097 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3098 (dsstate): Made global.
3099 (SUBTARGET_R3900): Added.
3100 (CANCELDELAYSLOT): New.
3101 (SignalException): Ignore SystemCall rather than ignore and
3102 terminate. Add DebugBreakPoint handling.
3103 (decode_coproc): New insns RFE, DERET; and new registers Debug
3104 and DEPC protected by SUBTARGET_R3900.
3105 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3106 bits explicitly.
3107 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3108 * configure: Update.
c906108c
SS		 3109
3110Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3111
3112 * gencode.c: Add r3900 (tx39).
72f4393d 3113
c906108c
SS		 3114
3115Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3116
3117 * gencode.c (build_instruction): Don't need to subtract 4 for
3118 JALR, just 2.
3119
3120Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3121
3122 * interp.c: Correct some HASFPU problems.
3123
3124Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3125
3126 * configure: Regenerated to track ../common/aclocal.m4 changes.
3127
3128Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * interp.c (mips_options): Fix samples option short form, should
3131 be `x'.
3132
3133Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3134
3135 * interp.c (sim_info): Enable info code. Was just returning.
3136
3137Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3140 MFC0.
3141
3142Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3143
3144 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3145 constants.
3146 (build_instruction): Ditto for LL.
3147
3148Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3149
3150 * configure: Regenerated to track ../common/aclocal.m4 changes.
3151
3152Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3153
3154 * configure: Regenerated to track ../common/aclocal.m4 changes.
3155 * config.in: Ditto.
3156
3157Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3158
3159 * interp.c (sim_open): Add call to sim_analyze_program, update
3160 call to sim_config.
3161
3162Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3163
3164 * interp.c (sim_kill): Delete.
3165 (sim_create_inferior): Add ABFD argument. Set PC from same.
3166 (sim_load): Move code initializing trap handlers from here.
3167 (sim_open): To here.
3168 (sim_load): Delete, use sim-hload.c.
3169
3170 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3171
3172Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3173
3174 * configure: Regenerated to track ../common/aclocal.m4 changes.
3175 * config.in: Ditto.
3176
3177Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3178
3179 * interp.c (sim_open): Add ABFD argument.
3180 (sim_load): Move call to sim_config from here.
3181 (sim_open): To here. Check return status.
3182
3183Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3184
c906108c
SS		 3185 * gencode.c (build_instruction): Two arg MADD should
3186 not assign result to $0.
72f4393d 3187
c906108c
SS		 3188Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3189
3190 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3191 * sim/mips/configure.in: Regenerate.
3192
3193Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3194
3195 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3196 signed8, unsigned8 et.al. types.
3197
3198 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3199 hosts when selecting subreg.
3200
3201Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3202
3203 * interp.c (sim_engine_run): Reset the ZERO register to zero
3204 regardless of FEATURE_WARN_ZERO.
3205 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3206
3207Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3208
3209 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3210 (SignalException): For BreakPoints ignore any mode bits and just
3211 save the PC.
3212 (SignalException): Always set the CAUSE register.
3213
3214Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3215
3216 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3217 exception has been taken.
3218
3219 * interp.c: Implement the ERET and mt/f sr instructions.
3220
3221Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3222
3223 * interp.c (SignalException): Don't bother restarting an
3224 interrupt.
3225
3226Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3227
3228 * interp.c (SignalException): Really take an interrupt.
3229 (interrupt_event): Only deliver interrupts when enabled.
3230
3231Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3232
3233 * interp.c (sim_info): Only print info when verbose.
3234 (sim_info) Use sim_io_printf for output.
72f4393d 3235
c906108c
SS		 3236Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3237
3238 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3239 mips architectures.
3240
3241Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3242
3243 * interp.c (sim_do_command): Check for common commands if a
3244 simulator specific command fails.
3245
3246Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3247
3248 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3249 and simBE when DEBUG is defined.
3250
3251Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3252
3253 * interp.c (interrupt_event): New function. Pass exception event
3254 onto exception handler.
3255
3256 * configure.in: Check for stdlib.h.
3257 * configure: Regenerate.
3258
3259 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3260 variable declaration.
3261 (build_instruction): Initialize memval1.
3262 (build_instruction): Add UNUSED attribute to byte, bigend,
3263 reverse.
3264 (build_operands): Ditto.
3265
3266 * interp.c: Fix GCC warnings.
3267 (sim_get_quit_code): Delete.
3268
3269 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3270 * Makefile.in: Ditto.
3271 * configure: Re-generate.
72f4393d 3272
c906108c
SS		 3273 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3274
3275Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3276
3277 * interp.c (mips_option_handler): New function parse argumes using
3278 sim-options.
3279 (myname): Replace with STATE_MY_NAME.
3280 (sim_open): Delete check for host endianness - performed by
3281 sim_config.
3282 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3283 (sim_open): Move much of the initialization from here.
3284 (sim_load): To here. After the image has been loaded and
3285 endianness set.
3286 (sim_open): Move ColdReset from here.
3287 (sim_create_inferior): To here.
3288 (sim_open): Make FP check less dependant on host endianness.
3289
3290 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3291 run.
3292 * interp.c (sim_set_callbacks): Delete.
3293
3294 * interp.c (membank, membank_base, membank_size): Replace with
3295 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3296 (sim_open): Remove call to callback->init. gdb/run do this.
3297
3298 * interp.c: Update
3299
3300 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3301
3302 * interp.c (big_endian_p): Delete, replaced by
3303 current_target_byte_order.
3304
3305Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3306
3307 * interp.c (host_read_long, host_read_word, host_swap_word,
3308 host_swap_long): Delete. Using common sim-endian.
3309 (sim_fetch_register, sim_store_register): Use H2T.
3310 (pipeline_ticks): Delete. Handled by sim-events.
3311 (sim_info): Update.
3312 (sim_engine_run): Update.
3313
3314Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3315
3316 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3317 reason from here.
3318 (SignalException): To here. Signal using sim_engine_halt.
3319 (sim_stop_reason): Delete, moved to common.
72f4393d 3320
c906108c
SS		 3321Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3322
3323 * interp.c (sim_open): Add callback argument.
3324 (sim_set_callbacks): Delete SIM_DESC argument.
3325 (sim_size): Ditto.
3326
3327Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * Makefile.in (SIM_OBJS): Add common modules.
3330
3331 * interp.c (sim_set_callbacks): Also set SD callback.
3332 (set_endianness, xfer_*, swap_*): Delete.
3333 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3334 Change to functions using sim-endian macros.
3335 (control_c, sim_stop): Delete, use common version.
3336 (simulate): Convert into.
3337 (sim_engine_run): This function.
3338 (sim_resume): Delete.
72f4393d 3339
c906108c
SS		 3340 * interp.c (simulation): New variable - the simulator object.
3341 (sim_kind): Delete global - merged into simulation.
3342 (sim_load): Cleanup. Move PC assignment from here.
3343 (sim_create_inferior): To here.
3344
3345 * sim-main.h: New file.
3346 * interp.c (sim-main.h): Include.
72f4393d 3347
c906108c
SS		 3348Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3349
3350 * configure: Regenerated to track ../common/aclocal.m4 changes.
3351
3352Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3353
3354 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3355
3356Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3357
72f4393d
L		 3358 * gencode.c (build_instruction): DIV instructions: check
3359 for division by zero and integer overflow before using
c906108c
SS		 3360 host's division operation.
3361
3362Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3363
3364 * Makefile.in (SIM_OBJS): Add sim-load.o.
3365 * interp.c: #include bfd.h.
3366 (target_byte_order): Delete.
3367 (sim_kind, myname, big_endian_p): New static locals.
3368 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3369 after argument parsing. Recognize -E arg, set endianness accordingly.
3370 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3371 load file into simulator. Set PC from bfd.
3372 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3373 (set_endianness): Use big_endian_p instead of target_byte_order.
3374
3375Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3376
3377 * interp.c (sim_size): Delete prototype - conflicts with
3378 definition in remote-sim.h. Correct definition.
3379
3380Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3381
3382 * configure: Regenerated to track ../common/aclocal.m4 changes.
3383 * config.in: Ditto.
3384
3385Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3386
3387 * interp.c (sim_open): New arg `kind'.
3388
3389 * configure: Regenerated to track ../common/aclocal.m4 changes.
3390
3391Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3392
3393 * configure: Regenerated to track ../common/aclocal.m4 changes.
3394
3395Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3396
3397 * interp.c (sim_open): Set optind to 0 before calling getopt.
3398
3399Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3400
3401 * configure: Regenerated to track ../common/aclocal.m4 changes.
3402
3403Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3404
3405 * interp.c : Replace uses of pr_addr with pr_uword64
3406 where the bit length is always 64 independent of SIM_ADDR.
3407 (pr_uword64) : added.
3408
3409Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3410
3411 * configure: Re-generate.
3412
3413Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3414
3415 * configure: Regenerate to track ../common/aclocal.m4 changes.
3416
3417Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3418
3419 * interp.c (sim_open): New SIM_DESC result. Argument is now
3420 in argv form.
3421 (other sim_*): New SIM_DESC argument.
3422
3423Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3424
3425 * interp.c: Fix printing of addresses for non-64-bit targets.
3426 (pr_addr): Add function to print address based on size.
3427
3428Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3429
3430 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3431
3432Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3433
3434 * gencode.c (build_mips16_operands): Correct computation of base
3435 address for extended PC relative instruction.
3436
3437Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3438
3439 * interp.c (mips16_entry): Add support for floating point cases.
3440 (SignalException): Pass floating point cases to mips16_entry.
3441 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3442 registers.
3443 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3444 or fmt_word.
3445 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3446 and then set the state to fmt_uninterpreted.
3447 (COP_SW): Temporarily set the state to fmt_word while calling
3448 ValueFPR.
3449
3450Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3451
3452 * gencode.c (build_instruction): The high order may be set in the
3453 comparison flags at any ISA level, not just ISA 4.
3454
3455Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3456
3457 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3458 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3459 * configure.in: sinclude ../common/aclocal.m4.
3460 * configure: Regenerated.
3461
3462Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3463
3464 * configure: Rebuild after change to aclocal.m4.
3465
3466Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3467
3468 * configure configure.in Makefile.in: Update to new configure
3469 scheme which is more compatible with WinGDB builds.
3470 * configure.in: Improve comment on how to run autoconf.
3471 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3472 * Makefile.in: Use autoconf substitution to install common
3473 makefile fragment.
3474
3475Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3476
3477 * gencode.c (build_instruction): Use BigEndianCPU instead of
3478 ByteSwapMem.
3479
3480Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3481
3482 * interp.c (sim_monitor): Make output to stdout visible in
3483 wingdb's I/O log window.
3484
3485Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3486
3487 * support.h: Undo previous change to SIGTRAP
3488 and SIGQUIT values.
3489
3490Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3491
3492 * interp.c (store_word, load_word): New static functions.
3493 (mips16_entry): New static function.
3494 (SignalException): Look for mips16 entry and exit instructions.
3495 (simulate): Use the correct index when setting fpr_state after
3496 doing a pending move.
3497
3498Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3499
3500 * interp.c: Fix byte-swapping code throughout to work on
3501 both little- and big-endian hosts.
3502
3503Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3504
3505 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3506 with gdb/config/i386/xm-windows.h.
3507
3508Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3509
3510 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3511 that messes up arithmetic shifts.
3512
3513Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3514
3515 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3516 SIGTRAP and SIGQUIT for _WIN32.
3517
3518Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3519
3520 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3521 force a 64 bit multiplication.
3522 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3523 destination register is 0, since that is the default mips16 nop
3524 instruction.
3525
3526Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3527
3528 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3529 (build_endian_shift): Don't check proc64.
3530 (build_instruction): Always set memval to uword64. Cast op2 to
3531 uword64 when shifting it left in memory instructions. Always use
3532 the same code for stores--don't special case proc64.
3533
3534 * gencode.c (build_mips16_operands): Fix base PC value for PC
3535 relative operands.
3536 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3537 jal instruction.
3538 * interp.c (simJALDELAYSLOT): Define.
3539 (JALDELAYSLOT): Define.
3540 (INDELAYSLOT, INJALDELAYSLOT): Define.
3541 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3542
3543Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3544
3545 * interp.c (sim_open): add flush_cache as a PMON routine
3546 (sim_monitor): handle flush_cache by ignoring it
3547
3548Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3549
3550 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3551 BigEndianMem.
3552 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3553 (BigEndianMem): Rename to ByteSwapMem and change sense.
3554 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3555 BigEndianMem references to !ByteSwapMem.
3556 (set_endianness): New function, with prototype.
3557 (sim_open): Call set_endianness.
3558 (sim_info): Use simBE instead of BigEndianMem.
3559 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3560 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3561 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3562 ifdefs, keeping the prototype declaration.
3563 (swap_word): Rewrite correctly.
3564 (ColdReset): Delete references to CONFIG. Delete endianness related
3565 code; moved to set_endianness.
72f4393d 3566
c906108c
SS		 3567Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3568
3569 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3570 * interp.c (CHECKHILO): Define away.
3571 (simSIGINT): New macro.
3572 (membank_size): Increase from 1MB to 2MB.
3573 (control_c): New function.
3574 (sim_resume): Rename parameter signal to signal_number. Add local
3575 variable prev. Call signal before and after simulate.
3576 (sim_stop_reason): Add simSIGINT support.
3577 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3578 functions always.
3579 (sim_warning): Delete call to SignalException. Do call printf_filtered
3580 if logfh is NULL.
3581 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3582 a call to sim_warning.
3583
3584Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3585
3586 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3587 16 bit instructions.
3588
3589Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3590
3591 Add support for mips16 (16 bit MIPS implementation):
3592 * gencode.c (inst_type): Add mips16 instruction encoding types.
3593 (GETDATASIZEINSN): Define.
3594 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3595 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3596 mtlo.
3597 (MIPS16_DECODE): New table, for mips16 instructions.
3598 (bitmap_val): New static function.
3599 (struct mips16_op): Define.
3600 (mips16_op_table): New table, for mips16 operands.
3601 (build_mips16_operands): New static function.
3602 (process_instructions): If PC is odd, decode a mips16
3603 instruction. Break out instruction handling into new
3604 build_instruction function.
3605 (build_instruction): New static function, broken out of
3606 process_instructions. Check modifiers rather than flags for SHIFT
3607 bit count and m[ft]{hi,lo} direction.
3608 (usage): Pass program name to fprintf.
3609 (main): Remove unused variable this_option_optind. Change
3610 ``*loptarg++'' to ``loptarg++''.
3611 (my_strtoul): Parenthesize && within ||.
3612 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3613 (simulate): If PC is odd, fetch a 16 bit instruction, and
3614 increment PC by 2 rather than 4.
3615 * configure.in: Add case for mips16*-*-*.
3616 * configure: Rebuild.
3617
3618Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3619
3620 * interp.c: Allow -t to enable tracing in standalone simulator.
3621 Fix garbage output in trace file and error messages.
3622
3623Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3624
3625 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3626 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3627 * configure.in: Simplify using macros in ../common/aclocal.m4.
3628 * configure: Regenerated.
3629 * tconfig.in: New file.
3630
3631Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3632
3633 * interp.c: Fix bugs in 64-bit port.
3634 Use ansi function declarations for msvc compiler.
3635 Initialize and test file pointer in trace code.
3636 Prevent duplicate definition of LAST_EMED_REGNUM.
3637
3638Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3639
3640 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3641
3642Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3643
3644 * interp.c (SignalException): Check for explicit terminating
3645 breakpoint value.
3646 * gencode.c: Pass instruction value through SignalException()
3647 calls for Trap, Breakpoint and Syscall.
3648
3649Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3650
3651 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3652 only used on those hosts that provide it.
3653 * configure.in: Add sqrt() to list of functions to be checked for.
3654 * config.in: Re-generated.
3655 * configure: Re-generated.
3656
3657Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3658
3659 * gencode.c (process_instructions): Call build_endian_shift when
3660 expanding STORE RIGHT, to fix swr.
3661 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3662 clear the high bits.
3663 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3664 Fix float to int conversions to produce signed values.
3665
3666Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3667
3668 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3669 (process_instructions): Correct handling of nor instruction.
3670 Correct shift count for 32 bit shift instructions. Correct sign
3671 extension for arithmetic shifts to not shift the number of bits in
3672 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3673 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3674 Fix madd.
3675 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3676 It's OK to have a mult follow a mult. What's not OK is to have a
3677 mult follow an mfhi.
3678 (Convert): Comment out incorrect rounding code.
3679
3680Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3681
3682 * interp.c (sim_monitor): Improved monitor printf
3683 simulation. Tidied up simulator warnings, and added "--log" option
3684 for directing warning message output.
3685 * gencode.c: Use sim_warning() rather than WARNING macro.
3686
3687Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3688
3689 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3690 getopt1.o, rather than on gencode.c. Link objects together.
3691 Don't link against -liberty.
3692 (gencode.o, getopt.o, getopt1.o): New targets.
3693 * gencode.c: Include <ctype.h> and "ansidecl.h".
3694 (AND): Undefine after including "ansidecl.h".
3695 (ULONG_MAX): Define if not defined.
3696 (OP_*): Don't define macros; now defined in opcode/mips.h.
3697 (main): Call my_strtoul rather than strtoul.
3698 (my_strtoul): New static function.
3699
3700Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3701
3702 * gencode.c (process_instructions): Generate word64 and uword64
3703 instead of `long long' and `unsigned long long' data types.
3704 * interp.c: #include sysdep.h to get signals, and define default
3705 for SIGBUS.
3706 * (Convert): Work around for Visual-C++ compiler bug with type
3707 conversion.
3708 * support.h: Make things compile under Visual-C++ by using
3709 __int64 instead of `long long'. Change many refs to long long
3710 into word64/uword64 typedefs.
3711
3712Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3713
72f4393d
L		 3714 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3715 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3716 (docdir): Removed.
3717 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3718 (AC_PROG_INSTALL): Added.
c906108c 3719 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3720 * configure: Rebuilt.
3721
c906108c
SS		 3722Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3723
3724 * configure.in: Define @SIMCONF@ depending on mips target.
3725 * configure: Rebuild.
3726 * Makefile.in (run): Add @SIMCONF@ to control simulator
3727 construction.
3728 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3729 * interp.c: Remove some debugging, provide more detailed error
3730 messages, update memory accesses to use LOADDRMASK.
72f4393d 3731
c906108c
SS		 3732Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3733
3734 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3735 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3736 stamp-h.
3737 * configure: Rebuild.
3738 * config.in: New file, generated by autoheader.
3739 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3740 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3741 HAVE_ANINT and HAVE_AINT, as appropriate.
3742 * Makefile.in (run): Use @LIBS@ rather than -lm.
3743 (interp.o): Depend upon config.h.
3744 (Makefile): Just rebuild Makefile.
3745 (clean): Remove stamp-h.
3746 (mostlyclean): Make the same as clean, not as distclean.
3747 (config.h, stamp-h): New targets.
3748
3749Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3750
3751 * interp.c (ColdReset): Fix boolean test. Make all simulator
3752 globals static.
3753
3754Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3755
3756 * interp.c (xfer_direct_word, xfer_direct_long,
3757 swap_direct_word, swap_direct_long, xfer_big_word,
3758 xfer_big_long, xfer_little_word, xfer_little_long,
3759 swap_word,swap_long): Added.
3760 * interp.c (ColdReset): Provide function indirection to
3761 host<->simulated_target transfer routines.
3762 * interp.c (sim_store_register, sim_fetch_register): Updated to
3763 make use of indirected transfer routines.
3764
3765Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3766
3767 * gencode.c (process_instructions): Ensure FP ABS instruction
3768 recognised.
3769 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3770 system call support.
3771
3772Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3773
3774 * interp.c (sim_do_command): Complain if callback structure not
3775 initialised.
3776
3777Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3778
3779 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3780 support for Sun hosts.
3781 * Makefile.in (gencode): Ensure the host compiler and libraries
3782 used for cross-hosted build.
3783
3784Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3785
3786 * interp.c, gencode.c: Some more (TODO) tidying.
3787
3788Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3789
3790 * gencode.c, interp.c: Replaced explicit long long references with
3791 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3792 * support.h (SET64LO, SET64HI): Macros added.
3793
3794Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3795
3796 * configure: Regenerate with autoconf 2.7.
3797
3798Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3799
3800 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3801 * support.h: Remove superfluous "1" from #if.
3802 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3803
3804Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3805
3806 * interp.c (StoreFPR): Control UndefinedResult() call on
3807 WARN_RESULT manifest.
3808
3809Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3810
3811 * gencode.c: Tidied instruction decoding, and added FP instruction
3812 support.
3813
3814 * interp.c: Added dineroIII, and BSD profiling support. Also
3815 run-time FP handling.
3816
3817Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3818
3819 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3820 gencode.c, interp.c, support.h: created.
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