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sim: clean up bfd_vma printing
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
adbaa7b8
MF		 12021-05-01 Mike Frysinger <vapier@gentoo.org>
2
3 * cp1.c (store_fcr): Mark static.
4
fe348617
MF		 52021-05-01 Mike Frysinger <vapier@gentoo.org>
6
7 * config.in, configure: Regenerate.
8
9d903352
MF		 92021-04-23 Mike Frysinger <vapier@gentoo.org>
10
11 * configure.ac (hw_enabled): Delete.
12 (SIM_AC_OPTION_HARDWARE): Delete first two args.
13 * configure: Regenerate.
14
19f6a43c
TT		 152021-04-22 Tom Tromey <tom@tromey.com>
16
17 * configure, config.in: Rebuild.
18
e7d8f1da
TT		 192021-04-22 Tom Tromey <tom@tromey.com>
20
21 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
22 Remove.
23 (SIM_EXTRA_DEPS): New variable.
24
efd82ac7
TT		 252021-04-22 Tom Tromey <tom@tromey.com>
26
27 * configure: Rebuild.
28
2662c237
MF		 292021-04-21 Mike Frysinger <vapier@gentoo.org>
30
31 * aclocal.m4: Regenerate.
32
1f195bc3
SM		 332021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
34
35 * configure: Regenerate.
36
37e9f182
MF		 372021-04-18 Mike Frysinger <vapier@gentoo.org>
38
39 * configure: Regenerate.
40
d5a71b11
MF		 412021-04-12 Mike Frysinger <vapier@gentoo.org>
42
43 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
44
2b8d134b
SM		 452021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
46
47 * Makefile.in: Set ASAN_OPTIONS when running igen.
48
5c6f091a
FS		 492021-04-04 Steve Ellcey <sellcey@mips.com>
50 Faraz Shahbazker <fshahbazker@wavecomp.com>
51
52 * interp.c (sim_monitor): Add switch entries for unlink (13),
53 lseek (14), and stat (15).
54
b6b1c790
MF		 552021-04-02 Mike Frysinger <vapier@gentoo.org>
56
57 * Makefile.in (../igen/igen): Delete rule.
58 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
59
c2783492
MF		 602021-04-02 Mike Frysinger <vapier@gentoo.org>
61
62 * aclocal.m4, configure: Regenerate.
63
ebe9564b
MF		 642021-02-28 Mike Frysinger <vapier@gentoo.org>
65
66 * configure: Regenerate.
67
f8069d55
MF		 682021-02-27 Mike Frysinger <vapier@gentoo.org>
69
70 * Makefile.in (SIM_EXTRA_ALL): Delete.
71 (all): New target.
72
760b3e8b
MF		 732021-02-21 Mike Frysinger <vapier@gentoo.org>
74
75 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
76 * aclocal.m4, configure: Regenerate.
77
136da8cd
MF		 782021-02-13 Mike Frysinger <vapier@gentoo.org>
79
80 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
81 * aclocal.m4, configure: Regenerate.
82
4c0d76b9
MF		 832021-02-06 Mike Frysinger <vapier@gentoo.org>
84
85 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
86
aa09469f
MF		 872021-02-06 Mike Frysinger <vapier@gentoo.org>
88
89 * configure: Regenerate.
90
d4e3adda
MF		 912021-01-30 Mike Frysinger <vapier@gentoo.org>
92
93 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
94
68ed2854
MF		 952021-01-11 Mike Frysinger <vapier@gentoo.org>
96
97 * config.in, configure: Regenerate.
98 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
99 and strings.h include.
100
50df264d
MF		 1012021-01-09 Mike Frysinger <vapier@gentoo.org>
102
103 * configure: Regenerate.
104
bf470982
MF		 1052021-01-09 Mike Frysinger <vapier@gentoo.org>
106
107 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
108 * configure: Regenerate.
109
46f900c0
MF		 1102021-01-08 Mike Frysinger <vapier@gentoo.org>
111
112 * configure: Regenerate.
113
dfb856ba
MF		 1142021-01-04 Mike Frysinger <vapier@gentoo.org>
115
116 * configure: Regenerate.
117
382bc56b
PK		 1182020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
119
120 * sim-main.c: Include <stdlib.h>.
121
ad9675dd
PK		 1222020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
123
124 * cp1.c: Include <stdlib.h>.
125
f693213d
SM		 1262020-07-29 Simon Marchi <simon.marchi@efficios.com>
127
128 * configure: Re-generate.
129
5c887dd5
JB		 1302017-09-06 John Baldwin <jhb@FreeBSD.org>
131
132 * configure: Regenerate.
133
91588b3a
MF		 1342016-11-11 Mike Frysinger <vapier@gentoo.org>
135
6cb2202b 136 PR sim/20808
91588b3a
MF		 137 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
138 and SD to sd.
139
e04659e8
MF		 1402016-11-11 Mike Frysinger <vapier@gentoo.org>
141
6cb2202b 142 PR sim/20809
e04659e8
MF		 143 * mips.igen (check_u64): Enable for `r3900'.
144
1554f758
MF		 1452016-02-05 Mike Frysinger <vapier@gentoo.org>
146
147 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
148 STATE_PROG_BFD (sd).
149 * configure: Regenerate.
150
3d304f48
AB		 1512016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
152 Maciej W. Rozycki <macro@imgtec.com>
153
154 PR sim/19441
155 * micromips.igen (delayslot_micromips): Enable for `micromips32',
156 `micromips64' and `micromipsdsp' only.
157 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
158 (do_micromips_jalr, do_micromips_jal): Likewise.
159 (compute_movep_src_reg): Likewise.
160 (compute_andi16_imm): Likewise.
161 (convert_fmt_micromips): Likewise.
162 (convert_fmt_micromips_cvt_d): Likewise.
163 (convert_fmt_micromips_cvt_s): Likewise.
164 (FMT_MICROMIPS): Likewise.
165 (FMT_MICROMIPS_CVT_D): Likewise.
166 (FMT_MICROMIPS_CVT_S): Likewise.
167
b36d953b
MF		 1682016-01-12 Mike Frysinger <vapier@gentoo.org>
169
170 * interp.c: Include elf-bfd.h.
171 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
172 ELFCLASS32.
173
ce39bd38
MF		 1742016-01-10 Mike Frysinger <vapier@gentoo.org>
175
176 * config.in, configure: Regenerate.
177
99d8e879
MF		 1782016-01-10 Mike Frysinger <vapier@gentoo.org>
179
180 * configure: Regenerate.
181
35656e95
MF		 1822016-01-10 Mike Frysinger <vapier@gentoo.org>
183
184 * configure: Regenerate.
185
16f7876d
MF		 1862016-01-10 Mike Frysinger <vapier@gentoo.org>
187
188 * configure: Regenerate.
189
e19418e0
MF		 1902016-01-10 Mike Frysinger <vapier@gentoo.org>
191
192 * configure: Regenerate.
193
6d90347b
MF		 1942016-01-10 Mike Frysinger <vapier@gentoo.org>
195
196 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
197 * configure: Regenerate.
198
347fe5bb
MF		 1992016-01-10 Mike Frysinger <vapier@gentoo.org>
200
201 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
202 * configure: Regenerate.
203
22be3fbe
MF		 2042016-01-10 Mike Frysinger <vapier@gentoo.org>
205
206 * configure: Regenerate.
207
0dc73ef7
MF		 2082016-01-10 Mike Frysinger <vapier@gentoo.org>
209
210 * configure: Regenerate.
211
936df756
MF		 2122016-01-09 Mike Frysinger <vapier@gentoo.org>
213
214 * config.in, configure: Regenerate.
215
2e3d4f4d
MF		 2162016-01-06 Mike Frysinger <vapier@gentoo.org>
217
218 * interp.c (sim_open): Mark argv const.
219 (sim_create_inferior): Mark argv and env const.
220
9bbf6f91
MF		 2212016-01-04 Mike Frysinger <vapier@gentoo.org>
222
223 * configure: Regenerate.
224
77cf2ef5
MF		 2252016-01-03 Mike Frysinger <vapier@gentoo.org>
226
227 * interp.c (sim_open): Update sim_parse_args comment.
228
0cb8d851
MF		 2292016-01-03 Mike Frysinger <vapier@gentoo.org>
230
231 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
232 * configure: Regenerate.
233
1ac72f06
MF		 2342016-01-02 Mike Frysinger <vapier@gentoo.org>
235
236 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
237 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
238 * configure: Regenerate.
239 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
240
d47f5b30
MF		 2412016-01-02 Mike Frysinger <vapier@gentoo.org>
242
243 * dv-tx3904cpu.c (CPU, SD): Delete.
244
e1211e55
MF		 2452015-12-30 Mike Frysinger <vapier@gentoo.org>
246
247 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
248 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
249 (sim_store_register): Rename to ...
250 (mips_reg_store): ... this. Delete local cpu var.
251 Update sim_io_eprintf calls.
252 (sim_fetch_register): Rename to ...
253 (mips_reg_fetch): ... this. Delete local cpu var.
254 Update sim_io_eprintf calls.
255
5e744ef8
MF		 2562015-12-27 Mike Frysinger <vapier@gentoo.org>
257
258 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
259
1b393626
MF		 2602015-12-26 Mike Frysinger <vapier@gentoo.org>
261
262 * config.in, configure: Regenerate.
263
26f8bf63
MF		 2642015-12-26 Mike Frysinger <vapier@gentoo.org>
265
266 * interp.c (sim_write, sim_read): Delete.
267 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
268 (load_word): Likewise.
269 * micromips.igen (cache): Likewise.
270 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
271 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
272 do_store_left, do_store_right, do_load_double, do_store_double):
273 Likewise.
274 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
275 (do_prefx): Likewise.
276 * sim-main.c (address_translation, prefetch): Delete.
277 (ifetch32, ifetch16): Delete call to AddressTranslation and set
278 paddr=vaddr.
279 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
280 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
281 (LoadMemory, StoreMemory): Delete CCA arg.
282
ef04e371
MF		 2832015-12-24 Mike Frysinger <vapier@gentoo.org>
284
285 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
286 * configure: Regenerated.
287
cb379ede
MF		 2882015-12-24 Mike Frysinger <vapier@gentoo.org>
289
290 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
291 * tconfig.h: Delete.
292
26936211
MF		 2932015-12-24 Mike Frysinger <vapier@gentoo.org>
294
295 * tconfig.h (SIM_HANDLES_LMA): Delete.
296
84e8e361
MF		 2972015-12-24 Mike Frysinger <vapier@gentoo.org>
298
299 * sim-main.h (WITH_WATCHPOINTS): Delete.
300
3cabaf66
MF		 3012015-12-24 Mike Frysinger <vapier@gentoo.org>
302
303 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
304
8abe6c66
MF		 3052015-12-24 Mike Frysinger <vapier@gentoo.org>
306
307 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
308
1d19cae7
DV		 3092015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
310
311 * micromips.igen (process_isa_mode): Fix left shift of negative
312 value.
313
cdf850e9
MF		 3142015-11-17 Mike Frysinger <vapier@gentoo.org>
315
316 * sim-main.h (WITH_MODULO_MEMORY): Delete.
317
797eee42
MF		 3182015-11-15 Mike Frysinger <vapier@gentoo.org>
319
320 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
321
6e4f085c
MF		 3222015-11-14 Mike Frysinger <vapier@gentoo.org>
323
324 * interp.c (sim_close): Rename to ...
325 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
326 sim_io_shutdown.
327 * sim-main.h (mips_sim_close): Declare.
328 (SIM_CLOSE_HOOK): Define.
329
8e394ffc
AB		 3302015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
331 Ali Lown <ali.lown@imgtec.com>
332
333 * Makefile.in (tmp-micromips): New rule.
334 (tmp-mach-multi): Add support for micromips.
335 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
336 that works for both mips64 and micromips64.
337 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
338 micromips32.
339 Add build support for micromips.
340 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
341 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
342 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
343 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
344 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
345 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
346 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
347 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
348 Refactored instruction code to use these functions.
349 * dsp2.igen: Refactored instruction code to use the new functions.
350 * interp.c (decode_coproc): Refactored to work with any instruction
351 encoding.
352 (isa_mode): New variable
353 (RSVD_INSTRUCTION): Changed to 0x00000039.
354 * m16.igen (BREAK16): Refactored instruction to use do_break16.
355 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
356 * micromips.dc: New file.
357 * micromips.igen: New file.
358 * micromips16.dc: New file.
359 * micromipsdsp.igen: New file.
360 * micromipsrun.c: New file.
361 * mips.igen (do_swc1): Changed to work with any instruction encoding.
362 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
363 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
364 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
365 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
366 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
367 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
368 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
369 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
370 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
371 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
372 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
373 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
374 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
375 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
376 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
377 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
378 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
379 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
380 instructions.
381 Refactored instruction code to use these functions.
382 (RSVD): Changed to use new reserved instruction.
383 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
384 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
385 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
386 do_store_double): Added micromips32 and micromips64 models.
387 Added include for micromips.igen and micromipsdsp.igen
388 Add micromips32 and micromips64 models.
389 (DecodeCoproc): Updated to use new macro definition.
390 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
391 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
392 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
393 Refactored instruction code to use these functions.
394 * sim-main.h (CP0_operation): New enum.
395 (DecodeCoproc): Updated macro.
396 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
397 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
398 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
399 ISA_MODE_MICROMIPS): New defines.
400 (sim_state): Add isa_mode field.
401
8d0978fb
MF		 4022015-06-23 Mike Frysinger <vapier@gentoo.org>
403
404 * configure: Regenerate.
405
306f4178
MF		 4062015-06-12 Mike Frysinger <vapier@gentoo.org>
407
408 * configure.ac: Change configure.in to configure.ac.
409 * configure: Regenerate.
410
a3487082
MF		 4112015-06-12 Mike Frysinger <vapier@gentoo.org>
412
413 * configure: Regenerate.
414
29bc024d
MF		 4152015-06-12 Mike Frysinger <vapier@gentoo.org>
416
417 * interp.c [TRACE]: Delete.
418 (TRACE): Change to WITH_TRACE_ANY_P.
419 [!WITH_TRACE_ANY_P] (open_trace): Define.
420 (mips_option_handler, open_trace, sim_close, dotrace):
421 Change defined(TRACE) to WITH_TRACE_ANY_P.
422 (sim_open): Delete TRACE ifdef check.
423 * sim-main.c (load_memory): Delete TRACE ifdef check.
424 (store_memory): Likewise.
425 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
426 [!WITH_TRACE_ANY_P] (dotrace): Define.
427
3ebe2863
MF		 4282015-04-18 Mike Frysinger <vapier@gentoo.org>
429
430 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
431 comments.
432
20bca71d
MF		 4332015-04-18 Mike Frysinger <vapier@gentoo.org>
434
435 * sim-main.h (SIM_CPU): Delete.
436
7e83aa92
MF		 4372015-04-18 Mike Frysinger <vapier@gentoo.org>
438
439 * sim-main.h (sim_cia): Delete.
440
034685f9
MF		 4412015-04-17 Mike Frysinger <vapier@gentoo.org>
442
443 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
444 PU_PC_GET.
445 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
446 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
447 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
448 CIA_SET to CPU_PC_SET.
449 * sim-main.h (CIA_GET, CIA_SET): Delete.
450
78e9aa70
MF		 4512015-04-15 Mike Frysinger <vapier@gentoo.org>
452
453 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
454 * sim-main.h (STATE_CPU): Delete.
455
bf12d44e
MF		 4562015-04-13 Mike Frysinger <vapier@gentoo.org>
457
458 * configure: Regenerate.
459
7bebb329
MF		 4602015-04-13 Mike Frysinger <vapier@gentoo.org>
461
462 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
463 * interp.c (mips_pc_get, mips_pc_set): New functions.
464 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
465 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
466 (sim_pc_get): Delete.
467 * sim-main.h (SIM_CPU): Define.
468 (struct sim_state): Change cpu to an array of pointers.
469 (STATE_CPU): Drop &.
470
8ac57fbd
MF		 4712015-04-13 Mike Frysinger <vapier@gentoo.org>
472
473 * interp.c (mips_option_handler, open_trace, sim_close,
474 sim_write, sim_read, sim_store_register, sim_fetch_register,
475 sim_create_inferior, pr_addr, pr_uword64): Convert old style
476 prototypes.
477 (sim_open): Convert old style prototype. Change casts with
478 sim_write to unsigned char *.
479 (fetch_str): Change null to unsigned char, and change cast to
480 unsigned char *.
481 (sim_monitor): Change c & ch to unsigned char. Change cast to
482 unsigned char *.
483
e787f858
MF		 4842015-04-12 Mike Frysinger <vapier@gentoo.org>
485
486 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
487
122bbfb5
MF		 4882015-04-06 Mike Frysinger <vapier@gentoo.org>
489
490 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
491
0fe84f3f
MF		 4922015-04-01 Mike Frysinger <vapier@gentoo.org>
493
494 * tconfig.h (SIM_HAVE_PROFILE): Delete.
495
aadc9410
MF		 4962015-03-31 Mike Frysinger <vapier@gentoo.org>
497
498 * config.in, configure: Regenerate.
499
05f53ed6
MF		 5002015-03-24 Mike Frysinger <vapier@gentoo.org>
501
502 * interp.c (sim_pc_get): New function.
503
c0931f26
MF		 5042015-03-24 Mike Frysinger <vapier@gentoo.org>
505
506 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
507 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
508
30452bbe
MF		 5092015-03-24 Mike Frysinger <vapier@gentoo.org>
510
511 * configure: Regenerate.
512
64dd13df
MF		 5132015-03-23 Mike Frysinger <vapier@gentoo.org>
514
515 * configure: Regenerate.
516
49cd1634
MF		 5172015-03-23 Mike Frysinger <vapier@gentoo.org>
518
519 * configure: Regenerate.
520 * configure.ac (mips_extra_objs): Delete.
521 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
522 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
523
3649cb06
MF		 5242015-03-23 Mike Frysinger <vapier@gentoo.org>
525
526 * configure: Regenerate.
527 * configure.ac: Delete sim_hw checks for dv-sockser.
528
ae7d0cac
MF		 5292015-03-16 Mike Frysinger <vapier@gentoo.org>
530
531 * config.in, configure: Regenerate.
532 * tconfig.in: Rename file ...
533 * tconfig.h: ... here.
534
8406bb59
MF		 5352015-03-15 Mike Frysinger <vapier@gentoo.org>
536
537 * tconfig.in: Delete includes.
538 [HAVE_DV_SOCKSER]: Delete.
539
465fb143
MF		 5402015-03-14 Mike Frysinger <vapier@gentoo.org>
541
542 * Makefile.in (SIM_RUN_OBJS): Delete.
543
5cddc23a
MF		 5442015-03-14 Mike Frysinger <vapier@gentoo.org>
545
546 * configure.ac (AC_CHECK_HEADERS): Delete.
547 * aclocal.m4, configure: Regenerate.
548
2974be62
AM		 5492014-08-19 Alan Modra <amodra@gmail.com>
550
551 * configure: Regenerate.
552
faa743bb
RM		 5532014-08-15 Roland McGrath <mcgrathr@google.com>
554
555 * configure: Regenerate.
556 * config.in: Regenerate.
557
1a8a700e
MF		 5582014-03-04 Mike Frysinger <vapier@gentoo.org>
559
560 * configure: Regenerate.
561
bf3d9781
AM		 5622013-09-23 Alan Modra <amodra@gmail.com>
563
564 * configure: Regenerate.
565
31e6ad7d
MF		 5662013-06-03 Mike Frysinger <vapier@gentoo.org>
567
568 * aclocal.m4, configure: Regenerate.
569
d3685d60
TT		 5702013-05-10 Freddie Chopin <freddie_chopin@op.pl>
571
572 * configure: Rebuild.
573
1517bd27
MF		 5742013-03-26 Mike Frysinger <vapier@gentoo.org>
575
576 * configure: Regenerate.
577
3be31516
JS		 5782013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
579
580 * configure.ac: Address use of dv-sockser.o.
581 * tconfig.in: Conditionalize use of dv_sockser_install.
582 * configure: Regenerated.
583 * config.in: Regenerated.
584
37cb8f8e
SE		 5852012-10-04 Chao-ying Fu <fu@mips.com>
586 Steve Ellcey <sellcey@mips.com>
587
588 * mips/mips3264r2.igen (rdhwr): New.
589
87c8644f
JS		 5902012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
591
592 * configure.ac: Always link against dv-sockser.o.
593 * configure: Regenerate.
594
5f3ef9d0
JB		 5952012-06-15 Joel Brobecker <brobecker@adacore.com>
596
597 * config.in, configure: Regenerate.
598
a6ff997c
NC		 5992012-05-18 Nick Clifton <nickc@redhat.com>
600
601 PR 14072
602 * interp.c: Include config.h before system header files.
603
2232061b
MF		 6042012-03-24 Mike Frysinger <vapier@gentoo.org>
605
606 * aclocal.m4, config.in, configure: Regenerate.
607
db2e4d67
MF		 6082011-12-03 Mike Frysinger <vapier@gentoo.org>
609
610 * aclocal.m4: New file.
611 * configure: Regenerate.
612
4399a56b
MF		 6132011-10-19 Mike Frysinger <vapier@gentoo.org>
614
615 * configure: Regenerate after common/acinclude.m4 update.
616
9c082ca8
MF		 6172011-10-17 Mike Frysinger <vapier@gentoo.org>
618
619 * configure.ac: Change include to common/acinclude.m4.
620
6ffe910a
MF		 6212011-10-17 Mike Frysinger <vapier@gentoo.org>
622
623 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
624 call. Replace common.m4 include with SIM_AC_COMMON.
625 * configure: Regenerate.
626
31b28250
HPN		 6272011-07-08 Hans-Peter Nilsson <hp@axis.com>
628
3faa01e3
HPN		 629 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
630 $(SIM_EXTRA_DEPS).
631 (tmp-mach-multi): Exit early when igen fails.
31b28250 632
2419798b
MF		 6332011-07-05 Mike Frysinger <vapier@gentoo.org>
634
635 * interp.c (sim_do_command): Delete.
636
d79fe0d6
MF		 6372011-02-14 Mike Frysinger <vapier@gentoo.org>
638
639 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
640 (tx3904sio_fifo_reset): Likewise.
641 * interp.c (sim_monitor): Likewise.
642
5558e7e6
MF		 6432010-04-14 Mike Frysinger <vapier@gentoo.org>
644
645 * interp.c (sim_write): Add const to buffer arg.
646
35aafff4
JB		 6472010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
648
649 * interp.c: Don't include sysdep.h
650
3725885a
RW		 6512010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
652
653 * configure: Regenerate.
654
d6416cdc
RW		 6552009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
656
81ecdfbb
RW		 657 * config.in: Regenerate.
658 * configure: Likewise.
659
d6416cdc
RW		 660 * configure: Regenerate.
661
b5bd9624
HPN		 6622008-07-11 Hans-Peter Nilsson <hp@axis.com>
663
664 * configure: Regenerate to track ../common/common.m4 changes.
665 * config.in: Ditto.
666
6efef468 6672008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 668 Daniel Jacobowitz <dan@codesourcery.com>
669 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 670
671 * configure: Regenerate.
672
60dc88db
RS		 6732007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
674
675 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
676 that unconditionally allows fmt_ps.
677 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
678 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
679 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
680 filter from 64,f to 32,f.
681 (PREFX): Change filter from 64 to 32.
682 (LDXC1, LUXC1): Provide separate mips32r2 implementations
683 that use do_load_double instead of do_load. Make both LUXC1
684 versions unpredictable if SizeFGR () != 64.
685 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
686 instead of do_store. Remove unused variable. Make both SUXC1
687 versions unpredictable if SizeFGR () != 64.
688
599ca73e
RS		 6892007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
690
691 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
692 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
693 shifts for that case.
694
2525df03
NC		 6952007-09-04 Nick Clifton <nickc@redhat.com>
696
697 * interp.c (options enum): Add OPTION_INFO_MEMORY.
698 (display_mem_info): New static variable.
699 (mips_option_handler): Handle OPTION_INFO_MEMORY.
700 (mips_options): Add info-memory and memory-info.
701 (sim_open): After processing the command line and board
702 specification, check display_mem_info. If it is set then
703 call the real handler for the --memory-info command line
704 switch.
705
35ee6e1e
JB		 7062007-08-24 Joel Brobecker <brobecker@adacore.com>
707
708 * configure.ac: Change license of multi-run.c to GPL version 3.
709 * configure: Regenerate.
710
d5fb0879
RS		 7112007-06-28 Richard Sandiford <richard@codesourcery.com>
712
713 * configure.ac, configure: Revert last patch.
714
2a2ce21b
RS		 7152007-06-26 Richard Sandiford <richard@codesourcery.com>
716
717 * configure.ac (sim_mipsisa3264_configs): New variable.
718 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
719 every configuration support all four targets, using the triplet to
720 determine the default.
721 * configure: Regenerate.
722
efdcccc9
RS		 7232007-06-25 Richard Sandiford <richard@codesourcery.com>
724
0a7692b2 725 * Makefile.in (m16run.o): New rule.
efdcccc9 726
f532a356
TS		 7272007-05-15 Thiemo Seufer <ths@mips.com>
728
729 * mips3264r2.igen (DSHD): Fix compile warning.
730
bfe9c90b
TS		 7312007-05-14 Thiemo Seufer <ths@mips.com>
732
733 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
734 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
735 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
736 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
737 for mips32r2.
738
53f4826b
TS		 7392007-03-01 Thiemo Seufer <ths@mips.com>
740
741 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
742 and mips64.
743
8bf3ddc8
TS		 7442007-02-20 Thiemo Seufer <ths@mips.com>
745
746 * dsp.igen: Update copyright notice.
747 * dsp2.igen: Fix copyright notice.
748
8b082fb1 7492007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 750 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 751
752 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
753 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
754 Add dsp2 to sim_igen_machine.
755 * configure: Regenerate.
756 * dsp.igen (do_ph_op): Add MUL support when op = 2.
757 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
758 (mulq_rs.ph): Use do_ph_mulq.
759 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
760 * mips.igen: Add dsp2 model and include dsp2.igen.
761 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
762 for *mips32r2, *mips64r2, *dsp.
763 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
764 for *mips32r2, *mips64r2, *dsp2.
765 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
766
b1004875 7672007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 768 Nigel Stephens <nigel@mips.com>
b1004875
TS		 769
770 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
771 jumps with hazard barrier.
772
f8df4c77 7732007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 774 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 775
776 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
777 after each call to sim_io_write.
778
b1004875 7792007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 780 Nigel Stephens <nigel@mips.com>
b1004875
TS		 781
782 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
783 supported by this simulator.
07802d98
TS		 784 (decode_coproc): Recognise additional CP0 Config registers
785 correctly.
786
14fb6c5a 7872007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 788 Nigel Stephens <nigel@mips.com>
789 David Ung <davidu@mips.com>
14fb6c5a
TS		 790
791 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
792 uninterpreted formats. If fmt is one of the uninterpreted types
793 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
794 fmt_word, and fmt_uninterpreted_64 like fmt_long.
795 (store_fpr): When writing an invalid odd register, set the
796 matching even register to fmt_unknown, not the following register.
797 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
798 the the memory window at offset 0 set by --memory-size command
799 line option.
800 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
801 point register.
802 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
803 register.
804 (sim_monitor): When returning the memory size to the MIPS
805 application, use the value in STATE_MEM_SIZE, not an arbitrary
806 hardcoded value.
807 (cop_lw): Don' mess around with FPR_STATE, just pass
808 fmt_uninterpreted_32 to StoreFPR.
809 (cop_sw): Similarly.
810 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
811 (cop_sd): Similarly.
812 * mips.igen (not_word_value): Single version for mips32, mips64
813 and mips16.
814
c8847145 8152007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 816 Nigel Stephens <nigel@mips.com>
c8847145
TS		 817
818 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
819 MBytes.
820
4b5d35ee
TS		 8212007-02-17 Thiemo Seufer <ths@mips.com>
822
823 * configure.ac (mips*-sde-elf*): Move in front of generic machine
824 configuration.
825 * configure: Regenerate.
826
3669427c
TS		 8272007-02-17 Thiemo Seufer <ths@mips.com>
828
829 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
830 Add mdmx to sim_igen_machine.
831 (mipsisa64*-*-*): Likewise. Remove dsp.
832 (mipsisa32*-*-*): Remove dsp.
833 * configure: Regenerate.
834
109ad085
TS		 8352007-02-13 Thiemo Seufer <ths@mips.com>
836
837 * configure.ac: Add mips*-sde-elf* target.
838 * configure: Regenerate.
839
921d7ad3
HPN		 8402006-12-21 Hans-Peter Nilsson <hp@axis.com>
841
842 * acconfig.h: Remove.
843 * config.in, configure: Regenerate.
844
02f97da7
TS		 8452006-11-07 Thiemo Seufer <ths@mips.com>
846
847 * dsp.igen (do_w_op): Fix compiler warning.
848
2d2733fc 8492006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 850 David Ung <davidu@mips.com>
2d2733fc
TS		 851
852 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
853 sim_igen_machine.
854 * configure: Regenerate.
855 * mips.igen (model): Add smartmips.
856 (MADDU): Increment ACX if carry.
857 (do_mult): Clear ACX.
858 (ROR,RORV): Add smartmips.
72f4393d 859 (include): Include smartmips.igen.
2d2733fc
TS		 860 * sim-main.h (ACX): Set to REGISTERS[89].
861 * smartmips.igen: New file.
862
d85c3a10 8632006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 864 David Ung <davidu@mips.com>
d85c3a10
TS		 865
866 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
867 mips3264r2.igen. Add missing dependency rules.
868 * m16e.igen: Support for mips16e save/restore instructions.
869
e85e3205
RE		 8702006-06-13 Richard Earnshaw <rearnsha@arm.com>
871
872 * configure: Regenerated.
873
2f0122dc
DJ		 8742006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
875
876 * configure: Regenerated.
877
20e95c23
DJ		 8782006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
879
880 * configure: Regenerated.
881
69088b17
CF		 8822006-05-15 Chao-ying Fu <fu@mips.com>
883
884 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
885
0275de4e
NC		 8862006-04-18 Nick Clifton <nickc@redhat.com>
887
888 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
889 statement.
890
b3a3ffef
HPN		 8912006-03-29 Hans-Peter Nilsson <hp@axis.com>
892
893 * configure: Regenerate.
894
40a5538e
CF		 8952005-12-14 Chao-ying Fu <fu@mips.com>
896
897 * Makefile.in (SIM_OBJS): Add dsp.o.
898 (dsp.o): New dependency.
899 (IGEN_INCLUDE): Add dsp.igen.
900 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
901 mipsisa64*-*-*): Add dsp to sim_igen_machine.
902 * configure: Regenerate.
903 * mips.igen: Add dsp model and include dsp.igen.
904 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
905 because these instructions are extended in DSP ASE.
906 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
907 adding 6 DSP accumulator registers and 1 DSP control register.
908 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
909 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
910 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
911 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
912 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
913 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
914 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
915 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
916 DSPCR_CCOND_SMASK): New define.
917 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
918 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
919
21d14896
ILT		 9202005-07-08 Ian Lance Taylor <ian@airs.com>
921
922 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
923
b16d63da 9242005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 925 Nigel Stephens <nigel@mips.com>
926
927 * mips.igen: New mips16e model and include m16e.igen.
928 (check_u64): Add mips16e tag.
929 * m16e.igen: New file for MIPS16e instructions.
930 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
931 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
932 models.
933 * configure: Regenerate.
b16d63da 934
e70cb6cd 9352005-05-26 David Ung <davidu@mips.com>
72f4393d 936
e70cb6cd
CD		 937 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
938 tags to all instructions which are applicable to the new ISAs.
939 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
940 vr.igen.
941 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 942 instructions.
e70cb6cd
CD		 943 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
944 to mips.igen.
945 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
946 * configure: Regenerate.
72f4393d 947
2b193c4a
MK		 9482005-03-23 Mark Kettenis <kettenis@gnu.org>
949
950 * configure: Regenerate.
951
35695fd6
AC		 9522005-01-14 Andrew Cagney <cagney@gnu.org>
953
954 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
955 explicit call to AC_CONFIG_HEADER.
956 * configure: Regenerate.
957
f0569246
AC		 9582005-01-12 Andrew Cagney <cagney@gnu.org>
959
960 * configure.ac: Update to use ../common/common.m4.
961 * configure: Re-generate.
962
38f48d72
AC		 9632005-01-11 Andrew Cagney <cagney@localhost.localdomain>
964
965 * configure: Regenerated to track ../common/aclocal.m4 changes.
966
b7026657
AC		 9672005-01-07 Andrew Cagney <cagney@gnu.org>
968
969 * configure.ac: Rename configure.in, require autoconf 2.59.
970 * configure: Re-generate.
971
379832de
HPN		 9722004-12-08 Hans-Peter Nilsson <hp@axis.com>
973
974 * configure: Regenerate for ../common/aclocal.m4 update.
975
cd62154c 9762004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 977
cd62154c
AC		 978 Committed by Andrew Cagney.
979 * m16.igen (CMP, CMPI): Fix assembler.
980
e5da76ec
CD		 9812004-08-18 Chris Demetriou <cgd@broadcom.com>
982
983 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
984 * configure: Regenerate.
985
139181c8
CD		 9862004-06-25 Chris Demetriou <cgd@broadcom.com>
987
988 * configure.in (sim_m16_machine): Include mipsIII.
989 * configure: Regenerate.
990
1a27f959
CD		 9912004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
992
72f4393d 993 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 994 from COP0_BADVADDR.
995 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
996
5dbb7b5a
CD		 9972004-04-10 Chris Demetriou <cgd@broadcom.com>
998
999 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1000
14234056
CD		 10012004-04-09 Chris Demetriou <cgd@broadcom.com>
1002
1003 * mips.igen (check_fmt): Remove.
1004 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1005 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1006 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1007 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1008 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1009 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1010 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1011 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1012 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1013 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1014
c6f9085c
CD		 10152004-04-09 Chris Demetriou <cgd@broadcom.com>
1016
1017 * sb1.igen (check_sbx): New function.
1018 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1019
11d66e66 10202004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1021 Richard Sandiford <rsandifo@redhat.com>
1022
1023 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1024 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1025 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1026 separate implementations for mipsIV and mipsV. Use new macros to
1027 determine whether the restrictions apply.
1028
b3208fb8
CD		 10292004-01-19 Chris Demetriou <cgd@broadcom.com>
1030
1031 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1032 (check_mult_hilo): Improve comments.
1033 (check_div_hilo): Likewise. Also, fork off a new version
1034 to handle mips32/mips64 (since there are no hazards to check
1035 in MIPS32/MIPS64).
1036
9a1d84fb
CD		 10372003-06-17 Richard Sandiford <rsandifo@redhat.com>
1038
1039 * mips.igen (do_dmultx): Fix check for negative operands.
1040
ae451ac6
ILT		 10412003-05-16 Ian Lance Taylor <ian@airs.com>
1042
1043 * Makefile.in (SHELL): Make sure this is defined.
1044 (various): Use $(SHELL) whenever we invoke move-if-change.
1045
dd69d292
CD		 10462003-05-03 Chris Demetriou <cgd@broadcom.com>
1047
1048 * cp1.c: Tweak attribution slightly.
1049 * cp1.h: Likewise.
1050 * mdmx.c: Likewise.
1051 * mdmx.igen: Likewise.
1052 * mips3d.igen: Likewise.
1053 * sb1.igen: Likewise.
1054
bcd0068e
CD		 10552003-04-15 Richard Sandiford <rsandifo@redhat.com>
1056
1057 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1058 unsigned operands.
1059
6b4a8935
AC		 10602003-02-27 Andrew Cagney <cagney@redhat.com>
1061
601da316
AC		 1062 * interp.c (sim_open): Rename _bfd to bfd.
1063 (sim_create_inferior): Ditto.
6b4a8935 1064
d29e330f
CD		 10652003-01-14 Chris Demetriou <cgd@broadcom.com>
1066
1067 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1068
a2353a08
CD		 10692003-01-14 Chris Demetriou <cgd@broadcom.com>
1070
1071 * mips.igen (EI, DI): Remove.
1072
80551777
CD		 10732003-01-05 Richard Sandiford <rsandifo@redhat.com>
1074
1075 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1076
4c54fc26
CD		 10772003-01-04 Richard Sandiford <rsandifo@redhat.com>
1078 Andrew Cagney <ac131313@redhat.com>
1079 Gavin Romig-Koch <gavin@redhat.com>
1080 Graydon Hoare <graydon@redhat.com>
1081 Aldy Hernandez <aldyh@redhat.com>
1082 Dave Brolley <brolley@redhat.com>
1083 Chris Demetriou <cgd@broadcom.com>
1084
1085 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1086 (sim_mach_default): New variable.
1087 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1088 Add a new simulator generator, MULTI.
1089 * configure: Regenerate.
1090 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1091 (multi-run.o): New dependency.
1092 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1093 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1094 (tmp-multi): Combine them.
1095 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1096 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1097 (distclean-extra): New rule.
1098 * sim-main.h: Include bfd.h.
1099 (MIPS_MACH): New macro.
1100 * mips.igen (vr4120, vr5400, vr5500): New models.
1101 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1102 * vr.igen: Replace with new version.
1103
e6c674b8
CD		 11042003-01-04 Chris Demetriou <cgd@broadcom.com>
1105
1106 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1107 * configure: Regenerate.
1108
28f50ac8
CD		 11092002-12-31 Chris Demetriou <cgd@broadcom.com>
1110
1111 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1112 * mips.igen: Remove all invocations of check_branch_bug and
1113 mark_branch_bug.
1114
5071ffe6
CD		 11152002-12-16 Chris Demetriou <cgd@broadcom.com>
1116
72f4393d 1117 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1118
06e7837e
CD		 11192002-07-30 Chris Demetriou <cgd@broadcom.com>
1120
1121 * mips.igen (do_load_double, do_store_double): New functions.
1122 (LDC1, SDC1): Rename to...
1123 (LDC1b, SDC1b): respectively.
1124 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1125
2265c243
MS		 11262002-07-29 Michael Snyder <msnyder@redhat.com>
1127
1128 * cp1.c (fp_recip2): Modify initialization expression so that
1129 GCC will recognize it as constant.
1130
a2f8b4f3
CD		 11312002-06-18 Chris Demetriou <cgd@broadcom.com>
1132
1133 * mdmx.c (SD_): Delete.
1134 (Unpredictable): Re-define, for now, to directly invoke
1135 unpredictable_action().
1136 (mdmx_acc_op): Fix error in .ob immediate handling.
1137
b4b6c939
AC		 11382002-06-18 Andrew Cagney <cagney@redhat.com>
1139
1140 * interp.c (sim_firmware_command): Initialize `address'.
1141
c8cca39f
AC		 11422002-06-16 Andrew Cagney <ac131313@redhat.com>
1143
1144 * configure: Regenerated to track ../common/aclocal.m4 changes.
1145
e7e81181 11462002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1147 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1148
1149 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1150 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1151 * mips.igen: Include mips3d.igen.
1152 (mips3d): New model name for MIPS-3D ASE instructions.
1153 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1154 instructions.
e7e81181
CD		 1155 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1156 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1157 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1158 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1159 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1160 (RSquareRoot1, RSquareRoot2): New macros.
1161 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1162 (fp_rsqrt2): New functions.
1163 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1164 * configure: Regenerate.
1165
3a2b820e 11662002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1167 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1168
1169 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1170 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1171 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1172 (convert): Note that this function is not used for paired-single
1173 format conversions.
1174 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1175 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1176 (check_fmt_p): Enable paired-single support.
1177 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1178 (PUU.PS): New instructions.
1179 (CVT.S.fmt): Don't use this instruction for paired-single format
1180 destinations.
1181 * sim-main.h (FP_formats): New value 'fmt_ps.'
1182 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1183 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1184
d18ea9c2
CD		 11852002-06-12 Chris Demetriou <cgd@broadcom.com>
1186
1187 * mips.igen: Fix formatting of function calls in
1188 many FP operations.
1189
95fd5cee
CD		 11902002-06-12 Chris Demetriou <cgd@broadcom.com>
1191
1192 * mips.igen (MOVN, MOVZ): Trace result.
1193 (TNEI): Print "tnei" as the opcode name in traces.
1194 (CEIL.W): Add disassembly string for traces.
1195 (RSQRT.fmt): Make location of disassembly string consistent
1196 with other instructions.
1197
4f0d55ae
CD		 11982002-06-12 Chris Demetriou <cgd@broadcom.com>
1199
1200 * mips.igen (X): Delete unused function.
1201
3c25f8c7
AC		 12022002-06-08 Andrew Cagney <cagney@redhat.com>
1203
1204 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1205
f3c08b7e 12062002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1207 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1208
1209 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1210 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1211 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1212 (fp_nmsub): New prototypes.
1213 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1214 (NegMultiplySub): New defines.
1215 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1216 (MADD.D, MADD.S): Replace with...
1217 (MADD.fmt): New instruction.
1218 (MSUB.D, MSUB.S): Replace with...
1219 (MSUB.fmt): New instruction.
1220 (NMADD.D, NMADD.S): Replace with...
1221 (NMADD.fmt): New instruction.
1222 (NMSUB.D, MSUB.S): Replace with...
1223 (NMSUB.fmt): New instruction.
1224
52714ff9 12252002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1226 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1227
1228 * cp1.c: Fix more comment spelling and formatting.
1229 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1230 (denorm_mode): New function.
1231 (fpu_unary, fpu_binary): Round results after operation, collect
1232 status from rounding operations, and update the FCSR.
1233 (convert): Collect status from integer conversions and rounding
1234 operations, and update the FCSR. Adjust NaN values that result
1235 from conversions. Convert to use sim_io_eprintf rather than
1236 fprintf, and remove some debugging code.
1237 * cp1.h (fenr_FS): New define.
1238
577d8c4b
CD		 12392002-06-07 Chris Demetriou <cgd@broadcom.com>
1240
1241 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1242 rounding mode to sim FP rounding mode flag conversion code into...
1243 (rounding_mode): New function.
1244
196496ed
CD		 12452002-06-07 Chris Demetriou <cgd@broadcom.com>
1246
1247 * cp1.c: Clean up formatting of a few comments.
1248 (value_fpr): Reformat switch statement.
1249
cfe9ea23 12502002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1251 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1252
1253 * cp1.h: New file.
1254 * sim-main.h: Include cp1.h.
1255 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1256 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1257 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1258 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1259 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1260 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1261 * cp1.c: Don't include sim-fpu.h; already included by
1262 sim-main.h. Clean up formatting of some comments.
1263 (NaN, Equal, Less): Remove.
1264 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1265 (fp_cmp): New functions.
1266 * mips.igen (do_c_cond_fmt): Remove.
1267 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1268 Compare. Add result tracing.
1269 (CxC1): Remove, replace with...
1270 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1271 (DMxC1): Remove, replace with...
1272 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1273 (MxC1): Remove, replace with...
1274 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1275
ee7254b0
CD		 12762002-06-04 Chris Demetriou <cgd@broadcom.com>
1277
1278 * sim-main.h (FGRIDX): Remove, replace all uses with...
1279 (FGR_BASE): New macro.
1280 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1281 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1282 (NR_FGR, FGR): Likewise.
1283 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1284 * mips.igen: Likewise.
1285
d3eb724f
CD		 12862002-06-04 Chris Demetriou <cgd@broadcom.com>
1287
1288 * cp1.c: Add an FSF Copyright notice to this file.
1289
ba46ddd0 12902002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1291 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1292
1293 * cp1.c (Infinity): Remove.
1294 * sim-main.h (Infinity): Likewise.
1295
1296 * cp1.c (fp_unary, fp_binary): New functions.
1297 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1298 (fp_sqrt): New functions, implemented in terms of the above.
1299 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1300 (Recip, SquareRoot): Remove (replaced by functions above).
1301 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1302 (fp_recip, fp_sqrt): New prototypes.
1303 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1304 (Recip, SquareRoot): Replace prototypes with #defines which
1305 invoke the functions above.
72f4393d 1306
18d8a52d
CD		 13072002-06-03 Chris Demetriou <cgd@broadcom.com>
1308
1309 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1310 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1311 file, remove PARAMS from prototypes.
1312 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1313 simulator state arguments.
1314 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1315 pass simulator state arguments.
1316 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1317 (store_fpr, convert): Remove 'sd' argument.
1318 (value_fpr): Likewise. Convert to use 'SD' instead.
1319
0f154cbd
CD		 13202002-06-03 Chris Demetriou <cgd@broadcom.com>
1321
1322 * cp1.c (Min, Max): Remove #if 0'd functions.
1323 * sim-main.h (Min, Max): Remove.
1324
e80fc152
CD		 13252002-06-03 Chris Demetriou <cgd@broadcom.com>
1326
1327 * cp1.c: fix formatting of switch case and default labels.
1328 * interp.c: Likewise.
1329 * sim-main.c: Likewise.
1330
bad673a9
CD		 13312002-06-03 Chris Demetriou <cgd@broadcom.com>
1332
1333 * cp1.c: Clean up comments which describe FP formats.
1334 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1335
7cbea089 13362002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1337 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1338
1339 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1340 Broadcom SiByte SB-1 processor configurations.
1341 * configure: Regenerate.
1342 * sb1.igen: New file.
1343 * mips.igen: Include sb1.igen.
1344 (sb1): New model.
1345 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1346 * mdmx.igen: Add "sb1" model to all appropriate functions and
1347 instructions.
1348 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1349 (ob_func, ob_acc): Reference the above.
1350 (qh_acc): Adjust to keep the same size as ob_acc.
1351 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1352 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1353
909daa82
CD		 13542002-06-03 Chris Demetriou <cgd@broadcom.com>
1355
1356 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1357
f4f1b9f1 13582002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1359 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1360
1361 * mips.igen (mdmx): New (pseudo-)model.
1362 * mdmx.c, mdmx.igen: New files.
1363 * Makefile.in (SIM_OBJS): Add mdmx.o.
1364 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1365 New typedefs.
1366 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1367 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1368 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1369 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1370 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1371 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1372 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1373 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1374 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1375 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1376 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1377 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1378 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1379 (qh_fmtsel): New macros.
1380 (_sim_cpu): New member "acc".
1381 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1382 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1383
5accf1ff
CD		 13842002-05-01 Chris Demetriou <cgd@broadcom.com>
1385
1386 * interp.c: Use 'deprecated' rather than 'depreciated.'
1387 * sim-main.h: Likewise.
1388
402586aa
CD		 13892002-05-01 Chris Demetriou <cgd@broadcom.com>
1390
1391 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1392 which wouldn't compile anyway.
1393 * sim-main.h (unpredictable_action): New function prototype.
1394 (Unpredictable): Define to call igen function unpredictable().
1395 (NotWordValue): New macro to call igen function not_word_value().
1396 (UndefinedResult): Remove.
1397 * interp.c (undefined_result): Remove.
1398 (unpredictable_action): New function.
1399 * mips.igen (not_word_value, unpredictable): New functions.
1400 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1401 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1402 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1403 NotWordValue() to check for unpredictable inputs, then
1404 Unpredictable() to handle them.
1405
c9b9995a
CD		 14062002-02-24 Chris Demetriou <cgd@broadcom.com>
1407
1408 * mips.igen: Fix formatting of calls to Unpredictable().
1409
e1015982
AC		 14102002-04-20 Andrew Cagney <ac131313@redhat.com>
1411
1412 * interp.c (sim_open): Revert previous change.
1413
b882a66b
AO		 14142002-04-18 Alexandre Oliva <aoliva@redhat.com>
1415
1416 * interp.c (sim_open): Disable chunk of code that wrote code in
1417 vector table entries.
1418
c429b7dd
CD		 14192002-03-19 Chris Demetriou <cgd@broadcom.com>
1420
1421 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1422 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1423 unused definitions.
1424
37d146fa
CD		 14252002-03-19 Chris Demetriou <cgd@broadcom.com>
1426
1427 * cp1.c: Fix many formatting issues.
1428
07892c0b
CD		 14292002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1430
1431 * cp1.c (fpu_format_name): New function to replace...
1432 (DOFMT): This. Delete, and update all callers.
1433 (fpu_rounding_mode_name): New function to replace...
1434 (RMMODE): This. Delete, and update all callers.
1435
487f79b7
CD		 14362002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1437
1438 * interp.c: Move FPU support routines from here to...
1439 * cp1.c: Here. New file.
1440 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1441 (cp1.o): New target.
1442
1e799e28
CD		 14432002-03-12 Chris Demetriou <cgd@broadcom.com>
1444
1445 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1446 * mips.igen (mips32, mips64): New models, add to all instructions
1447 and functions as appropriate.
1448 (loadstore_ea, check_u64): New variant for model mips64.
1449 (check_fmt_p): New variant for models mipsV and mips64, remove
1450 mipsV model marking fro other variant.
1451 (SLL) Rename to...
1452 (SLLa) this.
1453 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1454 for mips32 and mips64.
1455 (DCLO, DCLZ): New instructions for mips64.
1456
82f728db
CD		 14572002-03-07 Chris Demetriou <cgd@broadcom.com>
1458
1459 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1460 immediate or code as a hex value with the "%#lx" format.
1461 (ANDI): Likewise, and fix printed instruction name.
1462
b96e7ef1
CD		 14632002-03-05 Chris Demetriou <cgd@broadcom.com>
1464
1465 * sim-main.h (UndefinedResult, Unpredictable): New macros
1466 which currently do nothing.
1467
d35d4f70
CD		 14682002-03-05 Chris Demetriou <cgd@broadcom.com>
1469
1470 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1471 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1472 (status_CU3): New definitions.
1473
1474 * sim-main.h (ExceptionCause): Add new values for MIPS32
1475 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1476 for DebugBreakPoint and NMIReset to note their status in
1477 MIPS32 and MIPS64.
1478 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1479 (SignalExceptionCacheErr): New exception macros.
1480
3ad6f714
CD		 14812002-03-05 Chris Demetriou <cgd@broadcom.com>
1482
1483 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1484 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1485 is always enabled.
1486 (SignalExceptionCoProcessorUnusable): Take as argument the
1487 unusable coprocessor number.
1488
86b77b47
CD		 14892002-03-05 Chris Demetriou <cgd@broadcom.com>
1490
1491 * mips.igen: Fix formatting of all SignalException calls.
1492
97a88e93 14932002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1494
1495 * sim-main.h (SIGNEXTEND): Remove.
1496
97a88e93 14972002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1498
1499 * mips.igen: Remove gencode comment from top of file, fix
1500 spelling in another comment.
1501
97a88e93 15022002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1503
1504 * mips.igen (check_fmt, check_fmt_p): New functions to check
1505 whether specific floating point formats are usable.
1506 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1507 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1508 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1509 Use the new functions.
1510 (do_c_cond_fmt): Remove format checks...
1511 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1512
97a88e93 15132002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1514
1515 * mips.igen: Fix formatting of check_fpu calls.
1516
41774c9d
CD		 15172002-03-03 Chris Demetriou <cgd@broadcom.com>
1518
1519 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1520
4a0bd876
CD		 15212002-03-03 Chris Demetriou <cgd@broadcom.com>
1522
1523 * mips.igen: Remove whitespace at end of lines.
1524
09297648
CD		 15252002-03-02 Chris Demetriou <cgd@broadcom.com>
1526
1527 * mips.igen (loadstore_ea): New function to do effective
1528 address calculations.
1529 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1530 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1531 CACHE): Use loadstore_ea to do effective address computations.
1532
043b7057
CD		 15332002-03-02 Chris Demetriou <cgd@broadcom.com>
1534
1535 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1536 * mips.igen (LL, CxC1, MxC1): Likewise.
1537
c1e8ada4
CD		 15382002-03-02 Chris Demetriou <cgd@broadcom.com>
1539
1540 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1541 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1542 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1543 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1544 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1545 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1546 Don't split opcode fields by hand, use the opcode field values
1547 provided by igen.
1548
3e1dca16
CD		 15492002-03-01 Chris Demetriou <cgd@broadcom.com>
1550
1551 * mips.igen (do_divu): Fix spacing.
1552
1553 * mips.igen (do_dsllv): Move to be right before DSLLV,
1554 to match the rest of the do_<shift> functions.
1555
fff8d27d
CD		 15562002-03-01 Chris Demetriou <cgd@broadcom.com>
1557
1558 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1559 DSRL32, do_dsrlv): Trace inputs and results.
1560
0d3e762b
CD		 15612002-03-01 Chris Demetriou <cgd@broadcom.com>
1562
1563 * mips.igen (CACHE): Provide instruction-printing string.
1564
1565 * interp.c (signal_exception): Comment tokens after #endif.
1566
eb5fcf93
CD		 15672002-02-28 Chris Demetriou <cgd@broadcom.com>
1568
1569 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1570 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1571 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1572 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1573 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1574 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1575 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1576 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1577
bb22bd7d
CD		 15782002-02-28 Chris Demetriou <cgd@broadcom.com>
1579
1580 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1581 instruction-printing string.
1582 (LWU): Use '64' as the filter flag.
1583
91a177cf
CD		 15842002-02-28 Chris Demetriou <cgd@broadcom.com>
1585
1586 * mips.igen (SDXC1): Fix instruction-printing string.
1587
387f484a
CD		 15882002-02-28 Chris Demetriou <cgd@broadcom.com>
1589
1590 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1591 filter flags "32,f".
1592
3d81f391
CD		 15932002-02-27 Chris Demetriou <cgd@broadcom.com>
1594
1595 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1596 as the filter flag.
1597
af5107af
CD		 15982002-02-27 Chris Demetriou <cgd@broadcom.com>
1599
1600 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1601 add a comma) so that it more closely match the MIPS ISA
1602 documentation opcode partitioning.
1603 (PREF): Put useful names on opcode fields, and include
1604 instruction-printing string.
1605
ca971540
CD		 16062002-02-27 Chris Demetriou <cgd@broadcom.com>
1607
1608 * mips.igen (check_u64): New function which in the future will
1609 check whether 64-bit instructions are usable and signal an
1610 exception if not. Currently a no-op.
1611 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1612 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1613 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1614 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1615
1616 * mips.igen (check_fpu): New function which in the future will
1617 check whether FPU instructions are usable and signal an exception
1618 if not. Currently a no-op.
1619 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1620 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1621 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1622 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1623 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1624 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1625 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1626 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1627
1c47a468
CD		 16282002-02-27 Chris Demetriou <cgd@broadcom.com>
1629
1630 * mips.igen (do_load_left, do_load_right): Move to be immediately
1631 following do_load.
1632 (do_store_left, do_store_right): Move to be immediately following
1633 do_store.
1634
603a98e7
CD		 16352002-02-27 Chris Demetriou <cgd@broadcom.com>
1636
1637 * mips.igen (mipsV): New model name. Also, add it to
1638 all instructions and functions where it is appropriate.
1639
c5d00cc7
CD		 16402002-02-18 Chris Demetriou <cgd@broadcom.com>
1641
1642 * mips.igen: For all functions and instructions, list model
1643 names that support that instruction one per line.
1644
074e9cb8
CD		 16452002-02-11 Chris Demetriou <cgd@broadcom.com>
1646
1647 * mips.igen: Add some additional comments about supported
1648 models, and about which instructions go where.
1649 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1650 order as is used in the rest of the file.
1651
9805e229
CD		 16522002-02-11 Chris Demetriou <cgd@broadcom.com>
1653
1654 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1655 indicating that ALU32_END or ALU64_END are there to check
1656 for overflow.
1657 (DADD): Likewise, but also remove previous comment about
1658 overflow checking.
1659
f701dad2
CD		 16602002-02-10 Chris Demetriou <cgd@broadcom.com>
1661
1662 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1663 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1664 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1665 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1666 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1667 fields (i.e., add and move commas) so that they more closely
1668 match the MIPS ISA documentation opcode partitioning.
1669
16702002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1671
72f4393d
L		 1672 * mips.igen (ADDI): Print immediate value.
1673 (BREAK): Print code.
1674 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1675 (SLL): Print "nop" specially, and don't run the code
1676 that does the shift for the "nop" case.
20ae0098 1677
9e52972e
FF		 16782001-11-17 Fred Fish <fnf@redhat.com>
1679
1680 * sim-main.h (float_operation): Move enum declaration outside
1681 of _sim_cpu struct declaration.
1682
c0efbca4
JB		 16832001-04-12 Jim Blandy <jimb@redhat.com>
1684
1685 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1686 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1687 set of the FCSR.
1688 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1689 PENDING_FILL, and you can get the intended effect gracefully by
1690 calling PENDING_SCHED directly.
1691
fb891446
BE		 16922001-02-23 Ben Elliston <bje@redhat.com>
1693
1694 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1695 already defined elsewhere.
1696
8030f857
BE		 16972001-02-19 Ben Elliston <bje@redhat.com>
1698
1699 * sim-main.h (sim_monitor): Return an int.
1700 * interp.c (sim_monitor): Add return values.
1701 (signal_exception): Handle error conditions from sim_monitor.
1702
56b48a7a
CD		 17032001-02-08 Ben Elliston <bje@redhat.com>
1704
1705 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1706 (store_memory): Likewise, pass cia to sim_core_write*.
1707
d3ee60d9
FCE		 17082000-10-19 Frank Ch. Eigler <fche@redhat.com>
1709
1710 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1711 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1712
071da002
AC		 1713Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1716 * Makefile.in: Don't delete *.igen when cleaning directory.
1717
a28c02cd
AC		 1718Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1719
1720 * m16.igen (break): Call SignalException not sim_engine_halt.
1721
80ee11fa
AC		 1722Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1723
1724 From Jason Eckhardt:
1725 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1726
673388c0
AC		 1727Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1728
1729 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1730
4c0deff4
NC		 17312000-05-24 Michael Hayes <mhayes@cygnus.com>
1732
1733 * mips.igen (do_dmultx): Fix typo.
1734
eb2d80b4
AC		 1735Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1738
dd37a34b
AC		 1739Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1742
4c0deff4
NC		 17432000-04-12 Frank Ch. Eigler <fche@redhat.com>
1744
1745 * sim-main.h (GPR_CLEAR): Define macro.
1746
e30db738
AC		 1747Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * interp.c (decode_coproc): Output long using %lx and not %s.
1750
cb7450ea
FCE		 17512000-03-21 Frank Ch. Eigler <fche@redhat.com>
1752
1753 * interp.c (sim_open): Sort & extend dummy memory regions for
1754 --board=jmr3904 for eCos.
1755
a3027dd7
FCE		 17562000-03-02 Frank Ch. Eigler <fche@redhat.com>
1757
1758 * configure: Regenerated.
1759
1760Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1761
1762 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1763 calls, conditional on the simulator being in verbose mode.
1764
dfcd3bfb
JM		 1765Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1766
1767 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1768 cache don't get ReservedInstruction traps.
1769
c2d11a7d
JM		 17701999-11-29 Mark Salter <msalter@cygnus.com>
1771
1772 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1773 to clear status bits in sdisr register. This is how the hardware works.
1774
1775 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1776 being used by cygmon.
1777
4ce44c66
JM		 17781999-11-11 Andrew Haley <aph@cygnus.com>
1779
1780 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1781 instructions.
1782
cff3e48b
JM		 1783Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1784
1785 * mips.igen (MULT): Correct previous mis-applied patch.
1786
d4f3574e
SS		 1787Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1788
1789 * mips.igen (delayslot32): Handle sequence like
1790 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1791 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1792 (MULT): Actually pass the third register...
1793
17941999-09-03 Mark Salter <msalter@cygnus.com>
1795
1796 * interp.c (sim_open): Added more memory aliases for additional
1797 hardware being touched by cygmon on jmr3904 board.
1798
1799Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * configure: Regenerated to track ../common/aclocal.m4 changes.
1802
a0b3c4fd
JM		 1803Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1804
1805 * interp.c (sim_store_register): Handle case where client - GDB -
1806 specifies that a 4 byte register is 8 bytes in size.
1807 (sim_fetch_register): Ditto.
72f4393d 1808
adf40b2e
JM		 18091999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1810
1811 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1812 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1813 (idt_monitor_base): Base address for IDT monitor traps.
1814 (pmon_monitor_base): Ditto for PMON.
1815 (lsipmon_monitor_base): Ditto for LSI PMON.
1816 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1817 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1818 (sim_firmware_command): New function.
1819 (mips_option_handler): Call it for OPTION_FIRMWARE.
1820 (sim_open): Allocate memory for idt_monitor region. If "--board"
1821 option was given, add no monitor by default. Add BREAK hooks only if
1822 monitors are also there.
72f4393d 1823
43e526b9
JM		 1824Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1825
1826 * interp.c (sim_monitor): Flush output before reading input.
1827
1828Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * tconfig.in (SIM_HANDLES_LMA): Always define.
1831
1832Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 From Mark Salter <msalter@cygnus.com>:
1835 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1836 (sim_open): Add setup for BSP board.
1837
9846de1b
JM		 1838Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1841 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1842 them as unimplemented.
1843
cd0fc7c3
SS		 18441999-05-08 Felix Lee <flee@cygnus.com>
1845
1846 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1847
7a292a7a
SS		 18481999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1849
1850 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1851
1852Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1853
1854 * configure.in: Any mips64vr5*-*-* target should have
1855 -DTARGET_ENABLE_FR=1.
1856 (default_endian): Any mips64vr*el-*-* target should default to
1857 LITTLE_ENDIAN.
1858 * configure: Re-generate.
1859
18601999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1861
1862 * mips.igen (ldl): Extend from _16_, not 32.
1863
1864Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1865
1866 * interp.c (sim_store_register): Force registers written to by GDB
1867 into an un-interpreted state.
1868
c906108c
SS		 18691999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1870
1871 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1872 CPU, start periodic background I/O polls.
72f4393d 1873 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1874
18751998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1876
1877 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1878
c906108c
SS		 1879Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1880
1881 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1882 case statement.
1883
18841998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1885
1886 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1887 (load_word): Call SIM_CORE_SIGNAL hook on error.
1888 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1889 starting. For exception dispatching, pass PC instead of NULL_CIA.
1890 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1891 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1892 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1893 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1894 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1895 * mips.igen (*): Replace memory-related SignalException* calls
1896 with references to SIM_CORE_SIGNAL hook.
72f4393d 1897
c906108c
SS		 1898 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1899 fix.
1900 * sim-main.c (*): Minor warning cleanups.
72f4393d 1901
c906108c
SS		 19021998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1903
1904 * m16.igen (DADDIU5): Correct type-o.
1905
1906Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1907
1908 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1909 variables.
1910
1911Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1912
1913 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1914 to include path.
1915 (interp.o): Add dependency on itable.h
1916 (oengine.c, gencode): Delete remaining references.
1917 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1918
c906108c 19191998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1920
c906108c
SS		 1921 * vr4run.c: New.
1922 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1923 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1924 tmp-run-hack) : New.
1925 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1926 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1927 Drop the "64" qualifier to get the HACK generator working.
1928 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1929 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1930 qualifier to get the hack generator working.
1931 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1932 (DSLL): Use do_dsll.
1933 (DSLLV): Use do_dsllv.
1934 (DSRA): Use do_dsra.
1935 (DSRL): Use do_dsrl.
1936 (DSRLV): Use do_dsrlv.
1937 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1938 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1939 get the HACK generator working.
1940 (MACC) Rename to get the HACK generator working.
1941 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1942
c906108c
SS		 19431998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1944
1945 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1946 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1947
c906108c
SS		 19481998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1949
1950 * mips/interp.c (DEBUG): Cleanups.
1951
19521998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1953
1954 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1955 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1956
c906108c
SS		 19571998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1958
1959 * interp.c (sim_close): Uninstall modules.
1960
1961Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1962
1963 * sim-main.h, interp.c (sim_monitor): Change to global
1964 function.
1965
1966Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * configure.in (vr4100): Only include vr4100 instructions in
1969 simulator.
1970 * configure: Re-generate.
1971 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1972
1973Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1976 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1977 true alternative.
1978
1979 * configure.in (sim_default_gen, sim_use_gen): Replace with
1980 sim_gen.
1981 (--enable-sim-igen): Delete config option. Always using IGEN.
1982 * configure: Re-generate.
72f4393d 1983
c906108c
SS		 1984 * Makefile.in (gencode): Kill, kill, kill.
1985 * gencode.c: Ditto.
72f4393d 1986
c906108c
SS		 1987Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1990 bit mips16 igen simulator.
1991 * configure: Re-generate.
1992
1993 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1994 as part of vr4100 ISA.
1995 * vr.igen: Mark all instructions as 64 bit only.
1996
1997Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2000 Pacify GCC.
2001
2002Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2005 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2006 * configure: Re-generate.
2007
2008 * m16.igen (BREAK): Define breakpoint instruction.
2009 (JALX32): Mark instruction as mips16 and not r3900.
2010 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2011
2012 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2013
2014Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2015
2016 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2017 insn as a debug breakpoint.
2018
2019 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2020 pending.slot_size.
2021 (PENDING_SCHED): Clean up trace statement.
2022 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2023 (PENDING_FILL): Delay write by only one cycle.
2024 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2025
2026 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2027 of pending writes.
2028 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2029 32 & 64.
2030 (pending_tick): Move incrementing of index to FOR statement.
2031 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2032
c906108c
SS		 2033 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2034 build simulator.
2035 * configure: Re-generate.
72f4393d 2036
c906108c
SS		 2037 * interp.c (sim_engine_run OLD): Delete explicit call to
2038 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2039
c906108c
SS		 2040Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2041
2042 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2043 interrupt level number to match changed SignalExceptionInterrupt
2044 macro.
2045
2046Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2047
2048 * interp.c: #include "itable.h" if WITH_IGEN.
2049 (get_insn_name): New function.
2050 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2051 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2052
2053Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2054
2055 * configure: Rebuilt to inhale new common/aclocal.m4.
2056
2057Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2058
2059 * dv-tx3904sio.c: Include sim-assert.h.
2060
2061Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2062
2063 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2064 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2065 Reorganize target-specific sim-hardware checks.
2066 * configure: rebuilt.
2067 * interp.c (sim_open): For tx39 target boards, set
2068 OPERATING_ENVIRONMENT, add tx3904sio devices.
2069 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2070 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2071
c906108c
SS		 2072 * dv-tx3904irc.c: Compiler warning clean-up.
2073 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2074 frequent hw-trace messages.
2075
2076Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2079
2080Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2083
2084 * vr.igen: New file.
2085 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2086 * mips.igen: Define vr4100 model. Include vr.igen.
2087Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2088
2089 * mips.igen (check_mf_hilo): Correct check.
2090
2091Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * sim-main.h (interrupt_event): Add prototype.
2094
2095 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2096 register_ptr, register_value.
2097 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2098
2099 * sim-main.h (tracefh): Make extern.
2100
2101Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2102
2103 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2104 Reduce unnecessarily high timer event frequency.
c906108c 2105 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2106
c906108c
SS		 2107Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2108
2109 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2110 to allay warnings.
2111 (interrupt_event): Made non-static.
72f4393d 2112
c906108c
SS		 2113 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2114 interchange of configuration values for external vs. internal
2115 clock dividers.
72f4393d 2116
c906108c
SS		 2117Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2118
72f4393d 2119 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2120 simulator-reserved break instructions.
2121 * gencode.c (build_instruction): Ditto.
2122 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2123 reserved instructions now use exception vector, rather
c906108c
SS		 2124 than halting sim.
2125 * sim-main.h: Moved magic constants to here.
2126
2127Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2128
2129 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2130 register upon non-zero interrupt event level, clear upon zero
2131 event value.
2132 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2133 by passing zero event value.
2134 (*_io_{read,write}_buffer): Endianness fixes.
2135 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2136 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2137
2138 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2139 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2140
c906108c
SS		 2141Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2142
72f4393d 2143 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2144 and BigEndianCPU.
2145
2146Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2147
2148 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2149 parts.
2150 * configure: Update.
2151
2152Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2153
2154 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2155 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2156 * configure.in: Include tx3904tmr in hw_device list.
2157 * configure: Rebuilt.
2158 * interp.c (sim_open): Instantiate three timer instances.
2159 Fix address typo of tx3904irc instance.
2160
2161Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2162
2163 * interp.c (signal_exception): SystemCall exception now uses
2164 the exception vector.
2165
2166Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2167
2168 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2169 to allay warnings.
2170
2171Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2172
2173 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2174
2175Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2176
2177 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2178
2179 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2180 sim-main.h. Declare a struct hw_descriptor instead of struct
2181 hw_device_descriptor.
2182
2183Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2186 right bits and then re-align left hand bytes to correct byte
2187 lanes. Fix incorrect computation in do_store_left when loading
2188 bytes from second word.
2189
2190Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2193 * interp.c (sim_open): Only create a device tree when HW is
2194 enabled.
2195
2196 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2197 * interp.c (signal_exception): Ditto.
2198
2199Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2200
2201 * gencode.c: Mark BEGEZALL as LIKELY.
2202
2203Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2206 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2207
c906108c
SS		 2208Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2209
2210 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2211 modules. Recognize TX39 target with "mips*tx39" pattern.
2212 * configure: Rebuilt.
2213 * sim-main.h (*): Added many macros defining bits in
2214 TX39 control registers.
2215 (SignalInterrupt): Send actual PC instead of NULL.
2216 (SignalNMIReset): New exception type.
2217 * interp.c (board): New variable for future use to identify
2218 a particular board being simulated.
2219 (mips_option_handler,mips_options): Added "--board" option.
2220 (interrupt_event): Send actual PC.
2221 (sim_open): Make memory layout conditional on board setting.
2222 (signal_exception): Initial implementation of hardware interrupt
2223 handling. Accept another break instruction variant for simulator
2224 exit.
2225 (decode_coproc): Implement RFE instruction for TX39.
2226 (mips.igen): Decode RFE instruction as such.
2227 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2228 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2229 bbegin to implement memory map.
2230 * dv-tx3904cpu.c: New file.
2231 * dv-tx3904irc.c: New file.
2232
2233Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2234
2235 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2236
2237Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2238
2239 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2240 with calls to check_div_hilo.
2241
2242Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2243
2244 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2245 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2246 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2247 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2248 with calls to check_mult_hilo.
2249 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2250 with calls to check_div_hilo.
2251
2252Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2253
2254 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2255 Document a replacement.
2256
2257Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2258
2259 * interp.c (sim_monitor): Make mon_printf work.
2260
2261Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2262
2263 * sim-main.h (INSN_NAME): New arg `cpu'.
2264
2265Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2266
72f4393d 2267 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2268
2269Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2270
2271 * configure: Regenerated to track ../common/aclocal.m4 changes.
2272 * config.in: Ditto.
2273
2274Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2275
2276 * acconfig.h: New file.
2277 * configure.in: Reverted change of Apr 24; use sinclude again.
2278
2279Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2280
2281 * configure: Regenerated to track ../common/aclocal.m4 changes.
2282 * config.in: Ditto.
2283
2284Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2285
2286 * configure.in: Don't call sinclude.
2287
2288Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2289
2290 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2291
2292Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2293
2294 * mips.igen (ERET): Implement.
2295
2296 * interp.c (decode_coproc): Return sign-extended EPC.
2297
2298 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2299
2300 * interp.c (signal_exception): Do not ignore Trap.
2301 (signal_exception): On TRAP, restart at exception address.
2302 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2303 (signal_exception): Update.
2304 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2305 so that TRAP instructions are caught.
2306
2307Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2310 contains HI/LO access history.
2311 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2312 (HIACCESS, LOACCESS): Delete, replace with
2313 (HIHISTORY, LOHISTORY): New macros.
2314 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2315
c906108c
SS		 2316 * gencode.c (build_instruction): Do not generate checks for
2317 correct HI/LO register usage.
2318
2319 * interp.c (old_engine_run): Delete checks for correct HI/LO
2320 register usage.
2321
2322 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2323 check_mf_cycles): New functions.
2324 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2325 do_divu, domultx, do_mult, do_multu): Use.
2326
2327 * tx.igen ("madd", "maddu"): Use.
72f4393d 2328
c906108c
SS		 2329Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * mips.igen (DSRAV): Use function do_dsrav.
2332 (SRAV): Use new function do_srav.
2333
2334 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2335 (B): Sign extend 11 bit immediate.
2336 (EXT-B*): Shift 16 bit immediate left by 1.
2337 (ADDIU*): Don't sign extend immediate value.
2338
2339Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2340
2341 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2342
2343 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2344 functions.
2345
2346 * mips.igen (delayslot32, nullify_next_insn): New functions.
2347 (m16.igen): Always include.
2348 (do_*): Add more tracing.
2349
2350 * m16.igen (delayslot16): Add NIA argument, could be called by a
2351 32 bit MIPS16 instruction.
72f4393d 2352
c906108c
SS		 2353 * interp.c (ifetch16): Move function from here.
2354 * sim-main.c (ifetch16): To here.
72f4393d 2355
c906108c
SS		 2356 * sim-main.c (ifetch16, ifetch32): Update to match current
2357 implementations of LH, LW.
2358 (signal_exception): Don't print out incorrect hex value of illegal
2359 instruction.
2360
2361Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2362
2363 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2364 instruction.
2365
2366 * m16.igen: Implement MIPS16 instructions.
72f4393d 2367
c906108c
SS		 2368 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2369 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2370 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2371 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2372 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2373 bodies of corresponding code from 32 bit insn to these. Also used
2374 by MIPS16 versions of functions.
72f4393d 2375
c906108c
SS		 2376 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2377 (IMEM16): Drop NR argument from macro.
2378
2379Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * Makefile.in (SIM_OBJS): Add sim-main.o.
2382
2383 * sim-main.h (address_translation, load_memory, store_memory,
2384 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2385 as INLINE_SIM_MAIN.
2386 (pr_addr, pr_uword64): Declare.
2387 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2388
c906108c
SS		 2389 * interp.c (address_translation, load_memory, store_memory,
2390 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2391 from here.
2392 * sim-main.c: To here. Fix compilation problems.
72f4393d 2393
c906108c
SS		 2394 * configure.in: Enable inlining.
2395 * configure: Re-config.
2396
2397Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2398
2399 * configure: Regenerated to track ../common/aclocal.m4 changes.
2400
2401Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * mips.igen: Include tx.igen.
2404 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2405 * tx.igen: New file, contains MADD and MADDU.
2406
2407 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2408 the hardwired constant `7'.
2409 (store_memory): Ditto.
2410 (LOADDRMASK): Move definition to sim-main.h.
2411
2412 mips.igen (MTC0): Enable for r3900.
2413 (ADDU): Add trace.
2414
2415 mips.igen (do_load_byte): Delete.
2416 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2417 do_store_right): New functions.
2418 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2419
2420 configure.in: Let the tx39 use igen again.
2421 configure: Update.
72f4393d 2422
c906108c
SS		 2423Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2424
2425 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2426 not an address sized quantity. Return zero for cache sizes.
2427
2428Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2429
2430 * mips.igen (r3900): r3900 does not support 64 bit integer
2431 operations.
2432
2433Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2434
2435 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2436 than igen one.
2437 * configure : Rebuild.
72f4393d 2438
c906108c
SS		 2439Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2440
2441 * configure: Regenerated to track ../common/aclocal.m4 changes.
2442
2443Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2446
2447Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2448
2449 * configure: Regenerated to track ../common/aclocal.m4 changes.
2450 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2451
2452Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2453
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2455
2456Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2457
2458 * interp.c (Max, Min): Comment out functions. Not yet used.
2459
2460Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * configure: Regenerated to track ../common/aclocal.m4 changes.
2463
2464Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2465
2466 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2467 configurable settings for stand-alone simulator.
72f4393d 2468
c906108c 2469 * configure.in: Added X11 search, just in case.
72f4393d 2470
c906108c
SS		 2471 * configure: Regenerated.
2472
2473Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2474
2475 * interp.c (sim_write, sim_read, load_memory, store_memory):
2476 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2477
2478Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2479
2480 * sim-main.h (GETFCC): Return an unsigned value.
2481
2482Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2483
2484 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2485 (DADD): Result destination is RD not RT.
2486
2487Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2488
2489 * sim-main.h (HIACCESS, LOACCESS): Always define.
2490
2491 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2492
2493 * interp.c (sim_info): Delete.
2494
2495Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2496
2497 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2498 (mips_option_handler): New argument `cpu'.
2499 (sim_open): Update call to sim_add_option_table.
2500
2501Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * mips.igen (CxC1): Add tracing.
2504
2505Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2506
2507 * sim-main.h (Max, Min): Declare.
2508
2509 * interp.c (Max, Min): New functions.
2510
2511 * mips.igen (BC1): Add tracing.
72f4393d 2512
c906108c 2513Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2514
c906108c 2515 * interp.c Added memory map for stack in vr4100
72f4393d 2516
c906108c
SS		 2517Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2518
2519 * interp.c (load_memory): Add missing "break"'s.
2520
2521Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2522
2523 * interp.c (sim_store_register, sim_fetch_register): Pass in
2524 length parameter. Return -1.
2525
2526Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2527
2528 * interp.c: Added hardware init hook, fixed warnings.
2529
2530Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2533
2534Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2535
2536 * interp.c (ifetch16): New function.
2537
2538 * sim-main.h (IMEM32): Rename IMEM.
2539 (IMEM16_IMMED): Define.
2540 (IMEM16): Define.
2541 (DELAY_SLOT): Update.
72f4393d 2542
c906108c 2543 * m16run.c (sim_engine_run): New file.
72f4393d 2544
c906108c
SS		 2545 * m16.igen: All instructions except LB.
2546 (LB): Call do_load_byte.
2547 * mips.igen (do_load_byte): New function.
2548 (LB): Call do_load_byte.
2549
2550 * mips.igen: Move spec for insn bit size and high bit from here.
2551 * Makefile.in (tmp-igen, tmp-m16): To here.
2552
2553 * m16.dc: New file, decode mips16 instructions.
2554
2555 * Makefile.in (SIM_NO_ALL): Define.
2556 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2557
2558Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2559
2560 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2561 point unit to 32 bit registers.
2562 * configure: Re-generate.
2563
2564Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2565
2566 * configure.in (sim_use_gen): Make IGEN the default simulator
2567 generator for generic 32 and 64 bit mips targets.
2568 * configure: Re-generate.
2569
2570Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2571
2572 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2573 bitsize.
2574
2575 * interp.c (sim_fetch_register, sim_store_register): Read/write
2576 FGR from correct location.
2577 (sim_open): Set size of FGR's according to
2578 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2579
c906108c
SS		 2580 * sim-main.h (FGR): Store floating point registers in a separate
2581 array.
2582
2583Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * configure: Regenerated to track ../common/aclocal.m4 changes.
2586
2587Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2588
2589 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2590
2591 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2592
2593 * interp.c (pending_tick): New function. Deliver pending writes.
2594
2595 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2596 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2597 it can handle mixed sized quantites and single bits.
72f4393d 2598
c906108c
SS		 2599Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2600
2601 * interp.c (oengine.h): Do not include when building with IGEN.
2602 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2603 (sim_info): Ditto for PROCESSOR_64BIT.
2604 (sim_monitor): Replace ut_reg with unsigned_word.
2605 (*): Ditto for t_reg.
2606 (LOADDRMASK): Define.
2607 (sim_open): Remove defunct check that host FP is IEEE compliant,
2608 using software to emulate floating point.
2609 (value_fpr, ...): Always compile, was conditional on HASFPU.
2610
2611Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2614 size.
2615
2616 * interp.c (SD, CPU): Define.
2617 (mips_option_handler): Set flags in each CPU.
2618 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2619 (sim_close): Do not clear STATE, deleted anyway.
2620 (sim_write, sim_read): Assume CPU zero's vm should be used for
2621 data transfers.
2622 (sim_create_inferior): Set the PC for all processors.
2623 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2624 argument.
2625 (mips16_entry): Pass correct nr of args to store_word, load_word.
2626 (ColdReset): Cold reset all cpu's.
2627 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2628 (sim_monitor, load_memory, store_memory, signal_exception): Use
2629 `CPU' instead of STATE_CPU.
2630
2631
2632 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2633 SD or CPU_.
72f4393d 2634
c906108c
SS		 2635 * sim-main.h (signal_exception): Add sim_cpu arg.
2636 (SignalException*): Pass both SD and CPU to signal_exception.
2637 * interp.c (signal_exception): Update.
72f4393d 2638
c906108c
SS		 2639 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2640 Ditto
2641 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2642 address_translation): Ditto
2643 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2644
c906108c
SS		 2645Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2646
2647 * configure: Regenerated to track ../common/aclocal.m4 changes.
2648
2649Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2650
2651 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2652
72f4393d 2653 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2654
2655 * sim-main.h (CPU_CIA): Delete.
2656 (SET_CIA, GET_CIA): Define
2657
2658Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2659
2660 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2661 regiser.
2662
2663 * configure.in (default_endian): Configure a big-endian simulator
2664 by default.
2665 * configure: Re-generate.
72f4393d 2666
c906108c
SS		 2667Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2668
2669 * configure: Regenerated to track ../common/aclocal.m4 changes.
2670
2671Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2672
2673 * interp.c (sim_monitor): Handle Densan monitor outbyte
2674 and inbyte functions.
2675
26761997-12-29 Felix Lee <flee@cygnus.com>
2677
2678 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2679
2680Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2681
2682 * Makefile.in (tmp-igen): Arrange for $zero to always be
2683 reset to zero after every instruction.
2684
2685Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2686
2687 * configure: Regenerated to track ../common/aclocal.m4 changes.
2688 * config.in: Ditto.
2689
2690Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2691
2692 * mips.igen (MSUB): Fix to work like MADD.
2693 * gencode.c (MSUB): Similarly.
2694
2695Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2696
2697 * configure: Regenerated to track ../common/aclocal.m4 changes.
2698
2699Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700
2701 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2702
2703Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * sim-main.h (sim-fpu.h): Include.
2706
2707 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2708 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2709 using host independant sim_fpu module.
2710
2711Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * interp.c (signal_exception): Report internal errors with SIGABRT
2714 not SIGQUIT.
2715
2716 * sim-main.h (C0_CONFIG): New register.
2717 (signal.h): No longer include.
2718
2719 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2720
2721Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2722
2723 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2724
2725Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2726
2727 * mips.igen: Tag vr5000 instructions.
2728 (ANDI): Was missing mipsIV model, fix assembler syntax.
2729 (do_c_cond_fmt): New function.
2730 (C.cond.fmt): Handle mips I-III which do not support CC field
2731 separatly.
2732 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2733 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2734 in IV3.2 spec.
2735 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2736 vr5000 which saves LO in a GPR separatly.
72f4393d 2737
c906108c
SS		 2738 * configure.in (enable-sim-igen): For vr5000, select vr5000
2739 specific instructions.
2740 * configure: Re-generate.
72f4393d 2741
c906108c
SS		 2742Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2745
2746 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2747 fmt_uninterpreted_64 bit cases to switch. Convert to
2748 fmt_formatted,
2749
2750 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2751
2752 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2753 as specified in IV3.2 spec.
2754 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2755
2756Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2757
2758 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2759 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2760 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2761 PENDING_FILL versions of instructions. Simplify.
2762 (X): New function.
2763 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2764 instructions.
2765 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2766 a signed value.
2767 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2768
c906108c
SS		 2769 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2770 global.
2771 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2772
2773Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774
2775 * gencode.c (build_mips16_operands): Replace IPC with cia.
2776
2777 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2778 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2779 IPC to `cia'.
2780 (UndefinedResult): Replace function with macro/function
2781 combination.
2782 (sim_engine_run): Don't save PC in IPC.
2783
2784 * sim-main.h (IPC): Delete.
2785
2786
2787 * interp.c (signal_exception, store_word, load_word,
2788 address_translation, load_memory, store_memory, cache_op,
2789 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2790 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2791 current instruction address - cia - argument.
2792 (sim_read, sim_write): Call address_translation directly.
2793 (sim_engine_run): Rename variable vaddr to cia.
2794 (signal_exception): Pass cia to sim_monitor
72f4393d 2795
c906108c
SS		 2796 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2797 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2798 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2799
2800 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2801 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2802 SIM_ASSERT.
72f4393d 2803
c906108c
SS		 2804 * interp.c (signal_exception): Pass restart address to
2805 sim_engine_restart.
2806
2807 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2808 idecode.o): Add dependency.
2809
2810 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2811 Delete definitions
2812 (DELAY_SLOT): Update NIA not PC with branch address.
2813 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2814
2815 * mips.igen: Use CIA not PC in branch calculations.
2816 (illegal): Call SignalException.
2817 (BEQ, ADDIU): Fix assembler.
2818
2819Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2820
2821 * m16.igen (JALX): Was missing.
2822
2823 * configure.in (enable-sim-igen): New configuration option.
2824 * configure: Re-generate.
72f4393d 2825
c906108c
SS		 2826 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2827
2828 * interp.c (load_memory, store_memory): Delete parameter RAW.
2829 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2830 bypassing {load,store}_memory.
2831
2832 * sim-main.h (ByteSwapMem): Delete definition.
2833
2834 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2835
2836 * interp.c (sim_do_command, sim_commands): Delete mips specific
2837 commands. Handled by module sim-options.
72f4393d 2838
c906108c
SS		 2839 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2840 (WITH_MODULO_MEMORY): Define.
2841
2842 * interp.c (sim_info): Delete code printing memory size.
2843
2844 * interp.c (mips_size): Nee sim_size, delete function.
2845 (power2): Delete.
2846 (monitor, monitor_base, monitor_size): Delete global variables.
2847 (sim_open, sim_close): Delete code creating monitor and other
2848 memory regions. Use sim-memopts module, via sim_do_commandf, to
2849 manage memory regions.
2850 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2851
c906108c
SS		 2852 * interp.c (address_translation): Delete all memory map code
2853 except line forcing 32 bit addresses.
2854
2855Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2856
2857 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2858 trace options.
2859
2860 * interp.c (logfh, logfile): Delete globals.
2861 (sim_open, sim_close): Delete code opening & closing log file.
2862 (mips_option_handler): Delete -l and -n options.
2863 (OPTION mips_options): Ditto.
2864
2865 * interp.c (OPTION mips_options): Rename option trace to dinero.
2866 (mips_option_handler): Update.
2867
2868Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2869
2870 * interp.c (fetch_str): New function.
2871 (sim_monitor): Rewrite using sim_read & sim_write.
2872 (sim_open): Check magic number.
2873 (sim_open): Write monitor vectors into memory using sim_write.
2874 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2875 (sim_read, sim_write): Simplify - transfer data one byte at a
2876 time.
2877 (load_memory, store_memory): Clarify meaning of parameter RAW.
2878
2879 * sim-main.h (isHOST): Defete definition.
2880 (isTARGET): Mark as depreciated.
2881 (address_translation): Delete parameter HOST.
2882
2883 * interp.c (address_translation): Delete parameter HOST.
2884
2885Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2886
72f4393d 2887 * mips.igen:
c906108c
SS		 2888
2889 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2890 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2891
2892Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2893
2894 * mips.igen: Add model filter field to records.
2895
2896Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2897
2898 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2899
c906108c
SS		 2900 interp.c (sim_engine_run): Do not compile function sim_engine_run
2901 when WITH_IGEN == 1.
2902
2903 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2904 target architecture.
2905
2906 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2907 igen. Replace with configuration variables sim_igen_flags /
2908 sim_m16_flags.
2909
2910 * m16.igen: New file. Copy mips16 insns here.
2911 * mips.igen: From here.
2912
2913Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2914
2915 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2916 to top.
2917 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2918
2919Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2920
2921 * gencode.c (build_instruction): Follow sim_write's lead in using
2922 BigEndianMem instead of !ByteSwapMem.
2923
2924Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925
2926 * configure.in (sim_gen): Dependent on target, select type of
2927 generator. Always select old style generator.
2928
2929 configure: Re-generate.
2930
2931 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2932 targets.
2933 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2934 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2935 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2936 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2937 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2938
c906108c
SS		 2939Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940
2941 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2942
2943 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2944 CURRENT_FLOATING_POINT instead.
2945
2946 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2947 (address_translation): Raise exception InstructionFetch when
2948 translation fails and isINSTRUCTION.
72f4393d 2949
c906108c
SS		 2950 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2951 sim_engine_run): Change type of of vaddr and paddr to
2952 address_word.
2953 (address_translation, prefetch, load_memory, store_memory,
2954 cache_op): Change type of vAddr and pAddr to address_word.
2955
2956 * gencode.c (build_instruction): Change type of vaddr and paddr to
2957 address_word.
2958
2959Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960
2961 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2962 macro to obtain result of ALU op.
2963
2964Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * interp.c (sim_info): Call profile_print.
2967
2968Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2969
2970 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2971
2972 * sim-main.h (WITH_PROFILE): Do not define, defined in
2973 common/sim-config.h. Use sim-profile module.
2974 (simPROFILE): Delete defintion.
2975
2976 * interp.c (PROFILE): Delete definition.
2977 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2978 (sim_close): Delete code writing profile histogram.
2979 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2980 Delete.
2981 (sim_engine_run): Delete code profiling the PC.
2982
2983Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2986
2987 * interp.c (sim_monitor): Make register pointers of type
2988 unsigned_word*.
2989
2990 * sim-main.h: Make registers of type unsigned_word not
2991 signed_word.
2992
2993Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2994
2995 * interp.c (sync_operation): Rename from SyncOperation, make
2996 global, add SD argument.
2997 (prefetch): Rename from Prefetch, make global, add SD argument.
2998 (decode_coproc): Make global.
2999
3000 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3001
3002 * gencode.c (build_instruction): Generate DecodeCoproc not
3003 decode_coproc calls.
3004
3005 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3006 (SizeFGR): Move to sim-main.h
3007 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3008 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3009 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3010 sim-main.h.
3011 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3012 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3013 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3014 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3015 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3016 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3017
c906108c
SS		 3018 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3019 exception.
3020 (sim-alu.h): Include.
3021 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3022 (sim_cia): Typedef to instruction_address.
72f4393d 3023
c906108c
SS		 3024Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * Makefile.in (interp.o): Rename generated file engine.c to
3027 oengine.c.
72f4393d 3028
c906108c 3029 * interp.c: Update.
72f4393d 3030
c906108c
SS		 3031Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3032
3033 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3034
c906108c
SS		 3035Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3036
3037 * gencode.c (build_instruction): For "FPSQRT", output correct
3038 number of arguments to Recip.
72f4393d 3039
c906108c
SS		 3040Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3041
3042 * Makefile.in (interp.o): Depends on sim-main.h
3043
3044 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3045
3046 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3047 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3048 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3049 STATE, DSSTATE): Define
3050 (GPR, FGRIDX, ..): Define.
3051
3052 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3053 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3054 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3055
c906108c 3056 * interp.c: Update names to match defines from sim-main.h
72f4393d 3057
c906108c
SS		 3058Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3059
3060 * interp.c (sim_monitor): Add SD argument.
3061 (sim_warning): Delete. Replace calls with calls to
3062 sim_io_eprintf.
3063 (sim_error): Delete. Replace calls with sim_io_error.
3064 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3065 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3066 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3067 argument.
3068 (mips_size): Rename from sim_size. Add SD argument.
3069
3070 * interp.c (simulator): Delete global variable.
3071 (callback): Delete global variable.
3072 (mips_option_handler, sim_open, sim_write, sim_read,
3073 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3074 sim_size,sim_monitor): Use sim_io_* not callback->*.
3075 (sim_open): ZALLOC simulator struct.
3076 (PROFILE): Do not define.
3077
3078Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3081 support.h with corresponding code.
3082
3083 * sim-main.h (word64, uword64), support.h: Move definition to
3084 sim-main.h.
3085 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3086
3087 * support.h: Delete
3088 * Makefile.in: Update dependencies
3089 * interp.c: Do not include.
72f4393d 3090
c906108c
SS		 3091Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3092
3093 * interp.c (address_translation, load_memory, store_memory,
3094 cache_op): Rename to from AddressTranslation et.al., make global,
3095 add SD argument
72f4393d 3096
c906108c
SS		 3097 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3098 CacheOp): Define.
72f4393d 3099
c906108c
SS		 3100 * interp.c (SignalException): Rename to signal_exception, make
3101 global.
3102
3103 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3104
c906108c
SS		 3105 * sim-main.h (SignalException, SignalExceptionInterrupt,
3106 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3107 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3108 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3109 Define.
72f4393d 3110
c906108c 3111 * interp.c, support.h: Use.
72f4393d 3112
c906108c
SS		 3113Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3114
3115 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3116 to value_fpr / store_fpr. Add SD argument.
3117 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3118 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3119
3120 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3121
c906108c
SS		 3122Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3123
3124 * interp.c (sim_engine_run): Check consistency between configure
3125 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3126 and HASFPU.
3127
3128 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3129 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3130 (mips_endian): Configure WITH_TARGET_ENDIAN.
3131 * configure: Update.
3132
3133Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3134
3135 * configure: Regenerated to track ../common/aclocal.m4 changes.
3136
3137Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3138
3139 * configure: Regenerated.
3140
3141Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3142
3143 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3144
3145Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * gencode.c (print_igen_insn_models): Assume certain architectures
3148 include all mips* instructions.
3149 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3150 instruction.
3151
3152 * Makefile.in (tmp.igen): Add target. Generate igen input from
3153 gencode file.
3154
3155 * gencode.c (FEATURE_IGEN): Define.
3156 (main): Add --igen option. Generate output in igen format.
3157 (process_instructions): Format output according to igen option.
3158 (print_igen_insn_format): New function.
3159 (print_igen_insn_models): New function.
3160 (process_instructions): Only issue warnings and ignore
3161 instructions when no FEATURE_IGEN.
3162
3163Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3164
3165 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3166 MIPS targets.
3167
3168Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3169
3170 * configure: Regenerated to track ../common/aclocal.m4 changes.
3171
3172Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3173
3174 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3175 SIM_RESERVED_BITS): Delete, moved to common.
3176 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3177
c906108c
SS		 3178Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3179
3180 * configure.in: Configure non-strict memory alignment.
3181 * configure: Regenerated to track ../common/aclocal.m4 changes.
3182
3183Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * configure: Regenerated to track ../common/aclocal.m4 changes.
3186
3187Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3188
3189 * gencode.c (SDBBP,DERET): Added (3900) insns.
3190 (RFE): Turn on for 3900.
3191 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3192 (dsstate): Made global.
3193 (SUBTARGET_R3900): Added.
3194 (CANCELDELAYSLOT): New.
3195 (SignalException): Ignore SystemCall rather than ignore and
3196 terminate. Add DebugBreakPoint handling.
3197 (decode_coproc): New insns RFE, DERET; and new registers Debug
3198 and DEPC protected by SUBTARGET_R3900.
3199 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3200 bits explicitly.
3201 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3202 * configure: Update.
c906108c
SS		 3203
3204Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3205
3206 * gencode.c: Add r3900 (tx39).
72f4393d 3207
c906108c
SS		 3208
3209Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3210
3211 * gencode.c (build_instruction): Don't need to subtract 4 for
3212 JALR, just 2.
3213
3214Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3215
3216 * interp.c: Correct some HASFPU problems.
3217
3218Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3219
3220 * configure: Regenerated to track ../common/aclocal.m4 changes.
3221
3222Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3223
3224 * interp.c (mips_options): Fix samples option short form, should
3225 be `x'.
3226
3227Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3228
3229 * interp.c (sim_info): Enable info code. Was just returning.
3230
3231Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3232
3233 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3234 MFC0.
3235
3236Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3237
3238 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3239 constants.
3240 (build_instruction): Ditto for LL.
3241
3242Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3243
3244 * configure: Regenerated to track ../common/aclocal.m4 changes.
3245
3246Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3247
3248 * configure: Regenerated to track ../common/aclocal.m4 changes.
3249 * config.in: Ditto.
3250
3251Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3252
3253 * interp.c (sim_open): Add call to sim_analyze_program, update
3254 call to sim_config.
3255
3256Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3257
3258 * interp.c (sim_kill): Delete.
3259 (sim_create_inferior): Add ABFD argument. Set PC from same.
3260 (sim_load): Move code initializing trap handlers from here.
3261 (sim_open): To here.
3262 (sim_load): Delete, use sim-hload.c.
3263
3264 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3265
3266Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3267
3268 * configure: Regenerated to track ../common/aclocal.m4 changes.
3269 * config.in: Ditto.
3270
3271Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * interp.c (sim_open): Add ABFD argument.
3274 (sim_load): Move call to sim_config from here.
3275 (sim_open): To here. Check return status.
3276
3277Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3278
c906108c
SS		 3279 * gencode.c (build_instruction): Two arg MADD should
3280 not assign result to $0.
72f4393d 3281
c906108c
SS		 3282Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3283
3284 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3285 * sim/mips/configure.in: Regenerate.
3286
3287Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3288
3289 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3290 signed8, unsigned8 et.al. types.
3291
3292 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3293 hosts when selecting subreg.
3294
3295Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3296
3297 * interp.c (sim_engine_run): Reset the ZERO register to zero
3298 regardless of FEATURE_WARN_ZERO.
3299 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3300
3301Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3302
3303 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3304 (SignalException): For BreakPoints ignore any mode bits and just
3305 save the PC.
3306 (SignalException): Always set the CAUSE register.
3307
3308Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3309
3310 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3311 exception has been taken.
3312
3313 * interp.c: Implement the ERET and mt/f sr instructions.
3314
3315Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3316
3317 * interp.c (SignalException): Don't bother restarting an
3318 interrupt.
3319
3320Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3321
3322 * interp.c (SignalException): Really take an interrupt.
3323 (interrupt_event): Only deliver interrupts when enabled.
3324
3325Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3326
3327 * interp.c (sim_info): Only print info when verbose.
3328 (sim_info) Use sim_io_printf for output.
72f4393d 3329
c906108c
SS		 3330Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3331
3332 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3333 mips architectures.
3334
3335Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3336
3337 * interp.c (sim_do_command): Check for common commands if a
3338 simulator specific command fails.
3339
3340Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3341
3342 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3343 and simBE when DEBUG is defined.
3344
3345Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3346
3347 * interp.c (interrupt_event): New function. Pass exception event
3348 onto exception handler.
3349
3350 * configure.in: Check for stdlib.h.
3351 * configure: Regenerate.
3352
3353 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3354 variable declaration.
3355 (build_instruction): Initialize memval1.
3356 (build_instruction): Add UNUSED attribute to byte, bigend,
3357 reverse.
3358 (build_operands): Ditto.
3359
3360 * interp.c: Fix GCC warnings.
3361 (sim_get_quit_code): Delete.
3362
3363 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3364 * Makefile.in: Ditto.
3365 * configure: Re-generate.
72f4393d 3366
c906108c
SS		 3367 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3368
3369Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3370
3371 * interp.c (mips_option_handler): New function parse argumes using
3372 sim-options.
3373 (myname): Replace with STATE_MY_NAME.
3374 (sim_open): Delete check for host endianness - performed by
3375 sim_config.
3376 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3377 (sim_open): Move much of the initialization from here.
3378 (sim_load): To here. After the image has been loaded and
3379 endianness set.
3380 (sim_open): Move ColdReset from here.
3381 (sim_create_inferior): To here.
3382 (sim_open): Make FP check less dependant on host endianness.
3383
3384 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3385 run.
3386 * interp.c (sim_set_callbacks): Delete.
3387
3388 * interp.c (membank, membank_base, membank_size): Replace with
3389 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3390 (sim_open): Remove call to callback->init. gdb/run do this.
3391
3392 * interp.c: Update
3393
3394 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3395
3396 * interp.c (big_endian_p): Delete, replaced by
3397 current_target_byte_order.
3398
3399Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3400
3401 * interp.c (host_read_long, host_read_word, host_swap_word,
3402 host_swap_long): Delete. Using common sim-endian.
3403 (sim_fetch_register, sim_store_register): Use H2T.
3404 (pipeline_ticks): Delete. Handled by sim-events.
3405 (sim_info): Update.
3406 (sim_engine_run): Update.
3407
3408Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3409
3410 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3411 reason from here.
3412 (SignalException): To here. Signal using sim_engine_halt.
3413 (sim_stop_reason): Delete, moved to common.
72f4393d 3414
c906108c
SS		 3415Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3416
3417 * interp.c (sim_open): Add callback argument.
3418 (sim_set_callbacks): Delete SIM_DESC argument.
3419 (sim_size): Ditto.
3420
3421Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3422
3423 * Makefile.in (SIM_OBJS): Add common modules.
3424
3425 * interp.c (sim_set_callbacks): Also set SD callback.
3426 (set_endianness, xfer_*, swap_*): Delete.
3427 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3428 Change to functions using sim-endian macros.
3429 (control_c, sim_stop): Delete, use common version.
3430 (simulate): Convert into.
3431 (sim_engine_run): This function.
3432 (sim_resume): Delete.
72f4393d 3433
c906108c
SS		 3434 * interp.c (simulation): New variable - the simulator object.
3435 (sim_kind): Delete global - merged into simulation.
3436 (sim_load): Cleanup. Move PC assignment from here.
3437 (sim_create_inferior): To here.
3438
3439 * sim-main.h: New file.
3440 * interp.c (sim-main.h): Include.
72f4393d 3441
c906108c
SS		 3442Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3443
3444 * configure: Regenerated to track ../common/aclocal.m4 changes.
3445
3446Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3447
3448 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3449
3450Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3451
72f4393d
L		 3452 * gencode.c (build_instruction): DIV instructions: check
3453 for division by zero and integer overflow before using
c906108c
SS		 3454 host's division operation.
3455
3456Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3457
3458 * Makefile.in (SIM_OBJS): Add sim-load.o.
3459 * interp.c: #include bfd.h.
3460 (target_byte_order): Delete.
3461 (sim_kind, myname, big_endian_p): New static locals.
3462 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3463 after argument parsing. Recognize -E arg, set endianness accordingly.
3464 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3465 load file into simulator. Set PC from bfd.
3466 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3467 (set_endianness): Use big_endian_p instead of target_byte_order.
3468
3469Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3470
3471 * interp.c (sim_size): Delete prototype - conflicts with
3472 definition in remote-sim.h. Correct definition.
3473
3474Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3475
3476 * configure: Regenerated to track ../common/aclocal.m4 changes.
3477 * config.in: Ditto.
3478
3479Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3480
3481 * interp.c (sim_open): New arg `kind'.
3482
3483 * configure: Regenerated to track ../common/aclocal.m4 changes.
3484
3485Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3486
3487 * configure: Regenerated to track ../common/aclocal.m4 changes.
3488
3489Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3490
3491 * interp.c (sim_open): Set optind to 0 before calling getopt.
3492
3493Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3494
3495 * configure: Regenerated to track ../common/aclocal.m4 changes.
3496
3497Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3498
3499 * interp.c : Replace uses of pr_addr with pr_uword64
3500 where the bit length is always 64 independent of SIM_ADDR.
3501 (pr_uword64) : added.
3502
3503Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3504
3505 * configure: Re-generate.
3506
3507Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3508
3509 * configure: Regenerate to track ../common/aclocal.m4 changes.
3510
3511Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3512
3513 * interp.c (sim_open): New SIM_DESC result. Argument is now
3514 in argv form.
3515 (other sim_*): New SIM_DESC argument.
3516
3517Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3518
3519 * interp.c: Fix printing of addresses for non-64-bit targets.
3520 (pr_addr): Add function to print address based on size.
3521
3522Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3523
3524 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3525
3526Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3527
3528 * gencode.c (build_mips16_operands): Correct computation of base
3529 address for extended PC relative instruction.
3530
3531Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3532
3533 * interp.c (mips16_entry): Add support for floating point cases.
3534 (SignalException): Pass floating point cases to mips16_entry.
3535 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3536 registers.
3537 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3538 or fmt_word.
3539 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3540 and then set the state to fmt_uninterpreted.
3541 (COP_SW): Temporarily set the state to fmt_word while calling
3542 ValueFPR.
3543
3544Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3545
3546 * gencode.c (build_instruction): The high order may be set in the
3547 comparison flags at any ISA level, not just ISA 4.
3548
3549Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3550
3551 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3552 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3553 * configure.in: sinclude ../common/aclocal.m4.
3554 * configure: Regenerated.
3555
3556Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3557
3558 * configure: Rebuild after change to aclocal.m4.
3559
3560Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3561
3562 * configure configure.in Makefile.in: Update to new configure
3563 scheme which is more compatible with WinGDB builds.
3564 * configure.in: Improve comment on how to run autoconf.
3565 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3566 * Makefile.in: Use autoconf substitution to install common
3567 makefile fragment.
3568
3569Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3570
3571 * gencode.c (build_instruction): Use BigEndianCPU instead of
3572 ByteSwapMem.
3573
3574Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3575
3576 * interp.c (sim_monitor): Make output to stdout visible in
3577 wingdb's I/O log window.
3578
3579Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3580
3581 * support.h: Undo previous change to SIGTRAP
3582 and SIGQUIT values.
3583
3584Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3585
3586 * interp.c (store_word, load_word): New static functions.
3587 (mips16_entry): New static function.
3588 (SignalException): Look for mips16 entry and exit instructions.
3589 (simulate): Use the correct index when setting fpr_state after
3590 doing a pending move.
3591
3592Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3593
3594 * interp.c: Fix byte-swapping code throughout to work on
3595 both little- and big-endian hosts.
3596
3597Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3598
3599 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3600 with gdb/config/i386/xm-windows.h.
3601
3602Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3603
3604 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3605 that messes up arithmetic shifts.
3606
3607Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3608
3609 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3610 SIGTRAP and SIGQUIT for _WIN32.
3611
3612Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3613
3614 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3615 force a 64 bit multiplication.
3616 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3617 destination register is 0, since that is the default mips16 nop
3618 instruction.
3619
3620Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3621
3622 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3623 (build_endian_shift): Don't check proc64.
3624 (build_instruction): Always set memval to uword64. Cast op2 to
3625 uword64 when shifting it left in memory instructions. Always use
3626 the same code for stores--don't special case proc64.
3627
3628 * gencode.c (build_mips16_operands): Fix base PC value for PC
3629 relative operands.
3630 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3631 jal instruction.
3632 * interp.c (simJALDELAYSLOT): Define.
3633 (JALDELAYSLOT): Define.
3634 (INDELAYSLOT, INJALDELAYSLOT): Define.
3635 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3636
3637Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3638
3639 * interp.c (sim_open): add flush_cache as a PMON routine
3640 (sim_monitor): handle flush_cache by ignoring it
3641
3642Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3643
3644 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3645 BigEndianMem.
3646 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3647 (BigEndianMem): Rename to ByteSwapMem and change sense.
3648 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3649 BigEndianMem references to !ByteSwapMem.
3650 (set_endianness): New function, with prototype.
3651 (sim_open): Call set_endianness.
3652 (sim_info): Use simBE instead of BigEndianMem.
3653 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3654 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3655 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3656 ifdefs, keeping the prototype declaration.
3657 (swap_word): Rewrite correctly.
3658 (ColdReset): Delete references to CONFIG. Delete endianness related
3659 code; moved to set_endianness.
72f4393d 3660
c906108c
SS		 3661Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3662
3663 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3664 * interp.c (CHECKHILO): Define away.
3665 (simSIGINT): New macro.
3666 (membank_size): Increase from 1MB to 2MB.
3667 (control_c): New function.
3668 (sim_resume): Rename parameter signal to signal_number. Add local
3669 variable prev. Call signal before and after simulate.
3670 (sim_stop_reason): Add simSIGINT support.
3671 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3672 functions always.
3673 (sim_warning): Delete call to SignalException. Do call printf_filtered
3674 if logfh is NULL.
3675 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3676 a call to sim_warning.
3677
3678Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3679
3680 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3681 16 bit instructions.
3682
3683Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3684
3685 Add support for mips16 (16 bit MIPS implementation):
3686 * gencode.c (inst_type): Add mips16 instruction encoding types.
3687 (GETDATASIZEINSN): Define.
3688 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3689 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3690 mtlo.
3691 (MIPS16_DECODE): New table, for mips16 instructions.
3692 (bitmap_val): New static function.
3693 (struct mips16_op): Define.
3694 (mips16_op_table): New table, for mips16 operands.
3695 (build_mips16_operands): New static function.
3696 (process_instructions): If PC is odd, decode a mips16
3697 instruction. Break out instruction handling into new
3698 build_instruction function.
3699 (build_instruction): New static function, broken out of
3700 process_instructions. Check modifiers rather than flags for SHIFT
3701 bit count and m[ft]{hi,lo} direction.
3702 (usage): Pass program name to fprintf.
3703 (main): Remove unused variable this_option_optind. Change
3704 ``*loptarg++'' to ``loptarg++''.
3705 (my_strtoul): Parenthesize && within ||.
3706 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3707 (simulate): If PC is odd, fetch a 16 bit instruction, and
3708 increment PC by 2 rather than 4.
3709 * configure.in: Add case for mips16*-*-*.
3710 * configure: Rebuild.
3711
3712Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3713
3714 * interp.c: Allow -t to enable tracing in standalone simulator.
3715 Fix garbage output in trace file and error messages.
3716
3717Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3718
3719 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3720 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3721 * configure.in: Simplify using macros in ../common/aclocal.m4.
3722 * configure: Regenerated.
3723 * tconfig.in: New file.
3724
3725Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3726
3727 * interp.c: Fix bugs in 64-bit port.
3728 Use ansi function declarations for msvc compiler.
3729 Initialize and test file pointer in trace code.
3730 Prevent duplicate definition of LAST_EMED_REGNUM.
3731
3732Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3733
3734 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3735
3736Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3737
3738 * interp.c (SignalException): Check for explicit terminating
3739 breakpoint value.
3740 * gencode.c: Pass instruction value through SignalException()
3741 calls for Trap, Breakpoint and Syscall.
3742
3743Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3744
3745 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3746 only used on those hosts that provide it.
3747 * configure.in: Add sqrt() to list of functions to be checked for.
3748 * config.in: Re-generated.
3749 * configure: Re-generated.
3750
3751Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3752
3753 * gencode.c (process_instructions): Call build_endian_shift when
3754 expanding STORE RIGHT, to fix swr.
3755 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3756 clear the high bits.
3757 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3758 Fix float to int conversions to produce signed values.
3759
3760Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3761
3762 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3763 (process_instructions): Correct handling of nor instruction.
3764 Correct shift count for 32 bit shift instructions. Correct sign
3765 extension for arithmetic shifts to not shift the number of bits in
3766 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3767 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3768 Fix madd.
3769 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3770 It's OK to have a mult follow a mult. What's not OK is to have a
3771 mult follow an mfhi.
3772 (Convert): Comment out incorrect rounding code.
3773
3774Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3775
3776 * interp.c (sim_monitor): Improved monitor printf
3777 simulation. Tidied up simulator warnings, and added "--log" option
3778 for directing warning message output.
3779 * gencode.c: Use sim_warning() rather than WARNING macro.
3780
3781Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3782
3783 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3784 getopt1.o, rather than on gencode.c. Link objects together.
3785 Don't link against -liberty.
3786 (gencode.o, getopt.o, getopt1.o): New targets.
3787 * gencode.c: Include <ctype.h> and "ansidecl.h".
3788 (AND): Undefine after including "ansidecl.h".
3789 (ULONG_MAX): Define if not defined.
3790 (OP_*): Don't define macros; now defined in opcode/mips.h.
3791 (main): Call my_strtoul rather than strtoul.
3792 (my_strtoul): New static function.
3793
3794Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3795
3796 * gencode.c (process_instructions): Generate word64 and uword64
3797 instead of `long long' and `unsigned long long' data types.
3798 * interp.c: #include sysdep.h to get signals, and define default
3799 for SIGBUS.
3800 * (Convert): Work around for Visual-C++ compiler bug with type
3801 conversion.
3802 * support.h: Make things compile under Visual-C++ by using
3803 __int64 instead of `long long'. Change many refs to long long
3804 into word64/uword64 typedefs.
3805
3806Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3807
72f4393d
L		 3808 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3809 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3810 (docdir): Removed.
3811 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3812 (AC_PROG_INSTALL): Added.
c906108c 3813 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3814 * configure: Rebuilt.
3815
c906108c
SS		 3816Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3817
3818 * configure.in: Define @SIMCONF@ depending on mips target.
3819 * configure: Rebuild.
3820 * Makefile.in (run): Add @SIMCONF@ to control simulator
3821 construction.
3822 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3823 * interp.c: Remove some debugging, provide more detailed error
3824 messages, update memory accesses to use LOADDRMASK.
72f4393d 3825
c906108c
SS		 3826Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3827
3828 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3829 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3830 stamp-h.
3831 * configure: Rebuild.
3832 * config.in: New file, generated by autoheader.
3833 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3834 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3835 HAVE_ANINT and HAVE_AINT, as appropriate.
3836 * Makefile.in (run): Use @LIBS@ rather than -lm.
3837 (interp.o): Depend upon config.h.
3838 (Makefile): Just rebuild Makefile.
3839 (clean): Remove stamp-h.
3840 (mostlyclean): Make the same as clean, not as distclean.
3841 (config.h, stamp-h): New targets.
3842
3843Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3844
3845 * interp.c (ColdReset): Fix boolean test. Make all simulator
3846 globals static.
3847
3848Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3849
3850 * interp.c (xfer_direct_word, xfer_direct_long,
3851 swap_direct_word, swap_direct_long, xfer_big_word,
3852 xfer_big_long, xfer_little_word, xfer_little_long,
3853 swap_word,swap_long): Added.
3854 * interp.c (ColdReset): Provide function indirection to
3855 host<->simulated_target transfer routines.
3856 * interp.c (sim_store_register, sim_fetch_register): Updated to
3857 make use of indirected transfer routines.
3858
3859Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3860
3861 * gencode.c (process_instructions): Ensure FP ABS instruction
3862 recognised.
3863 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3864 system call support.
3865
3866Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3867
3868 * interp.c (sim_do_command): Complain if callback structure not
3869 initialised.
3870
3871Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3872
3873 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3874 support for Sun hosts.
3875 * Makefile.in (gencode): Ensure the host compiler and libraries
3876 used for cross-hosted build.
3877
3878Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3879
3880 * interp.c, gencode.c: Some more (TODO) tidying.
3881
3882Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3883
3884 * gencode.c, interp.c: Replaced explicit long long references with
3885 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3886 * support.h (SET64LO, SET64HI): Macros added.
3887
3888Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3889
3890 * configure: Regenerate with autoconf 2.7.
3891
3892Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3893
3894 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3895 * support.h: Remove superfluous "1" from #if.
3896 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3897
3898Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3899
3900 * interp.c (StoreFPR): Control UndefinedResult() call on
3901 WARN_RESULT manifest.
3902
3903Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3904
3905 * gencode.c: Tidied instruction decoding, and added FP instruction
3906 support.
3907
3908 * interp.c: Added dineroIII, and BSD profiling support. Also
3909 run-time FP handling.
3910
3911Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3912
3913 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3914 gencode.c, interp.c, support.h: created.
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