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sim: mips: delete unused constant variables
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d97ba9c6
MF		 12021-05-04 Mike Frysinger <vapier@gentoo.org>
2
3 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
4 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
5 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
6 * configure: Regenerate.
7
4df817de
MF		 82021-05-04 Mike Frysinger <vapier@gentoo.org>
9
10 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
11
aa0fca16
MF		 122021-05-04 Mike Frysinger <vapier@gentoo.org>
13
14 * configure: Regenerate.
15
adbaa7b8
MF		 162021-05-01 Mike Frysinger <vapier@gentoo.org>
17
18 * cp1.c (store_fcr): Mark static.
19
fe348617
MF		 202021-05-01 Mike Frysinger <vapier@gentoo.org>
21
22 * config.in, configure: Regenerate.
23
9d903352
MF		 242021-04-23 Mike Frysinger <vapier@gentoo.org>
25
26 * configure.ac (hw_enabled): Delete.
27 (SIM_AC_OPTION_HARDWARE): Delete first two args.
28 * configure: Regenerate.
29
19f6a43c
TT		 302021-04-22 Tom Tromey <tom@tromey.com>
31
32 * configure, config.in: Rebuild.
33
e7d8f1da
TT		 342021-04-22 Tom Tromey <tom@tromey.com>
35
36 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
37 Remove.
38 (SIM_EXTRA_DEPS): New variable.
39
efd82ac7
TT		 402021-04-22 Tom Tromey <tom@tromey.com>
41
42 * configure: Rebuild.
43
2662c237
MF		 442021-04-21 Mike Frysinger <vapier@gentoo.org>
45
46 * aclocal.m4: Regenerate.
47
1f195bc3
SM		 482021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
49
50 * configure: Regenerate.
51
37e9f182
MF		 522021-04-18 Mike Frysinger <vapier@gentoo.org>
53
54 * configure: Regenerate.
55
d5a71b11
MF		 562021-04-12 Mike Frysinger <vapier@gentoo.org>
57
58 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
59
2b8d134b
SM		 602021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
61
62 * Makefile.in: Set ASAN_OPTIONS when running igen.
63
5c6f091a
FS		 642021-04-04 Steve Ellcey <sellcey@mips.com>
65 Faraz Shahbazker <fshahbazker@wavecomp.com>
66
67 * interp.c (sim_monitor): Add switch entries for unlink (13),
68 lseek (14), and stat (15).
69
b6b1c790
MF		 702021-04-02 Mike Frysinger <vapier@gentoo.org>
71
72 * Makefile.in (../igen/igen): Delete rule.
73 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
74
c2783492
MF		 752021-04-02 Mike Frysinger <vapier@gentoo.org>
76
77 * aclocal.m4, configure: Regenerate.
78
ebe9564b
MF		 792021-02-28 Mike Frysinger <vapier@gentoo.org>
80
81 * configure: Regenerate.
82
f8069d55
MF		 832021-02-27 Mike Frysinger <vapier@gentoo.org>
84
85 * Makefile.in (SIM_EXTRA_ALL): Delete.
86 (all): New target.
87
760b3e8b
MF		 882021-02-21 Mike Frysinger <vapier@gentoo.org>
89
90 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
91 * aclocal.m4, configure: Regenerate.
92
136da8cd
MF		 932021-02-13 Mike Frysinger <vapier@gentoo.org>
94
95 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
96 * aclocal.m4, configure: Regenerate.
97
4c0d76b9
MF		 982021-02-06 Mike Frysinger <vapier@gentoo.org>
99
100 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
101
aa09469f
MF		 1022021-02-06 Mike Frysinger <vapier@gentoo.org>
103
104 * configure: Regenerate.
105
d4e3adda
MF		 1062021-01-30 Mike Frysinger <vapier@gentoo.org>
107
108 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
109
68ed2854
MF		 1102021-01-11 Mike Frysinger <vapier@gentoo.org>
111
112 * config.in, configure: Regenerate.
113 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
114 and strings.h include.
115
50df264d
MF		 1162021-01-09 Mike Frysinger <vapier@gentoo.org>
117
118 * configure: Regenerate.
119
bf470982
MF		 1202021-01-09 Mike Frysinger <vapier@gentoo.org>
121
122 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
123 * configure: Regenerate.
124
46f900c0
MF		 1252021-01-08 Mike Frysinger <vapier@gentoo.org>
126
127 * configure: Regenerate.
128
dfb856ba
MF		 1292021-01-04 Mike Frysinger <vapier@gentoo.org>
130
131 * configure: Regenerate.
132
382bc56b
PK		 1332020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
134
135 * sim-main.c: Include <stdlib.h>.
136
ad9675dd
PK		 1372020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
138
139 * cp1.c: Include <stdlib.h>.
140
f693213d
SM		 1412020-07-29 Simon Marchi <simon.marchi@efficios.com>
142
143 * configure: Re-generate.
144
5c887dd5
JB		 1452017-09-06 John Baldwin <jhb@FreeBSD.org>
146
147 * configure: Regenerate.
148
91588b3a
MF		 1492016-11-11 Mike Frysinger <vapier@gentoo.org>
150
6cb2202b 151 PR sim/20808
91588b3a
MF		 152 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
153 and SD to sd.
154
e04659e8
MF		 1552016-11-11 Mike Frysinger <vapier@gentoo.org>
156
6cb2202b 157 PR sim/20809
e04659e8
MF		 158 * mips.igen (check_u64): Enable for `r3900'.
159
1554f758
MF		 1602016-02-05 Mike Frysinger <vapier@gentoo.org>
161
162 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
163 STATE_PROG_BFD (sd).
164 * configure: Regenerate.
165
3d304f48
AB		 1662016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
167 Maciej W. Rozycki <macro@imgtec.com>
168
169 PR sim/19441
170 * micromips.igen (delayslot_micromips): Enable for `micromips32',
171 `micromips64' and `micromipsdsp' only.
172 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
173 (do_micromips_jalr, do_micromips_jal): Likewise.
174 (compute_movep_src_reg): Likewise.
175 (compute_andi16_imm): Likewise.
176 (convert_fmt_micromips): Likewise.
177 (convert_fmt_micromips_cvt_d): Likewise.
178 (convert_fmt_micromips_cvt_s): Likewise.
179 (FMT_MICROMIPS): Likewise.
180 (FMT_MICROMIPS_CVT_D): Likewise.
181 (FMT_MICROMIPS_CVT_S): Likewise.
182
b36d953b
MF		 1832016-01-12 Mike Frysinger <vapier@gentoo.org>
184
185 * interp.c: Include elf-bfd.h.
186 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
187 ELFCLASS32.
188
ce39bd38
MF		 1892016-01-10 Mike Frysinger <vapier@gentoo.org>
190
191 * config.in, configure: Regenerate.
192
99d8e879
MF		 1932016-01-10 Mike Frysinger <vapier@gentoo.org>
194
195 * configure: Regenerate.
196
35656e95
MF		 1972016-01-10 Mike Frysinger <vapier@gentoo.org>
198
199 * configure: Regenerate.
200
16f7876d
MF		 2012016-01-10 Mike Frysinger <vapier@gentoo.org>
202
203 * configure: Regenerate.
204
e19418e0
MF		 2052016-01-10 Mike Frysinger <vapier@gentoo.org>
206
207 * configure: Regenerate.
208
6d90347b
MF		 2092016-01-10 Mike Frysinger <vapier@gentoo.org>
210
211 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
212 * configure: Regenerate.
213
347fe5bb
MF		 2142016-01-10 Mike Frysinger <vapier@gentoo.org>
215
216 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
217 * configure: Regenerate.
218
22be3fbe
MF		 2192016-01-10 Mike Frysinger <vapier@gentoo.org>
220
221 * configure: Regenerate.
222
0dc73ef7
MF		 2232016-01-10 Mike Frysinger <vapier@gentoo.org>
224
225 * configure: Regenerate.
226
936df756
MF		 2272016-01-09 Mike Frysinger <vapier@gentoo.org>
228
229 * config.in, configure: Regenerate.
230
2e3d4f4d
MF		 2312016-01-06 Mike Frysinger <vapier@gentoo.org>
232
233 * interp.c (sim_open): Mark argv const.
234 (sim_create_inferior): Mark argv and env const.
235
9bbf6f91
MF		 2362016-01-04 Mike Frysinger <vapier@gentoo.org>
237
238 * configure: Regenerate.
239
77cf2ef5
MF		 2402016-01-03 Mike Frysinger <vapier@gentoo.org>
241
242 * interp.c (sim_open): Update sim_parse_args comment.
243
0cb8d851
MF		 2442016-01-03 Mike Frysinger <vapier@gentoo.org>
245
246 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
247 * configure: Regenerate.
248
1ac72f06
MF		 2492016-01-02 Mike Frysinger <vapier@gentoo.org>
250
251 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
252 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
253 * configure: Regenerate.
254 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
255
d47f5b30
MF		 2562016-01-02 Mike Frysinger <vapier@gentoo.org>
257
258 * dv-tx3904cpu.c (CPU, SD): Delete.
259
e1211e55
MF		 2602015-12-30 Mike Frysinger <vapier@gentoo.org>
261
262 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
263 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
264 (sim_store_register): Rename to ...
265 (mips_reg_store): ... this. Delete local cpu var.
266 Update sim_io_eprintf calls.
267 (sim_fetch_register): Rename to ...
268 (mips_reg_fetch): ... this. Delete local cpu var.
269 Update sim_io_eprintf calls.
270
5e744ef8
MF		 2712015-12-27 Mike Frysinger <vapier@gentoo.org>
272
273 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
274
1b393626
MF		 2752015-12-26 Mike Frysinger <vapier@gentoo.org>
276
277 * config.in, configure: Regenerate.
278
26f8bf63
MF		 2792015-12-26 Mike Frysinger <vapier@gentoo.org>
280
281 * interp.c (sim_write, sim_read): Delete.
282 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
283 (load_word): Likewise.
284 * micromips.igen (cache): Likewise.
285 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
286 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
287 do_store_left, do_store_right, do_load_double, do_store_double):
288 Likewise.
289 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
290 (do_prefx): Likewise.
291 * sim-main.c (address_translation, prefetch): Delete.
292 (ifetch32, ifetch16): Delete call to AddressTranslation and set
293 paddr=vaddr.
294 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
295 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
296 (LoadMemory, StoreMemory): Delete CCA arg.
297
ef04e371
MF		 2982015-12-24 Mike Frysinger <vapier@gentoo.org>
299
300 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
301 * configure: Regenerated.
302
cb379ede
MF		 3032015-12-24 Mike Frysinger <vapier@gentoo.org>
304
305 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
306 * tconfig.h: Delete.
307
26936211
MF		 3082015-12-24 Mike Frysinger <vapier@gentoo.org>
309
310 * tconfig.h (SIM_HANDLES_LMA): Delete.
311
84e8e361
MF		 3122015-12-24 Mike Frysinger <vapier@gentoo.org>
313
314 * sim-main.h (WITH_WATCHPOINTS): Delete.
315
3cabaf66
MF		 3162015-12-24 Mike Frysinger <vapier@gentoo.org>
317
318 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
319
8abe6c66
MF		 3202015-12-24 Mike Frysinger <vapier@gentoo.org>
321
322 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
323
1d19cae7
DV		 3242015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
325
326 * micromips.igen (process_isa_mode): Fix left shift of negative
327 value.
328
cdf850e9
MF		 3292015-11-17 Mike Frysinger <vapier@gentoo.org>
330
331 * sim-main.h (WITH_MODULO_MEMORY): Delete.
332
797eee42
MF		 3332015-11-15 Mike Frysinger <vapier@gentoo.org>
334
335 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
336
6e4f085c
MF		 3372015-11-14 Mike Frysinger <vapier@gentoo.org>
338
339 * interp.c (sim_close): Rename to ...
340 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
341 sim_io_shutdown.
342 * sim-main.h (mips_sim_close): Declare.
343 (SIM_CLOSE_HOOK): Define.
344
8e394ffc
AB		 3452015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
346 Ali Lown <ali.lown@imgtec.com>
347
348 * Makefile.in (tmp-micromips): New rule.
349 (tmp-mach-multi): Add support for micromips.
350 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
351 that works for both mips64 and micromips64.
352 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
353 micromips32.
354 Add build support for micromips.
355 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
356 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
357 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
358 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
359 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
360 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
361 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
362 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
363 Refactored instruction code to use these functions.
364 * dsp2.igen: Refactored instruction code to use the new functions.
365 * interp.c (decode_coproc): Refactored to work with any instruction
366 encoding.
367 (isa_mode): New variable
368 (RSVD_INSTRUCTION): Changed to 0x00000039.
369 * m16.igen (BREAK16): Refactored instruction to use do_break16.
370 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
371 * micromips.dc: New file.
372 * micromips.igen: New file.
373 * micromips16.dc: New file.
374 * micromipsdsp.igen: New file.
375 * micromipsrun.c: New file.
376 * mips.igen (do_swc1): Changed to work with any instruction encoding.
377 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
378 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
379 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
380 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
381 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
382 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
383 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
384 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
385 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
386 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
387 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
388 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
389 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
390 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
391 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
392 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
393 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
394 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
395 instructions.
396 Refactored instruction code to use these functions.
397 (RSVD): Changed to use new reserved instruction.
398 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
399 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
400 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
401 do_store_double): Added micromips32 and micromips64 models.
402 Added include for micromips.igen and micromipsdsp.igen
403 Add micromips32 and micromips64 models.
404 (DecodeCoproc): Updated to use new macro definition.
405 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
406 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
407 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
408 Refactored instruction code to use these functions.
409 * sim-main.h (CP0_operation): New enum.
410 (DecodeCoproc): Updated macro.
411 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
412 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
413 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
414 ISA_MODE_MICROMIPS): New defines.
415 (sim_state): Add isa_mode field.
416
8d0978fb
MF		 4172015-06-23 Mike Frysinger <vapier@gentoo.org>
418
419 * configure: Regenerate.
420
306f4178
MF		 4212015-06-12 Mike Frysinger <vapier@gentoo.org>
422
423 * configure.ac: Change configure.in to configure.ac.
424 * configure: Regenerate.
425
a3487082
MF		 4262015-06-12 Mike Frysinger <vapier@gentoo.org>
427
428 * configure: Regenerate.
429
29bc024d
MF		 4302015-06-12 Mike Frysinger <vapier@gentoo.org>
431
432 * interp.c [TRACE]: Delete.
433 (TRACE): Change to WITH_TRACE_ANY_P.
434 [!WITH_TRACE_ANY_P] (open_trace): Define.
435 (mips_option_handler, open_trace, sim_close, dotrace):
436 Change defined(TRACE) to WITH_TRACE_ANY_P.
437 (sim_open): Delete TRACE ifdef check.
438 * sim-main.c (load_memory): Delete TRACE ifdef check.
439 (store_memory): Likewise.
440 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
441 [!WITH_TRACE_ANY_P] (dotrace): Define.
442
3ebe2863
MF		 4432015-04-18 Mike Frysinger <vapier@gentoo.org>
444
445 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
446 comments.
447
20bca71d
MF		 4482015-04-18 Mike Frysinger <vapier@gentoo.org>
449
450 * sim-main.h (SIM_CPU): Delete.
451
7e83aa92
MF		 4522015-04-18 Mike Frysinger <vapier@gentoo.org>
453
454 * sim-main.h (sim_cia): Delete.
455
034685f9
MF		 4562015-04-17 Mike Frysinger <vapier@gentoo.org>
457
458 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
459 PU_PC_GET.
460 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
461 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
462 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
463 CIA_SET to CPU_PC_SET.
464 * sim-main.h (CIA_GET, CIA_SET): Delete.
465
78e9aa70
MF		 4662015-04-15 Mike Frysinger <vapier@gentoo.org>
467
468 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
469 * sim-main.h (STATE_CPU): Delete.
470
bf12d44e
MF		 4712015-04-13 Mike Frysinger <vapier@gentoo.org>
472
473 * configure: Regenerate.
474
7bebb329
MF		 4752015-04-13 Mike Frysinger <vapier@gentoo.org>
476
477 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
478 * interp.c (mips_pc_get, mips_pc_set): New functions.
479 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
480 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
481 (sim_pc_get): Delete.
482 * sim-main.h (SIM_CPU): Define.
483 (struct sim_state): Change cpu to an array of pointers.
484 (STATE_CPU): Drop &.
485
8ac57fbd
MF		 4862015-04-13 Mike Frysinger <vapier@gentoo.org>
487
488 * interp.c (mips_option_handler, open_trace, sim_close,
489 sim_write, sim_read, sim_store_register, sim_fetch_register,
490 sim_create_inferior, pr_addr, pr_uword64): Convert old style
491 prototypes.
492 (sim_open): Convert old style prototype. Change casts with
493 sim_write to unsigned char *.
494 (fetch_str): Change null to unsigned char, and change cast to
495 unsigned char *.
496 (sim_monitor): Change c & ch to unsigned char. Change cast to
497 unsigned char *.
498
e787f858
MF		 4992015-04-12 Mike Frysinger <vapier@gentoo.org>
500
501 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
502
122bbfb5
MF		 5032015-04-06 Mike Frysinger <vapier@gentoo.org>
504
505 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
506
0fe84f3f
MF		 5072015-04-01 Mike Frysinger <vapier@gentoo.org>
508
509 * tconfig.h (SIM_HAVE_PROFILE): Delete.
510
aadc9410
MF		 5112015-03-31 Mike Frysinger <vapier@gentoo.org>
512
513 * config.in, configure: Regenerate.
514
05f53ed6
MF		 5152015-03-24 Mike Frysinger <vapier@gentoo.org>
516
517 * interp.c (sim_pc_get): New function.
518
c0931f26
MF		 5192015-03-24 Mike Frysinger <vapier@gentoo.org>
520
521 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
522 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
523
30452bbe
MF		 5242015-03-24 Mike Frysinger <vapier@gentoo.org>
525
526 * configure: Regenerate.
527
64dd13df
MF		 5282015-03-23 Mike Frysinger <vapier@gentoo.org>
529
530 * configure: Regenerate.
531
49cd1634
MF		 5322015-03-23 Mike Frysinger <vapier@gentoo.org>
533
534 * configure: Regenerate.
535 * configure.ac (mips_extra_objs): Delete.
536 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
537 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
538
3649cb06
MF		 5392015-03-23 Mike Frysinger <vapier@gentoo.org>
540
541 * configure: Regenerate.
542 * configure.ac: Delete sim_hw checks for dv-sockser.
543
ae7d0cac
MF		 5442015-03-16 Mike Frysinger <vapier@gentoo.org>
545
546 * config.in, configure: Regenerate.
547 * tconfig.in: Rename file ...
548 * tconfig.h: ... here.
549
8406bb59
MF		 5502015-03-15 Mike Frysinger <vapier@gentoo.org>
551
552 * tconfig.in: Delete includes.
553 [HAVE_DV_SOCKSER]: Delete.
554
465fb143
MF		 5552015-03-14 Mike Frysinger <vapier@gentoo.org>
556
557 * Makefile.in (SIM_RUN_OBJS): Delete.
558
5cddc23a
MF		 5592015-03-14 Mike Frysinger <vapier@gentoo.org>
560
561 * configure.ac (AC_CHECK_HEADERS): Delete.
562 * aclocal.m4, configure: Regenerate.
563
2974be62
AM		 5642014-08-19 Alan Modra <amodra@gmail.com>
565
566 * configure: Regenerate.
567
faa743bb
RM		 5682014-08-15 Roland McGrath <mcgrathr@google.com>
569
570 * configure: Regenerate.
571 * config.in: Regenerate.
572
1a8a700e
MF		 5732014-03-04 Mike Frysinger <vapier@gentoo.org>
574
575 * configure: Regenerate.
576
bf3d9781
AM		 5772013-09-23 Alan Modra <amodra@gmail.com>
578
579 * configure: Regenerate.
580
31e6ad7d
MF		 5812013-06-03 Mike Frysinger <vapier@gentoo.org>
582
583 * aclocal.m4, configure: Regenerate.
584
d3685d60
TT		 5852013-05-10 Freddie Chopin <freddie_chopin@op.pl>
586
587 * configure: Rebuild.
588
1517bd27
MF		 5892013-03-26 Mike Frysinger <vapier@gentoo.org>
590
591 * configure: Regenerate.
592
3be31516
JS		 5932013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
594
595 * configure.ac: Address use of dv-sockser.o.
596 * tconfig.in: Conditionalize use of dv_sockser_install.
597 * configure: Regenerated.
598 * config.in: Regenerated.
599
37cb8f8e
SE		 6002012-10-04 Chao-ying Fu <fu@mips.com>
601 Steve Ellcey <sellcey@mips.com>
602
603 * mips/mips3264r2.igen (rdhwr): New.
604
87c8644f
JS		 6052012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
606
607 * configure.ac: Always link against dv-sockser.o.
608 * configure: Regenerate.
609
5f3ef9d0
JB		 6102012-06-15 Joel Brobecker <brobecker@adacore.com>
611
612 * config.in, configure: Regenerate.
613
a6ff997c
NC		 6142012-05-18 Nick Clifton <nickc@redhat.com>
615
616 PR 14072
617 * interp.c: Include config.h before system header files.
618
2232061b
MF		 6192012-03-24 Mike Frysinger <vapier@gentoo.org>
620
621 * aclocal.m4, config.in, configure: Regenerate.
622
db2e4d67
MF		 6232011-12-03 Mike Frysinger <vapier@gentoo.org>
624
625 * aclocal.m4: New file.
626 * configure: Regenerate.
627
4399a56b
MF		 6282011-10-19 Mike Frysinger <vapier@gentoo.org>
629
630 * configure: Regenerate after common/acinclude.m4 update.
631
9c082ca8
MF		 6322011-10-17 Mike Frysinger <vapier@gentoo.org>
633
634 * configure.ac: Change include to common/acinclude.m4.
635
6ffe910a
MF		 6362011-10-17 Mike Frysinger <vapier@gentoo.org>
637
638 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
639 call. Replace common.m4 include with SIM_AC_COMMON.
640 * configure: Regenerate.
641
31b28250
HPN		 6422011-07-08 Hans-Peter Nilsson <hp@axis.com>
643
3faa01e3
HPN		 644 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
645 $(SIM_EXTRA_DEPS).
646 (tmp-mach-multi): Exit early when igen fails.
31b28250 647
2419798b
MF		 6482011-07-05 Mike Frysinger <vapier@gentoo.org>
649
650 * interp.c (sim_do_command): Delete.
651
d79fe0d6
MF		 6522011-02-14 Mike Frysinger <vapier@gentoo.org>
653
654 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
655 (tx3904sio_fifo_reset): Likewise.
656 * interp.c (sim_monitor): Likewise.
657
5558e7e6
MF		 6582010-04-14 Mike Frysinger <vapier@gentoo.org>
659
660 * interp.c (sim_write): Add const to buffer arg.
661
35aafff4
JB		 6622010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
663
664 * interp.c: Don't include sysdep.h
665
3725885a
RW		 6662010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
667
668 * configure: Regenerate.
669
d6416cdc
RW		 6702009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
671
81ecdfbb
RW		 672 * config.in: Regenerate.
673 * configure: Likewise.
674
d6416cdc
RW		 675 * configure: Regenerate.
676
b5bd9624
HPN		 6772008-07-11 Hans-Peter Nilsson <hp@axis.com>
678
679 * configure: Regenerate to track ../common/common.m4 changes.
680 * config.in: Ditto.
681
6efef468 6822008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 683 Daniel Jacobowitz <dan@codesourcery.com>
684 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 685
686 * configure: Regenerate.
687
60dc88db
RS		 6882007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
689
690 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
691 that unconditionally allows fmt_ps.
692 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
693 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
694 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
695 filter from 64,f to 32,f.
696 (PREFX): Change filter from 64 to 32.
697 (LDXC1, LUXC1): Provide separate mips32r2 implementations
698 that use do_load_double instead of do_load. Make both LUXC1
699 versions unpredictable if SizeFGR () != 64.
700 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
701 instead of do_store. Remove unused variable. Make both SUXC1
702 versions unpredictable if SizeFGR () != 64.
703
599ca73e
RS		 7042007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
705
706 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
707 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
708 shifts for that case.
709
2525df03
NC		 7102007-09-04 Nick Clifton <nickc@redhat.com>
711
712 * interp.c (options enum): Add OPTION_INFO_MEMORY.
713 (display_mem_info): New static variable.
714 (mips_option_handler): Handle OPTION_INFO_MEMORY.
715 (mips_options): Add info-memory and memory-info.
716 (sim_open): After processing the command line and board
717 specification, check display_mem_info. If it is set then
718 call the real handler for the --memory-info command line
719 switch.
720
35ee6e1e
JB		 7212007-08-24 Joel Brobecker <brobecker@adacore.com>
722
723 * configure.ac: Change license of multi-run.c to GPL version 3.
724 * configure: Regenerate.
725
d5fb0879
RS		 7262007-06-28 Richard Sandiford <richard@codesourcery.com>
727
728 * configure.ac, configure: Revert last patch.
729
2a2ce21b
RS		 7302007-06-26 Richard Sandiford <richard@codesourcery.com>
731
732 * configure.ac (sim_mipsisa3264_configs): New variable.
733 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
734 every configuration support all four targets, using the triplet to
735 determine the default.
736 * configure: Regenerate.
737
efdcccc9
RS		 7382007-06-25 Richard Sandiford <richard@codesourcery.com>
739
0a7692b2 740 * Makefile.in (m16run.o): New rule.
efdcccc9 741
f532a356
TS		 7422007-05-15 Thiemo Seufer <ths@mips.com>
743
744 * mips3264r2.igen (DSHD): Fix compile warning.
745
bfe9c90b
TS		 7462007-05-14 Thiemo Seufer <ths@mips.com>
747
748 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
749 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
750 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
751 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
752 for mips32r2.
753
53f4826b
TS		 7542007-03-01 Thiemo Seufer <ths@mips.com>
755
756 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
757 and mips64.
758
8bf3ddc8
TS		 7592007-02-20 Thiemo Seufer <ths@mips.com>
760
761 * dsp.igen: Update copyright notice.
762 * dsp2.igen: Fix copyright notice.
763
8b082fb1 7642007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 765 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 766
767 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
768 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
769 Add dsp2 to sim_igen_machine.
770 * configure: Regenerate.
771 * dsp.igen (do_ph_op): Add MUL support when op = 2.
772 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
773 (mulq_rs.ph): Use do_ph_mulq.
774 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
775 * mips.igen: Add dsp2 model and include dsp2.igen.
776 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
777 for *mips32r2, *mips64r2, *dsp.
778 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
779 for *mips32r2, *mips64r2, *dsp2.
780 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
781
b1004875 7822007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 783 Nigel Stephens <nigel@mips.com>
b1004875
TS		 784
785 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
786 jumps with hazard barrier.
787
f8df4c77 7882007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 789 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 790
791 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
792 after each call to sim_io_write.
793
b1004875 7942007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 795 Nigel Stephens <nigel@mips.com>
b1004875
TS		 796
797 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
798 supported by this simulator.
07802d98
TS		 799 (decode_coproc): Recognise additional CP0 Config registers
800 correctly.
801
14fb6c5a 8022007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 803 Nigel Stephens <nigel@mips.com>
804 David Ung <davidu@mips.com>
14fb6c5a
TS		 805
806 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
807 uninterpreted formats. If fmt is one of the uninterpreted types
808 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
809 fmt_word, and fmt_uninterpreted_64 like fmt_long.
810 (store_fpr): When writing an invalid odd register, set the
811 matching even register to fmt_unknown, not the following register.
812 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
813 the the memory window at offset 0 set by --memory-size command
814 line option.
815 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
816 point register.
817 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
818 register.
819 (sim_monitor): When returning the memory size to the MIPS
820 application, use the value in STATE_MEM_SIZE, not an arbitrary
821 hardcoded value.
822 (cop_lw): Don' mess around with FPR_STATE, just pass
823 fmt_uninterpreted_32 to StoreFPR.
824 (cop_sw): Similarly.
825 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
826 (cop_sd): Similarly.
827 * mips.igen (not_word_value): Single version for mips32, mips64
828 and mips16.
829
c8847145 8302007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 831 Nigel Stephens <nigel@mips.com>
c8847145
TS		 832
833 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
834 MBytes.
835
4b5d35ee
TS		 8362007-02-17 Thiemo Seufer <ths@mips.com>
837
838 * configure.ac (mips*-sde-elf*): Move in front of generic machine
839 configuration.
840 * configure: Regenerate.
841
3669427c
TS		 8422007-02-17 Thiemo Seufer <ths@mips.com>
843
844 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
845 Add mdmx to sim_igen_machine.
846 (mipsisa64*-*-*): Likewise. Remove dsp.
847 (mipsisa32*-*-*): Remove dsp.
848 * configure: Regenerate.
849
109ad085
TS		 8502007-02-13 Thiemo Seufer <ths@mips.com>
851
852 * configure.ac: Add mips*-sde-elf* target.
853 * configure: Regenerate.
854
921d7ad3
HPN		 8552006-12-21 Hans-Peter Nilsson <hp@axis.com>
856
857 * acconfig.h: Remove.
858 * config.in, configure: Regenerate.
859
02f97da7
TS		 8602006-11-07 Thiemo Seufer <ths@mips.com>
861
862 * dsp.igen (do_w_op): Fix compiler warning.
863
2d2733fc 8642006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 865 David Ung <davidu@mips.com>
2d2733fc
TS		 866
867 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
868 sim_igen_machine.
869 * configure: Regenerate.
870 * mips.igen (model): Add smartmips.
871 (MADDU): Increment ACX if carry.
872 (do_mult): Clear ACX.
873 (ROR,RORV): Add smartmips.
72f4393d 874 (include): Include smartmips.igen.
2d2733fc
TS		 875 * sim-main.h (ACX): Set to REGISTERS[89].
876 * smartmips.igen: New file.
877
d85c3a10 8782006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 879 David Ung <davidu@mips.com>
d85c3a10
TS		 880
881 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
882 mips3264r2.igen. Add missing dependency rules.
883 * m16e.igen: Support for mips16e save/restore instructions.
884
e85e3205
RE		 8852006-06-13 Richard Earnshaw <rearnsha@arm.com>
886
887 * configure: Regenerated.
888
2f0122dc
DJ		 8892006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
890
891 * configure: Regenerated.
892
20e95c23
DJ		 8932006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
894
895 * configure: Regenerated.
896
69088b17
CF		 8972006-05-15 Chao-ying Fu <fu@mips.com>
898
899 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
900
0275de4e
NC		 9012006-04-18 Nick Clifton <nickc@redhat.com>
902
903 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
904 statement.
905
b3a3ffef
HPN		 9062006-03-29 Hans-Peter Nilsson <hp@axis.com>
907
908 * configure: Regenerate.
909
40a5538e
CF		 9102005-12-14 Chao-ying Fu <fu@mips.com>
911
912 * Makefile.in (SIM_OBJS): Add dsp.o.
913 (dsp.o): New dependency.
914 (IGEN_INCLUDE): Add dsp.igen.
915 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
916 mipsisa64*-*-*): Add dsp to sim_igen_machine.
917 * configure: Regenerate.
918 * mips.igen: Add dsp model and include dsp.igen.
919 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
920 because these instructions are extended in DSP ASE.
921 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
922 adding 6 DSP accumulator registers and 1 DSP control register.
923 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
924 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
925 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
926 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
927 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
928 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
929 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
930 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
931 DSPCR_CCOND_SMASK): New define.
932 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
933 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
934
21d14896
ILT		 9352005-07-08 Ian Lance Taylor <ian@airs.com>
936
937 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
938
b16d63da 9392005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 940 Nigel Stephens <nigel@mips.com>
941
942 * mips.igen: New mips16e model and include m16e.igen.
943 (check_u64): Add mips16e tag.
944 * m16e.igen: New file for MIPS16e instructions.
945 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
946 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
947 models.
948 * configure: Regenerate.
b16d63da 949
e70cb6cd 9502005-05-26 David Ung <davidu@mips.com>
72f4393d 951
e70cb6cd
CD		 952 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
953 tags to all instructions which are applicable to the new ISAs.
954 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
955 vr.igen.
956 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 957 instructions.
e70cb6cd
CD		 958 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
959 to mips.igen.
960 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
961 * configure: Regenerate.
72f4393d 962
2b193c4a
MK		 9632005-03-23 Mark Kettenis <kettenis@gnu.org>
964
965 * configure: Regenerate.
966
35695fd6
AC		 9672005-01-14 Andrew Cagney <cagney@gnu.org>
968
969 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
970 explicit call to AC_CONFIG_HEADER.
971 * configure: Regenerate.
972
f0569246
AC		 9732005-01-12 Andrew Cagney <cagney@gnu.org>
974
975 * configure.ac: Update to use ../common/common.m4.
976 * configure: Re-generate.
977
38f48d72
AC		 9782005-01-11 Andrew Cagney <cagney@localhost.localdomain>
979
980 * configure: Regenerated to track ../common/aclocal.m4 changes.
981
b7026657
AC		 9822005-01-07 Andrew Cagney <cagney@gnu.org>
983
984 * configure.ac: Rename configure.in, require autoconf 2.59.
985 * configure: Re-generate.
986
379832de
HPN		 9872004-12-08 Hans-Peter Nilsson <hp@axis.com>
988
989 * configure: Regenerate for ../common/aclocal.m4 update.
990
cd62154c 9912004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 992
cd62154c
AC		 993 Committed by Andrew Cagney.
994 * m16.igen (CMP, CMPI): Fix assembler.
995
e5da76ec
CD		 9962004-08-18 Chris Demetriou <cgd@broadcom.com>
997
998 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
999 * configure: Regenerate.
1000
139181c8
CD		 10012004-06-25 Chris Demetriou <cgd@broadcom.com>
1002
1003 * configure.in (sim_m16_machine): Include mipsIII.
1004 * configure: Regenerate.
1005
1a27f959
CD		 10062004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1007
72f4393d 1008 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1009 from COP0_BADVADDR.
1010 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1011
5dbb7b5a
CD		 10122004-04-10 Chris Demetriou <cgd@broadcom.com>
1013
1014 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1015
14234056
CD		 10162004-04-09 Chris Demetriou <cgd@broadcom.com>
1017
1018 * mips.igen (check_fmt): Remove.
1019 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1020 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1021 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1022 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1023 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1024 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1025 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1026 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1027 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1028 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1029
c6f9085c
CD		 10302004-04-09 Chris Demetriou <cgd@broadcom.com>
1031
1032 * sb1.igen (check_sbx): New function.
1033 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1034
11d66e66 10352004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1036 Richard Sandiford <rsandifo@redhat.com>
1037
1038 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1039 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1040 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1041 separate implementations for mipsIV and mipsV. Use new macros to
1042 determine whether the restrictions apply.
1043
b3208fb8
CD		 10442004-01-19 Chris Demetriou <cgd@broadcom.com>
1045
1046 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1047 (check_mult_hilo): Improve comments.
1048 (check_div_hilo): Likewise. Also, fork off a new version
1049 to handle mips32/mips64 (since there are no hazards to check
1050 in MIPS32/MIPS64).
1051
9a1d84fb
CD		 10522003-06-17 Richard Sandiford <rsandifo@redhat.com>
1053
1054 * mips.igen (do_dmultx): Fix check for negative operands.
1055
ae451ac6
ILT		 10562003-05-16 Ian Lance Taylor <ian@airs.com>
1057
1058 * Makefile.in (SHELL): Make sure this is defined.
1059 (various): Use $(SHELL) whenever we invoke move-if-change.
1060
dd69d292
CD		 10612003-05-03 Chris Demetriou <cgd@broadcom.com>
1062
1063 * cp1.c: Tweak attribution slightly.
1064 * cp1.h: Likewise.
1065 * mdmx.c: Likewise.
1066 * mdmx.igen: Likewise.
1067 * mips3d.igen: Likewise.
1068 * sb1.igen: Likewise.
1069
bcd0068e
CD		 10702003-04-15 Richard Sandiford <rsandifo@redhat.com>
1071
1072 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1073 unsigned operands.
1074
6b4a8935
AC		 10752003-02-27 Andrew Cagney <cagney@redhat.com>
1076
601da316
AC		 1077 * interp.c (sim_open): Rename _bfd to bfd.
1078 (sim_create_inferior): Ditto.
6b4a8935 1079
d29e330f
CD		 10802003-01-14 Chris Demetriou <cgd@broadcom.com>
1081
1082 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1083
a2353a08
CD		 10842003-01-14 Chris Demetriou <cgd@broadcom.com>
1085
1086 * mips.igen (EI, DI): Remove.
1087
80551777
CD		 10882003-01-05 Richard Sandiford <rsandifo@redhat.com>
1089
1090 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1091
4c54fc26
CD		 10922003-01-04 Richard Sandiford <rsandifo@redhat.com>
1093 Andrew Cagney <ac131313@redhat.com>
1094 Gavin Romig-Koch <gavin@redhat.com>
1095 Graydon Hoare <graydon@redhat.com>
1096 Aldy Hernandez <aldyh@redhat.com>
1097 Dave Brolley <brolley@redhat.com>
1098 Chris Demetriou <cgd@broadcom.com>
1099
1100 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1101 (sim_mach_default): New variable.
1102 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1103 Add a new simulator generator, MULTI.
1104 * configure: Regenerate.
1105 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1106 (multi-run.o): New dependency.
1107 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1108 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1109 (tmp-multi): Combine them.
1110 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1111 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1112 (distclean-extra): New rule.
1113 * sim-main.h: Include bfd.h.
1114 (MIPS_MACH): New macro.
1115 * mips.igen (vr4120, vr5400, vr5500): New models.
1116 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1117 * vr.igen: Replace with new version.
1118
e6c674b8
CD		 11192003-01-04 Chris Demetriou <cgd@broadcom.com>
1120
1121 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1122 * configure: Regenerate.
1123
28f50ac8
CD		 11242002-12-31 Chris Demetriou <cgd@broadcom.com>
1125
1126 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1127 * mips.igen: Remove all invocations of check_branch_bug and
1128 mark_branch_bug.
1129
5071ffe6
CD		 11302002-12-16 Chris Demetriou <cgd@broadcom.com>
1131
72f4393d 1132 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1133
06e7837e
CD		 11342002-07-30 Chris Demetriou <cgd@broadcom.com>
1135
1136 * mips.igen (do_load_double, do_store_double): New functions.
1137 (LDC1, SDC1): Rename to...
1138 (LDC1b, SDC1b): respectively.
1139 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1140
2265c243
MS		 11412002-07-29 Michael Snyder <msnyder@redhat.com>
1142
1143 * cp1.c (fp_recip2): Modify initialization expression so that
1144 GCC will recognize it as constant.
1145
a2f8b4f3
CD		 11462002-06-18 Chris Demetriou <cgd@broadcom.com>
1147
1148 * mdmx.c (SD_): Delete.
1149 (Unpredictable): Re-define, for now, to directly invoke
1150 unpredictable_action().
1151 (mdmx_acc_op): Fix error in .ob immediate handling.
1152
b4b6c939
AC		 11532002-06-18 Andrew Cagney <cagney@redhat.com>
1154
1155 * interp.c (sim_firmware_command): Initialize `address'.
1156
c8cca39f
AC		 11572002-06-16 Andrew Cagney <ac131313@redhat.com>
1158
1159 * configure: Regenerated to track ../common/aclocal.m4 changes.
1160
e7e81181 11612002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1162 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1163
1164 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1165 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1166 * mips.igen: Include mips3d.igen.
1167 (mips3d): New model name for MIPS-3D ASE instructions.
1168 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1169 instructions.
e7e81181
CD		 1170 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1171 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1172 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1173 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1174 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1175 (RSquareRoot1, RSquareRoot2): New macros.
1176 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1177 (fp_rsqrt2): New functions.
1178 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1179 * configure: Regenerate.
1180
3a2b820e 11812002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1182 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1183
1184 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1185 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1186 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1187 (convert): Note that this function is not used for paired-single
1188 format conversions.
1189 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1190 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1191 (check_fmt_p): Enable paired-single support.
1192 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1193 (PUU.PS): New instructions.
1194 (CVT.S.fmt): Don't use this instruction for paired-single format
1195 destinations.
1196 * sim-main.h (FP_formats): New value 'fmt_ps.'
1197 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1198 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1199
d18ea9c2
CD		 12002002-06-12 Chris Demetriou <cgd@broadcom.com>
1201
1202 * mips.igen: Fix formatting of function calls in
1203 many FP operations.
1204
95fd5cee
CD		 12052002-06-12 Chris Demetriou <cgd@broadcom.com>
1206
1207 * mips.igen (MOVN, MOVZ): Trace result.
1208 (TNEI): Print "tnei" as the opcode name in traces.
1209 (CEIL.W): Add disassembly string for traces.
1210 (RSQRT.fmt): Make location of disassembly string consistent
1211 with other instructions.
1212
4f0d55ae
CD		 12132002-06-12 Chris Demetriou <cgd@broadcom.com>
1214
1215 * mips.igen (X): Delete unused function.
1216
3c25f8c7
AC		 12172002-06-08 Andrew Cagney <cagney@redhat.com>
1218
1219 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1220
f3c08b7e 12212002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1222 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1223
1224 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1225 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1226 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1227 (fp_nmsub): New prototypes.
1228 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1229 (NegMultiplySub): New defines.
1230 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1231 (MADD.D, MADD.S): Replace with...
1232 (MADD.fmt): New instruction.
1233 (MSUB.D, MSUB.S): Replace with...
1234 (MSUB.fmt): New instruction.
1235 (NMADD.D, NMADD.S): Replace with...
1236 (NMADD.fmt): New instruction.
1237 (NMSUB.D, MSUB.S): Replace with...
1238 (NMSUB.fmt): New instruction.
1239
52714ff9 12402002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1241 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1242
1243 * cp1.c: Fix more comment spelling and formatting.
1244 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1245 (denorm_mode): New function.
1246 (fpu_unary, fpu_binary): Round results after operation, collect
1247 status from rounding operations, and update the FCSR.
1248 (convert): Collect status from integer conversions and rounding
1249 operations, and update the FCSR. Adjust NaN values that result
1250 from conversions. Convert to use sim_io_eprintf rather than
1251 fprintf, and remove some debugging code.
1252 * cp1.h (fenr_FS): New define.
1253
577d8c4b
CD		 12542002-06-07 Chris Demetriou <cgd@broadcom.com>
1255
1256 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1257 rounding mode to sim FP rounding mode flag conversion code into...
1258 (rounding_mode): New function.
1259
196496ed
CD		 12602002-06-07 Chris Demetriou <cgd@broadcom.com>
1261
1262 * cp1.c: Clean up formatting of a few comments.
1263 (value_fpr): Reformat switch statement.
1264
cfe9ea23 12652002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1266 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1267
1268 * cp1.h: New file.
1269 * sim-main.h: Include cp1.h.
1270 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1271 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1272 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1273 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1274 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1275 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1276 * cp1.c: Don't include sim-fpu.h; already included by
1277 sim-main.h. Clean up formatting of some comments.
1278 (NaN, Equal, Less): Remove.
1279 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1280 (fp_cmp): New functions.
1281 * mips.igen (do_c_cond_fmt): Remove.
1282 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1283 Compare. Add result tracing.
1284 (CxC1): Remove, replace with...
1285 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1286 (DMxC1): Remove, replace with...
1287 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1288 (MxC1): Remove, replace with...
1289 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1290
ee7254b0
CD		 12912002-06-04 Chris Demetriou <cgd@broadcom.com>
1292
1293 * sim-main.h (FGRIDX): Remove, replace all uses with...
1294 (FGR_BASE): New macro.
1295 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1296 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1297 (NR_FGR, FGR): Likewise.
1298 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1299 * mips.igen: Likewise.
1300
d3eb724f
CD		 13012002-06-04 Chris Demetriou <cgd@broadcom.com>
1302
1303 * cp1.c: Add an FSF Copyright notice to this file.
1304
ba46ddd0 13052002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1306 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1307
1308 * cp1.c (Infinity): Remove.
1309 * sim-main.h (Infinity): Likewise.
1310
1311 * cp1.c (fp_unary, fp_binary): New functions.
1312 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1313 (fp_sqrt): New functions, implemented in terms of the above.
1314 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1315 (Recip, SquareRoot): Remove (replaced by functions above).
1316 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1317 (fp_recip, fp_sqrt): New prototypes.
1318 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1319 (Recip, SquareRoot): Replace prototypes with #defines which
1320 invoke the functions above.
72f4393d 1321
18d8a52d
CD		 13222002-06-03 Chris Demetriou <cgd@broadcom.com>
1323
1324 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1325 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1326 file, remove PARAMS from prototypes.
1327 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1328 simulator state arguments.
1329 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1330 pass simulator state arguments.
1331 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1332 (store_fpr, convert): Remove 'sd' argument.
1333 (value_fpr): Likewise. Convert to use 'SD' instead.
1334
0f154cbd
CD		 13352002-06-03 Chris Demetriou <cgd@broadcom.com>
1336
1337 * cp1.c (Min, Max): Remove #if 0'd functions.
1338 * sim-main.h (Min, Max): Remove.
1339
e80fc152
CD		 13402002-06-03 Chris Demetriou <cgd@broadcom.com>
1341
1342 * cp1.c: fix formatting of switch case and default labels.
1343 * interp.c: Likewise.
1344 * sim-main.c: Likewise.
1345
bad673a9
CD		 13462002-06-03 Chris Demetriou <cgd@broadcom.com>
1347
1348 * cp1.c: Clean up comments which describe FP formats.
1349 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1350
7cbea089 13512002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1352 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1353
1354 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1355 Broadcom SiByte SB-1 processor configurations.
1356 * configure: Regenerate.
1357 * sb1.igen: New file.
1358 * mips.igen: Include sb1.igen.
1359 (sb1): New model.
1360 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1361 * mdmx.igen: Add "sb1" model to all appropriate functions and
1362 instructions.
1363 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1364 (ob_func, ob_acc): Reference the above.
1365 (qh_acc): Adjust to keep the same size as ob_acc.
1366 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1367 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1368
909daa82
CD		 13692002-06-03 Chris Demetriou <cgd@broadcom.com>
1370
1371 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1372
f4f1b9f1 13732002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1374 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1375
1376 * mips.igen (mdmx): New (pseudo-)model.
1377 * mdmx.c, mdmx.igen: New files.
1378 * Makefile.in (SIM_OBJS): Add mdmx.o.
1379 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1380 New typedefs.
1381 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1382 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1383 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1384 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1385 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1386 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1387 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1388 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1389 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1390 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1391 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1392 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1393 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1394 (qh_fmtsel): New macros.
1395 (_sim_cpu): New member "acc".
1396 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1397 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1398
5accf1ff
CD		 13992002-05-01 Chris Demetriou <cgd@broadcom.com>
1400
1401 * interp.c: Use 'deprecated' rather than 'depreciated.'
1402 * sim-main.h: Likewise.
1403
402586aa
CD		 14042002-05-01 Chris Demetriou <cgd@broadcom.com>
1405
1406 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1407 which wouldn't compile anyway.
1408 * sim-main.h (unpredictable_action): New function prototype.
1409 (Unpredictable): Define to call igen function unpredictable().
1410 (NotWordValue): New macro to call igen function not_word_value().
1411 (UndefinedResult): Remove.
1412 * interp.c (undefined_result): Remove.
1413 (unpredictable_action): New function.
1414 * mips.igen (not_word_value, unpredictable): New functions.
1415 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1416 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1417 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1418 NotWordValue() to check for unpredictable inputs, then
1419 Unpredictable() to handle them.
1420
c9b9995a
CD		 14212002-02-24 Chris Demetriou <cgd@broadcom.com>
1422
1423 * mips.igen: Fix formatting of calls to Unpredictable().
1424
e1015982
AC		 14252002-04-20 Andrew Cagney <ac131313@redhat.com>
1426
1427 * interp.c (sim_open): Revert previous change.
1428
b882a66b
AO		 14292002-04-18 Alexandre Oliva <aoliva@redhat.com>
1430
1431 * interp.c (sim_open): Disable chunk of code that wrote code in
1432 vector table entries.
1433
c429b7dd
CD		 14342002-03-19 Chris Demetriou <cgd@broadcom.com>
1435
1436 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1437 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1438 unused definitions.
1439
37d146fa
CD		 14402002-03-19 Chris Demetriou <cgd@broadcom.com>
1441
1442 * cp1.c: Fix many formatting issues.
1443
07892c0b
CD		 14442002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1445
1446 * cp1.c (fpu_format_name): New function to replace...
1447 (DOFMT): This. Delete, and update all callers.
1448 (fpu_rounding_mode_name): New function to replace...
1449 (RMMODE): This. Delete, and update all callers.
1450
487f79b7
CD		 14512002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1452
1453 * interp.c: Move FPU support routines from here to...
1454 * cp1.c: Here. New file.
1455 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1456 (cp1.o): New target.
1457
1e799e28
CD		 14582002-03-12 Chris Demetriou <cgd@broadcom.com>
1459
1460 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1461 * mips.igen (mips32, mips64): New models, add to all instructions
1462 and functions as appropriate.
1463 (loadstore_ea, check_u64): New variant for model mips64.
1464 (check_fmt_p): New variant for models mipsV and mips64, remove
1465 mipsV model marking fro other variant.
1466 (SLL) Rename to...
1467 (SLLa) this.
1468 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1469 for mips32 and mips64.
1470 (DCLO, DCLZ): New instructions for mips64.
1471
82f728db
CD		 14722002-03-07 Chris Demetriou <cgd@broadcom.com>
1473
1474 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1475 immediate or code as a hex value with the "%#lx" format.
1476 (ANDI): Likewise, and fix printed instruction name.
1477
b96e7ef1
CD		 14782002-03-05 Chris Demetriou <cgd@broadcom.com>
1479
1480 * sim-main.h (UndefinedResult, Unpredictable): New macros
1481 which currently do nothing.
1482
d35d4f70
CD		 14832002-03-05 Chris Demetriou <cgd@broadcom.com>
1484
1485 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1486 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1487 (status_CU3): New definitions.
1488
1489 * sim-main.h (ExceptionCause): Add new values for MIPS32
1490 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1491 for DebugBreakPoint and NMIReset to note their status in
1492 MIPS32 and MIPS64.
1493 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1494 (SignalExceptionCacheErr): New exception macros.
1495
3ad6f714
CD		 14962002-03-05 Chris Demetriou <cgd@broadcom.com>
1497
1498 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1499 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1500 is always enabled.
1501 (SignalExceptionCoProcessorUnusable): Take as argument the
1502 unusable coprocessor number.
1503
86b77b47
CD		 15042002-03-05 Chris Demetriou <cgd@broadcom.com>
1505
1506 * mips.igen: Fix formatting of all SignalException calls.
1507
97a88e93 15082002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1509
1510 * sim-main.h (SIGNEXTEND): Remove.
1511
97a88e93 15122002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1513
1514 * mips.igen: Remove gencode comment from top of file, fix
1515 spelling in another comment.
1516
97a88e93 15172002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1518
1519 * mips.igen (check_fmt, check_fmt_p): New functions to check
1520 whether specific floating point formats are usable.
1521 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1522 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1523 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1524 Use the new functions.
1525 (do_c_cond_fmt): Remove format checks...
1526 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1527
97a88e93 15282002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1529
1530 * mips.igen: Fix formatting of check_fpu calls.
1531
41774c9d
CD		 15322002-03-03 Chris Demetriou <cgd@broadcom.com>
1533
1534 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1535
4a0bd876
CD		 15362002-03-03 Chris Demetriou <cgd@broadcom.com>
1537
1538 * mips.igen: Remove whitespace at end of lines.
1539
09297648
CD		 15402002-03-02 Chris Demetriou <cgd@broadcom.com>
1541
1542 * mips.igen (loadstore_ea): New function to do effective
1543 address calculations.
1544 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1545 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1546 CACHE): Use loadstore_ea to do effective address computations.
1547
043b7057
CD		 15482002-03-02 Chris Demetriou <cgd@broadcom.com>
1549
1550 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1551 * mips.igen (LL, CxC1, MxC1): Likewise.
1552
c1e8ada4
CD		 15532002-03-02 Chris Demetriou <cgd@broadcom.com>
1554
1555 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1556 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1557 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1558 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1559 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1560 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1561 Don't split opcode fields by hand, use the opcode field values
1562 provided by igen.
1563
3e1dca16
CD		 15642002-03-01 Chris Demetriou <cgd@broadcom.com>
1565
1566 * mips.igen (do_divu): Fix spacing.
1567
1568 * mips.igen (do_dsllv): Move to be right before DSLLV,
1569 to match the rest of the do_<shift> functions.
1570
fff8d27d
CD		 15712002-03-01 Chris Demetriou <cgd@broadcom.com>
1572
1573 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1574 DSRL32, do_dsrlv): Trace inputs and results.
1575
0d3e762b
CD		 15762002-03-01 Chris Demetriou <cgd@broadcom.com>
1577
1578 * mips.igen (CACHE): Provide instruction-printing string.
1579
1580 * interp.c (signal_exception): Comment tokens after #endif.
1581
eb5fcf93
CD		 15822002-02-28 Chris Demetriou <cgd@broadcom.com>
1583
1584 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1585 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1586 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1587 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1588 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1589 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1590 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1591 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1592
bb22bd7d
CD		 15932002-02-28 Chris Demetriou <cgd@broadcom.com>
1594
1595 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1596 instruction-printing string.
1597 (LWU): Use '64' as the filter flag.
1598
91a177cf
CD		 15992002-02-28 Chris Demetriou <cgd@broadcom.com>
1600
1601 * mips.igen (SDXC1): Fix instruction-printing string.
1602
387f484a
CD		 16032002-02-28 Chris Demetriou <cgd@broadcom.com>
1604
1605 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1606 filter flags "32,f".
1607
3d81f391
CD		 16082002-02-27 Chris Demetriou <cgd@broadcom.com>
1609
1610 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1611 as the filter flag.
1612
af5107af
CD		 16132002-02-27 Chris Demetriou <cgd@broadcom.com>
1614
1615 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1616 add a comma) so that it more closely match the MIPS ISA
1617 documentation opcode partitioning.
1618 (PREF): Put useful names on opcode fields, and include
1619 instruction-printing string.
1620
ca971540
CD		 16212002-02-27 Chris Demetriou <cgd@broadcom.com>
1622
1623 * mips.igen (check_u64): New function which in the future will
1624 check whether 64-bit instructions are usable and signal an
1625 exception if not. Currently a no-op.
1626 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1627 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1628 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1629 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1630
1631 * mips.igen (check_fpu): New function which in the future will
1632 check whether FPU instructions are usable and signal an exception
1633 if not. Currently a no-op.
1634 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1635 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1636 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1637 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1638 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1639 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1640 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1641 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1642
1c47a468
CD		 16432002-02-27 Chris Demetriou <cgd@broadcom.com>
1644
1645 * mips.igen (do_load_left, do_load_right): Move to be immediately
1646 following do_load.
1647 (do_store_left, do_store_right): Move to be immediately following
1648 do_store.
1649
603a98e7
CD		 16502002-02-27 Chris Demetriou <cgd@broadcom.com>
1651
1652 * mips.igen (mipsV): New model name. Also, add it to
1653 all instructions and functions where it is appropriate.
1654
c5d00cc7
CD		 16552002-02-18 Chris Demetriou <cgd@broadcom.com>
1656
1657 * mips.igen: For all functions and instructions, list model
1658 names that support that instruction one per line.
1659
074e9cb8
CD		 16602002-02-11 Chris Demetriou <cgd@broadcom.com>
1661
1662 * mips.igen: Add some additional comments about supported
1663 models, and about which instructions go where.
1664 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1665 order as is used in the rest of the file.
1666
9805e229
CD		 16672002-02-11 Chris Demetriou <cgd@broadcom.com>
1668
1669 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1670 indicating that ALU32_END or ALU64_END are there to check
1671 for overflow.
1672 (DADD): Likewise, but also remove previous comment about
1673 overflow checking.
1674
f701dad2
CD		 16752002-02-10 Chris Demetriou <cgd@broadcom.com>
1676
1677 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1678 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1679 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1680 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1681 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1682 fields (i.e., add and move commas) so that they more closely
1683 match the MIPS ISA documentation opcode partitioning.
1684
16852002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1686
72f4393d
L		 1687 * mips.igen (ADDI): Print immediate value.
1688 (BREAK): Print code.
1689 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1690 (SLL): Print "nop" specially, and don't run the code
1691 that does the shift for the "nop" case.
20ae0098 1692
9e52972e
FF		 16932001-11-17 Fred Fish <fnf@redhat.com>
1694
1695 * sim-main.h (float_operation): Move enum declaration outside
1696 of _sim_cpu struct declaration.
1697
c0efbca4
JB		 16982001-04-12 Jim Blandy <jimb@redhat.com>
1699
1700 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1701 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1702 set of the FCSR.
1703 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1704 PENDING_FILL, and you can get the intended effect gracefully by
1705 calling PENDING_SCHED directly.
1706
fb891446
BE		 17072001-02-23 Ben Elliston <bje@redhat.com>
1708
1709 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1710 already defined elsewhere.
1711
8030f857
BE		 17122001-02-19 Ben Elliston <bje@redhat.com>
1713
1714 * sim-main.h (sim_monitor): Return an int.
1715 * interp.c (sim_monitor): Add return values.
1716 (signal_exception): Handle error conditions from sim_monitor.
1717
56b48a7a
CD		 17182001-02-08 Ben Elliston <bje@redhat.com>
1719
1720 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1721 (store_memory): Likewise, pass cia to sim_core_write*.
1722
d3ee60d9
FCE		 17232000-10-19 Frank Ch. Eigler <fche@redhat.com>
1724
1725 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1726 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1727
071da002
AC		 1728Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1729
1730 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1731 * Makefile.in: Don't delete *.igen when cleaning directory.
1732
a28c02cd
AC		 1733Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1734
1735 * m16.igen (break): Call SignalException not sim_engine_halt.
1736
80ee11fa
AC		 1737Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1738
1739 From Jason Eckhardt:
1740 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1741
673388c0
AC		 1742Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1745
4c0deff4
NC		 17462000-05-24 Michael Hayes <mhayes@cygnus.com>
1747
1748 * mips.igen (do_dmultx): Fix typo.
1749
eb2d80b4
AC		 1750Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * configure: Regenerated to track ../common/aclocal.m4 changes.
1753
dd37a34b
AC		 1754Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1755
1756 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1757
4c0deff4
NC		 17582000-04-12 Frank Ch. Eigler <fche@redhat.com>
1759
1760 * sim-main.h (GPR_CLEAR): Define macro.
1761
e30db738
AC		 1762Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1763
1764 * interp.c (decode_coproc): Output long using %lx and not %s.
1765
cb7450ea
FCE		 17662000-03-21 Frank Ch. Eigler <fche@redhat.com>
1767
1768 * interp.c (sim_open): Sort & extend dummy memory regions for
1769 --board=jmr3904 for eCos.
1770
a3027dd7
FCE		 17712000-03-02 Frank Ch. Eigler <fche@redhat.com>
1772
1773 * configure: Regenerated.
1774
1775Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1776
1777 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1778 calls, conditional on the simulator being in verbose mode.
1779
dfcd3bfb
JM		 1780Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1781
1782 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1783 cache don't get ReservedInstruction traps.
1784
c2d11a7d
JM		 17851999-11-29 Mark Salter <msalter@cygnus.com>
1786
1787 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1788 to clear status bits in sdisr register. This is how the hardware works.
1789
1790 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1791 being used by cygmon.
1792
4ce44c66
JM		 17931999-11-11 Andrew Haley <aph@cygnus.com>
1794
1795 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1796 instructions.
1797
cff3e48b
JM		 1798Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1799
1800 * mips.igen (MULT): Correct previous mis-applied patch.
1801
d4f3574e
SS		 1802Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1803
1804 * mips.igen (delayslot32): Handle sequence like
1805 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1806 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1807 (MULT): Actually pass the third register...
1808
18091999-09-03 Mark Salter <msalter@cygnus.com>
1810
1811 * interp.c (sim_open): Added more memory aliases for additional
1812 hardware being touched by cygmon on jmr3904 board.
1813
1814Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817
a0b3c4fd
JM		 1818Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1819
1820 * interp.c (sim_store_register): Handle case where client - GDB -
1821 specifies that a 4 byte register is 8 bytes in size.
1822 (sim_fetch_register): Ditto.
72f4393d 1823
adf40b2e
JM		 18241999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1825
1826 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1827 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1828 (idt_monitor_base): Base address for IDT monitor traps.
1829 (pmon_monitor_base): Ditto for PMON.
1830 (lsipmon_monitor_base): Ditto for LSI PMON.
1831 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1832 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1833 (sim_firmware_command): New function.
1834 (mips_option_handler): Call it for OPTION_FIRMWARE.
1835 (sim_open): Allocate memory for idt_monitor region. If "--board"
1836 option was given, add no monitor by default. Add BREAK hooks only if
1837 monitors are also there.
72f4393d 1838
43e526b9
JM		 1839Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1840
1841 * interp.c (sim_monitor): Flush output before reading input.
1842
1843Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1844
1845 * tconfig.in (SIM_HANDLES_LMA): Always define.
1846
1847Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 From Mark Salter <msalter@cygnus.com>:
1850 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1851 (sim_open): Add setup for BSP board.
1852
9846de1b
JM		 1853Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1856 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1857 them as unimplemented.
1858
cd0fc7c3
SS		 18591999-05-08 Felix Lee <flee@cygnus.com>
1860
1861 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1862
7a292a7a
SS		 18631999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1864
1865 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1866
1867Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1868
1869 * configure.in: Any mips64vr5*-*-* target should have
1870 -DTARGET_ENABLE_FR=1.
1871 (default_endian): Any mips64vr*el-*-* target should default to
1872 LITTLE_ENDIAN.
1873 * configure: Re-generate.
1874
18751999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1876
1877 * mips.igen (ldl): Extend from _16_, not 32.
1878
1879Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1880
1881 * interp.c (sim_store_register): Force registers written to by GDB
1882 into an un-interpreted state.
1883
c906108c
SS		 18841999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1885
1886 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1887 CPU, start periodic background I/O polls.
72f4393d 1888 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1889
18901998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1891
1892 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1893
c906108c
SS		 1894Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1895
1896 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1897 case statement.
1898
18991998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1900
1901 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1902 (load_word): Call SIM_CORE_SIGNAL hook on error.
1903 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1904 starting. For exception dispatching, pass PC instead of NULL_CIA.
1905 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1906 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1907 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1908 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1909 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1910 * mips.igen (*): Replace memory-related SignalException* calls
1911 with references to SIM_CORE_SIGNAL hook.
72f4393d 1912
c906108c
SS		 1913 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1914 fix.
1915 * sim-main.c (*): Minor warning cleanups.
72f4393d 1916
c906108c
SS		 19171998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1918
1919 * m16.igen (DADDIU5): Correct type-o.
1920
1921Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1922
1923 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1924 variables.
1925
1926Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1927
1928 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1929 to include path.
1930 (interp.o): Add dependency on itable.h
1931 (oengine.c, gencode): Delete remaining references.
1932 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1933
c906108c 19341998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1935
c906108c
SS		 1936 * vr4run.c: New.
1937 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1938 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1939 tmp-run-hack) : New.
1940 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1941 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1942 Drop the "64" qualifier to get the HACK generator working.
1943 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1944 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1945 qualifier to get the hack generator working.
1946 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1947 (DSLL): Use do_dsll.
1948 (DSLLV): Use do_dsllv.
1949 (DSRA): Use do_dsra.
1950 (DSRL): Use do_dsrl.
1951 (DSRLV): Use do_dsrlv.
1952 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1953 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1954 get the HACK generator working.
1955 (MACC) Rename to get the HACK generator working.
1956 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1957
c906108c
SS		 19581998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1959
1960 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1961 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1962
c906108c
SS		 19631998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1964
1965 * mips/interp.c (DEBUG): Cleanups.
1966
19671998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1968
1969 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1970 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1971
c906108c
SS		 19721998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1973
1974 * interp.c (sim_close): Uninstall modules.
1975
1976Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 * sim-main.h, interp.c (sim_monitor): Change to global
1979 function.
1980
1981Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * configure.in (vr4100): Only include vr4100 instructions in
1984 simulator.
1985 * configure: Re-generate.
1986 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1987
1988Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1991 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1992 true alternative.
1993
1994 * configure.in (sim_default_gen, sim_use_gen): Replace with
1995 sim_gen.
1996 (--enable-sim-igen): Delete config option. Always using IGEN.
1997 * configure: Re-generate.
72f4393d 1998
c906108c
SS		 1999 * Makefile.in (gencode): Kill, kill, kill.
2000 * gencode.c: Ditto.
72f4393d 2001
c906108c
SS		 2002Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2005 bit mips16 igen simulator.
2006 * configure: Re-generate.
2007
2008 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2009 as part of vr4100 ISA.
2010 * vr.igen: Mark all instructions as 64 bit only.
2011
2012Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2015 Pacify GCC.
2016
2017Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2020 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2021 * configure: Re-generate.
2022
2023 * m16.igen (BREAK): Define breakpoint instruction.
2024 (JALX32): Mark instruction as mips16 and not r3900.
2025 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2026
2027 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2028
2029Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2030
2031 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2032 insn as a debug breakpoint.
2033
2034 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2035 pending.slot_size.
2036 (PENDING_SCHED): Clean up trace statement.
2037 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2038 (PENDING_FILL): Delay write by only one cycle.
2039 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2040
2041 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2042 of pending writes.
2043 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2044 32 & 64.
2045 (pending_tick): Move incrementing of index to FOR statement.
2046 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2047
c906108c
SS		 2048 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2049 build simulator.
2050 * configure: Re-generate.
72f4393d 2051
c906108c
SS		 2052 * interp.c (sim_engine_run OLD): Delete explicit call to
2053 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2054
c906108c
SS		 2055Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2056
2057 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2058 interrupt level number to match changed SignalExceptionInterrupt
2059 macro.
2060
2061Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2062
2063 * interp.c: #include "itable.h" if WITH_IGEN.
2064 (get_insn_name): New function.
2065 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2066 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2067
2068Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2069
2070 * configure: Rebuilt to inhale new common/aclocal.m4.
2071
2072Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2073
2074 * dv-tx3904sio.c: Include sim-assert.h.
2075
2076Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2077
2078 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2079 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2080 Reorganize target-specific sim-hardware checks.
2081 * configure: rebuilt.
2082 * interp.c (sim_open): For tx39 target boards, set
2083 OPERATING_ENVIRONMENT, add tx3904sio devices.
2084 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2085 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2086
c906108c
SS		 2087 * dv-tx3904irc.c: Compiler warning clean-up.
2088 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2089 frequent hw-trace messages.
2090
2091Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2094
2095Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2096
2097 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2098
2099 * vr.igen: New file.
2100 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2101 * mips.igen: Define vr4100 model. Include vr.igen.
2102Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2103
2104 * mips.igen (check_mf_hilo): Correct check.
2105
2106Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * sim-main.h (interrupt_event): Add prototype.
2109
2110 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2111 register_ptr, register_value.
2112 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2113
2114 * sim-main.h (tracefh): Make extern.
2115
2116Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2117
2118 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2119 Reduce unnecessarily high timer event frequency.
c906108c 2120 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2121
c906108c
SS		 2122Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2123
2124 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2125 to allay warnings.
2126 (interrupt_event): Made non-static.
72f4393d 2127
c906108c
SS		 2128 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2129 interchange of configuration values for external vs. internal
2130 clock dividers.
72f4393d 2131
c906108c
SS		 2132Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2133
72f4393d 2134 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2135 simulator-reserved break instructions.
2136 * gencode.c (build_instruction): Ditto.
2137 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2138 reserved instructions now use exception vector, rather
c906108c
SS		 2139 than halting sim.
2140 * sim-main.h: Moved magic constants to here.
2141
2142Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2143
2144 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2145 register upon non-zero interrupt event level, clear upon zero
2146 event value.
2147 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2148 by passing zero event value.
2149 (*_io_{read,write}_buffer): Endianness fixes.
2150 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2151 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2152
2153 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2154 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2155
c906108c
SS		 2156Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2157
72f4393d 2158 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2159 and BigEndianCPU.
2160
2161Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2162
2163 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2164 parts.
2165 * configure: Update.
2166
2167Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2168
2169 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2170 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2171 * configure.in: Include tx3904tmr in hw_device list.
2172 * configure: Rebuilt.
2173 * interp.c (sim_open): Instantiate three timer instances.
2174 Fix address typo of tx3904irc instance.
2175
2176Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2177
2178 * interp.c (signal_exception): SystemCall exception now uses
2179 the exception vector.
2180
2181Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2182
2183 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2184 to allay warnings.
2185
2186Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2189
2190Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2193
2194 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2195 sim-main.h. Declare a struct hw_descriptor instead of struct
2196 hw_device_descriptor.
2197
2198Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2201 right bits and then re-align left hand bytes to correct byte
2202 lanes. Fix incorrect computation in do_store_left when loading
2203 bytes from second word.
2204
2205Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2206
2207 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2208 * interp.c (sim_open): Only create a device tree when HW is
2209 enabled.
2210
2211 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2212 * interp.c (signal_exception): Ditto.
2213
2214Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2215
2216 * gencode.c: Mark BEGEZALL as LIKELY.
2217
2218Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2219
2220 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2221 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2222
c906108c
SS		 2223Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2224
2225 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2226 modules. Recognize TX39 target with "mips*tx39" pattern.
2227 * configure: Rebuilt.
2228 * sim-main.h (*): Added many macros defining bits in
2229 TX39 control registers.
2230 (SignalInterrupt): Send actual PC instead of NULL.
2231 (SignalNMIReset): New exception type.
2232 * interp.c (board): New variable for future use to identify
2233 a particular board being simulated.
2234 (mips_option_handler,mips_options): Added "--board" option.
2235 (interrupt_event): Send actual PC.
2236 (sim_open): Make memory layout conditional on board setting.
2237 (signal_exception): Initial implementation of hardware interrupt
2238 handling. Accept another break instruction variant for simulator
2239 exit.
2240 (decode_coproc): Implement RFE instruction for TX39.
2241 (mips.igen): Decode RFE instruction as such.
2242 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2243 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2244 bbegin to implement memory map.
2245 * dv-tx3904cpu.c: New file.
2246 * dv-tx3904irc.c: New file.
2247
2248Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2249
2250 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2251
2252Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2253
2254 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2255 with calls to check_div_hilo.
2256
2257Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2258
2259 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2260 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2261 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2262 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2263 with calls to check_mult_hilo.
2264 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2265 with calls to check_div_hilo.
2266
2267Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2270 Document a replacement.
2271
2272Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2273
2274 * interp.c (sim_monitor): Make mon_printf work.
2275
2276Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2277
2278 * sim-main.h (INSN_NAME): New arg `cpu'.
2279
2280Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2281
72f4393d 2282 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2283
2284Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2285
2286 * configure: Regenerated to track ../common/aclocal.m4 changes.
2287 * config.in: Ditto.
2288
2289Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2290
2291 * acconfig.h: New file.
2292 * configure.in: Reverted change of Apr 24; use sinclude again.
2293
2294Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2295
2296 * configure: Regenerated to track ../common/aclocal.m4 changes.
2297 * config.in: Ditto.
2298
2299Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2300
2301 * configure.in: Don't call sinclude.
2302
2303Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2304
2305 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2306
2307Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * mips.igen (ERET): Implement.
2310
2311 * interp.c (decode_coproc): Return sign-extended EPC.
2312
2313 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2314
2315 * interp.c (signal_exception): Do not ignore Trap.
2316 (signal_exception): On TRAP, restart at exception address.
2317 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2318 (signal_exception): Update.
2319 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2320 so that TRAP instructions are caught.
2321
2322Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2323
2324 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2325 contains HI/LO access history.
2326 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2327 (HIACCESS, LOACCESS): Delete, replace with
2328 (HIHISTORY, LOHISTORY): New macros.
2329 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2330
c906108c
SS		 2331 * gencode.c (build_instruction): Do not generate checks for
2332 correct HI/LO register usage.
2333
2334 * interp.c (old_engine_run): Delete checks for correct HI/LO
2335 register usage.
2336
2337 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2338 check_mf_cycles): New functions.
2339 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2340 do_divu, domultx, do_mult, do_multu): Use.
2341
2342 * tx.igen ("madd", "maddu"): Use.
72f4393d 2343
c906108c
SS		 2344Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2345
2346 * mips.igen (DSRAV): Use function do_dsrav.
2347 (SRAV): Use new function do_srav.
2348
2349 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2350 (B): Sign extend 11 bit immediate.
2351 (EXT-B*): Shift 16 bit immediate left by 1.
2352 (ADDIU*): Don't sign extend immediate value.
2353
2354Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2355
2356 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2357
2358 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2359 functions.
2360
2361 * mips.igen (delayslot32, nullify_next_insn): New functions.
2362 (m16.igen): Always include.
2363 (do_*): Add more tracing.
2364
2365 * m16.igen (delayslot16): Add NIA argument, could be called by a
2366 32 bit MIPS16 instruction.
72f4393d 2367
c906108c
SS		 2368 * interp.c (ifetch16): Move function from here.
2369 * sim-main.c (ifetch16): To here.
72f4393d 2370
c906108c
SS		 2371 * sim-main.c (ifetch16, ifetch32): Update to match current
2372 implementations of LH, LW.
2373 (signal_exception): Don't print out incorrect hex value of illegal
2374 instruction.
2375
2376Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2379 instruction.
2380
2381 * m16.igen: Implement MIPS16 instructions.
72f4393d 2382
c906108c
SS		 2383 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2384 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2385 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2386 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2387 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2388 bodies of corresponding code from 32 bit insn to these. Also used
2389 by MIPS16 versions of functions.
72f4393d 2390
c906108c
SS		 2391 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2392 (IMEM16): Drop NR argument from macro.
2393
2394Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2395
2396 * Makefile.in (SIM_OBJS): Add sim-main.o.
2397
2398 * sim-main.h (address_translation, load_memory, store_memory,
2399 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2400 as INLINE_SIM_MAIN.
2401 (pr_addr, pr_uword64): Declare.
2402 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2403
c906108c
SS		 2404 * interp.c (address_translation, load_memory, store_memory,
2405 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2406 from here.
2407 * sim-main.c: To here. Fix compilation problems.
72f4393d 2408
c906108c
SS		 2409 * configure.in: Enable inlining.
2410 * configure: Re-config.
2411
2412Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2413
2414 * configure: Regenerated to track ../common/aclocal.m4 changes.
2415
2416Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2417
2418 * mips.igen: Include tx.igen.
2419 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2420 * tx.igen: New file, contains MADD and MADDU.
2421
2422 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2423 the hardwired constant `7'.
2424 (store_memory): Ditto.
2425 (LOADDRMASK): Move definition to sim-main.h.
2426
2427 mips.igen (MTC0): Enable for r3900.
2428 (ADDU): Add trace.
2429
2430 mips.igen (do_load_byte): Delete.
2431 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2432 do_store_right): New functions.
2433 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2434
2435 configure.in: Let the tx39 use igen again.
2436 configure: Update.
72f4393d 2437
c906108c
SS		 2438Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2439
2440 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2441 not an address sized quantity. Return zero for cache sizes.
2442
2443Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * mips.igen (r3900): r3900 does not support 64 bit integer
2446 operations.
2447
2448Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2449
2450 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2451 than igen one.
2452 * configure : Rebuild.
72f4393d 2453
c906108c
SS		 2454Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2455
2456 * configure: Regenerated to track ../common/aclocal.m4 changes.
2457
2458Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2459
2460 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2461
2462Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2463
2464 * configure: Regenerated to track ../common/aclocal.m4 changes.
2465 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2466
2467Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2468
2469 * configure: Regenerated to track ../common/aclocal.m4 changes.
2470
2471Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2472
2473 * interp.c (Max, Min): Comment out functions. Not yet used.
2474
2475Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2476
2477 * configure: Regenerated to track ../common/aclocal.m4 changes.
2478
2479Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2480
2481 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2482 configurable settings for stand-alone simulator.
72f4393d 2483
c906108c 2484 * configure.in: Added X11 search, just in case.
72f4393d 2485
c906108c
SS		 2486 * configure: Regenerated.
2487
2488Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * interp.c (sim_write, sim_read, load_memory, store_memory):
2491 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2492
2493Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * sim-main.h (GETFCC): Return an unsigned value.
2496
2497Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2500 (DADD): Result destination is RD not RT.
2501
2502Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2503
2504 * sim-main.h (HIACCESS, LOACCESS): Always define.
2505
2506 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2507
2508 * interp.c (sim_info): Delete.
2509
2510Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2511
2512 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2513 (mips_option_handler): New argument `cpu'.
2514 (sim_open): Update call to sim_add_option_table.
2515
2516Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2517
2518 * mips.igen (CxC1): Add tracing.
2519
2520Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2521
2522 * sim-main.h (Max, Min): Declare.
2523
2524 * interp.c (Max, Min): New functions.
2525
2526 * mips.igen (BC1): Add tracing.
72f4393d 2527
c906108c 2528Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2529
c906108c 2530 * interp.c Added memory map for stack in vr4100
72f4393d 2531
c906108c
SS		 2532Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2533
2534 * interp.c (load_memory): Add missing "break"'s.
2535
2536Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2537
2538 * interp.c (sim_store_register, sim_fetch_register): Pass in
2539 length parameter. Return -1.
2540
2541Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2542
2543 * interp.c: Added hardware init hook, fixed warnings.
2544
2545Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2546
2547 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2548
2549Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * interp.c (ifetch16): New function.
2552
2553 * sim-main.h (IMEM32): Rename IMEM.
2554 (IMEM16_IMMED): Define.
2555 (IMEM16): Define.
2556 (DELAY_SLOT): Update.
72f4393d 2557
c906108c 2558 * m16run.c (sim_engine_run): New file.
72f4393d 2559
c906108c
SS		 2560 * m16.igen: All instructions except LB.
2561 (LB): Call do_load_byte.
2562 * mips.igen (do_load_byte): New function.
2563 (LB): Call do_load_byte.
2564
2565 * mips.igen: Move spec for insn bit size and high bit from here.
2566 * Makefile.in (tmp-igen, tmp-m16): To here.
2567
2568 * m16.dc: New file, decode mips16 instructions.
2569
2570 * Makefile.in (SIM_NO_ALL): Define.
2571 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2572
2573Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2574
2575 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2576 point unit to 32 bit registers.
2577 * configure: Re-generate.
2578
2579Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * configure.in (sim_use_gen): Make IGEN the default simulator
2582 generator for generic 32 and 64 bit mips targets.
2583 * configure: Re-generate.
2584
2585Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2586
2587 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2588 bitsize.
2589
2590 * interp.c (sim_fetch_register, sim_store_register): Read/write
2591 FGR from correct location.
2592 (sim_open): Set size of FGR's according to
2593 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2594
c906108c
SS		 2595 * sim-main.h (FGR): Store floating point registers in a separate
2596 array.
2597
2598Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * configure: Regenerated to track ../common/aclocal.m4 changes.
2601
2602Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2605
2606 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2607
2608 * interp.c (pending_tick): New function. Deliver pending writes.
2609
2610 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2611 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2612 it can handle mixed sized quantites and single bits.
72f4393d 2613
c906108c
SS		 2614Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2615
2616 * interp.c (oengine.h): Do not include when building with IGEN.
2617 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2618 (sim_info): Ditto for PROCESSOR_64BIT.
2619 (sim_monitor): Replace ut_reg with unsigned_word.
2620 (*): Ditto for t_reg.
2621 (LOADDRMASK): Define.
2622 (sim_open): Remove defunct check that host FP is IEEE compliant,
2623 using software to emulate floating point.
2624 (value_fpr, ...): Always compile, was conditional on HASFPU.
2625
2626Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2627
2628 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2629 size.
2630
2631 * interp.c (SD, CPU): Define.
2632 (mips_option_handler): Set flags in each CPU.
2633 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2634 (sim_close): Do not clear STATE, deleted anyway.
2635 (sim_write, sim_read): Assume CPU zero's vm should be used for
2636 data transfers.
2637 (sim_create_inferior): Set the PC for all processors.
2638 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2639 argument.
2640 (mips16_entry): Pass correct nr of args to store_word, load_word.
2641 (ColdReset): Cold reset all cpu's.
2642 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2643 (sim_monitor, load_memory, store_memory, signal_exception): Use
2644 `CPU' instead of STATE_CPU.
2645
2646
2647 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2648 SD or CPU_.
72f4393d 2649
c906108c
SS		 2650 * sim-main.h (signal_exception): Add sim_cpu arg.
2651 (SignalException*): Pass both SD and CPU to signal_exception.
2652 * interp.c (signal_exception): Update.
72f4393d 2653
c906108c
SS		 2654 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2655 Ditto
2656 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2657 address_translation): Ditto
2658 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2659
c906108c
SS		 2660Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2661
2662 * configure: Regenerated to track ../common/aclocal.m4 changes.
2663
2664Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2665
2666 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2667
72f4393d 2668 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2669
2670 * sim-main.h (CPU_CIA): Delete.
2671 (SET_CIA, GET_CIA): Define
2672
2673Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2674
2675 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2676 regiser.
2677
2678 * configure.in (default_endian): Configure a big-endian simulator
2679 by default.
2680 * configure: Re-generate.
72f4393d 2681
c906108c
SS		 2682Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2683
2684 * configure: Regenerated to track ../common/aclocal.m4 changes.
2685
2686Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2687
2688 * interp.c (sim_monitor): Handle Densan monitor outbyte
2689 and inbyte functions.
2690
26911997-12-29 Felix Lee <flee@cygnus.com>
2692
2693 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2694
2695Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2696
2697 * Makefile.in (tmp-igen): Arrange for $zero to always be
2698 reset to zero after every instruction.
2699
2700Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701
2702 * configure: Regenerated to track ../common/aclocal.m4 changes.
2703 * config.in: Ditto.
2704
2705Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2706
2707 * mips.igen (MSUB): Fix to work like MADD.
2708 * gencode.c (MSUB): Similarly.
2709
2710Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2711
2712 * configure: Regenerated to track ../common/aclocal.m4 changes.
2713
2714Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715
2716 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2717
2718Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2719
2720 * sim-main.h (sim-fpu.h): Include.
2721
2722 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2723 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2724 using host independant sim_fpu module.
2725
2726Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2727
2728 * interp.c (signal_exception): Report internal errors with SIGABRT
2729 not SIGQUIT.
2730
2731 * sim-main.h (C0_CONFIG): New register.
2732 (signal.h): No longer include.
2733
2734 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2735
2736Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2737
2738 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2739
2740Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2741
2742 * mips.igen: Tag vr5000 instructions.
2743 (ANDI): Was missing mipsIV model, fix assembler syntax.
2744 (do_c_cond_fmt): New function.
2745 (C.cond.fmt): Handle mips I-III which do not support CC field
2746 separatly.
2747 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2748 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2749 in IV3.2 spec.
2750 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2751 vr5000 which saves LO in a GPR separatly.
72f4393d 2752
c906108c
SS		 2753 * configure.in (enable-sim-igen): For vr5000, select vr5000
2754 specific instructions.
2755 * configure: Re-generate.
72f4393d 2756
c906108c
SS		 2757Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2758
2759 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2760
2761 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2762 fmt_uninterpreted_64 bit cases to switch. Convert to
2763 fmt_formatted,
2764
2765 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2766
2767 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2768 as specified in IV3.2 spec.
2769 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2770
2771Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2772
2773 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2774 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2775 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2776 PENDING_FILL versions of instructions. Simplify.
2777 (X): New function.
2778 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2779 instructions.
2780 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2781 a signed value.
2782 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2783
c906108c
SS		 2784 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2785 global.
2786 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2787
2788Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789
2790 * gencode.c (build_mips16_operands): Replace IPC with cia.
2791
2792 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2793 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2794 IPC to `cia'.
2795 (UndefinedResult): Replace function with macro/function
2796 combination.
2797 (sim_engine_run): Don't save PC in IPC.
2798
2799 * sim-main.h (IPC): Delete.
2800
2801
2802 * interp.c (signal_exception, store_word, load_word,
2803 address_translation, load_memory, store_memory, cache_op,
2804 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2805 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2806 current instruction address - cia - argument.
2807 (sim_read, sim_write): Call address_translation directly.
2808 (sim_engine_run): Rename variable vaddr to cia.
2809 (signal_exception): Pass cia to sim_monitor
72f4393d 2810
c906108c
SS		 2811 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2812 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2813 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2814
2815 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2816 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2817 SIM_ASSERT.
72f4393d 2818
c906108c
SS		 2819 * interp.c (signal_exception): Pass restart address to
2820 sim_engine_restart.
2821
2822 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2823 idecode.o): Add dependency.
2824
2825 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2826 Delete definitions
2827 (DELAY_SLOT): Update NIA not PC with branch address.
2828 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2829
2830 * mips.igen: Use CIA not PC in branch calculations.
2831 (illegal): Call SignalException.
2832 (BEQ, ADDIU): Fix assembler.
2833
2834Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2835
2836 * m16.igen (JALX): Was missing.
2837
2838 * configure.in (enable-sim-igen): New configuration option.
2839 * configure: Re-generate.
72f4393d 2840
c906108c
SS		 2841 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2842
2843 * interp.c (load_memory, store_memory): Delete parameter RAW.
2844 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2845 bypassing {load,store}_memory.
2846
2847 * sim-main.h (ByteSwapMem): Delete definition.
2848
2849 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2850
2851 * interp.c (sim_do_command, sim_commands): Delete mips specific
2852 commands. Handled by module sim-options.
72f4393d 2853
c906108c
SS		 2854 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2855 (WITH_MODULO_MEMORY): Define.
2856
2857 * interp.c (sim_info): Delete code printing memory size.
2858
2859 * interp.c (mips_size): Nee sim_size, delete function.
2860 (power2): Delete.
2861 (monitor, monitor_base, monitor_size): Delete global variables.
2862 (sim_open, sim_close): Delete code creating monitor and other
2863 memory regions. Use sim-memopts module, via sim_do_commandf, to
2864 manage memory regions.
2865 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2866
c906108c
SS		 2867 * interp.c (address_translation): Delete all memory map code
2868 except line forcing 32 bit addresses.
2869
2870Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871
2872 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2873 trace options.
2874
2875 * interp.c (logfh, logfile): Delete globals.
2876 (sim_open, sim_close): Delete code opening & closing log file.
2877 (mips_option_handler): Delete -l and -n options.
2878 (OPTION mips_options): Ditto.
2879
2880 * interp.c (OPTION mips_options): Rename option trace to dinero.
2881 (mips_option_handler): Update.
2882
2883Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2884
2885 * interp.c (fetch_str): New function.
2886 (sim_monitor): Rewrite using sim_read & sim_write.
2887 (sim_open): Check magic number.
2888 (sim_open): Write monitor vectors into memory using sim_write.
2889 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2890 (sim_read, sim_write): Simplify - transfer data one byte at a
2891 time.
2892 (load_memory, store_memory): Clarify meaning of parameter RAW.
2893
2894 * sim-main.h (isHOST): Defete definition.
2895 (isTARGET): Mark as depreciated.
2896 (address_translation): Delete parameter HOST.
2897
2898 * interp.c (address_translation): Delete parameter HOST.
2899
2900Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2901
72f4393d 2902 * mips.igen:
c906108c
SS		 2903
2904 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2905 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2906
2907Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2908
2909 * mips.igen: Add model filter field to records.
2910
2911Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2912
2913 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2914
c906108c
SS		 2915 interp.c (sim_engine_run): Do not compile function sim_engine_run
2916 when WITH_IGEN == 1.
2917
2918 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2919 target architecture.
2920
2921 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2922 igen. Replace with configuration variables sim_igen_flags /
2923 sim_m16_flags.
2924
2925 * m16.igen: New file. Copy mips16 insns here.
2926 * mips.igen: From here.
2927
2928Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2929
2930 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2931 to top.
2932 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2933
2934Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2935
2936 * gencode.c (build_instruction): Follow sim_write's lead in using
2937 BigEndianMem instead of !ByteSwapMem.
2938
2939Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940
2941 * configure.in (sim_gen): Dependent on target, select type of
2942 generator. Always select old style generator.
2943
2944 configure: Re-generate.
2945
2946 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2947 targets.
2948 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2949 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2950 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2951 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2952 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2953
c906108c
SS		 2954Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2955
2956 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2957
2958 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2959 CURRENT_FLOATING_POINT instead.
2960
2961 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2962 (address_translation): Raise exception InstructionFetch when
2963 translation fails and isINSTRUCTION.
72f4393d 2964
c906108c
SS		 2965 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2966 sim_engine_run): Change type of of vaddr and paddr to
2967 address_word.
2968 (address_translation, prefetch, load_memory, store_memory,
2969 cache_op): Change type of vAddr and pAddr to address_word.
2970
2971 * gencode.c (build_instruction): Change type of vaddr and paddr to
2972 address_word.
2973
2974Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2975
2976 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2977 macro to obtain result of ALU op.
2978
2979Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2980
2981 * interp.c (sim_info): Call profile_print.
2982
2983Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2986
2987 * sim-main.h (WITH_PROFILE): Do not define, defined in
2988 common/sim-config.h. Use sim-profile module.
2989 (simPROFILE): Delete defintion.
2990
2991 * interp.c (PROFILE): Delete definition.
2992 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2993 (sim_close): Delete code writing profile histogram.
2994 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2995 Delete.
2996 (sim_engine_run): Delete code profiling the PC.
2997
2998Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2999
3000 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3001
3002 * interp.c (sim_monitor): Make register pointers of type
3003 unsigned_word*.
3004
3005 * sim-main.h: Make registers of type unsigned_word not
3006 signed_word.
3007
3008Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009
3010 * interp.c (sync_operation): Rename from SyncOperation, make
3011 global, add SD argument.
3012 (prefetch): Rename from Prefetch, make global, add SD argument.
3013 (decode_coproc): Make global.
3014
3015 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3016
3017 * gencode.c (build_instruction): Generate DecodeCoproc not
3018 decode_coproc calls.
3019
3020 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3021 (SizeFGR): Move to sim-main.h
3022 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3023 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3024 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3025 sim-main.h.
3026 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3027 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3028 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3029 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3030 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3031 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3032
c906108c
SS		 3033 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3034 exception.
3035 (sim-alu.h): Include.
3036 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3037 (sim_cia): Typedef to instruction_address.
72f4393d 3038
c906108c
SS		 3039Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * Makefile.in (interp.o): Rename generated file engine.c to
3042 oengine.c.
72f4393d 3043
c906108c 3044 * interp.c: Update.
72f4393d 3045
c906108c
SS		 3046Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3047
3048 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3049
c906108c
SS		 3050Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3051
3052 * gencode.c (build_instruction): For "FPSQRT", output correct
3053 number of arguments to Recip.
72f4393d 3054
c906108c
SS		 3055Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3056
3057 * Makefile.in (interp.o): Depends on sim-main.h
3058
3059 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3060
3061 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3062 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3063 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3064 STATE, DSSTATE): Define
3065 (GPR, FGRIDX, ..): Define.
3066
3067 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3068 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3069 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3070
c906108c 3071 * interp.c: Update names to match defines from sim-main.h
72f4393d 3072
c906108c
SS		 3073Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * interp.c (sim_monitor): Add SD argument.
3076 (sim_warning): Delete. Replace calls with calls to
3077 sim_io_eprintf.
3078 (sim_error): Delete. Replace calls with sim_io_error.
3079 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3080 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3081 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3082 argument.
3083 (mips_size): Rename from sim_size. Add SD argument.
3084
3085 * interp.c (simulator): Delete global variable.
3086 (callback): Delete global variable.
3087 (mips_option_handler, sim_open, sim_write, sim_read,
3088 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3089 sim_size,sim_monitor): Use sim_io_* not callback->*.
3090 (sim_open): ZALLOC simulator struct.
3091 (PROFILE): Do not define.
3092
3093Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3096 support.h with corresponding code.
3097
3098 * sim-main.h (word64, uword64), support.h: Move definition to
3099 sim-main.h.
3100 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3101
3102 * support.h: Delete
3103 * Makefile.in: Update dependencies
3104 * interp.c: Do not include.
72f4393d 3105
c906108c
SS		 3106Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (address_translation, load_memory, store_memory,
3109 cache_op): Rename to from AddressTranslation et.al., make global,
3110 add SD argument
72f4393d 3111
c906108c
SS		 3112 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3113 CacheOp): Define.
72f4393d 3114
c906108c
SS		 3115 * interp.c (SignalException): Rename to signal_exception, make
3116 global.
3117
3118 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3119
c906108c
SS		 3120 * sim-main.h (SignalException, SignalExceptionInterrupt,
3121 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3122 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3123 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3124 Define.
72f4393d 3125
c906108c 3126 * interp.c, support.h: Use.
72f4393d 3127
c906108c
SS		 3128Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3131 to value_fpr / store_fpr. Add SD argument.
3132 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3133 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3134
3135 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3136
c906108c
SS		 3137Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * interp.c (sim_engine_run): Check consistency between configure
3140 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3141 and HASFPU.
3142
3143 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3144 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3145 (mips_endian): Configure WITH_TARGET_ENDIAN.
3146 * configure: Update.
3147
3148Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3149
3150 * configure: Regenerated to track ../common/aclocal.m4 changes.
3151
3152Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3153
3154 * configure: Regenerated.
3155
3156Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3157
3158 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3159
3160Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3161
3162 * gencode.c (print_igen_insn_models): Assume certain architectures
3163 include all mips* instructions.
3164 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3165 instruction.
3166
3167 * Makefile.in (tmp.igen): Add target. Generate igen input from
3168 gencode file.
3169
3170 * gencode.c (FEATURE_IGEN): Define.
3171 (main): Add --igen option. Generate output in igen format.
3172 (process_instructions): Format output according to igen option.
3173 (print_igen_insn_format): New function.
3174 (print_igen_insn_models): New function.
3175 (process_instructions): Only issue warnings and ignore
3176 instructions when no FEATURE_IGEN.
3177
3178Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3179
3180 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3181 MIPS targets.
3182
3183Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * configure: Regenerated to track ../common/aclocal.m4 changes.
3186
3187Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3188
3189 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3190 SIM_RESERVED_BITS): Delete, moved to common.
3191 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3192
c906108c
SS		 3193Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3194
3195 * configure.in: Configure non-strict memory alignment.
3196 * configure: Regenerated to track ../common/aclocal.m4 changes.
3197
3198Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3199
3200 * configure: Regenerated to track ../common/aclocal.m4 changes.
3201
3202Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3203
3204 * gencode.c (SDBBP,DERET): Added (3900) insns.
3205 (RFE): Turn on for 3900.
3206 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3207 (dsstate): Made global.
3208 (SUBTARGET_R3900): Added.
3209 (CANCELDELAYSLOT): New.
3210 (SignalException): Ignore SystemCall rather than ignore and
3211 terminate. Add DebugBreakPoint handling.
3212 (decode_coproc): New insns RFE, DERET; and new registers Debug
3213 and DEPC protected by SUBTARGET_R3900.
3214 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3215 bits explicitly.
3216 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3217 * configure: Update.
c906108c
SS		 3218
3219Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3220
3221 * gencode.c: Add r3900 (tx39).
72f4393d 3222
c906108c
SS		 3223
3224Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3225
3226 * gencode.c (build_instruction): Don't need to subtract 4 for
3227 JALR, just 2.
3228
3229Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3230
3231 * interp.c: Correct some HASFPU problems.
3232
3233Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3234
3235 * configure: Regenerated to track ../common/aclocal.m4 changes.
3236
3237Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3238
3239 * interp.c (mips_options): Fix samples option short form, should
3240 be `x'.
3241
3242Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3243
3244 * interp.c (sim_info): Enable info code. Was just returning.
3245
3246Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3247
3248 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3249 MFC0.
3250
3251Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3252
3253 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3254 constants.
3255 (build_instruction): Ditto for LL.
3256
3257Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3258
3259 * configure: Regenerated to track ../common/aclocal.m4 changes.
3260
3261Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3262
3263 * configure: Regenerated to track ../common/aclocal.m4 changes.
3264 * config.in: Ditto.
3265
3266Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3267
3268 * interp.c (sim_open): Add call to sim_analyze_program, update
3269 call to sim_config.
3270
3271Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * interp.c (sim_kill): Delete.
3274 (sim_create_inferior): Add ABFD argument. Set PC from same.
3275 (sim_load): Move code initializing trap handlers from here.
3276 (sim_open): To here.
3277 (sim_load): Delete, use sim-hload.c.
3278
3279 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3280
3281Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3282
3283 * configure: Regenerated to track ../common/aclocal.m4 changes.
3284 * config.in: Ditto.
3285
3286Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3287
3288 * interp.c (sim_open): Add ABFD argument.
3289 (sim_load): Move call to sim_config from here.
3290 (sim_open): To here. Check return status.
3291
3292Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3293
c906108c
SS		 3294 * gencode.c (build_instruction): Two arg MADD should
3295 not assign result to $0.
72f4393d 3296
c906108c
SS		 3297Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3298
3299 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3300 * sim/mips/configure.in: Regenerate.
3301
3302Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3303
3304 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3305 signed8, unsigned8 et.al. types.
3306
3307 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3308 hosts when selecting subreg.
3309
3310Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3311
3312 * interp.c (sim_engine_run): Reset the ZERO register to zero
3313 regardless of FEATURE_WARN_ZERO.
3314 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3315
3316Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3317
3318 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3319 (SignalException): For BreakPoints ignore any mode bits and just
3320 save the PC.
3321 (SignalException): Always set the CAUSE register.
3322
3323Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3324
3325 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3326 exception has been taken.
3327
3328 * interp.c: Implement the ERET and mt/f sr instructions.
3329
3330Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3331
3332 * interp.c (SignalException): Don't bother restarting an
3333 interrupt.
3334
3335Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3336
3337 * interp.c (SignalException): Really take an interrupt.
3338 (interrupt_event): Only deliver interrupts when enabled.
3339
3340Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3341
3342 * interp.c (sim_info): Only print info when verbose.
3343 (sim_info) Use sim_io_printf for output.
72f4393d 3344
c906108c
SS		 3345Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3346
3347 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3348 mips architectures.
3349
3350Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3351
3352 * interp.c (sim_do_command): Check for common commands if a
3353 simulator specific command fails.
3354
3355Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3356
3357 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3358 and simBE when DEBUG is defined.
3359
3360Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3361
3362 * interp.c (interrupt_event): New function. Pass exception event
3363 onto exception handler.
3364
3365 * configure.in: Check for stdlib.h.
3366 * configure: Regenerate.
3367
3368 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3369 variable declaration.
3370 (build_instruction): Initialize memval1.
3371 (build_instruction): Add UNUSED attribute to byte, bigend,
3372 reverse.
3373 (build_operands): Ditto.
3374
3375 * interp.c: Fix GCC warnings.
3376 (sim_get_quit_code): Delete.
3377
3378 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3379 * Makefile.in: Ditto.
3380 * configure: Re-generate.
72f4393d 3381
c906108c
SS		 3382 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3383
3384Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3385
3386 * interp.c (mips_option_handler): New function parse argumes using
3387 sim-options.
3388 (myname): Replace with STATE_MY_NAME.
3389 (sim_open): Delete check for host endianness - performed by
3390 sim_config.
3391 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3392 (sim_open): Move much of the initialization from here.
3393 (sim_load): To here. After the image has been loaded and
3394 endianness set.
3395 (sim_open): Move ColdReset from here.
3396 (sim_create_inferior): To here.
3397 (sim_open): Make FP check less dependant on host endianness.
3398
3399 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3400 run.
3401 * interp.c (sim_set_callbacks): Delete.
3402
3403 * interp.c (membank, membank_base, membank_size): Replace with
3404 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3405 (sim_open): Remove call to callback->init. gdb/run do this.
3406
3407 * interp.c: Update
3408
3409 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3410
3411 * interp.c (big_endian_p): Delete, replaced by
3412 current_target_byte_order.
3413
3414Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3415
3416 * interp.c (host_read_long, host_read_word, host_swap_word,
3417 host_swap_long): Delete. Using common sim-endian.
3418 (sim_fetch_register, sim_store_register): Use H2T.
3419 (pipeline_ticks): Delete. Handled by sim-events.
3420 (sim_info): Update.
3421 (sim_engine_run): Update.
3422
3423Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3424
3425 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3426 reason from here.
3427 (SignalException): To here. Signal using sim_engine_halt.
3428 (sim_stop_reason): Delete, moved to common.
72f4393d 3429
c906108c
SS		 3430Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3431
3432 * interp.c (sim_open): Add callback argument.
3433 (sim_set_callbacks): Delete SIM_DESC argument.
3434 (sim_size): Ditto.
3435
3436Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3437
3438 * Makefile.in (SIM_OBJS): Add common modules.
3439
3440 * interp.c (sim_set_callbacks): Also set SD callback.
3441 (set_endianness, xfer_*, swap_*): Delete.
3442 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3443 Change to functions using sim-endian macros.
3444 (control_c, sim_stop): Delete, use common version.
3445 (simulate): Convert into.
3446 (sim_engine_run): This function.
3447 (sim_resume): Delete.
72f4393d 3448
c906108c
SS		 3449 * interp.c (simulation): New variable - the simulator object.
3450 (sim_kind): Delete global - merged into simulation.
3451 (sim_load): Cleanup. Move PC assignment from here.
3452 (sim_create_inferior): To here.
3453
3454 * sim-main.h: New file.
3455 * interp.c (sim-main.h): Include.
72f4393d 3456
c906108c
SS		 3457Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3458
3459 * configure: Regenerated to track ../common/aclocal.m4 changes.
3460
3461Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3462
3463 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3464
3465Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3466
72f4393d
L		 3467 * gencode.c (build_instruction): DIV instructions: check
3468 for division by zero and integer overflow before using
c906108c
SS		 3469 host's division operation.
3470
3471Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3472
3473 * Makefile.in (SIM_OBJS): Add sim-load.o.
3474 * interp.c: #include bfd.h.
3475 (target_byte_order): Delete.
3476 (sim_kind, myname, big_endian_p): New static locals.
3477 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3478 after argument parsing. Recognize -E arg, set endianness accordingly.
3479 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3480 load file into simulator. Set PC from bfd.
3481 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3482 (set_endianness): Use big_endian_p instead of target_byte_order.
3483
3484Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3485
3486 * interp.c (sim_size): Delete prototype - conflicts with
3487 definition in remote-sim.h. Correct definition.
3488
3489Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3490
3491 * configure: Regenerated to track ../common/aclocal.m4 changes.
3492 * config.in: Ditto.
3493
3494Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3495
3496 * interp.c (sim_open): New arg `kind'.
3497
3498 * configure: Regenerated to track ../common/aclocal.m4 changes.
3499
3500Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3501
3502 * configure: Regenerated to track ../common/aclocal.m4 changes.
3503
3504Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3505
3506 * interp.c (sim_open): Set optind to 0 before calling getopt.
3507
3508Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3509
3510 * configure: Regenerated to track ../common/aclocal.m4 changes.
3511
3512Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3513
3514 * interp.c : Replace uses of pr_addr with pr_uword64
3515 where the bit length is always 64 independent of SIM_ADDR.
3516 (pr_uword64) : added.
3517
3518Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3519
3520 * configure: Re-generate.
3521
3522Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3523
3524 * configure: Regenerate to track ../common/aclocal.m4 changes.
3525
3526Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3527
3528 * interp.c (sim_open): New SIM_DESC result. Argument is now
3529 in argv form.
3530 (other sim_*): New SIM_DESC argument.
3531
3532Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3533
3534 * interp.c: Fix printing of addresses for non-64-bit targets.
3535 (pr_addr): Add function to print address based on size.
3536
3537Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3538
3539 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3540
3541Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3542
3543 * gencode.c (build_mips16_operands): Correct computation of base
3544 address for extended PC relative instruction.
3545
3546Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3547
3548 * interp.c (mips16_entry): Add support for floating point cases.
3549 (SignalException): Pass floating point cases to mips16_entry.
3550 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3551 registers.
3552 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3553 or fmt_word.
3554 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3555 and then set the state to fmt_uninterpreted.
3556 (COP_SW): Temporarily set the state to fmt_word while calling
3557 ValueFPR.
3558
3559Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3560
3561 * gencode.c (build_instruction): The high order may be set in the
3562 comparison flags at any ISA level, not just ISA 4.
3563
3564Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3565
3566 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3567 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3568 * configure.in: sinclude ../common/aclocal.m4.
3569 * configure: Regenerated.
3570
3571Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3572
3573 * configure: Rebuild after change to aclocal.m4.
3574
3575Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3576
3577 * configure configure.in Makefile.in: Update to new configure
3578 scheme which is more compatible with WinGDB builds.
3579 * configure.in: Improve comment on how to run autoconf.
3580 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3581 * Makefile.in: Use autoconf substitution to install common
3582 makefile fragment.
3583
3584Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3585
3586 * gencode.c (build_instruction): Use BigEndianCPU instead of
3587 ByteSwapMem.
3588
3589Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3590
3591 * interp.c (sim_monitor): Make output to stdout visible in
3592 wingdb's I/O log window.
3593
3594Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3595
3596 * support.h: Undo previous change to SIGTRAP
3597 and SIGQUIT values.
3598
3599Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3600
3601 * interp.c (store_word, load_word): New static functions.
3602 (mips16_entry): New static function.
3603 (SignalException): Look for mips16 entry and exit instructions.
3604 (simulate): Use the correct index when setting fpr_state after
3605 doing a pending move.
3606
3607Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3608
3609 * interp.c: Fix byte-swapping code throughout to work on
3610 both little- and big-endian hosts.
3611
3612Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3613
3614 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3615 with gdb/config/i386/xm-windows.h.
3616
3617Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3618
3619 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3620 that messes up arithmetic shifts.
3621
3622Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3623
3624 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3625 SIGTRAP and SIGQUIT for _WIN32.
3626
3627Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3628
3629 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3630 force a 64 bit multiplication.
3631 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3632 destination register is 0, since that is the default mips16 nop
3633 instruction.
3634
3635Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3636
3637 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3638 (build_endian_shift): Don't check proc64.
3639 (build_instruction): Always set memval to uword64. Cast op2 to
3640 uword64 when shifting it left in memory instructions. Always use
3641 the same code for stores--don't special case proc64.
3642
3643 * gencode.c (build_mips16_operands): Fix base PC value for PC
3644 relative operands.
3645 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3646 jal instruction.
3647 * interp.c (simJALDELAYSLOT): Define.
3648 (JALDELAYSLOT): Define.
3649 (INDELAYSLOT, INJALDELAYSLOT): Define.
3650 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3651
3652Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3653
3654 * interp.c (sim_open): add flush_cache as a PMON routine
3655 (sim_monitor): handle flush_cache by ignoring it
3656
3657Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3658
3659 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3660 BigEndianMem.
3661 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3662 (BigEndianMem): Rename to ByteSwapMem and change sense.
3663 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3664 BigEndianMem references to !ByteSwapMem.
3665 (set_endianness): New function, with prototype.
3666 (sim_open): Call set_endianness.
3667 (sim_info): Use simBE instead of BigEndianMem.
3668 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3669 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3670 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3671 ifdefs, keeping the prototype declaration.
3672 (swap_word): Rewrite correctly.
3673 (ColdReset): Delete references to CONFIG. Delete endianness related
3674 code; moved to set_endianness.
72f4393d 3675
c906108c
SS		 3676Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3677
3678 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3679 * interp.c (CHECKHILO): Define away.
3680 (simSIGINT): New macro.
3681 (membank_size): Increase from 1MB to 2MB.
3682 (control_c): New function.
3683 (sim_resume): Rename parameter signal to signal_number. Add local
3684 variable prev. Call signal before and after simulate.
3685 (sim_stop_reason): Add simSIGINT support.
3686 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3687 functions always.
3688 (sim_warning): Delete call to SignalException. Do call printf_filtered
3689 if logfh is NULL.
3690 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3691 a call to sim_warning.
3692
3693Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3694
3695 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3696 16 bit instructions.
3697
3698Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3699
3700 Add support for mips16 (16 bit MIPS implementation):
3701 * gencode.c (inst_type): Add mips16 instruction encoding types.
3702 (GETDATASIZEINSN): Define.
3703 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3704 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3705 mtlo.
3706 (MIPS16_DECODE): New table, for mips16 instructions.
3707 (bitmap_val): New static function.
3708 (struct mips16_op): Define.
3709 (mips16_op_table): New table, for mips16 operands.
3710 (build_mips16_operands): New static function.
3711 (process_instructions): If PC is odd, decode a mips16
3712 instruction. Break out instruction handling into new
3713 build_instruction function.
3714 (build_instruction): New static function, broken out of
3715 process_instructions. Check modifiers rather than flags for SHIFT
3716 bit count and m[ft]{hi,lo} direction.
3717 (usage): Pass program name to fprintf.
3718 (main): Remove unused variable this_option_optind. Change
3719 ``*loptarg++'' to ``loptarg++''.
3720 (my_strtoul): Parenthesize && within ||.
3721 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3722 (simulate): If PC is odd, fetch a 16 bit instruction, and
3723 increment PC by 2 rather than 4.
3724 * configure.in: Add case for mips16*-*-*.
3725 * configure: Rebuild.
3726
3727Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3728
3729 * interp.c: Allow -t to enable tracing in standalone simulator.
3730 Fix garbage output in trace file and error messages.
3731
3732Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3733
3734 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3735 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3736 * configure.in: Simplify using macros in ../common/aclocal.m4.
3737 * configure: Regenerated.
3738 * tconfig.in: New file.
3739
3740Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3741
3742 * interp.c: Fix bugs in 64-bit port.
3743 Use ansi function declarations for msvc compiler.
3744 Initialize and test file pointer in trace code.
3745 Prevent duplicate definition of LAST_EMED_REGNUM.
3746
3747Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3748
3749 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3750
3751Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3752
3753 * interp.c (SignalException): Check for explicit terminating
3754 breakpoint value.
3755 * gencode.c: Pass instruction value through SignalException()
3756 calls for Trap, Breakpoint and Syscall.
3757
3758Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3759
3760 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3761 only used on those hosts that provide it.
3762 * configure.in: Add sqrt() to list of functions to be checked for.
3763 * config.in: Re-generated.
3764 * configure: Re-generated.
3765
3766Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3767
3768 * gencode.c (process_instructions): Call build_endian_shift when
3769 expanding STORE RIGHT, to fix swr.
3770 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3771 clear the high bits.
3772 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3773 Fix float to int conversions to produce signed values.
3774
3775Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3776
3777 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3778 (process_instructions): Correct handling of nor instruction.
3779 Correct shift count for 32 bit shift instructions. Correct sign
3780 extension for arithmetic shifts to not shift the number of bits in
3781 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3782 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3783 Fix madd.
3784 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3785 It's OK to have a mult follow a mult. What's not OK is to have a
3786 mult follow an mfhi.
3787 (Convert): Comment out incorrect rounding code.
3788
3789Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3790
3791 * interp.c (sim_monitor): Improved monitor printf
3792 simulation. Tidied up simulator warnings, and added "--log" option
3793 for directing warning message output.
3794 * gencode.c: Use sim_warning() rather than WARNING macro.
3795
3796Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3797
3798 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3799 getopt1.o, rather than on gencode.c. Link objects together.
3800 Don't link against -liberty.
3801 (gencode.o, getopt.o, getopt1.o): New targets.
3802 * gencode.c: Include <ctype.h> and "ansidecl.h".
3803 (AND): Undefine after including "ansidecl.h".
3804 (ULONG_MAX): Define if not defined.
3805 (OP_*): Don't define macros; now defined in opcode/mips.h.
3806 (main): Call my_strtoul rather than strtoul.
3807 (my_strtoul): New static function.
3808
3809Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3810
3811 * gencode.c (process_instructions): Generate word64 and uword64
3812 instead of `long long' and `unsigned long long' data types.
3813 * interp.c: #include sysdep.h to get signals, and define default
3814 for SIGBUS.
3815 * (Convert): Work around for Visual-C++ compiler bug with type
3816 conversion.
3817 * support.h: Make things compile under Visual-C++ by using
3818 __int64 instead of `long long'. Change many refs to long long
3819 into word64/uword64 typedefs.
3820
3821Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3822
72f4393d
L		 3823 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3824 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3825 (docdir): Removed.
3826 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3827 (AC_PROG_INSTALL): Added.
c906108c 3828 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3829 * configure: Rebuilt.
3830
c906108c
SS		 3831Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3832
3833 * configure.in: Define @SIMCONF@ depending on mips target.
3834 * configure: Rebuild.
3835 * Makefile.in (run): Add @SIMCONF@ to control simulator
3836 construction.
3837 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3838 * interp.c: Remove some debugging, provide more detailed error
3839 messages, update memory accesses to use LOADDRMASK.
72f4393d 3840
c906108c
SS		 3841Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3842
3843 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3844 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3845 stamp-h.
3846 * configure: Rebuild.
3847 * config.in: New file, generated by autoheader.
3848 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3849 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3850 HAVE_ANINT and HAVE_AINT, as appropriate.
3851 * Makefile.in (run): Use @LIBS@ rather than -lm.
3852 (interp.o): Depend upon config.h.
3853 (Makefile): Just rebuild Makefile.
3854 (clean): Remove stamp-h.
3855 (mostlyclean): Make the same as clean, not as distclean.
3856 (config.h, stamp-h): New targets.
3857
3858Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3859
3860 * interp.c (ColdReset): Fix boolean test. Make all simulator
3861 globals static.
3862
3863Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3864
3865 * interp.c (xfer_direct_word, xfer_direct_long,
3866 swap_direct_word, swap_direct_long, xfer_big_word,
3867 xfer_big_long, xfer_little_word, xfer_little_long,
3868 swap_word,swap_long): Added.
3869 * interp.c (ColdReset): Provide function indirection to
3870 host<->simulated_target transfer routines.
3871 * interp.c (sim_store_register, sim_fetch_register): Updated to
3872 make use of indirected transfer routines.
3873
3874Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3875
3876 * gencode.c (process_instructions): Ensure FP ABS instruction
3877 recognised.
3878 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3879 system call support.
3880
3881Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3882
3883 * interp.c (sim_do_command): Complain if callback structure not
3884 initialised.
3885
3886Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3887
3888 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3889 support for Sun hosts.
3890 * Makefile.in (gencode): Ensure the host compiler and libraries
3891 used for cross-hosted build.
3892
3893Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3894
3895 * interp.c, gencode.c: Some more (TODO) tidying.
3896
3897Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3898
3899 * gencode.c, interp.c: Replaced explicit long long references with
3900 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3901 * support.h (SET64LO, SET64HI): Macros added.
3902
3903Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3904
3905 * configure: Regenerate with autoconf 2.7.
3906
3907Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3908
3909 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3910 * support.h: Remove superfluous "1" from #if.
3911 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3912
3913Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3914
3915 * interp.c (StoreFPR): Control UndefinedResult() call on
3916 WARN_RESULT manifest.
3917
3918Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3919
3920 * gencode.c: Tidied instruction decoding, and added FP instruction
3921 support.
3922
3923 * interp.c: Added dineroIII, and BSD profiling support. Also
3924 run-time FP handling.
3925
3926Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3927
3928 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3929 gencode.c, interp.c, support.h: created.
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