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readelf: don't clear section_headers in process_file_header
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
a55b92be
MF		 12021-06-08 Mike Frysinger <vapier@gentoo.org>
2
3 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
4 with $(IGEN).
5
8ea881d9
MF		 62021-05-29 Mike Frysinger <vapier@gentoo.org>
7
8 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
9
b312488f
FS		 102021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
11
168671c1
FS		 12 * interp.c (sim_open): Add shadow mappings from 32-bit
13 address space to 64-bit sign-extended address space.
14
152021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
16
b312488f
FS		 17 * interp.c (sim_create_inferior): Only truncate sign extension
18 bits for 32-bit target models.
19
f4fdd845
MF		 202021-05-17 Mike Frysinger <vapier@gentoo.org>
21
22 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
23
8ea7241c
MF		 242021-05-17 Mike Frysinger <vapier@gentoo.org>
25
26 * interp.c (sim_open): Switch to sim_state_alloc_extra.
27 * micromips.igen: Change SD to mips_sim_state.
28 * micromipsrun.c (sim_engine_run): Likewise.
29 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
30 (watch_options_install): Delete.
31 (struct swatch): Delete.
32 (struct sim_state): Delete.
33 (struct mips_sim_state): New struct.
34 (MIPS_SIM_STATE): Define.
35
6df01ab8
MF		 362021-05-16 Mike Frysinger <vapier@gentoo.org>
37
38 * interp.c: Replace config.h include with defs.h.
39 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
40 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
41 Include defs.h.
42
79633c12
MF		 432021-05-16 Mike Frysinger <vapier@gentoo.org>
44
45 * config.in, configure: Regenerate.
46
df68e12b
MF		 472021-05-14 Mike Frysinger <vapier@gentoo.org>
48
49 * interp.c: Update include path.
50
77c0fdb7
MF		 512021-05-04 Mike Frysinger <vapier@gentoo.org>
52
53 * dv-tx3904sio.c: Include stdlib.h.
54
9b1af85c
MF		 552021-05-04 Mike Frysinger <vapier@gentoo.org>
56
57 * configure.ac (hw_extra_devices): Inline contents into
58 SIM_AC_OPTION_HARDWARE and delete.
59 * configure: Regenerate.
60
d97ba9c6
MF		 612021-05-04 Mike Frysinger <vapier@gentoo.org>
62
63 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
64 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
65 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
66 * configure: Regenerate.
67
4df817de
MF		 682021-05-04 Mike Frysinger <vapier@gentoo.org>
69
70 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
71
aa0fca16
MF		 722021-05-04 Mike Frysinger <vapier@gentoo.org>
73
74 * configure: Regenerate.
75
adbaa7b8
MF		 762021-05-01 Mike Frysinger <vapier@gentoo.org>
77
78 * cp1.c (store_fcr): Mark static.
79
fe348617
MF		 802021-05-01 Mike Frysinger <vapier@gentoo.org>
81
82 * config.in, configure: Regenerate.
83
9d903352
MF		 842021-04-23 Mike Frysinger <vapier@gentoo.org>
85
86 * configure.ac (hw_enabled): Delete.
87 (SIM_AC_OPTION_HARDWARE): Delete first two args.
88 * configure: Regenerate.
89
19f6a43c
TT		 902021-04-22 Tom Tromey <tom@tromey.com>
91
92 * configure, config.in: Rebuild.
93
e7d8f1da
TT		 942021-04-22 Tom Tromey <tom@tromey.com>
95
96 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
97 Remove.
98 (SIM_EXTRA_DEPS): New variable.
99
efd82ac7
TT		 1002021-04-22 Tom Tromey <tom@tromey.com>
101
102 * configure: Rebuild.
103
2662c237
MF		 1042021-04-21 Mike Frysinger <vapier@gentoo.org>
105
106 * aclocal.m4: Regenerate.
107
1f195bc3
SM		 1082021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
109
110 * configure: Regenerate.
111
37e9f182
MF		 1122021-04-18 Mike Frysinger <vapier@gentoo.org>
113
114 * configure: Regenerate.
115
d5a71b11
MF		 1162021-04-12 Mike Frysinger <vapier@gentoo.org>
117
118 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
119
2b8d134b
SM		 1202021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
121
122 * Makefile.in: Set ASAN_OPTIONS when running igen.
123
5c6f091a
FS		 1242021-04-04 Steve Ellcey <sellcey@mips.com>
125 Faraz Shahbazker <fshahbazker@wavecomp.com>
126
127 * interp.c (sim_monitor): Add switch entries for unlink (13),
128 lseek (14), and stat (15).
129
b6b1c790
MF		 1302021-04-02 Mike Frysinger <vapier@gentoo.org>
131
132 * Makefile.in (../igen/igen): Delete rule.
133 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
134
c2783492
MF		 1352021-04-02 Mike Frysinger <vapier@gentoo.org>
136
137 * aclocal.m4, configure: Regenerate.
138
ebe9564b
MF		 1392021-02-28 Mike Frysinger <vapier@gentoo.org>
140
141 * configure: Regenerate.
142
f8069d55
MF		 1432021-02-27 Mike Frysinger <vapier@gentoo.org>
144
145 * Makefile.in (SIM_EXTRA_ALL): Delete.
146 (all): New target.
147
760b3e8b
MF		 1482021-02-21 Mike Frysinger <vapier@gentoo.org>
149
150 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
151 * aclocal.m4, configure: Regenerate.
152
136da8cd
MF		 1532021-02-13 Mike Frysinger <vapier@gentoo.org>
154
155 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
156 * aclocal.m4, configure: Regenerate.
157
4c0d76b9
MF		 1582021-02-06 Mike Frysinger <vapier@gentoo.org>
159
160 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
161
aa09469f
MF		 1622021-02-06 Mike Frysinger <vapier@gentoo.org>
163
164 * configure: Regenerate.
165
d4e3adda
MF		 1662021-01-30 Mike Frysinger <vapier@gentoo.org>
167
168 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
169
68ed2854
MF		 1702021-01-11 Mike Frysinger <vapier@gentoo.org>
171
172 * config.in, configure: Regenerate.
173 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
174 and strings.h include.
175
50df264d
MF		 1762021-01-09 Mike Frysinger <vapier@gentoo.org>
177
178 * configure: Regenerate.
179
bf470982
MF		 1802021-01-09 Mike Frysinger <vapier@gentoo.org>
181
182 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
183 * configure: Regenerate.
184
46f900c0
MF		 1852021-01-08 Mike Frysinger <vapier@gentoo.org>
186
187 * configure: Regenerate.
188
dfb856ba
MF		 1892021-01-04 Mike Frysinger <vapier@gentoo.org>
190
191 * configure: Regenerate.
192
382bc56b
PK		 1932020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
194
195 * sim-main.c: Include <stdlib.h>.
196
ad9675dd
PK		 1972020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
198
199 * cp1.c: Include <stdlib.h>.
200
f693213d
SM		 2012020-07-29 Simon Marchi <simon.marchi@efficios.com>
202
203 * configure: Re-generate.
204
5c887dd5
JB		 2052017-09-06 John Baldwin <jhb@FreeBSD.org>
206
207 * configure: Regenerate.
208
91588b3a
MF		 2092016-11-11 Mike Frysinger <vapier@gentoo.org>
210
6cb2202b 211 PR sim/20808
91588b3a
MF		 212 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
213 and SD to sd.
214
e04659e8
MF		 2152016-11-11 Mike Frysinger <vapier@gentoo.org>
216
6cb2202b 217 PR sim/20809
e04659e8
MF		 218 * mips.igen (check_u64): Enable for `r3900'.
219
1554f758
MF		 2202016-02-05 Mike Frysinger <vapier@gentoo.org>
221
222 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
223 STATE_PROG_BFD (sd).
224 * configure: Regenerate.
225
3d304f48
AB		 2262016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
227 Maciej W. Rozycki <macro@imgtec.com>
228
229 PR sim/19441
230 * micromips.igen (delayslot_micromips): Enable for `micromips32',
231 `micromips64' and `micromipsdsp' only.
232 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
233 (do_micromips_jalr, do_micromips_jal): Likewise.
234 (compute_movep_src_reg): Likewise.
235 (compute_andi16_imm): Likewise.
236 (convert_fmt_micromips): Likewise.
237 (convert_fmt_micromips_cvt_d): Likewise.
238 (convert_fmt_micromips_cvt_s): Likewise.
239 (FMT_MICROMIPS): Likewise.
240 (FMT_MICROMIPS_CVT_D): Likewise.
241 (FMT_MICROMIPS_CVT_S): Likewise.
242
b36d953b
MF		 2432016-01-12 Mike Frysinger <vapier@gentoo.org>
244
245 * interp.c: Include elf-bfd.h.
246 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
247 ELFCLASS32.
248
ce39bd38
MF		 2492016-01-10 Mike Frysinger <vapier@gentoo.org>
250
251 * config.in, configure: Regenerate.
252
99d8e879
MF		 2532016-01-10 Mike Frysinger <vapier@gentoo.org>
254
255 * configure: Regenerate.
256
35656e95
MF		 2572016-01-10 Mike Frysinger <vapier@gentoo.org>
258
259 * configure: Regenerate.
260
16f7876d
MF		 2612016-01-10 Mike Frysinger <vapier@gentoo.org>
262
263 * configure: Regenerate.
264
e19418e0
MF		 2652016-01-10 Mike Frysinger <vapier@gentoo.org>
266
267 * configure: Regenerate.
268
6d90347b
MF		 2692016-01-10 Mike Frysinger <vapier@gentoo.org>
270
271 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
272 * configure: Regenerate.
273
347fe5bb
MF		 2742016-01-10 Mike Frysinger <vapier@gentoo.org>
275
276 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
277 * configure: Regenerate.
278
22be3fbe
MF		 2792016-01-10 Mike Frysinger <vapier@gentoo.org>
280
281 * configure: Regenerate.
282
0dc73ef7
MF		 2832016-01-10 Mike Frysinger <vapier@gentoo.org>
284
285 * configure: Regenerate.
286
936df756
MF		 2872016-01-09 Mike Frysinger <vapier@gentoo.org>
288
289 * config.in, configure: Regenerate.
290
2e3d4f4d
MF		 2912016-01-06 Mike Frysinger <vapier@gentoo.org>
292
293 * interp.c (sim_open): Mark argv const.
294 (sim_create_inferior): Mark argv and env const.
295
9bbf6f91
MF		 2962016-01-04 Mike Frysinger <vapier@gentoo.org>
297
298 * configure: Regenerate.
299
77cf2ef5
MF		 3002016-01-03 Mike Frysinger <vapier@gentoo.org>
301
302 * interp.c (sim_open): Update sim_parse_args comment.
303
0cb8d851
MF		 3042016-01-03 Mike Frysinger <vapier@gentoo.org>
305
306 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
307 * configure: Regenerate.
308
1ac72f06
MF		 3092016-01-02 Mike Frysinger <vapier@gentoo.org>
310
311 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
312 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
313 * configure: Regenerate.
314 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
315
d47f5b30
MF		 3162016-01-02 Mike Frysinger <vapier@gentoo.org>
317
318 * dv-tx3904cpu.c (CPU, SD): Delete.
319
e1211e55
MF		 3202015-12-30 Mike Frysinger <vapier@gentoo.org>
321
322 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
323 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
324 (sim_store_register): Rename to ...
325 (mips_reg_store): ... this. Delete local cpu var.
326 Update sim_io_eprintf calls.
327 (sim_fetch_register): Rename to ...
328 (mips_reg_fetch): ... this. Delete local cpu var.
329 Update sim_io_eprintf calls.
330
5e744ef8
MF		 3312015-12-27 Mike Frysinger <vapier@gentoo.org>
332
333 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
334
1b393626
MF		 3352015-12-26 Mike Frysinger <vapier@gentoo.org>
336
337 * config.in, configure: Regenerate.
338
26f8bf63
MF		 3392015-12-26 Mike Frysinger <vapier@gentoo.org>
340
341 * interp.c (sim_write, sim_read): Delete.
342 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
343 (load_word): Likewise.
344 * micromips.igen (cache): Likewise.
345 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
346 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
347 do_store_left, do_store_right, do_load_double, do_store_double):
348 Likewise.
349 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
350 (do_prefx): Likewise.
351 * sim-main.c (address_translation, prefetch): Delete.
352 (ifetch32, ifetch16): Delete call to AddressTranslation and set
353 paddr=vaddr.
354 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
355 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
356 (LoadMemory, StoreMemory): Delete CCA arg.
357
ef04e371
MF		 3582015-12-24 Mike Frysinger <vapier@gentoo.org>
359
360 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
361 * configure: Regenerated.
362
cb379ede
MF		 3632015-12-24 Mike Frysinger <vapier@gentoo.org>
364
365 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
366 * tconfig.h: Delete.
367
26936211
MF		 3682015-12-24 Mike Frysinger <vapier@gentoo.org>
369
370 * tconfig.h (SIM_HANDLES_LMA): Delete.
371
84e8e361
MF		 3722015-12-24 Mike Frysinger <vapier@gentoo.org>
373
374 * sim-main.h (WITH_WATCHPOINTS): Delete.
375
3cabaf66
MF		 3762015-12-24 Mike Frysinger <vapier@gentoo.org>
377
378 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
379
8abe6c66
MF		 3802015-12-24 Mike Frysinger <vapier@gentoo.org>
381
382 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
383
1d19cae7
DV		 3842015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
385
386 * micromips.igen (process_isa_mode): Fix left shift of negative
387 value.
388
cdf850e9
MF		 3892015-11-17 Mike Frysinger <vapier@gentoo.org>
390
391 * sim-main.h (WITH_MODULO_MEMORY): Delete.
392
797eee42
MF		 3932015-11-15 Mike Frysinger <vapier@gentoo.org>
394
395 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
396
6e4f085c
MF		 3972015-11-14 Mike Frysinger <vapier@gentoo.org>
398
399 * interp.c (sim_close): Rename to ...
400 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
401 sim_io_shutdown.
402 * sim-main.h (mips_sim_close): Declare.
403 (SIM_CLOSE_HOOK): Define.
404
8e394ffc
AB		 4052015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
406 Ali Lown <ali.lown@imgtec.com>
407
408 * Makefile.in (tmp-micromips): New rule.
409 (tmp-mach-multi): Add support for micromips.
410 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
411 that works for both mips64 and micromips64.
412 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
413 micromips32.
414 Add build support for micromips.
415 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
416 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
417 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
418 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
419 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
420 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
421 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
422 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
423 Refactored instruction code to use these functions.
424 * dsp2.igen: Refactored instruction code to use the new functions.
425 * interp.c (decode_coproc): Refactored to work with any instruction
426 encoding.
427 (isa_mode): New variable
428 (RSVD_INSTRUCTION): Changed to 0x00000039.
429 * m16.igen (BREAK16): Refactored instruction to use do_break16.
430 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
431 * micromips.dc: New file.
432 * micromips.igen: New file.
433 * micromips16.dc: New file.
434 * micromipsdsp.igen: New file.
435 * micromipsrun.c: New file.
436 * mips.igen (do_swc1): Changed to work with any instruction encoding.
437 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
438 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
439 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
440 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
441 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
442 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
443 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
444 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
445 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
446 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
447 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
448 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
449 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
450 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
451 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
452 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
453 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
454 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
455 instructions.
456 Refactored instruction code to use these functions.
457 (RSVD): Changed to use new reserved instruction.
458 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
459 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
460 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
461 do_store_double): Added micromips32 and micromips64 models.
462 Added include for micromips.igen and micromipsdsp.igen
463 Add micromips32 and micromips64 models.
464 (DecodeCoproc): Updated to use new macro definition.
465 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
466 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
467 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
468 Refactored instruction code to use these functions.
469 * sim-main.h (CP0_operation): New enum.
470 (DecodeCoproc): Updated macro.
471 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
472 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
473 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
474 ISA_MODE_MICROMIPS): New defines.
475 (sim_state): Add isa_mode field.
476
8d0978fb
MF		 4772015-06-23 Mike Frysinger <vapier@gentoo.org>
478
479 * configure: Regenerate.
480
306f4178
MF		 4812015-06-12 Mike Frysinger <vapier@gentoo.org>
482
483 * configure.ac: Change configure.in to configure.ac.
484 * configure: Regenerate.
485
a3487082
MF		 4862015-06-12 Mike Frysinger <vapier@gentoo.org>
487
488 * configure: Regenerate.
489
29bc024d
MF		 4902015-06-12 Mike Frysinger <vapier@gentoo.org>
491
492 * interp.c [TRACE]: Delete.
493 (TRACE): Change to WITH_TRACE_ANY_P.
494 [!WITH_TRACE_ANY_P] (open_trace): Define.
495 (mips_option_handler, open_trace, sim_close, dotrace):
496 Change defined(TRACE) to WITH_TRACE_ANY_P.
497 (sim_open): Delete TRACE ifdef check.
498 * sim-main.c (load_memory): Delete TRACE ifdef check.
499 (store_memory): Likewise.
500 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
501 [!WITH_TRACE_ANY_P] (dotrace): Define.
502
3ebe2863
MF		 5032015-04-18 Mike Frysinger <vapier@gentoo.org>
504
505 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
506 comments.
507
20bca71d
MF		 5082015-04-18 Mike Frysinger <vapier@gentoo.org>
509
510 * sim-main.h (SIM_CPU): Delete.
511
7e83aa92
MF		 5122015-04-18 Mike Frysinger <vapier@gentoo.org>
513
514 * sim-main.h (sim_cia): Delete.
515
034685f9
MF		 5162015-04-17 Mike Frysinger <vapier@gentoo.org>
517
518 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
519 PU_PC_GET.
520 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
521 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
522 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
523 CIA_SET to CPU_PC_SET.
524 * sim-main.h (CIA_GET, CIA_SET): Delete.
525
78e9aa70
MF		 5262015-04-15 Mike Frysinger <vapier@gentoo.org>
527
528 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
529 * sim-main.h (STATE_CPU): Delete.
530
bf12d44e
MF		 5312015-04-13 Mike Frysinger <vapier@gentoo.org>
532
533 * configure: Regenerate.
534
7bebb329
MF		 5352015-04-13 Mike Frysinger <vapier@gentoo.org>
536
537 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
538 * interp.c (mips_pc_get, mips_pc_set): New functions.
539 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
540 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
541 (sim_pc_get): Delete.
542 * sim-main.h (SIM_CPU): Define.
543 (struct sim_state): Change cpu to an array of pointers.
544 (STATE_CPU): Drop &.
545
8ac57fbd
MF		 5462015-04-13 Mike Frysinger <vapier@gentoo.org>
547
548 * interp.c (mips_option_handler, open_trace, sim_close,
549 sim_write, sim_read, sim_store_register, sim_fetch_register,
550 sim_create_inferior, pr_addr, pr_uword64): Convert old style
551 prototypes.
552 (sim_open): Convert old style prototype. Change casts with
553 sim_write to unsigned char *.
554 (fetch_str): Change null to unsigned char, and change cast to
555 unsigned char *.
556 (sim_monitor): Change c & ch to unsigned char. Change cast to
557 unsigned char *.
558
e787f858
MF		 5592015-04-12 Mike Frysinger <vapier@gentoo.org>
560
561 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
562
122bbfb5
MF		 5632015-04-06 Mike Frysinger <vapier@gentoo.org>
564
565 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
566
0fe84f3f
MF		 5672015-04-01 Mike Frysinger <vapier@gentoo.org>
568
569 * tconfig.h (SIM_HAVE_PROFILE): Delete.
570
aadc9410
MF		 5712015-03-31 Mike Frysinger <vapier@gentoo.org>
572
573 * config.in, configure: Regenerate.
574
05f53ed6
MF		 5752015-03-24 Mike Frysinger <vapier@gentoo.org>
576
577 * interp.c (sim_pc_get): New function.
578
c0931f26
MF		 5792015-03-24 Mike Frysinger <vapier@gentoo.org>
580
581 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
582 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
583
30452bbe
MF		 5842015-03-24 Mike Frysinger <vapier@gentoo.org>
585
586 * configure: Regenerate.
587
64dd13df
MF		 5882015-03-23 Mike Frysinger <vapier@gentoo.org>
589
590 * configure: Regenerate.
591
49cd1634
MF		 5922015-03-23 Mike Frysinger <vapier@gentoo.org>
593
594 * configure: Regenerate.
595 * configure.ac (mips_extra_objs): Delete.
596 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
597 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
598
3649cb06
MF		 5992015-03-23 Mike Frysinger <vapier@gentoo.org>
600
601 * configure: Regenerate.
602 * configure.ac: Delete sim_hw checks for dv-sockser.
603
ae7d0cac
MF		 6042015-03-16 Mike Frysinger <vapier@gentoo.org>
605
606 * config.in, configure: Regenerate.
607 * tconfig.in: Rename file ...
608 * tconfig.h: ... here.
609
8406bb59
MF		 6102015-03-15 Mike Frysinger <vapier@gentoo.org>
611
612 * tconfig.in: Delete includes.
613 [HAVE_DV_SOCKSER]: Delete.
614
465fb143
MF		 6152015-03-14 Mike Frysinger <vapier@gentoo.org>
616
617 * Makefile.in (SIM_RUN_OBJS): Delete.
618
5cddc23a
MF		 6192015-03-14 Mike Frysinger <vapier@gentoo.org>
620
621 * configure.ac (AC_CHECK_HEADERS): Delete.
622 * aclocal.m4, configure: Regenerate.
623
2974be62
AM		 6242014-08-19 Alan Modra <amodra@gmail.com>
625
626 * configure: Regenerate.
627
faa743bb
RM		 6282014-08-15 Roland McGrath <mcgrathr@google.com>
629
630 * configure: Regenerate.
631 * config.in: Regenerate.
632
1a8a700e
MF		 6332014-03-04 Mike Frysinger <vapier@gentoo.org>
634
635 * configure: Regenerate.
636
bf3d9781
AM		 6372013-09-23 Alan Modra <amodra@gmail.com>
638
639 * configure: Regenerate.
640
31e6ad7d
MF		 6412013-06-03 Mike Frysinger <vapier@gentoo.org>
642
643 * aclocal.m4, configure: Regenerate.
644
d3685d60
TT		 6452013-05-10 Freddie Chopin <freddie_chopin@op.pl>
646
647 * configure: Rebuild.
648
1517bd27
MF		 6492013-03-26 Mike Frysinger <vapier@gentoo.org>
650
651 * configure: Regenerate.
652
3be31516
JS		 6532013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
654
655 * configure.ac: Address use of dv-sockser.o.
656 * tconfig.in: Conditionalize use of dv_sockser_install.
657 * configure: Regenerated.
658 * config.in: Regenerated.
659
37cb8f8e
SE		 6602012-10-04 Chao-ying Fu <fu@mips.com>
661 Steve Ellcey <sellcey@mips.com>
662
663 * mips/mips3264r2.igen (rdhwr): New.
664
87c8644f
JS		 6652012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
666
667 * configure.ac: Always link against dv-sockser.o.
668 * configure: Regenerate.
669
5f3ef9d0
JB		 6702012-06-15 Joel Brobecker <brobecker@adacore.com>
671
672 * config.in, configure: Regenerate.
673
a6ff997c
NC		 6742012-05-18 Nick Clifton <nickc@redhat.com>
675
676 PR 14072
677 * interp.c: Include config.h before system header files.
678
2232061b
MF		 6792012-03-24 Mike Frysinger <vapier@gentoo.org>
680
681 * aclocal.m4, config.in, configure: Regenerate.
682
db2e4d67
MF		 6832011-12-03 Mike Frysinger <vapier@gentoo.org>
684
685 * aclocal.m4: New file.
686 * configure: Regenerate.
687
4399a56b
MF		 6882011-10-19 Mike Frysinger <vapier@gentoo.org>
689
690 * configure: Regenerate after common/acinclude.m4 update.
691
9c082ca8
MF		 6922011-10-17 Mike Frysinger <vapier@gentoo.org>
693
694 * configure.ac: Change include to common/acinclude.m4.
695
6ffe910a
MF		 6962011-10-17 Mike Frysinger <vapier@gentoo.org>
697
698 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
699 call. Replace common.m4 include with SIM_AC_COMMON.
700 * configure: Regenerate.
701
31b28250
HPN		 7022011-07-08 Hans-Peter Nilsson <hp@axis.com>
703
3faa01e3
HPN		 704 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
705 $(SIM_EXTRA_DEPS).
706 (tmp-mach-multi): Exit early when igen fails.
31b28250 707
2419798b
MF		 7082011-07-05 Mike Frysinger <vapier@gentoo.org>
709
710 * interp.c (sim_do_command): Delete.
711
d79fe0d6
MF		 7122011-02-14 Mike Frysinger <vapier@gentoo.org>
713
714 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
715 (tx3904sio_fifo_reset): Likewise.
716 * interp.c (sim_monitor): Likewise.
717
5558e7e6
MF		 7182010-04-14 Mike Frysinger <vapier@gentoo.org>
719
720 * interp.c (sim_write): Add const to buffer arg.
721
35aafff4
JB		 7222010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
723
724 * interp.c: Don't include sysdep.h
725
3725885a
RW		 7262010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
727
728 * configure: Regenerate.
729
d6416cdc
RW		 7302009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
731
81ecdfbb
RW		 732 * config.in: Regenerate.
733 * configure: Likewise.
734
d6416cdc
RW		 735 * configure: Regenerate.
736
b5bd9624
HPN		 7372008-07-11 Hans-Peter Nilsson <hp@axis.com>
738
739 * configure: Regenerate to track ../common/common.m4 changes.
740 * config.in: Ditto.
741
6efef468 7422008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 743 Daniel Jacobowitz <dan@codesourcery.com>
744 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 745
746 * configure: Regenerate.
747
60dc88db
RS		 7482007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
749
750 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
751 that unconditionally allows fmt_ps.
752 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
753 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
754 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
755 filter from 64,f to 32,f.
756 (PREFX): Change filter from 64 to 32.
757 (LDXC1, LUXC1): Provide separate mips32r2 implementations
758 that use do_load_double instead of do_load. Make both LUXC1
759 versions unpredictable if SizeFGR () != 64.
760 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
761 instead of do_store. Remove unused variable. Make both SUXC1
762 versions unpredictable if SizeFGR () != 64.
763
599ca73e
RS		 7642007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
765
766 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
767 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
768 shifts for that case.
769
2525df03
NC		 7702007-09-04 Nick Clifton <nickc@redhat.com>
771
772 * interp.c (options enum): Add OPTION_INFO_MEMORY.
773 (display_mem_info): New static variable.
774 (mips_option_handler): Handle OPTION_INFO_MEMORY.
775 (mips_options): Add info-memory and memory-info.
776 (sim_open): After processing the command line and board
777 specification, check display_mem_info. If it is set then
778 call the real handler for the --memory-info command line
779 switch.
780
35ee6e1e
JB		 7812007-08-24 Joel Brobecker <brobecker@adacore.com>
782
783 * configure.ac: Change license of multi-run.c to GPL version 3.
784 * configure: Regenerate.
785
d5fb0879
RS		 7862007-06-28 Richard Sandiford <richard@codesourcery.com>
787
788 * configure.ac, configure: Revert last patch.
789
2a2ce21b
RS		 7902007-06-26 Richard Sandiford <richard@codesourcery.com>
791
792 * configure.ac (sim_mipsisa3264_configs): New variable.
793 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
794 every configuration support all four targets, using the triplet to
795 determine the default.
796 * configure: Regenerate.
797
efdcccc9
RS		 7982007-06-25 Richard Sandiford <richard@codesourcery.com>
799
0a7692b2 800 * Makefile.in (m16run.o): New rule.
efdcccc9 801
f532a356
TS		 8022007-05-15 Thiemo Seufer <ths@mips.com>
803
804 * mips3264r2.igen (DSHD): Fix compile warning.
805
bfe9c90b
TS		 8062007-05-14 Thiemo Seufer <ths@mips.com>
807
808 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
809 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
810 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
811 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
812 for mips32r2.
813
53f4826b
TS		 8142007-03-01 Thiemo Seufer <ths@mips.com>
815
816 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
817 and mips64.
818
8bf3ddc8
TS		 8192007-02-20 Thiemo Seufer <ths@mips.com>
820
821 * dsp.igen: Update copyright notice.
822 * dsp2.igen: Fix copyright notice.
823
8b082fb1 8242007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 825 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 826
827 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
828 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
829 Add dsp2 to sim_igen_machine.
830 * configure: Regenerate.
831 * dsp.igen (do_ph_op): Add MUL support when op = 2.
832 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
833 (mulq_rs.ph): Use do_ph_mulq.
834 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
835 * mips.igen: Add dsp2 model and include dsp2.igen.
836 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
837 for *mips32r2, *mips64r2, *dsp.
838 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
839 for *mips32r2, *mips64r2, *dsp2.
840 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
841
b1004875 8422007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 843 Nigel Stephens <nigel@mips.com>
b1004875
TS		 844
845 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
846 jumps with hazard barrier.
847
f8df4c77 8482007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 849 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 850
851 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
852 after each call to sim_io_write.
853
b1004875 8542007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 855 Nigel Stephens <nigel@mips.com>
b1004875
TS		 856
857 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
858 supported by this simulator.
07802d98
TS		 859 (decode_coproc): Recognise additional CP0 Config registers
860 correctly.
861
14fb6c5a 8622007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 863 Nigel Stephens <nigel@mips.com>
864 David Ung <davidu@mips.com>
14fb6c5a
TS		 865
866 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
867 uninterpreted formats. If fmt is one of the uninterpreted types
868 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
869 fmt_word, and fmt_uninterpreted_64 like fmt_long.
870 (store_fpr): When writing an invalid odd register, set the
871 matching even register to fmt_unknown, not the following register.
872 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
873 the the memory window at offset 0 set by --memory-size command
874 line option.
875 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
876 point register.
877 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
878 register.
879 (sim_monitor): When returning the memory size to the MIPS
880 application, use the value in STATE_MEM_SIZE, not an arbitrary
881 hardcoded value.
882 (cop_lw): Don' mess around with FPR_STATE, just pass
883 fmt_uninterpreted_32 to StoreFPR.
884 (cop_sw): Similarly.
885 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
886 (cop_sd): Similarly.
887 * mips.igen (not_word_value): Single version for mips32, mips64
888 and mips16.
889
c8847145 8902007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 891 Nigel Stephens <nigel@mips.com>
c8847145
TS		 892
893 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
894 MBytes.
895
4b5d35ee
TS		 8962007-02-17 Thiemo Seufer <ths@mips.com>
897
898 * configure.ac (mips*-sde-elf*): Move in front of generic machine
899 configuration.
900 * configure: Regenerate.
901
3669427c
TS		 9022007-02-17 Thiemo Seufer <ths@mips.com>
903
904 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
905 Add mdmx to sim_igen_machine.
906 (mipsisa64*-*-*): Likewise. Remove dsp.
907 (mipsisa32*-*-*): Remove dsp.
908 * configure: Regenerate.
909
109ad085
TS		 9102007-02-13 Thiemo Seufer <ths@mips.com>
911
912 * configure.ac: Add mips*-sde-elf* target.
913 * configure: Regenerate.
914
921d7ad3
HPN		 9152006-12-21 Hans-Peter Nilsson <hp@axis.com>
916
917 * acconfig.h: Remove.
918 * config.in, configure: Regenerate.
919
02f97da7
TS		 9202006-11-07 Thiemo Seufer <ths@mips.com>
921
922 * dsp.igen (do_w_op): Fix compiler warning.
923
2d2733fc 9242006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 925 David Ung <davidu@mips.com>
2d2733fc
TS		 926
927 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
928 sim_igen_machine.
929 * configure: Regenerate.
930 * mips.igen (model): Add smartmips.
931 (MADDU): Increment ACX if carry.
932 (do_mult): Clear ACX.
933 (ROR,RORV): Add smartmips.
72f4393d 934 (include): Include smartmips.igen.
2d2733fc
TS		 935 * sim-main.h (ACX): Set to REGISTERS[89].
936 * smartmips.igen: New file.
937
d85c3a10 9382006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 939 David Ung <davidu@mips.com>
d85c3a10
TS		 940
941 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
942 mips3264r2.igen. Add missing dependency rules.
943 * m16e.igen: Support for mips16e save/restore instructions.
944
e85e3205
RE		 9452006-06-13 Richard Earnshaw <rearnsha@arm.com>
946
947 * configure: Regenerated.
948
2f0122dc
DJ		 9492006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
950
951 * configure: Regenerated.
952
20e95c23
DJ		 9532006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
954
955 * configure: Regenerated.
956
69088b17
CF		 9572006-05-15 Chao-ying Fu <fu@mips.com>
958
959 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
960
0275de4e
NC		 9612006-04-18 Nick Clifton <nickc@redhat.com>
962
963 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
964 statement.
965
b3a3ffef
HPN		 9662006-03-29 Hans-Peter Nilsson <hp@axis.com>
967
968 * configure: Regenerate.
969
40a5538e
CF		 9702005-12-14 Chao-ying Fu <fu@mips.com>
971
972 * Makefile.in (SIM_OBJS): Add dsp.o.
973 (dsp.o): New dependency.
974 (IGEN_INCLUDE): Add dsp.igen.
975 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
976 mipsisa64*-*-*): Add dsp to sim_igen_machine.
977 * configure: Regenerate.
978 * mips.igen: Add dsp model and include dsp.igen.
979 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
980 because these instructions are extended in DSP ASE.
981 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
982 adding 6 DSP accumulator registers and 1 DSP control register.
983 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
984 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
985 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
986 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
987 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
988 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
989 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
990 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
991 DSPCR_CCOND_SMASK): New define.
992 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
993 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
994
21d14896
ILT		 9952005-07-08 Ian Lance Taylor <ian@airs.com>
996
997 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
998
b16d63da 9992005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1000 Nigel Stephens <nigel@mips.com>
1001
1002 * mips.igen: New mips16e model and include m16e.igen.
1003 (check_u64): Add mips16e tag.
1004 * m16e.igen: New file for MIPS16e instructions.
1005 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1006 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1007 models.
1008 * configure: Regenerate.
b16d63da 1009
e70cb6cd 10102005-05-26 David Ung <davidu@mips.com>
72f4393d 1011
e70cb6cd
CD		 1012 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1013 tags to all instructions which are applicable to the new ISAs.
1014 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1015 vr.igen.
1016 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1017 instructions.
e70cb6cd
CD		 1018 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1019 to mips.igen.
1020 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1021 * configure: Regenerate.
72f4393d 1022
2b193c4a
MK		 10232005-03-23 Mark Kettenis <kettenis@gnu.org>
1024
1025 * configure: Regenerate.
1026
35695fd6
AC		 10272005-01-14 Andrew Cagney <cagney@gnu.org>
1028
1029 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1030 explicit call to AC_CONFIG_HEADER.
1031 * configure: Regenerate.
1032
f0569246
AC		 10332005-01-12 Andrew Cagney <cagney@gnu.org>
1034
1035 * configure.ac: Update to use ../common/common.m4.
1036 * configure: Re-generate.
1037
38f48d72
AC		 10382005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1039
1040 * configure: Regenerated to track ../common/aclocal.m4 changes.
1041
b7026657
AC		 10422005-01-07 Andrew Cagney <cagney@gnu.org>
1043
1044 * configure.ac: Rename configure.in, require autoconf 2.59.
1045 * configure: Re-generate.
1046
379832de
HPN		 10472004-12-08 Hans-Peter Nilsson <hp@axis.com>
1048
1049 * configure: Regenerate for ../common/aclocal.m4 update.
1050
cd62154c 10512004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1052
cd62154c
AC		 1053 Committed by Andrew Cagney.
1054 * m16.igen (CMP, CMPI): Fix assembler.
1055
e5da76ec
CD		 10562004-08-18 Chris Demetriou <cgd@broadcom.com>
1057
1058 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1059 * configure: Regenerate.
1060
139181c8
CD		 10612004-06-25 Chris Demetriou <cgd@broadcom.com>
1062
1063 * configure.in (sim_m16_machine): Include mipsIII.
1064 * configure: Regenerate.
1065
1a27f959
CD		 10662004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1067
72f4393d 1068 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1069 from COP0_BADVADDR.
1070 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1071
5dbb7b5a
CD		 10722004-04-10 Chris Demetriou <cgd@broadcom.com>
1073
1074 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1075
14234056
CD		 10762004-04-09 Chris Demetriou <cgd@broadcom.com>
1077
1078 * mips.igen (check_fmt): Remove.
1079 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1080 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1081 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1082 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1083 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1084 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1085 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1086 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1087 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1088 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1089
c6f9085c
CD		 10902004-04-09 Chris Demetriou <cgd@broadcom.com>
1091
1092 * sb1.igen (check_sbx): New function.
1093 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1094
11d66e66 10952004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1096 Richard Sandiford <rsandifo@redhat.com>
1097
1098 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1099 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1100 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1101 separate implementations for mipsIV and mipsV. Use new macros to
1102 determine whether the restrictions apply.
1103
b3208fb8
CD		 11042004-01-19 Chris Demetriou <cgd@broadcom.com>
1105
1106 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1107 (check_mult_hilo): Improve comments.
1108 (check_div_hilo): Likewise. Also, fork off a new version
1109 to handle mips32/mips64 (since there are no hazards to check
1110 in MIPS32/MIPS64).
1111
9a1d84fb
CD		 11122003-06-17 Richard Sandiford <rsandifo@redhat.com>
1113
1114 * mips.igen (do_dmultx): Fix check for negative operands.
1115
ae451ac6
ILT		 11162003-05-16 Ian Lance Taylor <ian@airs.com>
1117
1118 * Makefile.in (SHELL): Make sure this is defined.
1119 (various): Use $(SHELL) whenever we invoke move-if-change.
1120
dd69d292
CD		 11212003-05-03 Chris Demetriou <cgd@broadcom.com>
1122
1123 * cp1.c: Tweak attribution slightly.
1124 * cp1.h: Likewise.
1125 * mdmx.c: Likewise.
1126 * mdmx.igen: Likewise.
1127 * mips3d.igen: Likewise.
1128 * sb1.igen: Likewise.
1129
bcd0068e
CD		 11302003-04-15 Richard Sandiford <rsandifo@redhat.com>
1131
1132 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1133 unsigned operands.
1134
6b4a8935
AC		 11352003-02-27 Andrew Cagney <cagney@redhat.com>
1136
601da316
AC		 1137 * interp.c (sim_open): Rename _bfd to bfd.
1138 (sim_create_inferior): Ditto.
6b4a8935 1139
d29e330f
CD		 11402003-01-14 Chris Demetriou <cgd@broadcom.com>
1141
1142 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1143
a2353a08
CD		 11442003-01-14 Chris Demetriou <cgd@broadcom.com>
1145
1146 * mips.igen (EI, DI): Remove.
1147
80551777
CD		 11482003-01-05 Richard Sandiford <rsandifo@redhat.com>
1149
1150 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1151
4c54fc26
CD		 11522003-01-04 Richard Sandiford <rsandifo@redhat.com>
1153 Andrew Cagney <ac131313@redhat.com>
1154 Gavin Romig-Koch <gavin@redhat.com>
1155 Graydon Hoare <graydon@redhat.com>
1156 Aldy Hernandez <aldyh@redhat.com>
1157 Dave Brolley <brolley@redhat.com>
1158 Chris Demetriou <cgd@broadcom.com>
1159
1160 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1161 (sim_mach_default): New variable.
1162 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1163 Add a new simulator generator, MULTI.
1164 * configure: Regenerate.
1165 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1166 (multi-run.o): New dependency.
1167 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1168 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1169 (tmp-multi): Combine them.
1170 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1171 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1172 (distclean-extra): New rule.
1173 * sim-main.h: Include bfd.h.
1174 (MIPS_MACH): New macro.
1175 * mips.igen (vr4120, vr5400, vr5500): New models.
1176 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1177 * vr.igen: Replace with new version.
1178
e6c674b8
CD		 11792003-01-04 Chris Demetriou <cgd@broadcom.com>
1180
1181 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1182 * configure: Regenerate.
1183
28f50ac8
CD		 11842002-12-31 Chris Demetriou <cgd@broadcom.com>
1185
1186 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1187 * mips.igen: Remove all invocations of check_branch_bug and
1188 mark_branch_bug.
1189
5071ffe6
CD		 11902002-12-16 Chris Demetriou <cgd@broadcom.com>
1191
72f4393d 1192 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1193
06e7837e
CD		 11942002-07-30 Chris Demetriou <cgd@broadcom.com>
1195
1196 * mips.igen (do_load_double, do_store_double): New functions.
1197 (LDC1, SDC1): Rename to...
1198 (LDC1b, SDC1b): respectively.
1199 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1200
2265c243
MS		 12012002-07-29 Michael Snyder <msnyder@redhat.com>
1202
1203 * cp1.c (fp_recip2): Modify initialization expression so that
1204 GCC will recognize it as constant.
1205
a2f8b4f3
CD		 12062002-06-18 Chris Demetriou <cgd@broadcom.com>
1207
1208 * mdmx.c (SD_): Delete.
1209 (Unpredictable): Re-define, for now, to directly invoke
1210 unpredictable_action().
1211 (mdmx_acc_op): Fix error in .ob immediate handling.
1212
b4b6c939
AC		 12132002-06-18 Andrew Cagney <cagney@redhat.com>
1214
1215 * interp.c (sim_firmware_command): Initialize `address'.
1216
c8cca39f
AC		 12172002-06-16 Andrew Cagney <ac131313@redhat.com>
1218
1219 * configure: Regenerated to track ../common/aclocal.m4 changes.
1220
e7e81181 12212002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1222 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1223
1224 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1225 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1226 * mips.igen: Include mips3d.igen.
1227 (mips3d): New model name for MIPS-3D ASE instructions.
1228 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1229 instructions.
e7e81181
CD		 1230 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1231 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1232 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1233 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1234 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1235 (RSquareRoot1, RSquareRoot2): New macros.
1236 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1237 (fp_rsqrt2): New functions.
1238 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1239 * configure: Regenerate.
1240
3a2b820e 12412002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1242 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1243
1244 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1245 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1246 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1247 (convert): Note that this function is not used for paired-single
1248 format conversions.
1249 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1250 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1251 (check_fmt_p): Enable paired-single support.
1252 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1253 (PUU.PS): New instructions.
1254 (CVT.S.fmt): Don't use this instruction for paired-single format
1255 destinations.
1256 * sim-main.h (FP_formats): New value 'fmt_ps.'
1257 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1258 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1259
d18ea9c2
CD		 12602002-06-12 Chris Demetriou <cgd@broadcom.com>
1261
1262 * mips.igen: Fix formatting of function calls in
1263 many FP operations.
1264
95fd5cee
CD		 12652002-06-12 Chris Demetriou <cgd@broadcom.com>
1266
1267 * mips.igen (MOVN, MOVZ): Trace result.
1268 (TNEI): Print "tnei" as the opcode name in traces.
1269 (CEIL.W): Add disassembly string for traces.
1270 (RSQRT.fmt): Make location of disassembly string consistent
1271 with other instructions.
1272
4f0d55ae
CD		 12732002-06-12 Chris Demetriou <cgd@broadcom.com>
1274
1275 * mips.igen (X): Delete unused function.
1276
3c25f8c7
AC		 12772002-06-08 Andrew Cagney <cagney@redhat.com>
1278
1279 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1280
f3c08b7e 12812002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1282 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1283
1284 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1285 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1286 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1287 (fp_nmsub): New prototypes.
1288 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1289 (NegMultiplySub): New defines.
1290 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1291 (MADD.D, MADD.S): Replace with...
1292 (MADD.fmt): New instruction.
1293 (MSUB.D, MSUB.S): Replace with...
1294 (MSUB.fmt): New instruction.
1295 (NMADD.D, NMADD.S): Replace with...
1296 (NMADD.fmt): New instruction.
1297 (NMSUB.D, MSUB.S): Replace with...
1298 (NMSUB.fmt): New instruction.
1299
52714ff9 13002002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1301 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1302
1303 * cp1.c: Fix more comment spelling and formatting.
1304 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1305 (denorm_mode): New function.
1306 (fpu_unary, fpu_binary): Round results after operation, collect
1307 status from rounding operations, and update the FCSR.
1308 (convert): Collect status from integer conversions and rounding
1309 operations, and update the FCSR. Adjust NaN values that result
1310 from conversions. Convert to use sim_io_eprintf rather than
1311 fprintf, and remove some debugging code.
1312 * cp1.h (fenr_FS): New define.
1313
577d8c4b
CD		 13142002-06-07 Chris Demetriou <cgd@broadcom.com>
1315
1316 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1317 rounding mode to sim FP rounding mode flag conversion code into...
1318 (rounding_mode): New function.
1319
196496ed
CD		 13202002-06-07 Chris Demetriou <cgd@broadcom.com>
1321
1322 * cp1.c: Clean up formatting of a few comments.
1323 (value_fpr): Reformat switch statement.
1324
cfe9ea23 13252002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1326 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1327
1328 * cp1.h: New file.
1329 * sim-main.h: Include cp1.h.
1330 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1331 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1332 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1333 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1334 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1335 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1336 * cp1.c: Don't include sim-fpu.h; already included by
1337 sim-main.h. Clean up formatting of some comments.
1338 (NaN, Equal, Less): Remove.
1339 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1340 (fp_cmp): New functions.
1341 * mips.igen (do_c_cond_fmt): Remove.
1342 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1343 Compare. Add result tracing.
1344 (CxC1): Remove, replace with...
1345 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1346 (DMxC1): Remove, replace with...
1347 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1348 (MxC1): Remove, replace with...
1349 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1350
ee7254b0
CD		 13512002-06-04 Chris Demetriou <cgd@broadcom.com>
1352
1353 * sim-main.h (FGRIDX): Remove, replace all uses with...
1354 (FGR_BASE): New macro.
1355 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1356 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1357 (NR_FGR, FGR): Likewise.
1358 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1359 * mips.igen: Likewise.
1360
d3eb724f
CD		 13612002-06-04 Chris Demetriou <cgd@broadcom.com>
1362
1363 * cp1.c: Add an FSF Copyright notice to this file.
1364
ba46ddd0 13652002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1366 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1367
1368 * cp1.c (Infinity): Remove.
1369 * sim-main.h (Infinity): Likewise.
1370
1371 * cp1.c (fp_unary, fp_binary): New functions.
1372 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1373 (fp_sqrt): New functions, implemented in terms of the above.
1374 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1375 (Recip, SquareRoot): Remove (replaced by functions above).
1376 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1377 (fp_recip, fp_sqrt): New prototypes.
1378 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1379 (Recip, SquareRoot): Replace prototypes with #defines which
1380 invoke the functions above.
72f4393d 1381
18d8a52d
CD		 13822002-06-03 Chris Demetriou <cgd@broadcom.com>
1383
1384 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1385 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1386 file, remove PARAMS from prototypes.
1387 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1388 simulator state arguments.
1389 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1390 pass simulator state arguments.
1391 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1392 (store_fpr, convert): Remove 'sd' argument.
1393 (value_fpr): Likewise. Convert to use 'SD' instead.
1394
0f154cbd
CD		 13952002-06-03 Chris Demetriou <cgd@broadcom.com>
1396
1397 * cp1.c (Min, Max): Remove #if 0'd functions.
1398 * sim-main.h (Min, Max): Remove.
1399
e80fc152
CD		 14002002-06-03 Chris Demetriou <cgd@broadcom.com>
1401
1402 * cp1.c: fix formatting of switch case and default labels.
1403 * interp.c: Likewise.
1404 * sim-main.c: Likewise.
1405
bad673a9
CD		 14062002-06-03 Chris Demetriou <cgd@broadcom.com>
1407
1408 * cp1.c: Clean up comments which describe FP formats.
1409 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1410
7cbea089 14112002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1412 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1413
1414 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1415 Broadcom SiByte SB-1 processor configurations.
1416 * configure: Regenerate.
1417 * sb1.igen: New file.
1418 * mips.igen: Include sb1.igen.
1419 (sb1): New model.
1420 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1421 * mdmx.igen: Add "sb1" model to all appropriate functions and
1422 instructions.
1423 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1424 (ob_func, ob_acc): Reference the above.
1425 (qh_acc): Adjust to keep the same size as ob_acc.
1426 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1427 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1428
909daa82
CD		 14292002-06-03 Chris Demetriou <cgd@broadcom.com>
1430
1431 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1432
f4f1b9f1 14332002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1434 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1435
1436 * mips.igen (mdmx): New (pseudo-)model.
1437 * mdmx.c, mdmx.igen: New files.
1438 * Makefile.in (SIM_OBJS): Add mdmx.o.
1439 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1440 New typedefs.
1441 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1442 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1443 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1444 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1445 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1446 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1447 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1448 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1449 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1450 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1451 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1452 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1453 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1454 (qh_fmtsel): New macros.
1455 (_sim_cpu): New member "acc".
1456 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1457 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1458
5accf1ff
CD		 14592002-05-01 Chris Demetriou <cgd@broadcom.com>
1460
1461 * interp.c: Use 'deprecated' rather than 'depreciated.'
1462 * sim-main.h: Likewise.
1463
402586aa
CD		 14642002-05-01 Chris Demetriou <cgd@broadcom.com>
1465
1466 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1467 which wouldn't compile anyway.
1468 * sim-main.h (unpredictable_action): New function prototype.
1469 (Unpredictable): Define to call igen function unpredictable().
1470 (NotWordValue): New macro to call igen function not_word_value().
1471 (UndefinedResult): Remove.
1472 * interp.c (undefined_result): Remove.
1473 (unpredictable_action): New function.
1474 * mips.igen (not_word_value, unpredictable): New functions.
1475 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1476 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1477 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1478 NotWordValue() to check for unpredictable inputs, then
1479 Unpredictable() to handle them.
1480
c9b9995a
CD		 14812002-02-24 Chris Demetriou <cgd@broadcom.com>
1482
1483 * mips.igen: Fix formatting of calls to Unpredictable().
1484
e1015982
AC		 14852002-04-20 Andrew Cagney <ac131313@redhat.com>
1486
1487 * interp.c (sim_open): Revert previous change.
1488
b882a66b
AO		 14892002-04-18 Alexandre Oliva <aoliva@redhat.com>
1490
1491 * interp.c (sim_open): Disable chunk of code that wrote code in
1492 vector table entries.
1493
c429b7dd
CD		 14942002-03-19 Chris Demetriou <cgd@broadcom.com>
1495
1496 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1497 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1498 unused definitions.
1499
37d146fa
CD		 15002002-03-19 Chris Demetriou <cgd@broadcom.com>
1501
1502 * cp1.c: Fix many formatting issues.
1503
07892c0b
CD		 15042002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1505
1506 * cp1.c (fpu_format_name): New function to replace...
1507 (DOFMT): This. Delete, and update all callers.
1508 (fpu_rounding_mode_name): New function to replace...
1509 (RMMODE): This. Delete, and update all callers.
1510
487f79b7
CD		 15112002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1512
1513 * interp.c: Move FPU support routines from here to...
1514 * cp1.c: Here. New file.
1515 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1516 (cp1.o): New target.
1517
1e799e28
CD		 15182002-03-12 Chris Demetriou <cgd@broadcom.com>
1519
1520 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1521 * mips.igen (mips32, mips64): New models, add to all instructions
1522 and functions as appropriate.
1523 (loadstore_ea, check_u64): New variant for model mips64.
1524 (check_fmt_p): New variant for models mipsV and mips64, remove
1525 mipsV model marking fro other variant.
1526 (SLL) Rename to...
1527 (SLLa) this.
1528 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1529 for mips32 and mips64.
1530 (DCLO, DCLZ): New instructions for mips64.
1531
82f728db
CD		 15322002-03-07 Chris Demetriou <cgd@broadcom.com>
1533
1534 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1535 immediate or code as a hex value with the "%#lx" format.
1536 (ANDI): Likewise, and fix printed instruction name.
1537
b96e7ef1
CD		 15382002-03-05 Chris Demetriou <cgd@broadcom.com>
1539
1540 * sim-main.h (UndefinedResult, Unpredictable): New macros
1541 which currently do nothing.
1542
d35d4f70
CD		 15432002-03-05 Chris Demetriou <cgd@broadcom.com>
1544
1545 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1546 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1547 (status_CU3): New definitions.
1548
1549 * sim-main.h (ExceptionCause): Add new values for MIPS32
1550 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1551 for DebugBreakPoint and NMIReset to note their status in
1552 MIPS32 and MIPS64.
1553 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1554 (SignalExceptionCacheErr): New exception macros.
1555
3ad6f714
CD		 15562002-03-05 Chris Demetriou <cgd@broadcom.com>
1557
1558 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1559 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1560 is always enabled.
1561 (SignalExceptionCoProcessorUnusable): Take as argument the
1562 unusable coprocessor number.
1563
86b77b47
CD		 15642002-03-05 Chris Demetriou <cgd@broadcom.com>
1565
1566 * mips.igen: Fix formatting of all SignalException calls.
1567
97a88e93 15682002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1569
1570 * sim-main.h (SIGNEXTEND): Remove.
1571
97a88e93 15722002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1573
1574 * mips.igen: Remove gencode comment from top of file, fix
1575 spelling in another comment.
1576
97a88e93 15772002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1578
1579 * mips.igen (check_fmt, check_fmt_p): New functions to check
1580 whether specific floating point formats are usable.
1581 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1582 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1583 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1584 Use the new functions.
1585 (do_c_cond_fmt): Remove format checks...
1586 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1587
97a88e93 15882002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1589
1590 * mips.igen: Fix formatting of check_fpu calls.
1591
41774c9d
CD		 15922002-03-03 Chris Demetriou <cgd@broadcom.com>
1593
1594 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1595
4a0bd876
CD		 15962002-03-03 Chris Demetriou <cgd@broadcom.com>
1597
1598 * mips.igen: Remove whitespace at end of lines.
1599
09297648
CD		 16002002-03-02 Chris Demetriou <cgd@broadcom.com>
1601
1602 * mips.igen (loadstore_ea): New function to do effective
1603 address calculations.
1604 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1605 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1606 CACHE): Use loadstore_ea to do effective address computations.
1607
043b7057
CD		 16082002-03-02 Chris Demetriou <cgd@broadcom.com>
1609
1610 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1611 * mips.igen (LL, CxC1, MxC1): Likewise.
1612
c1e8ada4
CD		 16132002-03-02 Chris Demetriou <cgd@broadcom.com>
1614
1615 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1616 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1617 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1618 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1619 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1620 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1621 Don't split opcode fields by hand, use the opcode field values
1622 provided by igen.
1623
3e1dca16
CD		 16242002-03-01 Chris Demetriou <cgd@broadcom.com>
1625
1626 * mips.igen (do_divu): Fix spacing.
1627
1628 * mips.igen (do_dsllv): Move to be right before DSLLV,
1629 to match the rest of the do_<shift> functions.
1630
fff8d27d
CD		 16312002-03-01 Chris Demetriou <cgd@broadcom.com>
1632
1633 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1634 DSRL32, do_dsrlv): Trace inputs and results.
1635
0d3e762b
CD		 16362002-03-01 Chris Demetriou <cgd@broadcom.com>
1637
1638 * mips.igen (CACHE): Provide instruction-printing string.
1639
1640 * interp.c (signal_exception): Comment tokens after #endif.
1641
eb5fcf93
CD		 16422002-02-28 Chris Demetriou <cgd@broadcom.com>
1643
1644 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1645 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1646 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1647 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1648 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1649 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1650 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1651 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1652
bb22bd7d
CD		 16532002-02-28 Chris Demetriou <cgd@broadcom.com>
1654
1655 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1656 instruction-printing string.
1657 (LWU): Use '64' as the filter flag.
1658
91a177cf
CD		 16592002-02-28 Chris Demetriou <cgd@broadcom.com>
1660
1661 * mips.igen (SDXC1): Fix instruction-printing string.
1662
387f484a
CD		 16632002-02-28 Chris Demetriou <cgd@broadcom.com>
1664
1665 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1666 filter flags "32,f".
1667
3d81f391
CD		 16682002-02-27 Chris Demetriou <cgd@broadcom.com>
1669
1670 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1671 as the filter flag.
1672
af5107af
CD		 16732002-02-27 Chris Demetriou <cgd@broadcom.com>
1674
1675 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1676 add a comma) so that it more closely match the MIPS ISA
1677 documentation opcode partitioning.
1678 (PREF): Put useful names on opcode fields, and include
1679 instruction-printing string.
1680
ca971540
CD		 16812002-02-27 Chris Demetriou <cgd@broadcom.com>
1682
1683 * mips.igen (check_u64): New function which in the future will
1684 check whether 64-bit instructions are usable and signal an
1685 exception if not. Currently a no-op.
1686 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1687 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1688 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1689 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1690
1691 * mips.igen (check_fpu): New function which in the future will
1692 check whether FPU instructions are usable and signal an exception
1693 if not. Currently a no-op.
1694 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1695 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1696 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1697 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1698 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1699 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1700 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1701 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1702
1c47a468
CD		 17032002-02-27 Chris Demetriou <cgd@broadcom.com>
1704
1705 * mips.igen (do_load_left, do_load_right): Move to be immediately
1706 following do_load.
1707 (do_store_left, do_store_right): Move to be immediately following
1708 do_store.
1709
603a98e7
CD		 17102002-02-27 Chris Demetriou <cgd@broadcom.com>
1711
1712 * mips.igen (mipsV): New model name. Also, add it to
1713 all instructions and functions where it is appropriate.
1714
c5d00cc7
CD		 17152002-02-18 Chris Demetriou <cgd@broadcom.com>
1716
1717 * mips.igen: For all functions and instructions, list model
1718 names that support that instruction one per line.
1719
074e9cb8
CD		 17202002-02-11 Chris Demetriou <cgd@broadcom.com>
1721
1722 * mips.igen: Add some additional comments about supported
1723 models, and about which instructions go where.
1724 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1725 order as is used in the rest of the file.
1726
9805e229
CD		 17272002-02-11 Chris Demetriou <cgd@broadcom.com>
1728
1729 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1730 indicating that ALU32_END or ALU64_END are there to check
1731 for overflow.
1732 (DADD): Likewise, but also remove previous comment about
1733 overflow checking.
1734
f701dad2
CD		 17352002-02-10 Chris Demetriou <cgd@broadcom.com>
1736
1737 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1738 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1739 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1740 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1741 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1742 fields (i.e., add and move commas) so that they more closely
1743 match the MIPS ISA documentation opcode partitioning.
1744
17452002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1746
72f4393d
L		 1747 * mips.igen (ADDI): Print immediate value.
1748 (BREAK): Print code.
1749 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1750 (SLL): Print "nop" specially, and don't run the code
1751 that does the shift for the "nop" case.
20ae0098 1752
9e52972e
FF		 17532001-11-17 Fred Fish <fnf@redhat.com>
1754
1755 * sim-main.h (float_operation): Move enum declaration outside
1756 of _sim_cpu struct declaration.
1757
c0efbca4
JB		 17582001-04-12 Jim Blandy <jimb@redhat.com>
1759
1760 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1761 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1762 set of the FCSR.
1763 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1764 PENDING_FILL, and you can get the intended effect gracefully by
1765 calling PENDING_SCHED directly.
1766
fb891446
BE		 17672001-02-23 Ben Elliston <bje@redhat.com>
1768
1769 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1770 already defined elsewhere.
1771
8030f857
BE		 17722001-02-19 Ben Elliston <bje@redhat.com>
1773
1774 * sim-main.h (sim_monitor): Return an int.
1775 * interp.c (sim_monitor): Add return values.
1776 (signal_exception): Handle error conditions from sim_monitor.
1777
56b48a7a
CD		 17782001-02-08 Ben Elliston <bje@redhat.com>
1779
1780 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1781 (store_memory): Likewise, pass cia to sim_core_write*.
1782
d3ee60d9
FCE		 17832000-10-19 Frank Ch. Eigler <fche@redhat.com>
1784
1785 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1786 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1787
071da002
AC		 1788Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1791 * Makefile.in: Don't delete *.igen when cleaning directory.
1792
a28c02cd
AC		 1793Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1794
1795 * m16.igen (break): Call SignalException not sim_engine_halt.
1796
80ee11fa
AC		 1797Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1798
1799 From Jason Eckhardt:
1800 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1801
673388c0
AC		 1802Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1805
4c0deff4
NC		 18062000-05-24 Michael Hayes <mhayes@cygnus.com>
1807
1808 * mips.igen (do_dmultx): Fix typo.
1809
eb2d80b4
AC		 1810Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1811
1812 * configure: Regenerated to track ../common/aclocal.m4 changes.
1813
dd37a34b
AC		 1814Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1817
4c0deff4
NC		 18182000-04-12 Frank Ch. Eigler <fche@redhat.com>
1819
1820 * sim-main.h (GPR_CLEAR): Define macro.
1821
e30db738
AC		 1822Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * interp.c (decode_coproc): Output long using %lx and not %s.
1825
cb7450ea
FCE		 18262000-03-21 Frank Ch. Eigler <fche@redhat.com>
1827
1828 * interp.c (sim_open): Sort & extend dummy memory regions for
1829 --board=jmr3904 for eCos.
1830
a3027dd7
FCE		 18312000-03-02 Frank Ch. Eigler <fche@redhat.com>
1832
1833 * configure: Regenerated.
1834
1835Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1836
1837 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1838 calls, conditional on the simulator being in verbose mode.
1839
dfcd3bfb
JM		 1840Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1841
1842 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1843 cache don't get ReservedInstruction traps.
1844
c2d11a7d
JM		 18451999-11-29 Mark Salter <msalter@cygnus.com>
1846
1847 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1848 to clear status bits in sdisr register. This is how the hardware works.
1849
1850 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1851 being used by cygmon.
1852
4ce44c66
JM		 18531999-11-11 Andrew Haley <aph@cygnus.com>
1854
1855 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1856 instructions.
1857
cff3e48b
JM		 1858Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1859
1860 * mips.igen (MULT): Correct previous mis-applied patch.
1861
d4f3574e
SS		 1862Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1863
1864 * mips.igen (delayslot32): Handle sequence like
1865 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1866 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1867 (MULT): Actually pass the third register...
1868
18691999-09-03 Mark Salter <msalter@cygnus.com>
1870
1871 * interp.c (sim_open): Added more memory aliases for additional
1872 hardware being touched by cygmon on jmr3904 board.
1873
1874Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1875
1876 * configure: Regenerated to track ../common/aclocal.m4 changes.
1877
a0b3c4fd
JM		 1878Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1879
1880 * interp.c (sim_store_register): Handle case where client - GDB -
1881 specifies that a 4 byte register is 8 bytes in size.
1882 (sim_fetch_register): Ditto.
72f4393d 1883
adf40b2e
JM		 18841999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1885
1886 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1887 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1888 (idt_monitor_base): Base address for IDT monitor traps.
1889 (pmon_monitor_base): Ditto for PMON.
1890 (lsipmon_monitor_base): Ditto for LSI PMON.
1891 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1892 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1893 (sim_firmware_command): New function.
1894 (mips_option_handler): Call it for OPTION_FIRMWARE.
1895 (sim_open): Allocate memory for idt_monitor region. If "--board"
1896 option was given, add no monitor by default. Add BREAK hooks only if
1897 monitors are also there.
72f4393d 1898
43e526b9
JM		 1899Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1900
1901 * interp.c (sim_monitor): Flush output before reading input.
1902
1903Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * tconfig.in (SIM_HANDLES_LMA): Always define.
1906
1907Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 From Mark Salter <msalter@cygnus.com>:
1910 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1911 (sim_open): Add setup for BSP board.
1912
9846de1b
JM		 1913Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1914
1915 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1916 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1917 them as unimplemented.
1918
cd0fc7c3
SS		 19191999-05-08 Felix Lee <flee@cygnus.com>
1920
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1922
7a292a7a
SS		 19231999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1924
1925 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1926
1927Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1928
1929 * configure.in: Any mips64vr5*-*-* target should have
1930 -DTARGET_ENABLE_FR=1.
1931 (default_endian): Any mips64vr*el-*-* target should default to
1932 LITTLE_ENDIAN.
1933 * configure: Re-generate.
1934
19351999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1936
1937 * mips.igen (ldl): Extend from _16_, not 32.
1938
1939Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1940
1941 * interp.c (sim_store_register): Force registers written to by GDB
1942 into an un-interpreted state.
1943
c906108c
SS		 19441999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1945
1946 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1947 CPU, start periodic background I/O polls.
72f4393d 1948 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1949
19501998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1951
1952 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1953
c906108c
SS		 1954Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1955
1956 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1957 case statement.
1958
19591998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1960
1961 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1962 (load_word): Call SIM_CORE_SIGNAL hook on error.
1963 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1964 starting. For exception dispatching, pass PC instead of NULL_CIA.
1965 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1966 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1967 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1968 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1969 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1970 * mips.igen (*): Replace memory-related SignalException* calls
1971 with references to SIM_CORE_SIGNAL hook.
72f4393d 1972
c906108c
SS		 1973 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1974 fix.
1975 * sim-main.c (*): Minor warning cleanups.
72f4393d 1976
c906108c
SS		 19771998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1978
1979 * m16.igen (DADDIU5): Correct type-o.
1980
1981Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1982
1983 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1984 variables.
1985
1986Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1987
1988 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1989 to include path.
1990 (interp.o): Add dependency on itable.h
1991 (oengine.c, gencode): Delete remaining references.
1992 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1993
c906108c 19941998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1995
c906108c
SS		 1996 * vr4run.c: New.
1997 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1998 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1999 tmp-run-hack) : New.
2000 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2001 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2002 Drop the "64" qualifier to get the HACK generator working.
2003 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2004 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2005 qualifier to get the hack generator working.
2006 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2007 (DSLL): Use do_dsll.
2008 (DSLLV): Use do_dsllv.
2009 (DSRA): Use do_dsra.
2010 (DSRL): Use do_dsrl.
2011 (DSRLV): Use do_dsrlv.
2012 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2013 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2014 get the HACK generator working.
2015 (MACC) Rename to get the HACK generator working.
2016 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2017
c906108c
SS		 20181998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2019
2020 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2021 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2022
c906108c
SS		 20231998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2024
2025 * mips/interp.c (DEBUG): Cleanups.
2026
20271998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2028
2029 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2030 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2031
c906108c
SS		 20321998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2033
2034 * interp.c (sim_close): Uninstall modules.
2035
2036Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2037
2038 * sim-main.h, interp.c (sim_monitor): Change to global
2039 function.
2040
2041Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * configure.in (vr4100): Only include vr4100 instructions in
2044 simulator.
2045 * configure: Re-generate.
2046 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2047
2048Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2049
2050 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2051 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2052 true alternative.
2053
2054 * configure.in (sim_default_gen, sim_use_gen): Replace with
2055 sim_gen.
2056 (--enable-sim-igen): Delete config option. Always using IGEN.
2057 * configure: Re-generate.
72f4393d 2058
c906108c
SS		 2059 * Makefile.in (gencode): Kill, kill, kill.
2060 * gencode.c: Ditto.
72f4393d 2061
c906108c
SS		 2062Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2063
2064 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2065 bit mips16 igen simulator.
2066 * configure: Re-generate.
2067
2068 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2069 as part of vr4100 ISA.
2070 * vr.igen: Mark all instructions as 64 bit only.
2071
2072Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073
2074 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2075 Pacify GCC.
2076
2077Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2080 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2081 * configure: Re-generate.
2082
2083 * m16.igen (BREAK): Define breakpoint instruction.
2084 (JALX32): Mark instruction as mips16 and not r3900.
2085 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2086
2087 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2088
2089Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2092 insn as a debug breakpoint.
2093
2094 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2095 pending.slot_size.
2096 (PENDING_SCHED): Clean up trace statement.
2097 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2098 (PENDING_FILL): Delay write by only one cycle.
2099 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2100
2101 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2102 of pending writes.
2103 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2104 32 & 64.
2105 (pending_tick): Move incrementing of index to FOR statement.
2106 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2107
c906108c
SS		 2108 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2109 build simulator.
2110 * configure: Re-generate.
72f4393d 2111
c906108c
SS		 2112 * interp.c (sim_engine_run OLD): Delete explicit call to
2113 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2114
c906108c
SS		 2115Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2116
2117 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2118 interrupt level number to match changed SignalExceptionInterrupt
2119 macro.
2120
2121Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2122
2123 * interp.c: #include "itable.h" if WITH_IGEN.
2124 (get_insn_name): New function.
2125 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2126 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2127
2128Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2129
2130 * configure: Rebuilt to inhale new common/aclocal.m4.
2131
2132Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2133
2134 * dv-tx3904sio.c: Include sim-assert.h.
2135
2136Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2137
2138 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2139 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2140 Reorganize target-specific sim-hardware checks.
2141 * configure: rebuilt.
2142 * interp.c (sim_open): For tx39 target boards, set
2143 OPERATING_ENVIRONMENT, add tx3904sio devices.
2144 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2145 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2146
c906108c
SS		 2147 * dv-tx3904irc.c: Compiler warning clean-up.
2148 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2149 frequent hw-trace messages.
2150
2151Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2152
2153 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2154
2155Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2156
2157 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2158
2159 * vr.igen: New file.
2160 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2161 * mips.igen: Define vr4100 model. Include vr.igen.
2162Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2163
2164 * mips.igen (check_mf_hilo): Correct check.
2165
2166Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2167
2168 * sim-main.h (interrupt_event): Add prototype.
2169
2170 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2171 register_ptr, register_value.
2172 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2173
2174 * sim-main.h (tracefh): Make extern.
2175
2176Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2177
2178 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2179 Reduce unnecessarily high timer event frequency.
c906108c 2180 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2181
c906108c
SS		 2182Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2183
2184 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2185 to allay warnings.
2186 (interrupt_event): Made non-static.
72f4393d 2187
c906108c
SS		 2188 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2189 interchange of configuration values for external vs. internal
2190 clock dividers.
72f4393d 2191
c906108c
SS		 2192Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2193
72f4393d 2194 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2195 simulator-reserved break instructions.
2196 * gencode.c (build_instruction): Ditto.
2197 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2198 reserved instructions now use exception vector, rather
c906108c
SS		 2199 than halting sim.
2200 * sim-main.h: Moved magic constants to here.
2201
2202Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2203
2204 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2205 register upon non-zero interrupt event level, clear upon zero
2206 event value.
2207 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2208 by passing zero event value.
2209 (*_io_{read,write}_buffer): Endianness fixes.
2210 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2211 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2212
2213 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2214 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2215
c906108c
SS		 2216Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2217
72f4393d 2218 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2219 and BigEndianCPU.
2220
2221Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2222
2223 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2224 parts.
2225 * configure: Update.
2226
2227Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2228
2229 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2230 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2231 * configure.in: Include tx3904tmr in hw_device list.
2232 * configure: Rebuilt.
2233 * interp.c (sim_open): Instantiate three timer instances.
2234 Fix address typo of tx3904irc instance.
2235
2236Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2237
2238 * interp.c (signal_exception): SystemCall exception now uses
2239 the exception vector.
2240
2241Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2242
2243 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2244 to allay warnings.
2245
2246Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2247
2248 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2249
2250Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2251
2252 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2253
2254 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2255 sim-main.h. Declare a struct hw_descriptor instead of struct
2256 hw_device_descriptor.
2257
2258Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2261 right bits and then re-align left hand bytes to correct byte
2262 lanes. Fix incorrect computation in do_store_left when loading
2263 bytes from second word.
2264
2265Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2268 * interp.c (sim_open): Only create a device tree when HW is
2269 enabled.
2270
2271 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2272 * interp.c (signal_exception): Ditto.
2273
2274Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2275
2276 * gencode.c: Mark BEGEZALL as LIKELY.
2277
2278Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2279
2280 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2281 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2282
c906108c
SS		 2283Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2284
2285 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2286 modules. Recognize TX39 target with "mips*tx39" pattern.
2287 * configure: Rebuilt.
2288 * sim-main.h (*): Added many macros defining bits in
2289 TX39 control registers.
2290 (SignalInterrupt): Send actual PC instead of NULL.
2291 (SignalNMIReset): New exception type.
2292 * interp.c (board): New variable for future use to identify
2293 a particular board being simulated.
2294 (mips_option_handler,mips_options): Added "--board" option.
2295 (interrupt_event): Send actual PC.
2296 (sim_open): Make memory layout conditional on board setting.
2297 (signal_exception): Initial implementation of hardware interrupt
2298 handling. Accept another break instruction variant for simulator
2299 exit.
2300 (decode_coproc): Implement RFE instruction for TX39.
2301 (mips.igen): Decode RFE instruction as such.
2302 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2303 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2304 bbegin to implement memory map.
2305 * dv-tx3904cpu.c: New file.
2306 * dv-tx3904irc.c: New file.
2307
2308Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2309
2310 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2311
2312Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2313
2314 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2315 with calls to check_div_hilo.
2316
2317Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2318
2319 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2320 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2321 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2322 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2323 with calls to check_mult_hilo.
2324 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2325 with calls to check_div_hilo.
2326
2327Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2330 Document a replacement.
2331
2332Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2333
2334 * interp.c (sim_monitor): Make mon_printf work.
2335
2336Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2337
2338 * sim-main.h (INSN_NAME): New arg `cpu'.
2339
2340Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2341
72f4393d 2342 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2343
2344Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2345
2346 * configure: Regenerated to track ../common/aclocal.m4 changes.
2347 * config.in: Ditto.
2348
2349Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2350
2351 * acconfig.h: New file.
2352 * configure.in: Reverted change of Apr 24; use sinclude again.
2353
2354Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2355
2356 * configure: Regenerated to track ../common/aclocal.m4 changes.
2357 * config.in: Ditto.
2358
2359Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2360
2361 * configure.in: Don't call sinclude.
2362
2363Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2364
2365 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2366
2367Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2368
2369 * mips.igen (ERET): Implement.
2370
2371 * interp.c (decode_coproc): Return sign-extended EPC.
2372
2373 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2374
2375 * interp.c (signal_exception): Do not ignore Trap.
2376 (signal_exception): On TRAP, restart at exception address.
2377 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2378 (signal_exception): Update.
2379 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2380 so that TRAP instructions are caught.
2381
2382Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2383
2384 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2385 contains HI/LO access history.
2386 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2387 (HIACCESS, LOACCESS): Delete, replace with
2388 (HIHISTORY, LOHISTORY): New macros.
2389 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2390
c906108c
SS		 2391 * gencode.c (build_instruction): Do not generate checks for
2392 correct HI/LO register usage.
2393
2394 * interp.c (old_engine_run): Delete checks for correct HI/LO
2395 register usage.
2396
2397 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2398 check_mf_cycles): New functions.
2399 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2400 do_divu, domultx, do_mult, do_multu): Use.
2401
2402 * tx.igen ("madd", "maddu"): Use.
72f4393d 2403
c906108c
SS		 2404Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * mips.igen (DSRAV): Use function do_dsrav.
2407 (SRAV): Use new function do_srav.
2408
2409 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2410 (B): Sign extend 11 bit immediate.
2411 (EXT-B*): Shift 16 bit immediate left by 1.
2412 (ADDIU*): Don't sign extend immediate value.
2413
2414Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2415
2416 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2417
2418 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2419 functions.
2420
2421 * mips.igen (delayslot32, nullify_next_insn): New functions.
2422 (m16.igen): Always include.
2423 (do_*): Add more tracing.
2424
2425 * m16.igen (delayslot16): Add NIA argument, could be called by a
2426 32 bit MIPS16 instruction.
72f4393d 2427
c906108c
SS		 2428 * interp.c (ifetch16): Move function from here.
2429 * sim-main.c (ifetch16): To here.
72f4393d 2430
c906108c
SS		 2431 * sim-main.c (ifetch16, ifetch32): Update to match current
2432 implementations of LH, LW.
2433 (signal_exception): Don't print out incorrect hex value of illegal
2434 instruction.
2435
2436Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2439 instruction.
2440
2441 * m16.igen: Implement MIPS16 instructions.
72f4393d 2442
c906108c
SS		 2443 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2444 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2445 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2446 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2447 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2448 bodies of corresponding code from 32 bit insn to these. Also used
2449 by MIPS16 versions of functions.
72f4393d 2450
c906108c
SS		 2451 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2452 (IMEM16): Drop NR argument from macro.
2453
2454Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2455
2456 * Makefile.in (SIM_OBJS): Add sim-main.o.
2457
2458 * sim-main.h (address_translation, load_memory, store_memory,
2459 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2460 as INLINE_SIM_MAIN.
2461 (pr_addr, pr_uword64): Declare.
2462 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2463
c906108c
SS		 2464 * interp.c (address_translation, load_memory, store_memory,
2465 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2466 from here.
2467 * sim-main.c: To here. Fix compilation problems.
72f4393d 2468
c906108c
SS		 2469 * configure.in: Enable inlining.
2470 * configure: Re-config.
2471
2472Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2473
2474 * configure: Regenerated to track ../common/aclocal.m4 changes.
2475
2476Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2477
2478 * mips.igen: Include tx.igen.
2479 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2480 * tx.igen: New file, contains MADD and MADDU.
2481
2482 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2483 the hardwired constant `7'.
2484 (store_memory): Ditto.
2485 (LOADDRMASK): Move definition to sim-main.h.
2486
2487 mips.igen (MTC0): Enable for r3900.
2488 (ADDU): Add trace.
2489
2490 mips.igen (do_load_byte): Delete.
2491 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2492 do_store_right): New functions.
2493 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2494
2495 configure.in: Let the tx39 use igen again.
2496 configure: Update.
72f4393d 2497
c906108c
SS		 2498Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2501 not an address sized quantity. Return zero for cache sizes.
2502
2503Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2504
2505 * mips.igen (r3900): r3900 does not support 64 bit integer
2506 operations.
2507
2508Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2509
2510 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2511 than igen one.
2512 * configure : Rebuild.
72f4393d 2513
c906108c
SS		 2514Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * configure: Regenerated to track ../common/aclocal.m4 changes.
2517
2518Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2521
2522Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2523
2524 * configure: Regenerated to track ../common/aclocal.m4 changes.
2525 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2526
2527Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2528
2529 * configure: Regenerated to track ../common/aclocal.m4 changes.
2530
2531Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2532
2533 * interp.c (Max, Min): Comment out functions. Not yet used.
2534
2535Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * configure: Regenerated to track ../common/aclocal.m4 changes.
2538
2539Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2540
2541 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2542 configurable settings for stand-alone simulator.
72f4393d 2543
c906108c 2544 * configure.in: Added X11 search, just in case.
72f4393d 2545
c906108c
SS		 2546 * configure: Regenerated.
2547
2548Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * interp.c (sim_write, sim_read, load_memory, store_memory):
2551 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2552
2553Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2554
2555 * sim-main.h (GETFCC): Return an unsigned value.
2556
2557Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2560 (DADD): Result destination is RD not RT.
2561
2562Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2563
2564 * sim-main.h (HIACCESS, LOACCESS): Always define.
2565
2566 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2567
2568 * interp.c (sim_info): Delete.
2569
2570Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2571
2572 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2573 (mips_option_handler): New argument `cpu'.
2574 (sim_open): Update call to sim_add_option_table.
2575
2576Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2577
2578 * mips.igen (CxC1): Add tracing.
2579
2580Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2581
2582 * sim-main.h (Max, Min): Declare.
2583
2584 * interp.c (Max, Min): New functions.
2585
2586 * mips.igen (BC1): Add tracing.
72f4393d 2587
c906108c 2588Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2589
c906108c 2590 * interp.c Added memory map for stack in vr4100
72f4393d 2591
c906108c
SS		 2592Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2593
2594 * interp.c (load_memory): Add missing "break"'s.
2595
2596Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2597
2598 * interp.c (sim_store_register, sim_fetch_register): Pass in
2599 length parameter. Return -1.
2600
2601Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2602
2603 * interp.c: Added hardware init hook, fixed warnings.
2604
2605Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2606
2607 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2608
2609Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2610
2611 * interp.c (ifetch16): New function.
2612
2613 * sim-main.h (IMEM32): Rename IMEM.
2614 (IMEM16_IMMED): Define.
2615 (IMEM16): Define.
2616 (DELAY_SLOT): Update.
72f4393d 2617
c906108c 2618 * m16run.c (sim_engine_run): New file.
72f4393d 2619
c906108c
SS		 2620 * m16.igen: All instructions except LB.
2621 (LB): Call do_load_byte.
2622 * mips.igen (do_load_byte): New function.
2623 (LB): Call do_load_byte.
2624
2625 * mips.igen: Move spec for insn bit size and high bit from here.
2626 * Makefile.in (tmp-igen, tmp-m16): To here.
2627
2628 * m16.dc: New file, decode mips16 instructions.
2629
2630 * Makefile.in (SIM_NO_ALL): Define.
2631 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2632
2633Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2634
2635 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2636 point unit to 32 bit registers.
2637 * configure: Re-generate.
2638
2639Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2640
2641 * configure.in (sim_use_gen): Make IGEN the default simulator
2642 generator for generic 32 and 64 bit mips targets.
2643 * configure: Re-generate.
2644
2645Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2646
2647 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2648 bitsize.
2649
2650 * interp.c (sim_fetch_register, sim_store_register): Read/write
2651 FGR from correct location.
2652 (sim_open): Set size of FGR's according to
2653 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2654
c906108c
SS		 2655 * sim-main.h (FGR): Store floating point registers in a separate
2656 array.
2657
2658Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2659
2660 * configure: Regenerated to track ../common/aclocal.m4 changes.
2661
2662Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2663
2664 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2665
2666 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2667
2668 * interp.c (pending_tick): New function. Deliver pending writes.
2669
2670 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2671 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2672 it can handle mixed sized quantites and single bits.
72f4393d 2673
c906108c
SS		 2674Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * interp.c (oengine.h): Do not include when building with IGEN.
2677 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2678 (sim_info): Ditto for PROCESSOR_64BIT.
2679 (sim_monitor): Replace ut_reg with unsigned_word.
2680 (*): Ditto for t_reg.
2681 (LOADDRMASK): Define.
2682 (sim_open): Remove defunct check that host FP is IEEE compliant,
2683 using software to emulate floating point.
2684 (value_fpr, ...): Always compile, was conditional on HASFPU.
2685
2686Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2687
2688 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2689 size.
2690
2691 * interp.c (SD, CPU): Define.
2692 (mips_option_handler): Set flags in each CPU.
2693 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2694 (sim_close): Do not clear STATE, deleted anyway.
2695 (sim_write, sim_read): Assume CPU zero's vm should be used for
2696 data transfers.
2697 (sim_create_inferior): Set the PC for all processors.
2698 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2699 argument.
2700 (mips16_entry): Pass correct nr of args to store_word, load_word.
2701 (ColdReset): Cold reset all cpu's.
2702 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2703 (sim_monitor, load_memory, store_memory, signal_exception): Use
2704 `CPU' instead of STATE_CPU.
2705
2706
2707 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2708 SD or CPU_.
72f4393d 2709
c906108c
SS		 2710 * sim-main.h (signal_exception): Add sim_cpu arg.
2711 (SignalException*): Pass both SD and CPU to signal_exception.
2712 * interp.c (signal_exception): Update.
72f4393d 2713
c906108c
SS		 2714 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2715 Ditto
2716 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2717 address_translation): Ditto
2718 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2719
c906108c
SS		 2720Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2721
2722 * configure: Regenerated to track ../common/aclocal.m4 changes.
2723
2724Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2727
72f4393d 2728 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2729
2730 * sim-main.h (CPU_CIA): Delete.
2731 (SET_CIA, GET_CIA): Define
2732
2733Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2736 regiser.
2737
2738 * configure.in (default_endian): Configure a big-endian simulator
2739 by default.
2740 * configure: Re-generate.
72f4393d 2741
c906108c
SS		 2742Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2743
2744 * configure: Regenerated to track ../common/aclocal.m4 changes.
2745
2746Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2747
2748 * interp.c (sim_monitor): Handle Densan monitor outbyte
2749 and inbyte functions.
2750
27511997-12-29 Felix Lee <flee@cygnus.com>
2752
2753 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2754
2755Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2756
2757 * Makefile.in (tmp-igen): Arrange for $zero to always be
2758 reset to zero after every instruction.
2759
2760Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2761
2762 * configure: Regenerated to track ../common/aclocal.m4 changes.
2763 * config.in: Ditto.
2764
2765Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2766
2767 * mips.igen (MSUB): Fix to work like MADD.
2768 * gencode.c (MSUB): Similarly.
2769
2770Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2771
2772 * configure: Regenerated to track ../common/aclocal.m4 changes.
2773
2774Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775
2776 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2777
2778Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * sim-main.h (sim-fpu.h): Include.
2781
2782 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2783 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2784 using host independant sim_fpu module.
2785
2786Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2787
2788 * interp.c (signal_exception): Report internal errors with SIGABRT
2789 not SIGQUIT.
2790
2791 * sim-main.h (C0_CONFIG): New register.
2792 (signal.h): No longer include.
2793
2794 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2795
2796Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2797
2798 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2799
2800Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801
2802 * mips.igen: Tag vr5000 instructions.
2803 (ANDI): Was missing mipsIV model, fix assembler syntax.
2804 (do_c_cond_fmt): New function.
2805 (C.cond.fmt): Handle mips I-III which do not support CC field
2806 separatly.
2807 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2808 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2809 in IV3.2 spec.
2810 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2811 vr5000 which saves LO in a GPR separatly.
72f4393d 2812
c906108c
SS		 2813 * configure.in (enable-sim-igen): For vr5000, select vr5000
2814 specific instructions.
2815 * configure: Re-generate.
72f4393d 2816
c906108c
SS		 2817Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2818
2819 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2820
2821 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2822 fmt_uninterpreted_64 bit cases to switch. Convert to
2823 fmt_formatted,
2824
2825 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2826
2827 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2828 as specified in IV3.2 spec.
2829 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2830
2831Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2832
2833 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2834 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2835 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2836 PENDING_FILL versions of instructions. Simplify.
2837 (X): New function.
2838 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2839 instructions.
2840 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2841 a signed value.
2842 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2843
c906108c
SS		 2844 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2845 global.
2846 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2847
2848Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2849
2850 * gencode.c (build_mips16_operands): Replace IPC with cia.
2851
2852 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2853 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2854 IPC to `cia'.
2855 (UndefinedResult): Replace function with macro/function
2856 combination.
2857 (sim_engine_run): Don't save PC in IPC.
2858
2859 * sim-main.h (IPC): Delete.
2860
2861
2862 * interp.c (signal_exception, store_word, load_word,
2863 address_translation, load_memory, store_memory, cache_op,
2864 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2865 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2866 current instruction address - cia - argument.
2867 (sim_read, sim_write): Call address_translation directly.
2868 (sim_engine_run): Rename variable vaddr to cia.
2869 (signal_exception): Pass cia to sim_monitor
72f4393d 2870
c906108c
SS		 2871 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2872 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2873 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2874
2875 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2876 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2877 SIM_ASSERT.
72f4393d 2878
c906108c
SS		 2879 * interp.c (signal_exception): Pass restart address to
2880 sim_engine_restart.
2881
2882 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2883 idecode.o): Add dependency.
2884
2885 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2886 Delete definitions
2887 (DELAY_SLOT): Update NIA not PC with branch address.
2888 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2889
2890 * mips.igen: Use CIA not PC in branch calculations.
2891 (illegal): Call SignalException.
2892 (BEQ, ADDIU): Fix assembler.
2893
2894Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2895
2896 * m16.igen (JALX): Was missing.
2897
2898 * configure.in (enable-sim-igen): New configuration option.
2899 * configure: Re-generate.
72f4393d 2900
c906108c
SS		 2901 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2902
2903 * interp.c (load_memory, store_memory): Delete parameter RAW.
2904 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2905 bypassing {load,store}_memory.
2906
2907 * sim-main.h (ByteSwapMem): Delete definition.
2908
2909 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2910
2911 * interp.c (sim_do_command, sim_commands): Delete mips specific
2912 commands. Handled by module sim-options.
72f4393d 2913
c906108c
SS		 2914 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2915 (WITH_MODULO_MEMORY): Define.
2916
2917 * interp.c (sim_info): Delete code printing memory size.
2918
2919 * interp.c (mips_size): Nee sim_size, delete function.
2920 (power2): Delete.
2921 (monitor, monitor_base, monitor_size): Delete global variables.
2922 (sim_open, sim_close): Delete code creating monitor and other
2923 memory regions. Use sim-memopts module, via sim_do_commandf, to
2924 manage memory regions.
2925 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2926
c906108c
SS		 2927 * interp.c (address_translation): Delete all memory map code
2928 except line forcing 32 bit addresses.
2929
2930Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2933 trace options.
2934
2935 * interp.c (logfh, logfile): Delete globals.
2936 (sim_open, sim_close): Delete code opening & closing log file.
2937 (mips_option_handler): Delete -l and -n options.
2938 (OPTION mips_options): Ditto.
2939
2940 * interp.c (OPTION mips_options): Rename option trace to dinero.
2941 (mips_option_handler): Update.
2942
2943Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2944
2945 * interp.c (fetch_str): New function.
2946 (sim_monitor): Rewrite using sim_read & sim_write.
2947 (sim_open): Check magic number.
2948 (sim_open): Write monitor vectors into memory using sim_write.
2949 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2950 (sim_read, sim_write): Simplify - transfer data one byte at a
2951 time.
2952 (load_memory, store_memory): Clarify meaning of parameter RAW.
2953
2954 * sim-main.h (isHOST): Defete definition.
2955 (isTARGET): Mark as depreciated.
2956 (address_translation): Delete parameter HOST.
2957
2958 * interp.c (address_translation): Delete parameter HOST.
2959
2960Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2961
72f4393d 2962 * mips.igen:
c906108c
SS		 2963
2964 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2965 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2966
2967Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2968
2969 * mips.igen: Add model filter field to records.
2970
2971Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2972
2973 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2974
c906108c
SS		 2975 interp.c (sim_engine_run): Do not compile function sim_engine_run
2976 when WITH_IGEN == 1.
2977
2978 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2979 target architecture.
2980
2981 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2982 igen. Replace with configuration variables sim_igen_flags /
2983 sim_m16_flags.
2984
2985 * m16.igen: New file. Copy mips16 insns here.
2986 * mips.igen: From here.
2987
2988Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2989
2990 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2991 to top.
2992 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2993
2994Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2995
2996 * gencode.c (build_instruction): Follow sim_write's lead in using
2997 BigEndianMem instead of !ByteSwapMem.
2998
2999Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3000
3001 * configure.in (sim_gen): Dependent on target, select type of
3002 generator. Always select old style generator.
3003
3004 configure: Re-generate.
3005
3006 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3007 targets.
3008 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3009 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3010 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3011 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3012 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3013
c906108c
SS		 3014Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3015
3016 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3017
3018 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3019 CURRENT_FLOATING_POINT instead.
3020
3021 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3022 (address_translation): Raise exception InstructionFetch when
3023 translation fails and isINSTRUCTION.
72f4393d 3024
c906108c
SS		 3025 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3026 sim_engine_run): Change type of of vaddr and paddr to
3027 address_word.
3028 (address_translation, prefetch, load_memory, store_memory,
3029 cache_op): Change type of vAddr and pAddr to address_word.
3030
3031 * gencode.c (build_instruction): Change type of vaddr and paddr to
3032 address_word.
3033
3034Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035
3036 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3037 macro to obtain result of ALU op.
3038
3039Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * interp.c (sim_info): Call profile_print.
3042
3043Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3046
3047 * sim-main.h (WITH_PROFILE): Do not define, defined in
3048 common/sim-config.h. Use sim-profile module.
3049 (simPROFILE): Delete defintion.
3050
3051 * interp.c (PROFILE): Delete definition.
3052 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3053 (sim_close): Delete code writing profile histogram.
3054 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3055 Delete.
3056 (sim_engine_run): Delete code profiling the PC.
3057
3058Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3059
3060 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3061
3062 * interp.c (sim_monitor): Make register pointers of type
3063 unsigned_word*.
3064
3065 * sim-main.h: Make registers of type unsigned_word not
3066 signed_word.
3067
3068Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * interp.c (sync_operation): Rename from SyncOperation, make
3071 global, add SD argument.
3072 (prefetch): Rename from Prefetch, make global, add SD argument.
3073 (decode_coproc): Make global.
3074
3075 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3076
3077 * gencode.c (build_instruction): Generate DecodeCoproc not
3078 decode_coproc calls.
3079
3080 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3081 (SizeFGR): Move to sim-main.h
3082 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3083 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3084 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3085 sim-main.h.
3086 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3087 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3088 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3089 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3090 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3091 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3092
c906108c
SS		 3093 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3094 exception.
3095 (sim-alu.h): Include.
3096 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3097 (sim_cia): Typedef to instruction_address.
72f4393d 3098
c906108c
SS		 3099Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3100
3101 * Makefile.in (interp.o): Rename generated file engine.c to
3102 oengine.c.
72f4393d 3103
c906108c 3104 * interp.c: Update.
72f4393d 3105
c906108c
SS		 3106Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3109
c906108c
SS		 3110Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3111
3112 * gencode.c (build_instruction): For "FPSQRT", output correct
3113 number of arguments to Recip.
72f4393d 3114
c906108c
SS		 3115Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3116
3117 * Makefile.in (interp.o): Depends on sim-main.h
3118
3119 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3120
3121 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3122 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3123 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3124 STATE, DSSTATE): Define
3125 (GPR, FGRIDX, ..): Define.
3126
3127 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3128 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3129 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3130
c906108c 3131 * interp.c: Update names to match defines from sim-main.h
72f4393d 3132
c906108c
SS		 3133Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3134
3135 * interp.c (sim_monitor): Add SD argument.
3136 (sim_warning): Delete. Replace calls with calls to
3137 sim_io_eprintf.
3138 (sim_error): Delete. Replace calls with sim_io_error.
3139 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3140 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3141 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3142 argument.
3143 (mips_size): Rename from sim_size. Add SD argument.
3144
3145 * interp.c (simulator): Delete global variable.
3146 (callback): Delete global variable.
3147 (mips_option_handler, sim_open, sim_write, sim_read,
3148 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3149 sim_size,sim_monitor): Use sim_io_* not callback->*.
3150 (sim_open): ZALLOC simulator struct.
3151 (PROFILE): Do not define.
3152
3153Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3154
3155 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3156 support.h with corresponding code.
3157
3158 * sim-main.h (word64, uword64), support.h: Move definition to
3159 sim-main.h.
3160 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3161
3162 * support.h: Delete
3163 * Makefile.in: Update dependencies
3164 * interp.c: Do not include.
72f4393d 3165
c906108c
SS		 3166Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3167
3168 * interp.c (address_translation, load_memory, store_memory,
3169 cache_op): Rename to from AddressTranslation et.al., make global,
3170 add SD argument
72f4393d 3171
c906108c
SS		 3172 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3173 CacheOp): Define.
72f4393d 3174
c906108c
SS		 3175 * interp.c (SignalException): Rename to signal_exception, make
3176 global.
3177
3178 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3179
c906108c
SS		 3180 * sim-main.h (SignalException, SignalExceptionInterrupt,
3181 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3182 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3183 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3184 Define.
72f4393d 3185
c906108c 3186 * interp.c, support.h: Use.
72f4393d 3187
c906108c
SS		 3188Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3191 to value_fpr / store_fpr. Add SD argument.
3192 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3193 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3194
3195 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3196
c906108c
SS		 3197Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3198
3199 * interp.c (sim_engine_run): Check consistency between configure
3200 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3201 and HASFPU.
3202
3203 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3204 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3205 (mips_endian): Configure WITH_TARGET_ENDIAN.
3206 * configure: Update.
3207
3208Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3209
3210 * configure: Regenerated to track ../common/aclocal.m4 changes.
3211
3212Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3213
3214 * configure: Regenerated.
3215
3216Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3217
3218 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3219
3220Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3221
3222 * gencode.c (print_igen_insn_models): Assume certain architectures
3223 include all mips* instructions.
3224 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3225 instruction.
3226
3227 * Makefile.in (tmp.igen): Add target. Generate igen input from
3228 gencode file.
3229
3230 * gencode.c (FEATURE_IGEN): Define.
3231 (main): Add --igen option. Generate output in igen format.
3232 (process_instructions): Format output according to igen option.
3233 (print_igen_insn_format): New function.
3234 (print_igen_insn_models): New function.
3235 (process_instructions): Only issue warnings and ignore
3236 instructions when no FEATURE_IGEN.
3237
3238Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3239
3240 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3241 MIPS targets.
3242
3243Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3244
3245 * configure: Regenerated to track ../common/aclocal.m4 changes.
3246
3247Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3248
3249 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3250 SIM_RESERVED_BITS): Delete, moved to common.
3251 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3252
c906108c
SS		 3253Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3254
3255 * configure.in: Configure non-strict memory alignment.
3256 * configure: Regenerated to track ../common/aclocal.m4 changes.
3257
3258Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3259
3260 * configure: Regenerated to track ../common/aclocal.m4 changes.
3261
3262Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3263
3264 * gencode.c (SDBBP,DERET): Added (3900) insns.
3265 (RFE): Turn on for 3900.
3266 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3267 (dsstate): Made global.
3268 (SUBTARGET_R3900): Added.
3269 (CANCELDELAYSLOT): New.
3270 (SignalException): Ignore SystemCall rather than ignore and
3271 terminate. Add DebugBreakPoint handling.
3272 (decode_coproc): New insns RFE, DERET; and new registers Debug
3273 and DEPC protected by SUBTARGET_R3900.
3274 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3275 bits explicitly.
3276 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3277 * configure: Update.
c906108c
SS		 3278
3279Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3280
3281 * gencode.c: Add r3900 (tx39).
72f4393d 3282
c906108c
SS		 3283
3284Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3285
3286 * gencode.c (build_instruction): Don't need to subtract 4 for
3287 JALR, just 2.
3288
3289Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3290
3291 * interp.c: Correct some HASFPU problems.
3292
3293Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3294
3295 * configure: Regenerated to track ../common/aclocal.m4 changes.
3296
3297Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3298
3299 * interp.c (mips_options): Fix samples option short form, should
3300 be `x'.
3301
3302Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3303
3304 * interp.c (sim_info): Enable info code. Was just returning.
3305
3306Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3307
3308 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3309 MFC0.
3310
3311Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3312
3313 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3314 constants.
3315 (build_instruction): Ditto for LL.
3316
3317Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3318
3319 * configure: Regenerated to track ../common/aclocal.m4 changes.
3320
3321Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3322
3323 * configure: Regenerated to track ../common/aclocal.m4 changes.
3324 * config.in: Ditto.
3325
3326Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3327
3328 * interp.c (sim_open): Add call to sim_analyze_program, update
3329 call to sim_config.
3330
3331Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3332
3333 * interp.c (sim_kill): Delete.
3334 (sim_create_inferior): Add ABFD argument. Set PC from same.
3335 (sim_load): Move code initializing trap handlers from here.
3336 (sim_open): To here.
3337 (sim_load): Delete, use sim-hload.c.
3338
3339 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3340
3341Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3342
3343 * configure: Regenerated to track ../common/aclocal.m4 changes.
3344 * config.in: Ditto.
3345
3346Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3347
3348 * interp.c (sim_open): Add ABFD argument.
3349 (sim_load): Move call to sim_config from here.
3350 (sim_open): To here. Check return status.
3351
3352Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3353
c906108c
SS		 3354 * gencode.c (build_instruction): Two arg MADD should
3355 not assign result to $0.
72f4393d 3356
c906108c
SS		 3357Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3358
3359 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3360 * sim/mips/configure.in: Regenerate.
3361
3362Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3363
3364 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3365 signed8, unsigned8 et.al. types.
3366
3367 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3368 hosts when selecting subreg.
3369
3370Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3371
3372 * interp.c (sim_engine_run): Reset the ZERO register to zero
3373 regardless of FEATURE_WARN_ZERO.
3374 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3375
3376Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3379 (SignalException): For BreakPoints ignore any mode bits and just
3380 save the PC.
3381 (SignalException): Always set the CAUSE register.
3382
3383Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3384
3385 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3386 exception has been taken.
3387
3388 * interp.c: Implement the ERET and mt/f sr instructions.
3389
3390Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3391
3392 * interp.c (SignalException): Don't bother restarting an
3393 interrupt.
3394
3395Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3396
3397 * interp.c (SignalException): Really take an interrupt.
3398 (interrupt_event): Only deliver interrupts when enabled.
3399
3400Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * interp.c (sim_info): Only print info when verbose.
3403 (sim_info) Use sim_io_printf for output.
72f4393d 3404
c906108c
SS		 3405Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3408 mips architectures.
3409
3410Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3411
3412 * interp.c (sim_do_command): Check for common commands if a
3413 simulator specific command fails.
3414
3415Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3416
3417 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3418 and simBE when DEBUG is defined.
3419
3420Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3421
3422 * interp.c (interrupt_event): New function. Pass exception event
3423 onto exception handler.
3424
3425 * configure.in: Check for stdlib.h.
3426 * configure: Regenerate.
3427
3428 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3429 variable declaration.
3430 (build_instruction): Initialize memval1.
3431 (build_instruction): Add UNUSED attribute to byte, bigend,
3432 reverse.
3433 (build_operands): Ditto.
3434
3435 * interp.c: Fix GCC warnings.
3436 (sim_get_quit_code): Delete.
3437
3438 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3439 * Makefile.in: Ditto.
3440 * configure: Re-generate.
72f4393d 3441
c906108c
SS		 3442 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3443
3444Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3445
3446 * interp.c (mips_option_handler): New function parse argumes using
3447 sim-options.
3448 (myname): Replace with STATE_MY_NAME.
3449 (sim_open): Delete check for host endianness - performed by
3450 sim_config.
3451 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3452 (sim_open): Move much of the initialization from here.
3453 (sim_load): To here. After the image has been loaded and
3454 endianness set.
3455 (sim_open): Move ColdReset from here.
3456 (sim_create_inferior): To here.
3457 (sim_open): Make FP check less dependant on host endianness.
3458
3459 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3460 run.
3461 * interp.c (sim_set_callbacks): Delete.
3462
3463 * interp.c (membank, membank_base, membank_size): Replace with
3464 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3465 (sim_open): Remove call to callback->init. gdb/run do this.
3466
3467 * interp.c: Update
3468
3469 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3470
3471 * interp.c (big_endian_p): Delete, replaced by
3472 current_target_byte_order.
3473
3474Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3475
3476 * interp.c (host_read_long, host_read_word, host_swap_word,
3477 host_swap_long): Delete. Using common sim-endian.
3478 (sim_fetch_register, sim_store_register): Use H2T.
3479 (pipeline_ticks): Delete. Handled by sim-events.
3480 (sim_info): Update.
3481 (sim_engine_run): Update.
3482
3483Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3484
3485 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3486 reason from here.
3487 (SignalException): To here. Signal using sim_engine_halt.
3488 (sim_stop_reason): Delete, moved to common.
72f4393d 3489
c906108c
SS		 3490Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3491
3492 * interp.c (sim_open): Add callback argument.
3493 (sim_set_callbacks): Delete SIM_DESC argument.
3494 (sim_size): Ditto.
3495
3496Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3497
3498 * Makefile.in (SIM_OBJS): Add common modules.
3499
3500 * interp.c (sim_set_callbacks): Also set SD callback.
3501 (set_endianness, xfer_*, swap_*): Delete.
3502 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3503 Change to functions using sim-endian macros.
3504 (control_c, sim_stop): Delete, use common version.
3505 (simulate): Convert into.
3506 (sim_engine_run): This function.
3507 (sim_resume): Delete.
72f4393d 3508
c906108c
SS		 3509 * interp.c (simulation): New variable - the simulator object.
3510 (sim_kind): Delete global - merged into simulation.
3511 (sim_load): Cleanup. Move PC assignment from here.
3512 (sim_create_inferior): To here.
3513
3514 * sim-main.h: New file.
3515 * interp.c (sim-main.h): Include.
72f4393d 3516
c906108c
SS		 3517Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3518
3519 * configure: Regenerated to track ../common/aclocal.m4 changes.
3520
3521Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3522
3523 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3524
3525Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3526
72f4393d
L		 3527 * gencode.c (build_instruction): DIV instructions: check
3528 for division by zero and integer overflow before using
c906108c
SS		 3529 host's division operation.
3530
3531Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3532
3533 * Makefile.in (SIM_OBJS): Add sim-load.o.
3534 * interp.c: #include bfd.h.
3535 (target_byte_order): Delete.
3536 (sim_kind, myname, big_endian_p): New static locals.
3537 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3538 after argument parsing. Recognize -E arg, set endianness accordingly.
3539 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3540 load file into simulator. Set PC from bfd.
3541 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3542 (set_endianness): Use big_endian_p instead of target_byte_order.
3543
3544Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3545
3546 * interp.c (sim_size): Delete prototype - conflicts with
3547 definition in remote-sim.h. Correct definition.
3548
3549Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3550
3551 * configure: Regenerated to track ../common/aclocal.m4 changes.
3552 * config.in: Ditto.
3553
3554Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3555
3556 * interp.c (sim_open): New arg `kind'.
3557
3558 * configure: Regenerated to track ../common/aclocal.m4 changes.
3559
3560Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3561
3562 * configure: Regenerated to track ../common/aclocal.m4 changes.
3563
3564Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3565
3566 * interp.c (sim_open): Set optind to 0 before calling getopt.
3567
3568Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3569
3570 * configure: Regenerated to track ../common/aclocal.m4 changes.
3571
3572Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3573
3574 * interp.c : Replace uses of pr_addr with pr_uword64
3575 where the bit length is always 64 independent of SIM_ADDR.
3576 (pr_uword64) : added.
3577
3578Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3579
3580 * configure: Re-generate.
3581
3582Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3583
3584 * configure: Regenerate to track ../common/aclocal.m4 changes.
3585
3586Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3587
3588 * interp.c (sim_open): New SIM_DESC result. Argument is now
3589 in argv form.
3590 (other sim_*): New SIM_DESC argument.
3591
3592Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3593
3594 * interp.c: Fix printing of addresses for non-64-bit targets.
3595 (pr_addr): Add function to print address based on size.
3596
3597Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3598
3599 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3600
3601Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3602
3603 * gencode.c (build_mips16_operands): Correct computation of base
3604 address for extended PC relative instruction.
3605
3606Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3607
3608 * interp.c (mips16_entry): Add support for floating point cases.
3609 (SignalException): Pass floating point cases to mips16_entry.
3610 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3611 registers.
3612 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3613 or fmt_word.
3614 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3615 and then set the state to fmt_uninterpreted.
3616 (COP_SW): Temporarily set the state to fmt_word while calling
3617 ValueFPR.
3618
3619Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3620
3621 * gencode.c (build_instruction): The high order may be set in the
3622 comparison flags at any ISA level, not just ISA 4.
3623
3624Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3625
3626 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3627 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3628 * configure.in: sinclude ../common/aclocal.m4.
3629 * configure: Regenerated.
3630
3631Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3632
3633 * configure: Rebuild after change to aclocal.m4.
3634
3635Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3636
3637 * configure configure.in Makefile.in: Update to new configure
3638 scheme which is more compatible with WinGDB builds.
3639 * configure.in: Improve comment on how to run autoconf.
3640 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3641 * Makefile.in: Use autoconf substitution to install common
3642 makefile fragment.
3643
3644Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3645
3646 * gencode.c (build_instruction): Use BigEndianCPU instead of
3647 ByteSwapMem.
3648
3649Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3650
3651 * interp.c (sim_monitor): Make output to stdout visible in
3652 wingdb's I/O log window.
3653
3654Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3655
3656 * support.h: Undo previous change to SIGTRAP
3657 and SIGQUIT values.
3658
3659Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3660
3661 * interp.c (store_word, load_word): New static functions.
3662 (mips16_entry): New static function.
3663 (SignalException): Look for mips16 entry and exit instructions.
3664 (simulate): Use the correct index when setting fpr_state after
3665 doing a pending move.
3666
3667Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3668
3669 * interp.c: Fix byte-swapping code throughout to work on
3670 both little- and big-endian hosts.
3671
3672Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3673
3674 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3675 with gdb/config/i386/xm-windows.h.
3676
3677Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3678
3679 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3680 that messes up arithmetic shifts.
3681
3682Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3683
3684 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3685 SIGTRAP and SIGQUIT for _WIN32.
3686
3687Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3688
3689 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3690 force a 64 bit multiplication.
3691 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3692 destination register is 0, since that is the default mips16 nop
3693 instruction.
3694
3695Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3696
3697 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3698 (build_endian_shift): Don't check proc64.
3699 (build_instruction): Always set memval to uword64. Cast op2 to
3700 uword64 when shifting it left in memory instructions. Always use
3701 the same code for stores--don't special case proc64.
3702
3703 * gencode.c (build_mips16_operands): Fix base PC value for PC
3704 relative operands.
3705 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3706 jal instruction.
3707 * interp.c (simJALDELAYSLOT): Define.
3708 (JALDELAYSLOT): Define.
3709 (INDELAYSLOT, INJALDELAYSLOT): Define.
3710 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3711
3712Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3713
3714 * interp.c (sim_open): add flush_cache as a PMON routine
3715 (sim_monitor): handle flush_cache by ignoring it
3716
3717Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3718
3719 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3720 BigEndianMem.
3721 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3722 (BigEndianMem): Rename to ByteSwapMem and change sense.
3723 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3724 BigEndianMem references to !ByteSwapMem.
3725 (set_endianness): New function, with prototype.
3726 (sim_open): Call set_endianness.
3727 (sim_info): Use simBE instead of BigEndianMem.
3728 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3729 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3730 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3731 ifdefs, keeping the prototype declaration.
3732 (swap_word): Rewrite correctly.
3733 (ColdReset): Delete references to CONFIG. Delete endianness related
3734 code; moved to set_endianness.
72f4393d 3735
c906108c
SS		 3736Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3737
3738 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3739 * interp.c (CHECKHILO): Define away.
3740 (simSIGINT): New macro.
3741 (membank_size): Increase from 1MB to 2MB.
3742 (control_c): New function.
3743 (sim_resume): Rename parameter signal to signal_number. Add local
3744 variable prev. Call signal before and after simulate.
3745 (sim_stop_reason): Add simSIGINT support.
3746 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3747 functions always.
3748 (sim_warning): Delete call to SignalException. Do call printf_filtered
3749 if logfh is NULL.
3750 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3751 a call to sim_warning.
3752
3753Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3754
3755 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3756 16 bit instructions.
3757
3758Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3759
3760 Add support for mips16 (16 bit MIPS implementation):
3761 * gencode.c (inst_type): Add mips16 instruction encoding types.
3762 (GETDATASIZEINSN): Define.
3763 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3764 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3765 mtlo.
3766 (MIPS16_DECODE): New table, for mips16 instructions.
3767 (bitmap_val): New static function.
3768 (struct mips16_op): Define.
3769 (mips16_op_table): New table, for mips16 operands.
3770 (build_mips16_operands): New static function.
3771 (process_instructions): If PC is odd, decode a mips16
3772 instruction. Break out instruction handling into new
3773 build_instruction function.
3774 (build_instruction): New static function, broken out of
3775 process_instructions. Check modifiers rather than flags for SHIFT
3776 bit count and m[ft]{hi,lo} direction.
3777 (usage): Pass program name to fprintf.
3778 (main): Remove unused variable this_option_optind. Change
3779 ``*loptarg++'' to ``loptarg++''.
3780 (my_strtoul): Parenthesize && within ||.
3781 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3782 (simulate): If PC is odd, fetch a 16 bit instruction, and
3783 increment PC by 2 rather than 4.
3784 * configure.in: Add case for mips16*-*-*.
3785 * configure: Rebuild.
3786
3787Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3788
3789 * interp.c: Allow -t to enable tracing in standalone simulator.
3790 Fix garbage output in trace file and error messages.
3791
3792Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3793
3794 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3795 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3796 * configure.in: Simplify using macros in ../common/aclocal.m4.
3797 * configure: Regenerated.
3798 * tconfig.in: New file.
3799
3800Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3801
3802 * interp.c: Fix bugs in 64-bit port.
3803 Use ansi function declarations for msvc compiler.
3804 Initialize and test file pointer in trace code.
3805 Prevent duplicate definition of LAST_EMED_REGNUM.
3806
3807Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3808
3809 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3810
3811Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3812
3813 * interp.c (SignalException): Check for explicit terminating
3814 breakpoint value.
3815 * gencode.c: Pass instruction value through SignalException()
3816 calls for Trap, Breakpoint and Syscall.
3817
3818Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3819
3820 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3821 only used on those hosts that provide it.
3822 * configure.in: Add sqrt() to list of functions to be checked for.
3823 * config.in: Re-generated.
3824 * configure: Re-generated.
3825
3826Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3827
3828 * gencode.c (process_instructions): Call build_endian_shift when
3829 expanding STORE RIGHT, to fix swr.
3830 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3831 clear the high bits.
3832 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3833 Fix float to int conversions to produce signed values.
3834
3835Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3836
3837 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3838 (process_instructions): Correct handling of nor instruction.
3839 Correct shift count for 32 bit shift instructions. Correct sign
3840 extension for arithmetic shifts to not shift the number of bits in
3841 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3842 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3843 Fix madd.
3844 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3845 It's OK to have a mult follow a mult. What's not OK is to have a
3846 mult follow an mfhi.
3847 (Convert): Comment out incorrect rounding code.
3848
3849Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3850
3851 * interp.c (sim_monitor): Improved monitor printf
3852 simulation. Tidied up simulator warnings, and added "--log" option
3853 for directing warning message output.
3854 * gencode.c: Use sim_warning() rather than WARNING macro.
3855
3856Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3857
3858 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3859 getopt1.o, rather than on gencode.c. Link objects together.
3860 Don't link against -liberty.
3861 (gencode.o, getopt.o, getopt1.o): New targets.
3862 * gencode.c: Include <ctype.h> and "ansidecl.h".
3863 (AND): Undefine after including "ansidecl.h".
3864 (ULONG_MAX): Define if not defined.
3865 (OP_*): Don't define macros; now defined in opcode/mips.h.
3866 (main): Call my_strtoul rather than strtoul.
3867 (my_strtoul): New static function.
3868
3869Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3870
3871 * gencode.c (process_instructions): Generate word64 and uword64
3872 instead of `long long' and `unsigned long long' data types.
3873 * interp.c: #include sysdep.h to get signals, and define default
3874 for SIGBUS.
3875 * (Convert): Work around for Visual-C++ compiler bug with type
3876 conversion.
3877 * support.h: Make things compile under Visual-C++ by using
3878 __int64 instead of `long long'. Change many refs to long long
3879 into word64/uword64 typedefs.
3880
3881Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3882
72f4393d
L		 3883 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3884 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3885 (docdir): Removed.
3886 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3887 (AC_PROG_INSTALL): Added.
c906108c 3888 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3889 * configure: Rebuilt.
3890
c906108c
SS		 3891Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3892
3893 * configure.in: Define @SIMCONF@ depending on mips target.
3894 * configure: Rebuild.
3895 * Makefile.in (run): Add @SIMCONF@ to control simulator
3896 construction.
3897 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3898 * interp.c: Remove some debugging, provide more detailed error
3899 messages, update memory accesses to use LOADDRMASK.
72f4393d 3900
c906108c
SS		 3901Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3902
3903 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3904 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3905 stamp-h.
3906 * configure: Rebuild.
3907 * config.in: New file, generated by autoheader.
3908 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3909 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3910 HAVE_ANINT and HAVE_AINT, as appropriate.
3911 * Makefile.in (run): Use @LIBS@ rather than -lm.
3912 (interp.o): Depend upon config.h.
3913 (Makefile): Just rebuild Makefile.
3914 (clean): Remove stamp-h.
3915 (mostlyclean): Make the same as clean, not as distclean.
3916 (config.h, stamp-h): New targets.
3917
3918Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3919
3920 * interp.c (ColdReset): Fix boolean test. Make all simulator
3921 globals static.
3922
3923Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3924
3925 * interp.c (xfer_direct_word, xfer_direct_long,
3926 swap_direct_word, swap_direct_long, xfer_big_word,
3927 xfer_big_long, xfer_little_word, xfer_little_long,
3928 swap_word,swap_long): Added.
3929 * interp.c (ColdReset): Provide function indirection to
3930 host<->simulated_target transfer routines.
3931 * interp.c (sim_store_register, sim_fetch_register): Updated to
3932 make use of indirected transfer routines.
3933
3934Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3935
3936 * gencode.c (process_instructions): Ensure FP ABS instruction
3937 recognised.
3938 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3939 system call support.
3940
3941Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3942
3943 * interp.c (sim_do_command): Complain if callback structure not
3944 initialised.
3945
3946Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3947
3948 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3949 support for Sun hosts.
3950 * Makefile.in (gencode): Ensure the host compiler and libraries
3951 used for cross-hosted build.
3952
3953Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3954
3955 * interp.c, gencode.c: Some more (TODO) tidying.
3956
3957Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3958
3959 * gencode.c, interp.c: Replaced explicit long long references with
3960 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3961 * support.h (SET64LO, SET64HI): Macros added.
3962
3963Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3964
3965 * configure: Regenerate with autoconf 2.7.
3966
3967Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3968
3969 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3970 * support.h: Remove superfluous "1" from #if.
3971 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3972
3973Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3974
3975 * interp.c (StoreFPR): Control UndefinedResult() call on
3976 WARN_RESULT manifest.
3977
3978Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3979
3980 * gencode.c: Tidied instruction decoding, and added FP instruction
3981 support.
3982
3983 * interp.c: Added dineroIII, and BSD profiling support. Also
3984 run-time FP handling.
3985
3986Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3987
3988 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3989 gencode.c, interp.c, support.h: created.
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