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sim: move default model to the runtime sim state
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d414eb3e
MF		 12021-06-30 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4
36bb57e4
MF		 52021-06-22 Mike Frysinger <vapier@gentoo.org>
6
7 * configure: Regenerate.
8
456ef1c1
MF		 92021-06-21 Mike Frysinger <vapier@gentoo.org>
10
11 * aclocal.m4: Regenerate.
12 * configure: Regenerate.
13
be0387ee
MF		 142021-06-21 Mike Frysinger <vapier@gentoo.org>
15
16 * Makefile.in (SIM_EXTRA_HW_DEVICES): Define.
17 * configure.ac (SIM_AC_OPTION_HARDWARE): Delete call.
18 * configure: Regenerate.
19
3eda63f2
MF		 202021-06-20 Mike Frysinger <vapier@gentoo.org>
21
22 * configure.ac (SIM_AC_COMMON): Delete.
23 * aclocal.m4, configure: Regenerate.
24
d73f39ee
MF		 252021-06-20 Mike Frysinger <vapier@gentoo.org>
26
27 * aclocal.m4: Regenerate.
28 * configure: Regenerate.
29
b5689863
MF		 302021-06-19 Mike Frysinger <vapier@gentoo.org>
31
32 * aclocal.m4: Regenerate.
33 * configure: Regenerate.
34
17a5da80
MF		 352021-06-19 Mike Frysinger <vapier@gentoo.org>
36
37 * configure.ac: Delete AC_PATH_X call.
38 * configure: Regenerate.
39
07490bf8
MF		 402021-06-19 Mike Frysinger <vapier@gentoo.org>
41
42 * configure.ac: Delete AC_CHECK_LIB calls.
43 * configure: Regenerate.
44
47ce766a
MF		 452021-06-18 Mike Frysinger <vapier@gentoo.org>
46
47 * aclocal.m4, configure: Regenerate.
48
982c3a65
MF		 492021-06-18 Mike Frysinger <vapier@gentoo.org>
50
51 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
52 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
53 * configure: Regenerate.
54
1fef66b0
MF		 552021-06-18 Mike Frysinger <vapier@gentoo.org>
56
57 * interp.c: Include sim-signal.h.
58
f9a4d543
MF		 592021-06-17 Mike Frysinger <vapier@gentoo.org>
60
61 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
62 * aclocal.m4, configure: Regenerate.
63
b80d4475
MF		 642021-06-16 Mike Frysinger <vapier@gentoo.org>
65
66 * interp.c (dotrace): Make comment const.
67 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
68
6828a302
MF		 692021-06-16 Mike Frysinger <vapier@gentoo.org>
70
71 * interp.c (sim_monitor): Change ap type to address_word*.
72 (_P, P): New macros. Rewrite dynamic printf logic to use these.
73
df32b446
MF		 742021-06-16 Mike Frysinger <vapier@gentoo.org>
75
76 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
77 unsigned_1.
78
7b2298cb
MF		 792021-06-16 Mike Frysinger <vapier@gentoo.org>
80
81 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
82 register_value to 0.
83
a8a3d907
MF		 842021-06-16 Mike Frysinger <vapier@gentoo.org>
85
86 * configure: Regenerate.
87
dae666c9
MF		 882021-06-16 Mike Frysinger <vapier@gentoo.org>
89
90 * interp.c (sim_open): Change %lx to %x and PRIx macros.
91
52d37d2c
MF		 922021-06-16 Mike Frysinger <vapier@gentoo.org>
93
94 * configure: Regenerate.
95 * config.in: Removed.
96
bcaa61f7
MF		 972021-06-15 Mike Frysinger <vapier@gentoo.org>
98
99 * config.in, configure: Regenerate.
100
ba307cdd
MF		 1012021-06-12 Mike Frysinger <vapier@gentoo.org>
102
103 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
104
dba333c1
MF		 1052021-06-12 Mike Frysinger <vapier@gentoo.org>
106
107 * aclocal.m4, config.in, configure: Regenerate.
108
b15c5d7a
MF		 1092021-06-12 Mike Frysinger <vapier@gentoo.org>
110
111 * configure.ac: Delete call to AC_CHECK_FUNCS.
112 * config.in, configure: Regenerate.
113
a55b92be
MF		 1142021-06-08 Mike Frysinger <vapier@gentoo.org>
115
116 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
117 with $(IGEN).
118
8ea881d9
MF		 1192021-05-29 Mike Frysinger <vapier@gentoo.org>
120
121 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
122
b312488f
FS		 1232021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
124
168671c1
FS		 125 * interp.c (sim_open): Add shadow mappings from 32-bit
126 address space to 64-bit sign-extended address space.
127
1282021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
129
b312488f
FS		 130 * interp.c (sim_create_inferior): Only truncate sign extension
131 bits for 32-bit target models.
132
f4fdd845
MF		 1332021-05-17 Mike Frysinger <vapier@gentoo.org>
134
135 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
136
8ea7241c
MF		 1372021-05-17 Mike Frysinger <vapier@gentoo.org>
138
139 * interp.c (sim_open): Switch to sim_state_alloc_extra.
140 * micromips.igen: Change SD to mips_sim_state.
141 * micromipsrun.c (sim_engine_run): Likewise.
142 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
143 (watch_options_install): Delete.
144 (struct swatch): Delete.
145 (struct sim_state): Delete.
146 (struct mips_sim_state): New struct.
147 (MIPS_SIM_STATE): Define.
148
6df01ab8
MF		 1492021-05-16 Mike Frysinger <vapier@gentoo.org>
150
151 * interp.c: Replace config.h include with defs.h.
152 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
153 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
154 Include defs.h.
155
79633c12
MF		 1562021-05-16 Mike Frysinger <vapier@gentoo.org>
157
158 * config.in, configure: Regenerate.
159
df68e12b
MF		 1602021-05-14 Mike Frysinger <vapier@gentoo.org>
161
162 * interp.c: Update include path.
163
77c0fdb7
MF		 1642021-05-04 Mike Frysinger <vapier@gentoo.org>
165
166 * dv-tx3904sio.c: Include stdlib.h.
167
9b1af85c
MF		 1682021-05-04 Mike Frysinger <vapier@gentoo.org>
169
170 * configure.ac (hw_extra_devices): Inline contents into
171 SIM_AC_OPTION_HARDWARE and delete.
172 * configure: Regenerate.
173
d97ba9c6
MF		 1742021-05-04 Mike Frysinger <vapier@gentoo.org>
175
176 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
177 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
178 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
179 * configure: Regenerate.
180
4df817de
MF		 1812021-05-04 Mike Frysinger <vapier@gentoo.org>
182
183 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
184
aa0fca16
MF		 1852021-05-04 Mike Frysinger <vapier@gentoo.org>
186
187 * configure: Regenerate.
188
adbaa7b8
MF		 1892021-05-01 Mike Frysinger <vapier@gentoo.org>
190
191 * cp1.c (store_fcr): Mark static.
192
fe348617
MF		 1932021-05-01 Mike Frysinger <vapier@gentoo.org>
194
195 * config.in, configure: Regenerate.
196
9d903352
MF		 1972021-04-23 Mike Frysinger <vapier@gentoo.org>
198
199 * configure.ac (hw_enabled): Delete.
200 (SIM_AC_OPTION_HARDWARE): Delete first two args.
201 * configure: Regenerate.
202
19f6a43c
TT		 2032021-04-22 Tom Tromey <tom@tromey.com>
204
205 * configure, config.in: Rebuild.
206
e7d8f1da
TT		 2072021-04-22 Tom Tromey <tom@tromey.com>
208
209 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
210 Remove.
211 (SIM_EXTRA_DEPS): New variable.
212
efd82ac7
TT		 2132021-04-22 Tom Tromey <tom@tromey.com>
214
215 * configure: Rebuild.
216
2662c237
MF		 2172021-04-21 Mike Frysinger <vapier@gentoo.org>
218
219 * aclocal.m4: Regenerate.
220
1f195bc3
SM		 2212021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
222
223 * configure: Regenerate.
224
37e9f182
MF		 2252021-04-18 Mike Frysinger <vapier@gentoo.org>
226
227 * configure: Regenerate.
228
d5a71b11
MF		 2292021-04-12 Mike Frysinger <vapier@gentoo.org>
230
231 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
232
2b8d134b
SM		 2332021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
234
235 * Makefile.in: Set ASAN_OPTIONS when running igen.
236
5c6f091a
FS		 2372021-04-04 Steve Ellcey <sellcey@mips.com>
238 Faraz Shahbazker <fshahbazker@wavecomp.com>
239
240 * interp.c (sim_monitor): Add switch entries for unlink (13),
241 lseek (14), and stat (15).
242
b6b1c790
MF		 2432021-04-02 Mike Frysinger <vapier@gentoo.org>
244
245 * Makefile.in (../igen/igen): Delete rule.
246 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
247
c2783492
MF		 2482021-04-02 Mike Frysinger <vapier@gentoo.org>
249
250 * aclocal.m4, configure: Regenerate.
251
ebe9564b
MF		 2522021-02-28 Mike Frysinger <vapier@gentoo.org>
253
254 * configure: Regenerate.
255
f8069d55
MF		 2562021-02-27 Mike Frysinger <vapier@gentoo.org>
257
258 * Makefile.in (SIM_EXTRA_ALL): Delete.
259 (all): New target.
260
760b3e8b
MF		 2612021-02-21 Mike Frysinger <vapier@gentoo.org>
262
263 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
264 * aclocal.m4, configure: Regenerate.
265
136da8cd
MF		 2662021-02-13 Mike Frysinger <vapier@gentoo.org>
267
268 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
269 * aclocal.m4, configure: Regenerate.
270
4c0d76b9
MF		 2712021-02-06 Mike Frysinger <vapier@gentoo.org>
272
273 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
274
aa09469f
MF		 2752021-02-06 Mike Frysinger <vapier@gentoo.org>
276
277 * configure: Regenerate.
278
d4e3adda
MF		 2792021-01-30 Mike Frysinger <vapier@gentoo.org>
280
281 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
282
68ed2854
MF		 2832021-01-11 Mike Frysinger <vapier@gentoo.org>
284
285 * config.in, configure: Regenerate.
286 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
287 and strings.h include.
288
50df264d
MF		 2892021-01-09 Mike Frysinger <vapier@gentoo.org>
290
291 * configure: Regenerate.
292
bf470982
MF		 2932021-01-09 Mike Frysinger <vapier@gentoo.org>
294
295 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
296 * configure: Regenerate.
297
46f900c0
MF		 2982021-01-08 Mike Frysinger <vapier@gentoo.org>
299
300 * configure: Regenerate.
301
dfb856ba
MF		 3022021-01-04 Mike Frysinger <vapier@gentoo.org>
303
304 * configure: Regenerate.
305
382bc56b
PK		 3062020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
307
308 * sim-main.c: Include <stdlib.h>.
309
ad9675dd
PK		 3102020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
311
312 * cp1.c: Include <stdlib.h>.
313
f693213d
SM		 3142020-07-29 Simon Marchi <simon.marchi@efficios.com>
315
316 * configure: Re-generate.
317
5c887dd5
JB		 3182017-09-06 John Baldwin <jhb@FreeBSD.org>
319
320 * configure: Regenerate.
321
91588b3a
MF		 3222016-11-11 Mike Frysinger <vapier@gentoo.org>
323
6cb2202b 324 PR sim/20808
91588b3a
MF		 325 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
326 and SD to sd.
327
e04659e8
MF		 3282016-11-11 Mike Frysinger <vapier@gentoo.org>
329
6cb2202b 330 PR sim/20809
e04659e8
MF		 331 * mips.igen (check_u64): Enable for `r3900'.
332
1554f758
MF		 3332016-02-05 Mike Frysinger <vapier@gentoo.org>
334
335 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
336 STATE_PROG_BFD (sd).
337 * configure: Regenerate.
338
3d304f48
AB		 3392016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
340 Maciej W. Rozycki <macro@imgtec.com>
341
342 PR sim/19441
343 * micromips.igen (delayslot_micromips): Enable for `micromips32',
344 `micromips64' and `micromipsdsp' only.
345 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
346 (do_micromips_jalr, do_micromips_jal): Likewise.
347 (compute_movep_src_reg): Likewise.
348 (compute_andi16_imm): Likewise.
349 (convert_fmt_micromips): Likewise.
350 (convert_fmt_micromips_cvt_d): Likewise.
351 (convert_fmt_micromips_cvt_s): Likewise.
352 (FMT_MICROMIPS): Likewise.
353 (FMT_MICROMIPS_CVT_D): Likewise.
354 (FMT_MICROMIPS_CVT_S): Likewise.
355
b36d953b
MF		 3562016-01-12 Mike Frysinger <vapier@gentoo.org>
357
358 * interp.c: Include elf-bfd.h.
359 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
360 ELFCLASS32.
361
ce39bd38
MF		 3622016-01-10 Mike Frysinger <vapier@gentoo.org>
363
364 * config.in, configure: Regenerate.
365
99d8e879
MF		 3662016-01-10 Mike Frysinger <vapier@gentoo.org>
367
368 * configure: Regenerate.
369
35656e95
MF		 3702016-01-10 Mike Frysinger <vapier@gentoo.org>
371
372 * configure: Regenerate.
373
16f7876d
MF		 3742016-01-10 Mike Frysinger <vapier@gentoo.org>
375
376 * configure: Regenerate.
377
e19418e0
MF		 3782016-01-10 Mike Frysinger <vapier@gentoo.org>
379
380 * configure: Regenerate.
381
6d90347b
MF		 3822016-01-10 Mike Frysinger <vapier@gentoo.org>
383
384 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
385 * configure: Regenerate.
386
347fe5bb
MF		 3872016-01-10 Mike Frysinger <vapier@gentoo.org>
388
389 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
390 * configure: Regenerate.
391
22be3fbe
MF		 3922016-01-10 Mike Frysinger <vapier@gentoo.org>
393
394 * configure: Regenerate.
395
0dc73ef7
MF		 3962016-01-10 Mike Frysinger <vapier@gentoo.org>
397
398 * configure: Regenerate.
399
936df756
MF		 4002016-01-09 Mike Frysinger <vapier@gentoo.org>
401
402 * config.in, configure: Regenerate.
403
2e3d4f4d
MF		 4042016-01-06 Mike Frysinger <vapier@gentoo.org>
405
406 * interp.c (sim_open): Mark argv const.
407 (sim_create_inferior): Mark argv and env const.
408
9bbf6f91
MF		 4092016-01-04 Mike Frysinger <vapier@gentoo.org>
410
411 * configure: Regenerate.
412
77cf2ef5
MF		 4132016-01-03 Mike Frysinger <vapier@gentoo.org>
414
415 * interp.c (sim_open): Update sim_parse_args comment.
416
0cb8d851
MF		 4172016-01-03 Mike Frysinger <vapier@gentoo.org>
418
419 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
420 * configure: Regenerate.
421
1ac72f06
MF		 4222016-01-02 Mike Frysinger <vapier@gentoo.org>
423
424 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
425 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
426 * configure: Regenerate.
427 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
428
d47f5b30
MF		 4292016-01-02 Mike Frysinger <vapier@gentoo.org>
430
431 * dv-tx3904cpu.c (CPU, SD): Delete.
432
e1211e55
MF		 4332015-12-30 Mike Frysinger <vapier@gentoo.org>
434
435 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
436 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
437 (sim_store_register): Rename to ...
438 (mips_reg_store): ... this. Delete local cpu var.
439 Update sim_io_eprintf calls.
440 (sim_fetch_register): Rename to ...
441 (mips_reg_fetch): ... this. Delete local cpu var.
442 Update sim_io_eprintf calls.
443
5e744ef8
MF		 4442015-12-27 Mike Frysinger <vapier@gentoo.org>
445
446 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
447
1b393626
MF		 4482015-12-26 Mike Frysinger <vapier@gentoo.org>
449
450 * config.in, configure: Regenerate.
451
26f8bf63
MF		 4522015-12-26 Mike Frysinger <vapier@gentoo.org>
453
454 * interp.c (sim_write, sim_read): Delete.
455 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
456 (load_word): Likewise.
457 * micromips.igen (cache): Likewise.
458 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
459 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
460 do_store_left, do_store_right, do_load_double, do_store_double):
461 Likewise.
462 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
463 (do_prefx): Likewise.
464 * sim-main.c (address_translation, prefetch): Delete.
465 (ifetch32, ifetch16): Delete call to AddressTranslation and set
466 paddr=vaddr.
467 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
468 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
469 (LoadMemory, StoreMemory): Delete CCA arg.
470
ef04e371
MF		 4712015-12-24 Mike Frysinger <vapier@gentoo.org>
472
473 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
474 * configure: Regenerated.
475
cb379ede
MF		 4762015-12-24 Mike Frysinger <vapier@gentoo.org>
477
478 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
479 * tconfig.h: Delete.
480
26936211
MF		 4812015-12-24 Mike Frysinger <vapier@gentoo.org>
482
483 * tconfig.h (SIM_HANDLES_LMA): Delete.
484
84e8e361
MF		 4852015-12-24 Mike Frysinger <vapier@gentoo.org>
486
487 * sim-main.h (WITH_WATCHPOINTS): Delete.
488
3cabaf66
MF		 4892015-12-24 Mike Frysinger <vapier@gentoo.org>
490
491 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
492
8abe6c66
MF		 4932015-12-24 Mike Frysinger <vapier@gentoo.org>
494
495 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
496
1d19cae7
DV		 4972015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
498
499 * micromips.igen (process_isa_mode): Fix left shift of negative
500 value.
501
cdf850e9
MF		 5022015-11-17 Mike Frysinger <vapier@gentoo.org>
503
504 * sim-main.h (WITH_MODULO_MEMORY): Delete.
505
797eee42
MF		 5062015-11-15 Mike Frysinger <vapier@gentoo.org>
507
508 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
509
6e4f085c
MF		 5102015-11-14 Mike Frysinger <vapier@gentoo.org>
511
512 * interp.c (sim_close): Rename to ...
513 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
514 sim_io_shutdown.
515 * sim-main.h (mips_sim_close): Declare.
516 (SIM_CLOSE_HOOK): Define.
517
8e394ffc
AB		 5182015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
519 Ali Lown <ali.lown@imgtec.com>
520
521 * Makefile.in (tmp-micromips): New rule.
522 (tmp-mach-multi): Add support for micromips.
523 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
524 that works for both mips64 and micromips64.
525 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
526 micromips32.
527 Add build support for micromips.
528 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
529 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
530 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
531 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
532 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
533 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
534 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
535 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
536 Refactored instruction code to use these functions.
537 * dsp2.igen: Refactored instruction code to use the new functions.
538 * interp.c (decode_coproc): Refactored to work with any instruction
539 encoding.
540 (isa_mode): New variable
541 (RSVD_INSTRUCTION): Changed to 0x00000039.
542 * m16.igen (BREAK16): Refactored instruction to use do_break16.
543 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
544 * micromips.dc: New file.
545 * micromips.igen: New file.
546 * micromips16.dc: New file.
547 * micromipsdsp.igen: New file.
548 * micromipsrun.c: New file.
549 * mips.igen (do_swc1): Changed to work with any instruction encoding.
550 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
551 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
552 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
553 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
554 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
555 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
556 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
557 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
558 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
559 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
560 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
561 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
562 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
563 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
564 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
565 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
566 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
567 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
568 instructions.
569 Refactored instruction code to use these functions.
570 (RSVD): Changed to use new reserved instruction.
571 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
572 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
573 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
574 do_store_double): Added micromips32 and micromips64 models.
575 Added include for micromips.igen and micromipsdsp.igen
576 Add micromips32 and micromips64 models.
577 (DecodeCoproc): Updated to use new macro definition.
578 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
579 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
580 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
581 Refactored instruction code to use these functions.
582 * sim-main.h (CP0_operation): New enum.
583 (DecodeCoproc): Updated macro.
584 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
585 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
586 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
587 ISA_MODE_MICROMIPS): New defines.
588 (sim_state): Add isa_mode field.
589
8d0978fb
MF		 5902015-06-23 Mike Frysinger <vapier@gentoo.org>
591
592 * configure: Regenerate.
593
306f4178
MF		 5942015-06-12 Mike Frysinger <vapier@gentoo.org>
595
596 * configure.ac: Change configure.in to configure.ac.
597 * configure: Regenerate.
598
a3487082
MF		 5992015-06-12 Mike Frysinger <vapier@gentoo.org>
600
601 * configure: Regenerate.
602
29bc024d
MF		 6032015-06-12 Mike Frysinger <vapier@gentoo.org>
604
605 * interp.c [TRACE]: Delete.
606 (TRACE): Change to WITH_TRACE_ANY_P.
607 [!WITH_TRACE_ANY_P] (open_trace): Define.
608 (mips_option_handler, open_trace, sim_close, dotrace):
609 Change defined(TRACE) to WITH_TRACE_ANY_P.
610 (sim_open): Delete TRACE ifdef check.
611 * sim-main.c (load_memory): Delete TRACE ifdef check.
612 (store_memory): Likewise.
613 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
614 [!WITH_TRACE_ANY_P] (dotrace): Define.
615
3ebe2863
MF		 6162015-04-18 Mike Frysinger <vapier@gentoo.org>
617
618 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
619 comments.
620
20bca71d
MF		 6212015-04-18 Mike Frysinger <vapier@gentoo.org>
622
623 * sim-main.h (SIM_CPU): Delete.
624
7e83aa92
MF		 6252015-04-18 Mike Frysinger <vapier@gentoo.org>
626
627 * sim-main.h (sim_cia): Delete.
628
034685f9
MF		 6292015-04-17 Mike Frysinger <vapier@gentoo.org>
630
631 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
632 PU_PC_GET.
633 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
634 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
635 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
636 CIA_SET to CPU_PC_SET.
637 * sim-main.h (CIA_GET, CIA_SET): Delete.
638
78e9aa70
MF		 6392015-04-15 Mike Frysinger <vapier@gentoo.org>
640
641 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
642 * sim-main.h (STATE_CPU): Delete.
643
bf12d44e
MF		 6442015-04-13 Mike Frysinger <vapier@gentoo.org>
645
646 * configure: Regenerate.
647
7bebb329
MF		 6482015-04-13 Mike Frysinger <vapier@gentoo.org>
649
650 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
651 * interp.c (mips_pc_get, mips_pc_set): New functions.
652 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
653 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
654 (sim_pc_get): Delete.
655 * sim-main.h (SIM_CPU): Define.
656 (struct sim_state): Change cpu to an array of pointers.
657 (STATE_CPU): Drop &.
658
8ac57fbd
MF		 6592015-04-13 Mike Frysinger <vapier@gentoo.org>
660
661 * interp.c (mips_option_handler, open_trace, sim_close,
662 sim_write, sim_read, sim_store_register, sim_fetch_register,
663 sim_create_inferior, pr_addr, pr_uword64): Convert old style
664 prototypes.
665 (sim_open): Convert old style prototype. Change casts with
666 sim_write to unsigned char *.
667 (fetch_str): Change null to unsigned char, and change cast to
668 unsigned char *.
669 (sim_monitor): Change c & ch to unsigned char. Change cast to
670 unsigned char *.
671
e787f858
MF		 6722015-04-12 Mike Frysinger <vapier@gentoo.org>
673
674 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
675
122bbfb5
MF		 6762015-04-06 Mike Frysinger <vapier@gentoo.org>
677
678 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
679
0fe84f3f
MF		 6802015-04-01 Mike Frysinger <vapier@gentoo.org>
681
682 * tconfig.h (SIM_HAVE_PROFILE): Delete.
683
aadc9410
MF		 6842015-03-31 Mike Frysinger <vapier@gentoo.org>
685
686 * config.in, configure: Regenerate.
687
05f53ed6
MF		 6882015-03-24 Mike Frysinger <vapier@gentoo.org>
689
690 * interp.c (sim_pc_get): New function.
691
c0931f26
MF		 6922015-03-24 Mike Frysinger <vapier@gentoo.org>
693
694 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
695 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
696
30452bbe
MF		 6972015-03-24 Mike Frysinger <vapier@gentoo.org>
698
699 * configure: Regenerate.
700
64dd13df
MF		 7012015-03-23 Mike Frysinger <vapier@gentoo.org>
702
703 * configure: Regenerate.
704
49cd1634
MF		 7052015-03-23 Mike Frysinger <vapier@gentoo.org>
706
707 * configure: Regenerate.
708 * configure.ac (mips_extra_objs): Delete.
709 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
710 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
711
3649cb06
MF		 7122015-03-23 Mike Frysinger <vapier@gentoo.org>
713
714 * configure: Regenerate.
715 * configure.ac: Delete sim_hw checks for dv-sockser.
716
ae7d0cac
MF		 7172015-03-16 Mike Frysinger <vapier@gentoo.org>
718
719 * config.in, configure: Regenerate.
720 * tconfig.in: Rename file ...
721 * tconfig.h: ... here.
722
8406bb59
MF		 7232015-03-15 Mike Frysinger <vapier@gentoo.org>
724
725 * tconfig.in: Delete includes.
726 [HAVE_DV_SOCKSER]: Delete.
727
465fb143
MF		 7282015-03-14 Mike Frysinger <vapier@gentoo.org>
729
730 * Makefile.in (SIM_RUN_OBJS): Delete.
731
5cddc23a
MF		 7322015-03-14 Mike Frysinger <vapier@gentoo.org>
733
734 * configure.ac (AC_CHECK_HEADERS): Delete.
735 * aclocal.m4, configure: Regenerate.
736
2974be62
AM		 7372014-08-19 Alan Modra <amodra@gmail.com>
738
739 * configure: Regenerate.
740
faa743bb
RM		 7412014-08-15 Roland McGrath <mcgrathr@google.com>
742
743 * configure: Regenerate.
744 * config.in: Regenerate.
745
1a8a700e
MF		 7462014-03-04 Mike Frysinger <vapier@gentoo.org>
747
748 * configure: Regenerate.
749
bf3d9781
AM		 7502013-09-23 Alan Modra <amodra@gmail.com>
751
752 * configure: Regenerate.
753
31e6ad7d
MF		 7542013-06-03 Mike Frysinger <vapier@gentoo.org>
755
756 * aclocal.m4, configure: Regenerate.
757
d3685d60
TT		 7582013-05-10 Freddie Chopin <freddie_chopin@op.pl>
759
760 * configure: Rebuild.
761
1517bd27
MF		 7622013-03-26 Mike Frysinger <vapier@gentoo.org>
763
764 * configure: Regenerate.
765
3be31516
JS		 7662013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
767
768 * configure.ac: Address use of dv-sockser.o.
769 * tconfig.in: Conditionalize use of dv_sockser_install.
770 * configure: Regenerated.
771 * config.in: Regenerated.
772
37cb8f8e
SE		 7732012-10-04 Chao-ying Fu <fu@mips.com>
774 Steve Ellcey <sellcey@mips.com>
775
776 * mips/mips3264r2.igen (rdhwr): New.
777
87c8644f
JS		 7782012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
779
780 * configure.ac: Always link against dv-sockser.o.
781 * configure: Regenerate.
782
5f3ef9d0
JB		 7832012-06-15 Joel Brobecker <brobecker@adacore.com>
784
785 * config.in, configure: Regenerate.
786
a6ff997c
NC		 7872012-05-18 Nick Clifton <nickc@redhat.com>
788
789 PR 14072
790 * interp.c: Include config.h before system header files.
791
2232061b
MF		 7922012-03-24 Mike Frysinger <vapier@gentoo.org>
793
794 * aclocal.m4, config.in, configure: Regenerate.
795
db2e4d67
MF		 7962011-12-03 Mike Frysinger <vapier@gentoo.org>
797
798 * aclocal.m4: New file.
799 * configure: Regenerate.
800
4399a56b
MF		 8012011-10-19 Mike Frysinger <vapier@gentoo.org>
802
803 * configure: Regenerate after common/acinclude.m4 update.
804
9c082ca8
MF		 8052011-10-17 Mike Frysinger <vapier@gentoo.org>
806
807 * configure.ac: Change include to common/acinclude.m4.
808
6ffe910a
MF		 8092011-10-17 Mike Frysinger <vapier@gentoo.org>
810
811 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
812 call. Replace common.m4 include with SIM_AC_COMMON.
813 * configure: Regenerate.
814
31b28250
HPN		 8152011-07-08 Hans-Peter Nilsson <hp@axis.com>
816
3faa01e3
HPN		 817 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
818 $(SIM_EXTRA_DEPS).
819 (tmp-mach-multi): Exit early when igen fails.
31b28250 820
2419798b
MF		 8212011-07-05 Mike Frysinger <vapier@gentoo.org>
822
823 * interp.c (sim_do_command): Delete.
824
d79fe0d6
MF		 8252011-02-14 Mike Frysinger <vapier@gentoo.org>
826
827 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
828 (tx3904sio_fifo_reset): Likewise.
829 * interp.c (sim_monitor): Likewise.
830
5558e7e6
MF		 8312010-04-14 Mike Frysinger <vapier@gentoo.org>
832
833 * interp.c (sim_write): Add const to buffer arg.
834
35aafff4
JB		 8352010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
836
837 * interp.c: Don't include sysdep.h
838
3725885a
RW		 8392010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
840
841 * configure: Regenerate.
842
d6416cdc
RW		 8432009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
844
81ecdfbb
RW		 845 * config.in: Regenerate.
846 * configure: Likewise.
847
d6416cdc
RW		 848 * configure: Regenerate.
849
b5bd9624
HPN		 8502008-07-11 Hans-Peter Nilsson <hp@axis.com>
851
852 * configure: Regenerate to track ../common/common.m4 changes.
853 * config.in: Ditto.
854
6efef468 8552008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 856 Daniel Jacobowitz <dan@codesourcery.com>
857 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 858
859 * configure: Regenerate.
860
60dc88db
RS		 8612007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
862
863 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
864 that unconditionally allows fmt_ps.
865 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
866 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
867 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
868 filter from 64,f to 32,f.
869 (PREFX): Change filter from 64 to 32.
870 (LDXC1, LUXC1): Provide separate mips32r2 implementations
871 that use do_load_double instead of do_load. Make both LUXC1
872 versions unpredictable if SizeFGR () != 64.
873 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
874 instead of do_store. Remove unused variable. Make both SUXC1
875 versions unpredictable if SizeFGR () != 64.
876
599ca73e
RS		 8772007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
878
879 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
880 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
881 shifts for that case.
882
2525df03
NC		 8832007-09-04 Nick Clifton <nickc@redhat.com>
884
885 * interp.c (options enum): Add OPTION_INFO_MEMORY.
886 (display_mem_info): New static variable.
887 (mips_option_handler): Handle OPTION_INFO_MEMORY.
888 (mips_options): Add info-memory and memory-info.
889 (sim_open): After processing the command line and board
890 specification, check display_mem_info. If it is set then
891 call the real handler for the --memory-info command line
892 switch.
893
35ee6e1e
JB		 8942007-08-24 Joel Brobecker <brobecker@adacore.com>
895
896 * configure.ac: Change license of multi-run.c to GPL version 3.
897 * configure: Regenerate.
898
d5fb0879
RS		 8992007-06-28 Richard Sandiford <richard@codesourcery.com>
900
901 * configure.ac, configure: Revert last patch.
902
2a2ce21b
RS		 9032007-06-26 Richard Sandiford <richard@codesourcery.com>
904
905 * configure.ac (sim_mipsisa3264_configs): New variable.
906 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
907 every configuration support all four targets, using the triplet to
908 determine the default.
909 * configure: Regenerate.
910
efdcccc9
RS		 9112007-06-25 Richard Sandiford <richard@codesourcery.com>
912
0a7692b2 913 * Makefile.in (m16run.o): New rule.
efdcccc9 914
f532a356
TS		 9152007-05-15 Thiemo Seufer <ths@mips.com>
916
917 * mips3264r2.igen (DSHD): Fix compile warning.
918
bfe9c90b
TS		 9192007-05-14 Thiemo Seufer <ths@mips.com>
920
921 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
922 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
923 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
924 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
925 for mips32r2.
926
53f4826b
TS		 9272007-03-01 Thiemo Seufer <ths@mips.com>
928
929 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
930 and mips64.
931
8bf3ddc8
TS		 9322007-02-20 Thiemo Seufer <ths@mips.com>
933
934 * dsp.igen: Update copyright notice.
935 * dsp2.igen: Fix copyright notice.
936
8b082fb1 9372007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 938 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 939
940 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
941 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
942 Add dsp2 to sim_igen_machine.
943 * configure: Regenerate.
944 * dsp.igen (do_ph_op): Add MUL support when op = 2.
945 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
946 (mulq_rs.ph): Use do_ph_mulq.
947 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
948 * mips.igen: Add dsp2 model and include dsp2.igen.
949 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
950 for *mips32r2, *mips64r2, *dsp.
951 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
952 for *mips32r2, *mips64r2, *dsp2.
953 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
954
b1004875 9552007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 956 Nigel Stephens <nigel@mips.com>
b1004875
TS		 957
958 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
959 jumps with hazard barrier.
960
f8df4c77 9612007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 962 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 963
964 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
965 after each call to sim_io_write.
966
b1004875 9672007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 968 Nigel Stephens <nigel@mips.com>
b1004875
TS		 969
970 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
971 supported by this simulator.
07802d98
TS		 972 (decode_coproc): Recognise additional CP0 Config registers
973 correctly.
974
14fb6c5a 9752007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 976 Nigel Stephens <nigel@mips.com>
977 David Ung <davidu@mips.com>
14fb6c5a
TS		 978
979 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
980 uninterpreted formats. If fmt is one of the uninterpreted types
981 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
982 fmt_word, and fmt_uninterpreted_64 like fmt_long.
983 (store_fpr): When writing an invalid odd register, set the
984 matching even register to fmt_unknown, not the following register.
985 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
986 the the memory window at offset 0 set by --memory-size command
987 line option.
988 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
989 point register.
990 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
991 register.
992 (sim_monitor): When returning the memory size to the MIPS
993 application, use the value in STATE_MEM_SIZE, not an arbitrary
994 hardcoded value.
995 (cop_lw): Don' mess around with FPR_STATE, just pass
996 fmt_uninterpreted_32 to StoreFPR.
997 (cop_sw): Similarly.
998 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
999 (cop_sd): Similarly.
1000 * mips.igen (not_word_value): Single version for mips32, mips64
1001 and mips16.
1002
c8847145 10032007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 1004 Nigel Stephens <nigel@mips.com>
c8847145
TS		 1005
1006 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
1007 MBytes.
1008
4b5d35ee
TS		 10092007-02-17 Thiemo Seufer <ths@mips.com>
1010
1011 * configure.ac (mips*-sde-elf*): Move in front of generic machine
1012 configuration.
1013 * configure: Regenerate.
1014
3669427c
TS		 10152007-02-17 Thiemo Seufer <ths@mips.com>
1016
1017 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
1018 Add mdmx to sim_igen_machine.
1019 (mipsisa64*-*-*): Likewise. Remove dsp.
1020 (mipsisa32*-*-*): Remove dsp.
1021 * configure: Regenerate.
1022
109ad085
TS		 10232007-02-13 Thiemo Seufer <ths@mips.com>
1024
1025 * configure.ac: Add mips*-sde-elf* target.
1026 * configure: Regenerate.
1027
921d7ad3
HPN		 10282006-12-21 Hans-Peter Nilsson <hp@axis.com>
1029
1030 * acconfig.h: Remove.
1031 * config.in, configure: Regenerate.
1032
02f97da7
TS		 10332006-11-07 Thiemo Seufer <ths@mips.com>
1034
1035 * dsp.igen (do_w_op): Fix compiler warning.
1036
2d2733fc 10372006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1038 David Ung <davidu@mips.com>
2d2733fc
TS		 1039
1040 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
1041 sim_igen_machine.
1042 * configure: Regenerate.
1043 * mips.igen (model): Add smartmips.
1044 (MADDU): Increment ACX if carry.
1045 (do_mult): Clear ACX.
1046 (ROR,RORV): Add smartmips.
72f4393d 1047 (include): Include smartmips.igen.
2d2733fc
TS		 1048 * sim-main.h (ACX): Set to REGISTERS[89].
1049 * smartmips.igen: New file.
1050
d85c3a10 10512006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1052 David Ung <davidu@mips.com>
d85c3a10
TS		 1053
1054 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1055 mips3264r2.igen. Add missing dependency rules.
1056 * m16e.igen: Support for mips16e save/restore instructions.
1057
e85e3205
RE		 10582006-06-13 Richard Earnshaw <rearnsha@arm.com>
1059
1060 * configure: Regenerated.
1061
2f0122dc
DJ		 10622006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1063
1064 * configure: Regenerated.
1065
20e95c23
DJ		 10662006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1067
1068 * configure: Regenerated.
1069
69088b17
CF		 10702006-05-15 Chao-ying Fu <fu@mips.com>
1071
1072 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1073
0275de4e
NC		 10742006-04-18 Nick Clifton <nickc@redhat.com>
1075
1076 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1077 statement.
1078
b3a3ffef
HPN		 10792006-03-29 Hans-Peter Nilsson <hp@axis.com>
1080
1081 * configure: Regenerate.
1082
40a5538e
CF		 10832005-12-14 Chao-ying Fu <fu@mips.com>
1084
1085 * Makefile.in (SIM_OBJS): Add dsp.o.
1086 (dsp.o): New dependency.
1087 (IGEN_INCLUDE): Add dsp.igen.
1088 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1089 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1090 * configure: Regenerate.
1091 * mips.igen: Add dsp model and include dsp.igen.
1092 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1093 because these instructions are extended in DSP ASE.
1094 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1095 adding 6 DSP accumulator registers and 1 DSP control register.
1096 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1097 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1098 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1099 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1100 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1101 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1102 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1103 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1104 DSPCR_CCOND_SMASK): New define.
1105 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1106 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1107
21d14896
ILT		 11082005-07-08 Ian Lance Taylor <ian@airs.com>
1109
1110 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1111
b16d63da 11122005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1113 Nigel Stephens <nigel@mips.com>
1114
1115 * mips.igen: New mips16e model and include m16e.igen.
1116 (check_u64): Add mips16e tag.
1117 * m16e.igen: New file for MIPS16e instructions.
1118 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1119 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1120 models.
1121 * configure: Regenerate.
b16d63da 1122
e70cb6cd 11232005-05-26 David Ung <davidu@mips.com>
72f4393d 1124
e70cb6cd
CD		 1125 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1126 tags to all instructions which are applicable to the new ISAs.
1127 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1128 vr.igen.
1129 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1130 instructions.
e70cb6cd
CD		 1131 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1132 to mips.igen.
1133 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1134 * configure: Regenerate.
72f4393d 1135
2b193c4a
MK		 11362005-03-23 Mark Kettenis <kettenis@gnu.org>
1137
1138 * configure: Regenerate.
1139
35695fd6
AC		 11402005-01-14 Andrew Cagney <cagney@gnu.org>
1141
1142 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1143 explicit call to AC_CONFIG_HEADER.
1144 * configure: Regenerate.
1145
f0569246
AC		 11462005-01-12 Andrew Cagney <cagney@gnu.org>
1147
1148 * configure.ac: Update to use ../common/common.m4.
1149 * configure: Re-generate.
1150
38f48d72
AC		 11512005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1152
1153 * configure: Regenerated to track ../common/aclocal.m4 changes.
1154
b7026657
AC		 11552005-01-07 Andrew Cagney <cagney@gnu.org>
1156
1157 * configure.ac: Rename configure.in, require autoconf 2.59.
1158 * configure: Re-generate.
1159
379832de
HPN		 11602004-12-08 Hans-Peter Nilsson <hp@axis.com>
1161
1162 * configure: Regenerate for ../common/aclocal.m4 update.
1163
cd62154c 11642004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1165
cd62154c
AC		 1166 Committed by Andrew Cagney.
1167 * m16.igen (CMP, CMPI): Fix assembler.
1168
e5da76ec
CD		 11692004-08-18 Chris Demetriou <cgd@broadcom.com>
1170
1171 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1172 * configure: Regenerate.
1173
139181c8
CD		 11742004-06-25 Chris Demetriou <cgd@broadcom.com>
1175
1176 * configure.in (sim_m16_machine): Include mipsIII.
1177 * configure: Regenerate.
1178
1a27f959
CD		 11792004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1180
72f4393d 1181 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1182 from COP0_BADVADDR.
1183 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1184
5dbb7b5a
CD		 11852004-04-10 Chris Demetriou <cgd@broadcom.com>
1186
1187 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1188
14234056
CD		 11892004-04-09 Chris Demetriou <cgd@broadcom.com>
1190
1191 * mips.igen (check_fmt): Remove.
1192 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1193 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1194 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1195 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1196 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1197 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1198 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1199 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1200 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1201 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1202
c6f9085c
CD		 12032004-04-09 Chris Demetriou <cgd@broadcom.com>
1204
1205 * sb1.igen (check_sbx): New function.
1206 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1207
11d66e66 12082004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1209 Richard Sandiford <rsandifo@redhat.com>
1210
1211 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1212 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1213 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1214 separate implementations for mipsIV and mipsV. Use new macros to
1215 determine whether the restrictions apply.
1216
b3208fb8
CD		 12172004-01-19 Chris Demetriou <cgd@broadcom.com>
1218
1219 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1220 (check_mult_hilo): Improve comments.
1221 (check_div_hilo): Likewise. Also, fork off a new version
1222 to handle mips32/mips64 (since there are no hazards to check
1223 in MIPS32/MIPS64).
1224
9a1d84fb
CD		 12252003-06-17 Richard Sandiford <rsandifo@redhat.com>
1226
1227 * mips.igen (do_dmultx): Fix check for negative operands.
1228
ae451ac6
ILT		 12292003-05-16 Ian Lance Taylor <ian@airs.com>
1230
1231 * Makefile.in (SHELL): Make sure this is defined.
1232 (various): Use $(SHELL) whenever we invoke move-if-change.
1233
dd69d292
CD		 12342003-05-03 Chris Demetriou <cgd@broadcom.com>
1235
1236 * cp1.c: Tweak attribution slightly.
1237 * cp1.h: Likewise.
1238 * mdmx.c: Likewise.
1239 * mdmx.igen: Likewise.
1240 * mips3d.igen: Likewise.
1241 * sb1.igen: Likewise.
1242
bcd0068e
CD		 12432003-04-15 Richard Sandiford <rsandifo@redhat.com>
1244
1245 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1246 unsigned operands.
1247
6b4a8935
AC		 12482003-02-27 Andrew Cagney <cagney@redhat.com>
1249
601da316
AC		 1250 * interp.c (sim_open): Rename _bfd to bfd.
1251 (sim_create_inferior): Ditto.
6b4a8935 1252
d29e330f
CD		 12532003-01-14 Chris Demetriou <cgd@broadcom.com>
1254
1255 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1256
a2353a08
CD		 12572003-01-14 Chris Demetriou <cgd@broadcom.com>
1258
1259 * mips.igen (EI, DI): Remove.
1260
80551777
CD		 12612003-01-05 Richard Sandiford <rsandifo@redhat.com>
1262
1263 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1264
4c54fc26
CD		 12652003-01-04 Richard Sandiford <rsandifo@redhat.com>
1266 Andrew Cagney <ac131313@redhat.com>
1267 Gavin Romig-Koch <gavin@redhat.com>
1268 Graydon Hoare <graydon@redhat.com>
1269 Aldy Hernandez <aldyh@redhat.com>
1270 Dave Brolley <brolley@redhat.com>
1271 Chris Demetriou <cgd@broadcom.com>
1272
1273 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1274 (sim_mach_default): New variable.
1275 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1276 Add a new simulator generator, MULTI.
1277 * configure: Regenerate.
1278 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1279 (multi-run.o): New dependency.
1280 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1281 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1282 (tmp-multi): Combine them.
1283 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1284 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1285 (distclean-extra): New rule.
1286 * sim-main.h: Include bfd.h.
1287 (MIPS_MACH): New macro.
1288 * mips.igen (vr4120, vr5400, vr5500): New models.
1289 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1290 * vr.igen: Replace with new version.
1291
e6c674b8
CD		 12922003-01-04 Chris Demetriou <cgd@broadcom.com>
1293
1294 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1295 * configure: Regenerate.
1296
28f50ac8
CD		 12972002-12-31 Chris Demetriou <cgd@broadcom.com>
1298
1299 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1300 * mips.igen: Remove all invocations of check_branch_bug and
1301 mark_branch_bug.
1302
5071ffe6
CD		 13032002-12-16 Chris Demetriou <cgd@broadcom.com>
1304
72f4393d 1305 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1306
06e7837e
CD		 13072002-07-30 Chris Demetriou <cgd@broadcom.com>
1308
1309 * mips.igen (do_load_double, do_store_double): New functions.
1310 (LDC1, SDC1): Rename to...
1311 (LDC1b, SDC1b): respectively.
1312 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1313
2265c243
MS		 13142002-07-29 Michael Snyder <msnyder@redhat.com>
1315
1316 * cp1.c (fp_recip2): Modify initialization expression so that
1317 GCC will recognize it as constant.
1318
a2f8b4f3
CD		 13192002-06-18 Chris Demetriou <cgd@broadcom.com>
1320
1321 * mdmx.c (SD_): Delete.
1322 (Unpredictable): Re-define, for now, to directly invoke
1323 unpredictable_action().
1324 (mdmx_acc_op): Fix error in .ob immediate handling.
1325
b4b6c939
AC		 13262002-06-18 Andrew Cagney <cagney@redhat.com>
1327
1328 * interp.c (sim_firmware_command): Initialize `address'.
1329
c8cca39f
AC		 13302002-06-16 Andrew Cagney <ac131313@redhat.com>
1331
1332 * configure: Regenerated to track ../common/aclocal.m4 changes.
1333
e7e81181 13342002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1335 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1336
1337 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1338 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1339 * mips.igen: Include mips3d.igen.
1340 (mips3d): New model name for MIPS-3D ASE instructions.
1341 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1342 instructions.
e7e81181
CD		 1343 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1344 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1345 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1346 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1347 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1348 (RSquareRoot1, RSquareRoot2): New macros.
1349 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1350 (fp_rsqrt2): New functions.
1351 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1352 * configure: Regenerate.
1353
3a2b820e 13542002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1355 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1356
1357 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1358 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1359 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1360 (convert): Note that this function is not used for paired-single
1361 format conversions.
1362 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1363 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1364 (check_fmt_p): Enable paired-single support.
1365 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1366 (PUU.PS): New instructions.
1367 (CVT.S.fmt): Don't use this instruction for paired-single format
1368 destinations.
1369 * sim-main.h (FP_formats): New value 'fmt_ps.'
1370 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1371 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1372
d18ea9c2
CD		 13732002-06-12 Chris Demetriou <cgd@broadcom.com>
1374
1375 * mips.igen: Fix formatting of function calls in
1376 many FP operations.
1377
95fd5cee
CD		 13782002-06-12 Chris Demetriou <cgd@broadcom.com>
1379
1380 * mips.igen (MOVN, MOVZ): Trace result.
1381 (TNEI): Print "tnei" as the opcode name in traces.
1382 (CEIL.W): Add disassembly string for traces.
1383 (RSQRT.fmt): Make location of disassembly string consistent
1384 with other instructions.
1385
4f0d55ae
CD		 13862002-06-12 Chris Demetriou <cgd@broadcom.com>
1387
1388 * mips.igen (X): Delete unused function.
1389
3c25f8c7
AC		 13902002-06-08 Andrew Cagney <cagney@redhat.com>
1391
1392 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1393
f3c08b7e 13942002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1395 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1396
1397 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1398 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1399 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1400 (fp_nmsub): New prototypes.
1401 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1402 (NegMultiplySub): New defines.
1403 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1404 (MADD.D, MADD.S): Replace with...
1405 (MADD.fmt): New instruction.
1406 (MSUB.D, MSUB.S): Replace with...
1407 (MSUB.fmt): New instruction.
1408 (NMADD.D, NMADD.S): Replace with...
1409 (NMADD.fmt): New instruction.
1410 (NMSUB.D, MSUB.S): Replace with...
1411 (NMSUB.fmt): New instruction.
1412
52714ff9 14132002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1414 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1415
1416 * cp1.c: Fix more comment spelling and formatting.
1417 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1418 (denorm_mode): New function.
1419 (fpu_unary, fpu_binary): Round results after operation, collect
1420 status from rounding operations, and update the FCSR.
1421 (convert): Collect status from integer conversions and rounding
1422 operations, and update the FCSR. Adjust NaN values that result
1423 from conversions. Convert to use sim_io_eprintf rather than
1424 fprintf, and remove some debugging code.
1425 * cp1.h (fenr_FS): New define.
1426
577d8c4b
CD		 14272002-06-07 Chris Demetriou <cgd@broadcom.com>
1428
1429 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1430 rounding mode to sim FP rounding mode flag conversion code into...
1431 (rounding_mode): New function.
1432
196496ed
CD		 14332002-06-07 Chris Demetriou <cgd@broadcom.com>
1434
1435 * cp1.c: Clean up formatting of a few comments.
1436 (value_fpr): Reformat switch statement.
1437
cfe9ea23 14382002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1439 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1440
1441 * cp1.h: New file.
1442 * sim-main.h: Include cp1.h.
1443 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1444 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1445 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1446 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1447 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1448 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1449 * cp1.c: Don't include sim-fpu.h; already included by
1450 sim-main.h. Clean up formatting of some comments.
1451 (NaN, Equal, Less): Remove.
1452 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1453 (fp_cmp): New functions.
1454 * mips.igen (do_c_cond_fmt): Remove.
1455 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1456 Compare. Add result tracing.
1457 (CxC1): Remove, replace with...
1458 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1459 (DMxC1): Remove, replace with...
1460 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1461 (MxC1): Remove, replace with...
1462 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1463
ee7254b0
CD		 14642002-06-04 Chris Demetriou <cgd@broadcom.com>
1465
1466 * sim-main.h (FGRIDX): Remove, replace all uses with...
1467 (FGR_BASE): New macro.
1468 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1469 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1470 (NR_FGR, FGR): Likewise.
1471 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1472 * mips.igen: Likewise.
1473
d3eb724f
CD		 14742002-06-04 Chris Demetriou <cgd@broadcom.com>
1475
1476 * cp1.c: Add an FSF Copyright notice to this file.
1477
ba46ddd0 14782002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1479 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1480
1481 * cp1.c (Infinity): Remove.
1482 * sim-main.h (Infinity): Likewise.
1483
1484 * cp1.c (fp_unary, fp_binary): New functions.
1485 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1486 (fp_sqrt): New functions, implemented in terms of the above.
1487 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1488 (Recip, SquareRoot): Remove (replaced by functions above).
1489 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1490 (fp_recip, fp_sqrt): New prototypes.
1491 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1492 (Recip, SquareRoot): Replace prototypes with #defines which
1493 invoke the functions above.
72f4393d 1494
18d8a52d
CD		 14952002-06-03 Chris Demetriou <cgd@broadcom.com>
1496
1497 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1498 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1499 file, remove PARAMS from prototypes.
1500 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1501 simulator state arguments.
1502 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1503 pass simulator state arguments.
1504 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1505 (store_fpr, convert): Remove 'sd' argument.
1506 (value_fpr): Likewise. Convert to use 'SD' instead.
1507
0f154cbd
CD		 15082002-06-03 Chris Demetriou <cgd@broadcom.com>
1509
1510 * cp1.c (Min, Max): Remove #if 0'd functions.
1511 * sim-main.h (Min, Max): Remove.
1512
e80fc152
CD		 15132002-06-03 Chris Demetriou <cgd@broadcom.com>
1514
1515 * cp1.c: fix formatting of switch case and default labels.
1516 * interp.c: Likewise.
1517 * sim-main.c: Likewise.
1518
bad673a9
CD		 15192002-06-03 Chris Demetriou <cgd@broadcom.com>
1520
1521 * cp1.c: Clean up comments which describe FP formats.
1522 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1523
7cbea089 15242002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1525 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1526
1527 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1528 Broadcom SiByte SB-1 processor configurations.
1529 * configure: Regenerate.
1530 * sb1.igen: New file.
1531 * mips.igen: Include sb1.igen.
1532 (sb1): New model.
1533 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1534 * mdmx.igen: Add "sb1" model to all appropriate functions and
1535 instructions.
1536 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1537 (ob_func, ob_acc): Reference the above.
1538 (qh_acc): Adjust to keep the same size as ob_acc.
1539 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1540 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1541
909daa82
CD		 15422002-06-03 Chris Demetriou <cgd@broadcom.com>
1543
1544 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1545
f4f1b9f1 15462002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1547 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1548
1549 * mips.igen (mdmx): New (pseudo-)model.
1550 * mdmx.c, mdmx.igen: New files.
1551 * Makefile.in (SIM_OBJS): Add mdmx.o.
1552 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1553 New typedefs.
1554 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1555 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1556 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1557 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1558 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1559 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1560 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1561 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1562 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1563 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1564 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1565 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1566 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1567 (qh_fmtsel): New macros.
1568 (_sim_cpu): New member "acc".
1569 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1570 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1571
5accf1ff
CD		 15722002-05-01 Chris Demetriou <cgd@broadcom.com>
1573
1574 * interp.c: Use 'deprecated' rather than 'depreciated.'
1575 * sim-main.h: Likewise.
1576
402586aa
CD		 15772002-05-01 Chris Demetriou <cgd@broadcom.com>
1578
1579 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1580 which wouldn't compile anyway.
1581 * sim-main.h (unpredictable_action): New function prototype.
1582 (Unpredictable): Define to call igen function unpredictable().
1583 (NotWordValue): New macro to call igen function not_word_value().
1584 (UndefinedResult): Remove.
1585 * interp.c (undefined_result): Remove.
1586 (unpredictable_action): New function.
1587 * mips.igen (not_word_value, unpredictable): New functions.
1588 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1589 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1590 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1591 NotWordValue() to check for unpredictable inputs, then
1592 Unpredictable() to handle them.
1593
c9b9995a
CD		 15942002-02-24 Chris Demetriou <cgd@broadcom.com>
1595
1596 * mips.igen: Fix formatting of calls to Unpredictable().
1597
e1015982
AC		 15982002-04-20 Andrew Cagney <ac131313@redhat.com>
1599
1600 * interp.c (sim_open): Revert previous change.
1601
b882a66b
AO		 16022002-04-18 Alexandre Oliva <aoliva@redhat.com>
1603
1604 * interp.c (sim_open): Disable chunk of code that wrote code in
1605 vector table entries.
1606
c429b7dd
CD		 16072002-03-19 Chris Demetriou <cgd@broadcom.com>
1608
1609 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1610 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1611 unused definitions.
1612
37d146fa
CD		 16132002-03-19 Chris Demetriou <cgd@broadcom.com>
1614
1615 * cp1.c: Fix many formatting issues.
1616
07892c0b
CD		 16172002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1618
1619 * cp1.c (fpu_format_name): New function to replace...
1620 (DOFMT): This. Delete, and update all callers.
1621 (fpu_rounding_mode_name): New function to replace...
1622 (RMMODE): This. Delete, and update all callers.
1623
487f79b7
CD		 16242002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1625
1626 * interp.c: Move FPU support routines from here to...
1627 * cp1.c: Here. New file.
1628 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1629 (cp1.o): New target.
1630
1e799e28
CD		 16312002-03-12 Chris Demetriou <cgd@broadcom.com>
1632
1633 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1634 * mips.igen (mips32, mips64): New models, add to all instructions
1635 and functions as appropriate.
1636 (loadstore_ea, check_u64): New variant for model mips64.
1637 (check_fmt_p): New variant for models mipsV and mips64, remove
1638 mipsV model marking fro other variant.
1639 (SLL) Rename to...
1640 (SLLa) this.
1641 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1642 for mips32 and mips64.
1643 (DCLO, DCLZ): New instructions for mips64.
1644
82f728db
CD		 16452002-03-07 Chris Demetriou <cgd@broadcom.com>
1646
1647 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1648 immediate or code as a hex value with the "%#lx" format.
1649 (ANDI): Likewise, and fix printed instruction name.
1650
b96e7ef1
CD		 16512002-03-05 Chris Demetriou <cgd@broadcom.com>
1652
1653 * sim-main.h (UndefinedResult, Unpredictable): New macros
1654 which currently do nothing.
1655
d35d4f70
CD		 16562002-03-05 Chris Demetriou <cgd@broadcom.com>
1657
1658 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1659 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1660 (status_CU3): New definitions.
1661
1662 * sim-main.h (ExceptionCause): Add new values for MIPS32
1663 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1664 for DebugBreakPoint and NMIReset to note their status in
1665 MIPS32 and MIPS64.
1666 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1667 (SignalExceptionCacheErr): New exception macros.
1668
3ad6f714
CD		 16692002-03-05 Chris Demetriou <cgd@broadcom.com>
1670
1671 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1672 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1673 is always enabled.
1674 (SignalExceptionCoProcessorUnusable): Take as argument the
1675 unusable coprocessor number.
1676
86b77b47
CD		 16772002-03-05 Chris Demetriou <cgd@broadcom.com>
1678
1679 * mips.igen: Fix formatting of all SignalException calls.
1680
97a88e93 16812002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1682
1683 * sim-main.h (SIGNEXTEND): Remove.
1684
97a88e93 16852002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1686
1687 * mips.igen: Remove gencode comment from top of file, fix
1688 spelling in another comment.
1689
97a88e93 16902002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1691
1692 * mips.igen (check_fmt, check_fmt_p): New functions to check
1693 whether specific floating point formats are usable.
1694 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1695 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1696 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1697 Use the new functions.
1698 (do_c_cond_fmt): Remove format checks...
1699 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1700
97a88e93 17012002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1702
1703 * mips.igen: Fix formatting of check_fpu calls.
1704
41774c9d
CD		 17052002-03-03 Chris Demetriou <cgd@broadcom.com>
1706
1707 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1708
4a0bd876
CD		 17092002-03-03 Chris Demetriou <cgd@broadcom.com>
1710
1711 * mips.igen: Remove whitespace at end of lines.
1712
09297648
CD		 17132002-03-02 Chris Demetriou <cgd@broadcom.com>
1714
1715 * mips.igen (loadstore_ea): New function to do effective
1716 address calculations.
1717 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1718 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1719 CACHE): Use loadstore_ea to do effective address computations.
1720
043b7057
CD		 17212002-03-02 Chris Demetriou <cgd@broadcom.com>
1722
1723 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1724 * mips.igen (LL, CxC1, MxC1): Likewise.
1725
c1e8ada4
CD		 17262002-03-02 Chris Demetriou <cgd@broadcom.com>
1727
1728 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1729 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1730 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1731 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1732 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1733 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1734 Don't split opcode fields by hand, use the opcode field values
1735 provided by igen.
1736
3e1dca16
CD		 17372002-03-01 Chris Demetriou <cgd@broadcom.com>
1738
1739 * mips.igen (do_divu): Fix spacing.
1740
1741 * mips.igen (do_dsllv): Move to be right before DSLLV,
1742 to match the rest of the do_<shift> functions.
1743
fff8d27d
CD		 17442002-03-01 Chris Demetriou <cgd@broadcom.com>
1745
1746 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1747 DSRL32, do_dsrlv): Trace inputs and results.
1748
0d3e762b
CD		 17492002-03-01 Chris Demetriou <cgd@broadcom.com>
1750
1751 * mips.igen (CACHE): Provide instruction-printing string.
1752
1753 * interp.c (signal_exception): Comment tokens after #endif.
1754
eb5fcf93
CD		 17552002-02-28 Chris Demetriou <cgd@broadcom.com>
1756
1757 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1758 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1759 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1760 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1761 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1762 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1763 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1764 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1765
bb22bd7d
CD		 17662002-02-28 Chris Demetriou <cgd@broadcom.com>
1767
1768 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1769 instruction-printing string.
1770 (LWU): Use '64' as the filter flag.
1771
91a177cf
CD		 17722002-02-28 Chris Demetriou <cgd@broadcom.com>
1773
1774 * mips.igen (SDXC1): Fix instruction-printing string.
1775
387f484a
CD		 17762002-02-28 Chris Demetriou <cgd@broadcom.com>
1777
1778 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1779 filter flags "32,f".
1780
3d81f391
CD		 17812002-02-27 Chris Demetriou <cgd@broadcom.com>
1782
1783 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1784 as the filter flag.
1785
af5107af
CD		 17862002-02-27 Chris Demetriou <cgd@broadcom.com>
1787
1788 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1789 add a comma) so that it more closely match the MIPS ISA
1790 documentation opcode partitioning.
1791 (PREF): Put useful names on opcode fields, and include
1792 instruction-printing string.
1793
ca971540
CD		 17942002-02-27 Chris Demetriou <cgd@broadcom.com>
1795
1796 * mips.igen (check_u64): New function which in the future will
1797 check whether 64-bit instructions are usable and signal an
1798 exception if not. Currently a no-op.
1799 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1800 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1801 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1802 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1803
1804 * mips.igen (check_fpu): New function which in the future will
1805 check whether FPU instructions are usable and signal an exception
1806 if not. Currently a no-op.
1807 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1808 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1809 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1810 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1811 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1812 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1813 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1814 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1815
1c47a468
CD		 18162002-02-27 Chris Demetriou <cgd@broadcom.com>
1817
1818 * mips.igen (do_load_left, do_load_right): Move to be immediately
1819 following do_load.
1820 (do_store_left, do_store_right): Move to be immediately following
1821 do_store.
1822
603a98e7
CD		 18232002-02-27 Chris Demetriou <cgd@broadcom.com>
1824
1825 * mips.igen (mipsV): New model name. Also, add it to
1826 all instructions and functions where it is appropriate.
1827
c5d00cc7
CD		 18282002-02-18 Chris Demetriou <cgd@broadcom.com>
1829
1830 * mips.igen: For all functions and instructions, list model
1831 names that support that instruction one per line.
1832
074e9cb8
CD		 18332002-02-11 Chris Demetriou <cgd@broadcom.com>
1834
1835 * mips.igen: Add some additional comments about supported
1836 models, and about which instructions go where.
1837 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1838 order as is used in the rest of the file.
1839
9805e229
CD		 18402002-02-11 Chris Demetriou <cgd@broadcom.com>
1841
1842 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1843 indicating that ALU32_END or ALU64_END are there to check
1844 for overflow.
1845 (DADD): Likewise, but also remove previous comment about
1846 overflow checking.
1847
f701dad2
CD		 18482002-02-10 Chris Demetriou <cgd@broadcom.com>
1849
1850 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1851 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1852 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1853 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1854 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1855 fields (i.e., add and move commas) so that they more closely
1856 match the MIPS ISA documentation opcode partitioning.
1857
18582002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1859
72f4393d
L		 1860 * mips.igen (ADDI): Print immediate value.
1861 (BREAK): Print code.
1862 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1863 (SLL): Print "nop" specially, and don't run the code
1864 that does the shift for the "nop" case.
20ae0098 1865
9e52972e
FF		 18662001-11-17 Fred Fish <fnf@redhat.com>
1867
1868 * sim-main.h (float_operation): Move enum declaration outside
1869 of _sim_cpu struct declaration.
1870
c0efbca4
JB		 18712001-04-12 Jim Blandy <jimb@redhat.com>
1872
1873 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1874 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1875 set of the FCSR.
1876 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1877 PENDING_FILL, and you can get the intended effect gracefully by
1878 calling PENDING_SCHED directly.
1879
fb891446
BE		 18802001-02-23 Ben Elliston <bje@redhat.com>
1881
1882 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1883 already defined elsewhere.
1884
8030f857
BE		 18852001-02-19 Ben Elliston <bje@redhat.com>
1886
1887 * sim-main.h (sim_monitor): Return an int.
1888 * interp.c (sim_monitor): Add return values.
1889 (signal_exception): Handle error conditions from sim_monitor.
1890
56b48a7a
CD		 18912001-02-08 Ben Elliston <bje@redhat.com>
1892
1893 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1894 (store_memory): Likewise, pass cia to sim_core_write*.
1895
d3ee60d9
FCE		 18962000-10-19 Frank Ch. Eigler <fche@redhat.com>
1897
1898 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1899 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1900
071da002
AC		 1901Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1904 * Makefile.in: Don't delete *.igen when cleaning directory.
1905
a28c02cd
AC		 1906Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * m16.igen (break): Call SignalException not sim_engine_halt.
1909
80ee11fa
AC		 1910Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 From Jason Eckhardt:
1913 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1914
673388c0
AC		 1915Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1916
1917 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1918
4c0deff4
NC		 19192000-05-24 Michael Hayes <mhayes@cygnus.com>
1920
1921 * mips.igen (do_dmultx): Fix typo.
1922
eb2d80b4
AC		 1923Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * configure: Regenerated to track ../common/aclocal.m4 changes.
1926
dd37a34b
AC		 1927Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1930
4c0deff4
NC		 19312000-04-12 Frank Ch. Eigler <fche@redhat.com>
1932
1933 * sim-main.h (GPR_CLEAR): Define macro.
1934
e30db738
AC		 1935Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1936
1937 * interp.c (decode_coproc): Output long using %lx and not %s.
1938
cb7450ea
FCE		 19392000-03-21 Frank Ch. Eigler <fche@redhat.com>
1940
1941 * interp.c (sim_open): Sort & extend dummy memory regions for
1942 --board=jmr3904 for eCos.
1943
a3027dd7
FCE		 19442000-03-02 Frank Ch. Eigler <fche@redhat.com>
1945
1946 * configure: Regenerated.
1947
1948Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1949
1950 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1951 calls, conditional on the simulator being in verbose mode.
1952
dfcd3bfb
JM		 1953Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1954
1955 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1956 cache don't get ReservedInstruction traps.
1957
c2d11a7d
JM		 19581999-11-29 Mark Salter <msalter@cygnus.com>
1959
1960 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1961 to clear status bits in sdisr register. This is how the hardware works.
1962
1963 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1964 being used by cygmon.
1965
4ce44c66
JM		 19661999-11-11 Andrew Haley <aph@cygnus.com>
1967
1968 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1969 instructions.
1970
cff3e48b
JM		 1971Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1972
1973 * mips.igen (MULT): Correct previous mis-applied patch.
1974
d4f3574e
SS		 1975Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1976
1977 * mips.igen (delayslot32): Handle sequence like
1978 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1979 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1980 (MULT): Actually pass the third register...
1981
19821999-09-03 Mark Salter <msalter@cygnus.com>
1983
1984 * interp.c (sim_open): Added more memory aliases for additional
1985 hardware being touched by cygmon on jmr3904 board.
1986
1987Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * configure: Regenerated to track ../common/aclocal.m4 changes.
1990
a0b3c4fd
JM		 1991Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1992
1993 * interp.c (sim_store_register): Handle case where client - GDB -
1994 specifies that a 4 byte register is 8 bytes in size.
1995 (sim_fetch_register): Ditto.
72f4393d 1996
adf40b2e
JM		 19971999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1998
1999 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
2000 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
2001 (idt_monitor_base): Base address for IDT monitor traps.
2002 (pmon_monitor_base): Ditto for PMON.
2003 (lsipmon_monitor_base): Ditto for LSI PMON.
2004 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
2005 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
2006 (sim_firmware_command): New function.
2007 (mips_option_handler): Call it for OPTION_FIRMWARE.
2008 (sim_open): Allocate memory for idt_monitor region. If "--board"
2009 option was given, add no monitor by default. Add BREAK hooks only if
2010 monitors are also there.
72f4393d 2011
43e526b9
JM		 2012Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
2013
2014 * interp.c (sim_monitor): Flush output before reading input.
2015
2016Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
2017
2018 * tconfig.in (SIM_HANDLES_LMA): Always define.
2019
2020Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
2021
2022 From Mark Salter <msalter@cygnus.com>:
2023 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
2024 (sim_open): Add setup for BSP board.
2025
9846de1b
JM		 2026Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
2027
2028 * mips.igen (MULT, MULTU): Add syntax for two operand version.
2029 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
2030 them as unimplemented.
2031
cd0fc7c3
SS		 20321999-05-08 Felix Lee <flee@cygnus.com>
2033
2034 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 2035
7a292a7a
SS		 20361999-04-21 Frank Ch. Eigler <fche@cygnus.com>
2037
2038 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
2039
2040Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
2041
2042 * configure.in: Any mips64vr5*-*-* target should have
2043 -DTARGET_ENABLE_FR=1.
2044 (default_endian): Any mips64vr*el-*-* target should default to
2045 LITTLE_ENDIAN.
2046 * configure: Re-generate.
2047
20481999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2049
2050 * mips.igen (ldl): Extend from _16_, not 32.
2051
2052Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2053
2054 * interp.c (sim_store_register): Force registers written to by GDB
2055 into an un-interpreted state.
2056
c906108c
SS		 20571999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2058
2059 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2060 CPU, start periodic background I/O polls.
72f4393d 2061 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2062
20631998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2064
2065 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2066
c906108c
SS		 2067Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2068
2069 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2070 case statement.
2071
20721998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2073
2074 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2075 (load_word): Call SIM_CORE_SIGNAL hook on error.
2076 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2077 starting. For exception dispatching, pass PC instead of NULL_CIA.
2078 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2079 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2080 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2081 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2082 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2083 * mips.igen (*): Replace memory-related SignalException* calls
2084 with references to SIM_CORE_SIGNAL hook.
72f4393d 2085
c906108c
SS		 2086 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2087 fix.
2088 * sim-main.c (*): Minor warning cleanups.
72f4393d 2089
c906108c
SS		 20901998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2091
2092 * m16.igen (DADDIU5): Correct type-o.
2093
2094Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2095
2096 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2097 variables.
2098
2099Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2100
2101 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2102 to include path.
2103 (interp.o): Add dependency on itable.h
2104 (oengine.c, gencode): Delete remaining references.
2105 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2106
c906108c 21071998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2108
c906108c
SS		 2109 * vr4run.c: New.
2110 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2111 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2112 tmp-run-hack) : New.
2113 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2114 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2115 Drop the "64" qualifier to get the HACK generator working.
2116 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2117 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2118 qualifier to get the hack generator working.
2119 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2120 (DSLL): Use do_dsll.
2121 (DSLLV): Use do_dsllv.
2122 (DSRA): Use do_dsra.
2123 (DSRL): Use do_dsrl.
2124 (DSRLV): Use do_dsrlv.
2125 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2126 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2127 get the HACK generator working.
2128 (MACC) Rename to get the HACK generator working.
2129 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2130
c906108c
SS		 21311998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2132
2133 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2134 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2135
c906108c
SS		 21361998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2137
2138 * mips/interp.c (DEBUG): Cleanups.
2139
21401998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2141
2142 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2143 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2144
c906108c
SS		 21451998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2146
2147 * interp.c (sim_close): Uninstall modules.
2148
2149Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2150
2151 * sim-main.h, interp.c (sim_monitor): Change to global
2152 function.
2153
2154Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * configure.in (vr4100): Only include vr4100 instructions in
2157 simulator.
2158 * configure: Re-generate.
2159 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2160
2161Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2164 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2165 true alternative.
2166
2167 * configure.in (sim_default_gen, sim_use_gen): Replace with
2168 sim_gen.
2169 (--enable-sim-igen): Delete config option. Always using IGEN.
2170 * configure: Re-generate.
72f4393d 2171
c906108c
SS		 2172 * Makefile.in (gencode): Kill, kill, kill.
2173 * gencode.c: Ditto.
72f4393d 2174
c906108c
SS		 2175Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2176
2177 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2178 bit mips16 igen simulator.
2179 * configure: Re-generate.
2180
2181 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2182 as part of vr4100 ISA.
2183 * vr.igen: Mark all instructions as 64 bit only.
2184
2185Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2186
2187 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2188 Pacify GCC.
2189
2190Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2193 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2194 * configure: Re-generate.
2195
2196 * m16.igen (BREAK): Define breakpoint instruction.
2197 (JALX32): Mark instruction as mips16 and not r3900.
2198 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2199
2200 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2201
2202Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2203
2204 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2205 insn as a debug breakpoint.
2206
2207 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2208 pending.slot_size.
2209 (PENDING_SCHED): Clean up trace statement.
2210 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2211 (PENDING_FILL): Delay write by only one cycle.
2212 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2213
2214 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2215 of pending writes.
2216 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2217 32 & 64.
2218 (pending_tick): Move incrementing of index to FOR statement.
2219 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2220
c906108c
SS		 2221 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2222 build simulator.
2223 * configure: Re-generate.
72f4393d 2224
c906108c
SS		 2225 * interp.c (sim_engine_run OLD): Delete explicit call to
2226 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2227
c906108c
SS		 2228Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2229
2230 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2231 interrupt level number to match changed SignalExceptionInterrupt
2232 macro.
2233
2234Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2235
2236 * interp.c: #include "itable.h" if WITH_IGEN.
2237 (get_insn_name): New function.
2238 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2239 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2240
2241Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2242
2243 * configure: Rebuilt to inhale new common/aclocal.m4.
2244
2245Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2246
2247 * dv-tx3904sio.c: Include sim-assert.h.
2248
2249Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2250
2251 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2252 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2253 Reorganize target-specific sim-hardware checks.
2254 * configure: rebuilt.
2255 * interp.c (sim_open): For tx39 target boards, set
2256 OPERATING_ENVIRONMENT, add tx3904sio devices.
2257 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2258 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2259
c906108c
SS		 2260 * dv-tx3904irc.c: Compiler warning clean-up.
2261 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2262 frequent hw-trace messages.
2263
2264Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2265
2266 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2267
2268Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2269
2270 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2271
2272 * vr.igen: New file.
2273 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2274 * mips.igen: Define vr4100 model. Include vr.igen.
2275Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2276
2277 * mips.igen (check_mf_hilo): Correct check.
2278
2279Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2280
2281 * sim-main.h (interrupt_event): Add prototype.
2282
2283 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2284 register_ptr, register_value.
2285 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2286
2287 * sim-main.h (tracefh): Make extern.
2288
2289Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2290
2291 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2292 Reduce unnecessarily high timer event frequency.
c906108c 2293 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2294
c906108c
SS		 2295Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2296
2297 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2298 to allay warnings.
2299 (interrupt_event): Made non-static.
72f4393d 2300
c906108c
SS		 2301 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2302 interchange of configuration values for external vs. internal
2303 clock dividers.
72f4393d 2304
c906108c
SS		 2305Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2306
72f4393d 2307 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2308 simulator-reserved break instructions.
2309 * gencode.c (build_instruction): Ditto.
2310 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2311 reserved instructions now use exception vector, rather
c906108c
SS		 2312 than halting sim.
2313 * sim-main.h: Moved magic constants to here.
2314
2315Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2316
2317 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2318 register upon non-zero interrupt event level, clear upon zero
2319 event value.
2320 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2321 by passing zero event value.
2322 (*_io_{read,write}_buffer): Endianness fixes.
2323 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2324 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2325
2326 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2327 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2328
c906108c
SS		 2329Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2330
72f4393d 2331 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2332 and BigEndianCPU.
2333
2334Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2335
2336 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2337 parts.
2338 * configure: Update.
2339
2340Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2341
2342 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2343 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2344 * configure.in: Include tx3904tmr in hw_device list.
2345 * configure: Rebuilt.
2346 * interp.c (sim_open): Instantiate three timer instances.
2347 Fix address typo of tx3904irc instance.
2348
2349Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2350
2351 * interp.c (signal_exception): SystemCall exception now uses
2352 the exception vector.
2353
2354Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2355
2356 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2357 to allay warnings.
2358
2359Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2362
2363Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2366
2367 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2368 sim-main.h. Declare a struct hw_descriptor instead of struct
2369 hw_device_descriptor.
2370
2371Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2372
2373 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2374 right bits and then re-align left hand bytes to correct byte
2375 lanes. Fix incorrect computation in do_store_left when loading
2376 bytes from second word.
2377
2378Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2379
2380 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2381 * interp.c (sim_open): Only create a device tree when HW is
2382 enabled.
2383
2384 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2385 * interp.c (signal_exception): Ditto.
2386
2387Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2388
2389 * gencode.c: Mark BEGEZALL as LIKELY.
2390
2391Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2392
2393 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2394 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2395
c906108c
SS		 2396Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2397
2398 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2399 modules. Recognize TX39 target with "mips*tx39" pattern.
2400 * configure: Rebuilt.
2401 * sim-main.h (*): Added many macros defining bits in
2402 TX39 control registers.
2403 (SignalInterrupt): Send actual PC instead of NULL.
2404 (SignalNMIReset): New exception type.
2405 * interp.c (board): New variable for future use to identify
2406 a particular board being simulated.
2407 (mips_option_handler,mips_options): Added "--board" option.
2408 (interrupt_event): Send actual PC.
2409 (sim_open): Make memory layout conditional on board setting.
2410 (signal_exception): Initial implementation of hardware interrupt
2411 handling. Accept another break instruction variant for simulator
2412 exit.
2413 (decode_coproc): Implement RFE instruction for TX39.
2414 (mips.igen): Decode RFE instruction as such.
2415 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2416 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2417 bbegin to implement memory map.
2418 * dv-tx3904cpu.c: New file.
2419 * dv-tx3904irc.c: New file.
2420
2421Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2422
2423 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2424
2425Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2426
2427 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2428 with calls to check_div_hilo.
2429
2430Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2431
2432 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2433 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2434 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2435 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2436 with calls to check_mult_hilo.
2437 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2438 with calls to check_div_hilo.
2439
2440Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2443 Document a replacement.
2444
2445Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2446
2447 * interp.c (sim_monitor): Make mon_printf work.
2448
2449Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2450
2451 * sim-main.h (INSN_NAME): New arg `cpu'.
2452
2453Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2454
72f4393d 2455 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2456
2457Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2458
2459 * configure: Regenerated to track ../common/aclocal.m4 changes.
2460 * config.in: Ditto.
2461
2462Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2463
2464 * acconfig.h: New file.
2465 * configure.in: Reverted change of Apr 24; use sinclude again.
2466
2467Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2468
2469 * configure: Regenerated to track ../common/aclocal.m4 changes.
2470 * config.in: Ditto.
2471
2472Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2473
2474 * configure.in: Don't call sinclude.
2475
2476Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2477
2478 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2479
2480Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2481
2482 * mips.igen (ERET): Implement.
2483
2484 * interp.c (decode_coproc): Return sign-extended EPC.
2485
2486 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2487
2488 * interp.c (signal_exception): Do not ignore Trap.
2489 (signal_exception): On TRAP, restart at exception address.
2490 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2491 (signal_exception): Update.
2492 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2493 so that TRAP instructions are caught.
2494
2495Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2496
2497 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2498 contains HI/LO access history.
2499 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2500 (HIACCESS, LOACCESS): Delete, replace with
2501 (HIHISTORY, LOHISTORY): New macros.
2502 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2503
c906108c
SS		 2504 * gencode.c (build_instruction): Do not generate checks for
2505 correct HI/LO register usage.
2506
2507 * interp.c (old_engine_run): Delete checks for correct HI/LO
2508 register usage.
2509
2510 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2511 check_mf_cycles): New functions.
2512 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2513 do_divu, domultx, do_mult, do_multu): Use.
2514
2515 * tx.igen ("madd", "maddu"): Use.
72f4393d 2516
c906108c
SS		 2517Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2518
2519 * mips.igen (DSRAV): Use function do_dsrav.
2520 (SRAV): Use new function do_srav.
2521
2522 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2523 (B): Sign extend 11 bit immediate.
2524 (EXT-B*): Shift 16 bit immediate left by 1.
2525 (ADDIU*): Don't sign extend immediate value.
2526
2527Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2528
2529 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2530
2531 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2532 functions.
2533
2534 * mips.igen (delayslot32, nullify_next_insn): New functions.
2535 (m16.igen): Always include.
2536 (do_*): Add more tracing.
2537
2538 * m16.igen (delayslot16): Add NIA argument, could be called by a
2539 32 bit MIPS16 instruction.
72f4393d 2540
c906108c
SS		 2541 * interp.c (ifetch16): Move function from here.
2542 * sim-main.c (ifetch16): To here.
72f4393d 2543
c906108c
SS		 2544 * sim-main.c (ifetch16, ifetch32): Update to match current
2545 implementations of LH, LW.
2546 (signal_exception): Don't print out incorrect hex value of illegal
2547 instruction.
2548
2549Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2552 instruction.
2553
2554 * m16.igen: Implement MIPS16 instructions.
72f4393d 2555
c906108c
SS		 2556 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2557 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2558 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2559 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2560 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2561 bodies of corresponding code from 32 bit insn to these. Also used
2562 by MIPS16 versions of functions.
72f4393d 2563
c906108c
SS		 2564 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2565 (IMEM16): Drop NR argument from macro.
2566
2567Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2568
2569 * Makefile.in (SIM_OBJS): Add sim-main.o.
2570
2571 * sim-main.h (address_translation, load_memory, store_memory,
2572 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2573 as INLINE_SIM_MAIN.
2574 (pr_addr, pr_uword64): Declare.
2575 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2576
c906108c
SS		 2577 * interp.c (address_translation, load_memory, store_memory,
2578 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2579 from here.
2580 * sim-main.c: To here. Fix compilation problems.
72f4393d 2581
c906108c
SS		 2582 * configure.in: Enable inlining.
2583 * configure: Re-config.
2584
2585Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2586
2587 * configure: Regenerated to track ../common/aclocal.m4 changes.
2588
2589Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2590
2591 * mips.igen: Include tx.igen.
2592 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2593 * tx.igen: New file, contains MADD and MADDU.
2594
2595 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2596 the hardwired constant `7'.
2597 (store_memory): Ditto.
2598 (LOADDRMASK): Move definition to sim-main.h.
2599
2600 mips.igen (MTC0): Enable for r3900.
2601 (ADDU): Add trace.
2602
2603 mips.igen (do_load_byte): Delete.
2604 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2605 do_store_right): New functions.
2606 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2607
2608 configure.in: Let the tx39 use igen again.
2609 configure: Update.
72f4393d 2610
c906108c
SS		 2611Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2614 not an address sized quantity. Return zero for cache sizes.
2615
2616Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2617
2618 * mips.igen (r3900): r3900 does not support 64 bit integer
2619 operations.
2620
2621Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2622
2623 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2624 than igen one.
2625 * configure : Rebuild.
72f4393d 2626
c906108c
SS		 2627Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * configure: Regenerated to track ../common/aclocal.m4 changes.
2630
2631Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2634
2635Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2636
2637 * configure: Regenerated to track ../common/aclocal.m4 changes.
2638 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2639
2640Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2643
2644Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * interp.c (Max, Min): Comment out functions. Not yet used.
2647
2648Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2649
2650 * configure: Regenerated to track ../common/aclocal.m4 changes.
2651
2652Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2653
2654 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2655 configurable settings for stand-alone simulator.
72f4393d 2656
c906108c 2657 * configure.in: Added X11 search, just in case.
72f4393d 2658
c906108c
SS		 2659 * configure: Regenerated.
2660
2661Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * interp.c (sim_write, sim_read, load_memory, store_memory):
2664 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2665
2666Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2667
2668 * sim-main.h (GETFCC): Return an unsigned value.
2669
2670Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2671
2672 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2673 (DADD): Result destination is RD not RT.
2674
2675Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2676
2677 * sim-main.h (HIACCESS, LOACCESS): Always define.
2678
2679 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2680
2681 * interp.c (sim_info): Delete.
2682
2683Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2684
2685 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2686 (mips_option_handler): New argument `cpu'.
2687 (sim_open): Update call to sim_add_option_table.
2688
2689Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2690
2691 * mips.igen (CxC1): Add tracing.
2692
2693Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * sim-main.h (Max, Min): Declare.
2696
2697 * interp.c (Max, Min): New functions.
2698
2699 * mips.igen (BC1): Add tracing.
72f4393d 2700
c906108c 2701Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2702
c906108c 2703 * interp.c Added memory map for stack in vr4100
72f4393d 2704
c906108c
SS		 2705Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2706
2707 * interp.c (load_memory): Add missing "break"'s.
2708
2709Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2710
2711 * interp.c (sim_store_register, sim_fetch_register): Pass in
2712 length parameter. Return -1.
2713
2714Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2715
2716 * interp.c: Added hardware init hook, fixed warnings.
2717
2718Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2719
2720 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2721
2722Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2723
2724 * interp.c (ifetch16): New function.
2725
2726 * sim-main.h (IMEM32): Rename IMEM.
2727 (IMEM16_IMMED): Define.
2728 (IMEM16): Define.
2729 (DELAY_SLOT): Update.
72f4393d 2730
c906108c 2731 * m16run.c (sim_engine_run): New file.
72f4393d 2732
c906108c
SS		 2733 * m16.igen: All instructions except LB.
2734 (LB): Call do_load_byte.
2735 * mips.igen (do_load_byte): New function.
2736 (LB): Call do_load_byte.
2737
2738 * mips.igen: Move spec for insn bit size and high bit from here.
2739 * Makefile.in (tmp-igen, tmp-m16): To here.
2740
2741 * m16.dc: New file, decode mips16 instructions.
2742
2743 * Makefile.in (SIM_NO_ALL): Define.
2744 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2745
2746Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2747
2748 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2749 point unit to 32 bit registers.
2750 * configure: Re-generate.
2751
2752Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2753
2754 * configure.in (sim_use_gen): Make IGEN the default simulator
2755 generator for generic 32 and 64 bit mips targets.
2756 * configure: Re-generate.
2757
2758Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2761 bitsize.
2762
2763 * interp.c (sim_fetch_register, sim_store_register): Read/write
2764 FGR from correct location.
2765 (sim_open): Set size of FGR's according to
2766 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2767
c906108c
SS		 2768 * sim-main.h (FGR): Store floating point registers in a separate
2769 array.
2770
2771Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2772
2773 * configure: Regenerated to track ../common/aclocal.m4 changes.
2774
2775Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2776
2777 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2778
2779 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2780
2781 * interp.c (pending_tick): New function. Deliver pending writes.
2782
2783 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2784 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2785 it can handle mixed sized quantites and single bits.
72f4393d 2786
c906108c
SS		 2787Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2788
2789 * interp.c (oengine.h): Do not include when building with IGEN.
2790 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2791 (sim_info): Ditto for PROCESSOR_64BIT.
2792 (sim_monitor): Replace ut_reg with unsigned_word.
2793 (*): Ditto for t_reg.
2794 (LOADDRMASK): Define.
2795 (sim_open): Remove defunct check that host FP is IEEE compliant,
2796 using software to emulate floating point.
2797 (value_fpr, ...): Always compile, was conditional on HASFPU.
2798
2799Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2800
2801 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2802 size.
2803
2804 * interp.c (SD, CPU): Define.
2805 (mips_option_handler): Set flags in each CPU.
2806 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2807 (sim_close): Do not clear STATE, deleted anyway.
2808 (sim_write, sim_read): Assume CPU zero's vm should be used for
2809 data transfers.
2810 (sim_create_inferior): Set the PC for all processors.
2811 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2812 argument.
2813 (mips16_entry): Pass correct nr of args to store_word, load_word.
2814 (ColdReset): Cold reset all cpu's.
2815 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2816 (sim_monitor, load_memory, store_memory, signal_exception): Use
2817 `CPU' instead of STATE_CPU.
2818
2819
2820 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2821 SD or CPU_.
72f4393d 2822
c906108c
SS		 2823 * sim-main.h (signal_exception): Add sim_cpu arg.
2824 (SignalException*): Pass both SD and CPU to signal_exception.
2825 * interp.c (signal_exception): Update.
72f4393d 2826
c906108c
SS		 2827 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2828 Ditto
2829 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2830 address_translation): Ditto
2831 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2832
c906108c
SS		 2833Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * configure: Regenerated to track ../common/aclocal.m4 changes.
2836
2837Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2838
2839 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2840
72f4393d 2841 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2842
2843 * sim-main.h (CPU_CIA): Delete.
2844 (SET_CIA, GET_CIA): Define
2845
2846Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2847
2848 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2849 regiser.
2850
2851 * configure.in (default_endian): Configure a big-endian simulator
2852 by default.
2853 * configure: Re-generate.
72f4393d 2854
c906108c
SS		 2855Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2856
2857 * configure: Regenerated to track ../common/aclocal.m4 changes.
2858
2859Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2860
2861 * interp.c (sim_monitor): Handle Densan monitor outbyte
2862 and inbyte functions.
2863
28641997-12-29 Felix Lee <flee@cygnus.com>
2865
2866 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2867
2868Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2869
2870 * Makefile.in (tmp-igen): Arrange for $zero to always be
2871 reset to zero after every instruction.
2872
2873Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2874
2875 * configure: Regenerated to track ../common/aclocal.m4 changes.
2876 * config.in: Ditto.
2877
2878Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2879
2880 * mips.igen (MSUB): Fix to work like MADD.
2881 * gencode.c (MSUB): Similarly.
2882
2883Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2884
2885 * configure: Regenerated to track ../common/aclocal.m4 changes.
2886
2887Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2888
2889 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2890
2891Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2892
2893 * sim-main.h (sim-fpu.h): Include.
2894
2895 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2896 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2897 using host independant sim_fpu module.
2898
2899Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2900
2901 * interp.c (signal_exception): Report internal errors with SIGABRT
2902 not SIGQUIT.
2903
2904 * sim-main.h (C0_CONFIG): New register.
2905 (signal.h): No longer include.
2906
2907 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2908
2909Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2910
2911 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2912
2913Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2914
2915 * mips.igen: Tag vr5000 instructions.
2916 (ANDI): Was missing mipsIV model, fix assembler syntax.
2917 (do_c_cond_fmt): New function.
2918 (C.cond.fmt): Handle mips I-III which do not support CC field
2919 separatly.
2920 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2921 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2922 in IV3.2 spec.
2923 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2924 vr5000 which saves LO in a GPR separatly.
72f4393d 2925
c906108c
SS		 2926 * configure.in (enable-sim-igen): For vr5000, select vr5000
2927 specific instructions.
2928 * configure: Re-generate.
72f4393d 2929
c906108c
SS		 2930Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2933
2934 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2935 fmt_uninterpreted_64 bit cases to switch. Convert to
2936 fmt_formatted,
2937
2938 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2939
2940 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2941 as specified in IV3.2 spec.
2942 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2943
2944Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2945
2946 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2947 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2948 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2949 PENDING_FILL versions of instructions. Simplify.
2950 (X): New function.
2951 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2952 instructions.
2953 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2954 a signed value.
2955 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2956
c906108c
SS		 2957 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2958 global.
2959 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2960
2961Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2962
2963 * gencode.c (build_mips16_operands): Replace IPC with cia.
2964
2965 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2966 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2967 IPC to `cia'.
2968 (UndefinedResult): Replace function with macro/function
2969 combination.
2970 (sim_engine_run): Don't save PC in IPC.
2971
2972 * sim-main.h (IPC): Delete.
2973
2974
2975 * interp.c (signal_exception, store_word, load_word,
2976 address_translation, load_memory, store_memory, cache_op,
2977 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2978 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2979 current instruction address - cia - argument.
2980 (sim_read, sim_write): Call address_translation directly.
2981 (sim_engine_run): Rename variable vaddr to cia.
2982 (signal_exception): Pass cia to sim_monitor
72f4393d 2983
c906108c
SS		 2984 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2985 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2986 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2987
2988 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2989 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2990 SIM_ASSERT.
72f4393d 2991
c906108c
SS		 2992 * interp.c (signal_exception): Pass restart address to
2993 sim_engine_restart.
2994
2995 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2996 idecode.o): Add dependency.
2997
2998 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2999 Delete definitions
3000 (DELAY_SLOT): Update NIA not PC with branch address.
3001 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
3002
3003 * mips.igen: Use CIA not PC in branch calculations.
3004 (illegal): Call SignalException.
3005 (BEQ, ADDIU): Fix assembler.
3006
3007Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3008
3009 * m16.igen (JALX): Was missing.
3010
3011 * configure.in (enable-sim-igen): New configuration option.
3012 * configure: Re-generate.
72f4393d 3013
c906108c
SS		 3014 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
3015
3016 * interp.c (load_memory, store_memory): Delete parameter RAW.
3017 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
3018 bypassing {load,store}_memory.
3019
3020 * sim-main.h (ByteSwapMem): Delete definition.
3021
3022 * Makefile.in (SIM_OBJS): Add sim-memopt module.
3023
3024 * interp.c (sim_do_command, sim_commands): Delete mips specific
3025 commands. Handled by module sim-options.
72f4393d 3026
c906108c
SS		 3027 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
3028 (WITH_MODULO_MEMORY): Define.
3029
3030 * interp.c (sim_info): Delete code printing memory size.
3031
3032 * interp.c (mips_size): Nee sim_size, delete function.
3033 (power2): Delete.
3034 (monitor, monitor_base, monitor_size): Delete global variables.
3035 (sim_open, sim_close): Delete code creating monitor and other
3036 memory regions. Use sim-memopts module, via sim_do_commandf, to
3037 manage memory regions.
3038 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 3039
c906108c
SS		 3040 * interp.c (address_translation): Delete all memory map code
3041 except line forcing 32 bit addresses.
3042
3043Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * sim-main.h (WITH_TRACE): Delete definition. Enables common
3046 trace options.
3047
3048 * interp.c (logfh, logfile): Delete globals.
3049 (sim_open, sim_close): Delete code opening & closing log file.
3050 (mips_option_handler): Delete -l and -n options.
3051 (OPTION mips_options): Ditto.
3052
3053 * interp.c (OPTION mips_options): Rename option trace to dinero.
3054 (mips_option_handler): Update.
3055
3056Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3057
3058 * interp.c (fetch_str): New function.
3059 (sim_monitor): Rewrite using sim_read & sim_write.
3060 (sim_open): Check magic number.
3061 (sim_open): Write monitor vectors into memory using sim_write.
3062 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3063 (sim_read, sim_write): Simplify - transfer data one byte at a
3064 time.
3065 (load_memory, store_memory): Clarify meaning of parameter RAW.
3066
3067 * sim-main.h (isHOST): Defete definition.
3068 (isTARGET): Mark as depreciated.
3069 (address_translation): Delete parameter HOST.
3070
3071 * interp.c (address_translation): Delete parameter HOST.
3072
3073Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
72f4393d 3075 * mips.igen:
c906108c
SS		 3076
3077 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3078 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3079
3080Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3081
3082 * mips.igen: Add model filter field to records.
3083
3084Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3085
3086 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3087
c906108c
SS		 3088 interp.c (sim_engine_run): Do not compile function sim_engine_run
3089 when WITH_IGEN == 1.
3090
3091 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3092 target architecture.
3093
3094 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3095 igen. Replace with configuration variables sim_igen_flags /
3096 sim_m16_flags.
3097
3098 * m16.igen: New file. Copy mips16 insns here.
3099 * mips.igen: From here.
3100
3101Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3104 to top.
3105 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3106
3107Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3108
3109 * gencode.c (build_instruction): Follow sim_write's lead in using
3110 BigEndianMem instead of !ByteSwapMem.
3111
3112Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3113
3114 * configure.in (sim_gen): Dependent on target, select type of
3115 generator. Always select old style generator.
3116
3117 configure: Re-generate.
3118
3119 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3120 targets.
3121 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3122 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3123 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3124 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3125 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3126
c906108c
SS		 3127Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3130
3131 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3132 CURRENT_FLOATING_POINT instead.
3133
3134 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3135 (address_translation): Raise exception InstructionFetch when
3136 translation fails and isINSTRUCTION.
72f4393d 3137
c906108c
SS		 3138 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3139 sim_engine_run): Change type of of vaddr and paddr to
3140 address_word.
3141 (address_translation, prefetch, load_memory, store_memory,
3142 cache_op): Change type of vAddr and pAddr to address_word.
3143
3144 * gencode.c (build_instruction): Change type of vaddr and paddr to
3145 address_word.
3146
3147Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3148
3149 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3150 macro to obtain result of ALU op.
3151
3152Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3153
3154 * interp.c (sim_info): Call profile_print.
3155
3156Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3157
3158 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3159
3160 * sim-main.h (WITH_PROFILE): Do not define, defined in
3161 common/sim-config.h. Use sim-profile module.
3162 (simPROFILE): Delete defintion.
3163
3164 * interp.c (PROFILE): Delete definition.
3165 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3166 (sim_close): Delete code writing profile histogram.
3167 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3168 Delete.
3169 (sim_engine_run): Delete code profiling the PC.
3170
3171Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3172
3173 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3174
3175 * interp.c (sim_monitor): Make register pointers of type
3176 unsigned_word*.
3177
3178 * sim-main.h: Make registers of type unsigned_word not
3179 signed_word.
3180
3181Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3182
3183 * interp.c (sync_operation): Rename from SyncOperation, make
3184 global, add SD argument.
3185 (prefetch): Rename from Prefetch, make global, add SD argument.
3186 (decode_coproc): Make global.
3187
3188 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3189
3190 * gencode.c (build_instruction): Generate DecodeCoproc not
3191 decode_coproc calls.
3192
3193 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3194 (SizeFGR): Move to sim-main.h
3195 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3196 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3197 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3198 sim-main.h.
3199 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3200 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3201 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3202 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3203 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3204 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3205
c906108c
SS		 3206 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3207 exception.
3208 (sim-alu.h): Include.
3209 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3210 (sim_cia): Typedef to instruction_address.
72f4393d 3211
c906108c
SS		 3212Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3213
3214 * Makefile.in (interp.o): Rename generated file engine.c to
3215 oengine.c.
72f4393d 3216
c906108c 3217 * interp.c: Update.
72f4393d 3218
c906108c
SS		 3219Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220
3221 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3222
c906108c
SS		 3223Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3224
3225 * gencode.c (build_instruction): For "FPSQRT", output correct
3226 number of arguments to Recip.
72f4393d 3227
c906108c
SS		 3228Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3229
3230 * Makefile.in (interp.o): Depends on sim-main.h
3231
3232 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3233
3234 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3235 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3236 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3237 STATE, DSSTATE): Define
3238 (GPR, FGRIDX, ..): Define.
3239
3240 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3241 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3242 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3243
c906108c 3244 * interp.c: Update names to match defines from sim-main.h
72f4393d 3245
c906108c
SS		 3246Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3247
3248 * interp.c (sim_monitor): Add SD argument.
3249 (sim_warning): Delete. Replace calls with calls to
3250 sim_io_eprintf.
3251 (sim_error): Delete. Replace calls with sim_io_error.
3252 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3253 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3254 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3255 argument.
3256 (mips_size): Rename from sim_size. Add SD argument.
3257
3258 * interp.c (simulator): Delete global variable.
3259 (callback): Delete global variable.
3260 (mips_option_handler, sim_open, sim_write, sim_read,
3261 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3262 sim_size,sim_monitor): Use sim_io_* not callback->*.
3263 (sim_open): ZALLOC simulator struct.
3264 (PROFILE): Do not define.
3265
3266Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3267
3268 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3269 support.h with corresponding code.
3270
3271 * sim-main.h (word64, uword64), support.h: Move definition to
3272 sim-main.h.
3273 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3274
3275 * support.h: Delete
3276 * Makefile.in: Update dependencies
3277 * interp.c: Do not include.
72f4393d 3278
c906108c
SS		 3279Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3280
3281 * interp.c (address_translation, load_memory, store_memory,
3282 cache_op): Rename to from AddressTranslation et.al., make global,
3283 add SD argument
72f4393d 3284
c906108c
SS		 3285 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3286 CacheOp): Define.
72f4393d 3287
c906108c
SS		 3288 * interp.c (SignalException): Rename to signal_exception, make
3289 global.
3290
3291 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3292
c906108c
SS		 3293 * sim-main.h (SignalException, SignalExceptionInterrupt,
3294 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3295 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3296 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3297 Define.
72f4393d 3298
c906108c 3299 * interp.c, support.h: Use.
72f4393d 3300
c906108c
SS		 3301Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3302
3303 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3304 to value_fpr / store_fpr. Add SD argument.
3305 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3306 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3307
3308 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3309
c906108c
SS		 3310Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3311
3312 * interp.c (sim_engine_run): Check consistency between configure
3313 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3314 and HASFPU.
3315
3316 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3317 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3318 (mips_endian): Configure WITH_TARGET_ENDIAN.
3319 * configure: Update.
3320
3321Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3322
3323 * configure: Regenerated to track ../common/aclocal.m4 changes.
3324
3325Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3326
3327 * configure: Regenerated.
3328
3329Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3330
3331 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3332
3333Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3334
3335 * gencode.c (print_igen_insn_models): Assume certain architectures
3336 include all mips* instructions.
3337 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3338 instruction.
3339
3340 * Makefile.in (tmp.igen): Add target. Generate igen input from
3341 gencode file.
3342
3343 * gencode.c (FEATURE_IGEN): Define.
3344 (main): Add --igen option. Generate output in igen format.
3345 (process_instructions): Format output according to igen option.
3346 (print_igen_insn_format): New function.
3347 (print_igen_insn_models): New function.
3348 (process_instructions): Only issue warnings and ignore
3349 instructions when no FEATURE_IGEN.
3350
3351Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3352
3353 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3354 MIPS targets.
3355
3356Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3357
3358 * configure: Regenerated to track ../common/aclocal.m4 changes.
3359
3360Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3361
3362 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3363 SIM_RESERVED_BITS): Delete, moved to common.
3364 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3365
c906108c
SS		 3366Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3367
3368 * configure.in: Configure non-strict memory alignment.
3369 * configure: Regenerated to track ../common/aclocal.m4 changes.
3370
3371Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * configure: Regenerated to track ../common/aclocal.m4 changes.
3374
3375Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3376
3377 * gencode.c (SDBBP,DERET): Added (3900) insns.
3378 (RFE): Turn on for 3900.
3379 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3380 (dsstate): Made global.
3381 (SUBTARGET_R3900): Added.
3382 (CANCELDELAYSLOT): New.
3383 (SignalException): Ignore SystemCall rather than ignore and
3384 terminate. Add DebugBreakPoint handling.
3385 (decode_coproc): New insns RFE, DERET; and new registers Debug
3386 and DEPC protected by SUBTARGET_R3900.
3387 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3388 bits explicitly.
3389 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3390 * configure: Update.
c906108c
SS		 3391
3392Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3393
3394 * gencode.c: Add r3900 (tx39).
72f4393d 3395
c906108c
SS		 3396
3397Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3398
3399 * gencode.c (build_instruction): Don't need to subtract 4 for
3400 JALR, just 2.
3401
3402Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3403
3404 * interp.c: Correct some HASFPU problems.
3405
3406Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3407
3408 * configure: Regenerated to track ../common/aclocal.m4 changes.
3409
3410Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3411
3412 * interp.c (mips_options): Fix samples option short form, should
3413 be `x'.
3414
3415Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3416
3417 * interp.c (sim_info): Enable info code. Was just returning.
3418
3419Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3420
3421 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3422 MFC0.
3423
3424Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3425
3426 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3427 constants.
3428 (build_instruction): Ditto for LL.
3429
3430Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3431
3432 * configure: Regenerated to track ../common/aclocal.m4 changes.
3433
3434Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3435
3436 * configure: Regenerated to track ../common/aclocal.m4 changes.
3437 * config.in: Ditto.
3438
3439Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3440
3441 * interp.c (sim_open): Add call to sim_analyze_program, update
3442 call to sim_config.
3443
3444Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3445
3446 * interp.c (sim_kill): Delete.
3447 (sim_create_inferior): Add ABFD argument. Set PC from same.
3448 (sim_load): Move code initializing trap handlers from here.
3449 (sim_open): To here.
3450 (sim_load): Delete, use sim-hload.c.
3451
3452 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3453
3454Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3455
3456 * configure: Regenerated to track ../common/aclocal.m4 changes.
3457 * config.in: Ditto.
3458
3459Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3460
3461 * interp.c (sim_open): Add ABFD argument.
3462 (sim_load): Move call to sim_config from here.
3463 (sim_open): To here. Check return status.
3464
3465Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3466
c906108c
SS		 3467 * gencode.c (build_instruction): Two arg MADD should
3468 not assign result to $0.
72f4393d 3469
c906108c
SS		 3470Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3471
3472 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3473 * sim/mips/configure.in: Regenerate.
3474
3475Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3476
3477 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3478 signed8, unsigned8 et.al. types.
3479
3480 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3481 hosts when selecting subreg.
3482
3483Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3484
3485 * interp.c (sim_engine_run): Reset the ZERO register to zero
3486 regardless of FEATURE_WARN_ZERO.
3487 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3488
3489Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3490
3491 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3492 (SignalException): For BreakPoints ignore any mode bits and just
3493 save the PC.
3494 (SignalException): Always set the CAUSE register.
3495
3496Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3497
3498 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3499 exception has been taken.
3500
3501 * interp.c: Implement the ERET and mt/f sr instructions.
3502
3503Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3504
3505 * interp.c (SignalException): Don't bother restarting an
3506 interrupt.
3507
3508Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3509
3510 * interp.c (SignalException): Really take an interrupt.
3511 (interrupt_event): Only deliver interrupts when enabled.
3512
3513Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3514
3515 * interp.c (sim_info): Only print info when verbose.
3516 (sim_info) Use sim_io_printf for output.
72f4393d 3517
c906108c
SS		 3518Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3519
3520 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3521 mips architectures.
3522
3523Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3524
3525 * interp.c (sim_do_command): Check for common commands if a
3526 simulator specific command fails.
3527
3528Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3529
3530 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3531 and simBE when DEBUG is defined.
3532
3533Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3534
3535 * interp.c (interrupt_event): New function. Pass exception event
3536 onto exception handler.
3537
3538 * configure.in: Check for stdlib.h.
3539 * configure: Regenerate.
3540
3541 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3542 variable declaration.
3543 (build_instruction): Initialize memval1.
3544 (build_instruction): Add UNUSED attribute to byte, bigend,
3545 reverse.
3546 (build_operands): Ditto.
3547
3548 * interp.c: Fix GCC warnings.
3549 (sim_get_quit_code): Delete.
3550
3551 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3552 * Makefile.in: Ditto.
3553 * configure: Re-generate.
72f4393d 3554
c906108c
SS		 3555 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3556
3557Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3558
3559 * interp.c (mips_option_handler): New function parse argumes using
3560 sim-options.
3561 (myname): Replace with STATE_MY_NAME.
3562 (sim_open): Delete check for host endianness - performed by
3563 sim_config.
3564 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3565 (sim_open): Move much of the initialization from here.
3566 (sim_load): To here. After the image has been loaded and
3567 endianness set.
3568 (sim_open): Move ColdReset from here.
3569 (sim_create_inferior): To here.
3570 (sim_open): Make FP check less dependant on host endianness.
3571
3572 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3573 run.
3574 * interp.c (sim_set_callbacks): Delete.
3575
3576 * interp.c (membank, membank_base, membank_size): Replace with
3577 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3578 (sim_open): Remove call to callback->init. gdb/run do this.
3579
3580 * interp.c: Update
3581
3582 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3583
3584 * interp.c (big_endian_p): Delete, replaced by
3585 current_target_byte_order.
3586
3587Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3588
3589 * interp.c (host_read_long, host_read_word, host_swap_word,
3590 host_swap_long): Delete. Using common sim-endian.
3591 (sim_fetch_register, sim_store_register): Use H2T.
3592 (pipeline_ticks): Delete. Handled by sim-events.
3593 (sim_info): Update.
3594 (sim_engine_run): Update.
3595
3596Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3597
3598 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3599 reason from here.
3600 (SignalException): To here. Signal using sim_engine_halt.
3601 (sim_stop_reason): Delete, moved to common.
72f4393d 3602
c906108c
SS		 3603Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3604
3605 * interp.c (sim_open): Add callback argument.
3606 (sim_set_callbacks): Delete SIM_DESC argument.
3607 (sim_size): Ditto.
3608
3609Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3610
3611 * Makefile.in (SIM_OBJS): Add common modules.
3612
3613 * interp.c (sim_set_callbacks): Also set SD callback.
3614 (set_endianness, xfer_*, swap_*): Delete.
3615 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3616 Change to functions using sim-endian macros.
3617 (control_c, sim_stop): Delete, use common version.
3618 (simulate): Convert into.
3619 (sim_engine_run): This function.
3620 (sim_resume): Delete.
72f4393d 3621
c906108c
SS		 3622 * interp.c (simulation): New variable - the simulator object.
3623 (sim_kind): Delete global - merged into simulation.
3624 (sim_load): Cleanup. Move PC assignment from here.
3625 (sim_create_inferior): To here.
3626
3627 * sim-main.h: New file.
3628 * interp.c (sim-main.h): Include.
72f4393d 3629
c906108c
SS		 3630Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3631
3632 * configure: Regenerated to track ../common/aclocal.m4 changes.
3633
3634Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3635
3636 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3637
3638Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3639
72f4393d
L		 3640 * gencode.c (build_instruction): DIV instructions: check
3641 for division by zero and integer overflow before using
c906108c
SS		 3642 host's division operation.
3643
3644Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3645
3646 * Makefile.in (SIM_OBJS): Add sim-load.o.
3647 * interp.c: #include bfd.h.
3648 (target_byte_order): Delete.
3649 (sim_kind, myname, big_endian_p): New static locals.
3650 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3651 after argument parsing. Recognize -E arg, set endianness accordingly.
3652 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3653 load file into simulator. Set PC from bfd.
3654 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3655 (set_endianness): Use big_endian_p instead of target_byte_order.
3656
3657Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3658
3659 * interp.c (sim_size): Delete prototype - conflicts with
3660 definition in remote-sim.h. Correct definition.
3661
3662Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3663
3664 * configure: Regenerated to track ../common/aclocal.m4 changes.
3665 * config.in: Ditto.
3666
3667Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3668
3669 * interp.c (sim_open): New arg `kind'.
3670
3671 * configure: Regenerated to track ../common/aclocal.m4 changes.
3672
3673Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3674
3675 * configure: Regenerated to track ../common/aclocal.m4 changes.
3676
3677Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3678
3679 * interp.c (sim_open): Set optind to 0 before calling getopt.
3680
3681Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3682
3683 * configure: Regenerated to track ../common/aclocal.m4 changes.
3684
3685Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3686
3687 * interp.c : Replace uses of pr_addr with pr_uword64
3688 where the bit length is always 64 independent of SIM_ADDR.
3689 (pr_uword64) : added.
3690
3691Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3692
3693 * configure: Re-generate.
3694
3695Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3696
3697 * configure: Regenerate to track ../common/aclocal.m4 changes.
3698
3699Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3700
3701 * interp.c (sim_open): New SIM_DESC result. Argument is now
3702 in argv form.
3703 (other sim_*): New SIM_DESC argument.
3704
3705Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3706
3707 * interp.c: Fix printing of addresses for non-64-bit targets.
3708 (pr_addr): Add function to print address based on size.
3709
3710Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3711
3712 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3713
3714Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3715
3716 * gencode.c (build_mips16_operands): Correct computation of base
3717 address for extended PC relative instruction.
3718
3719Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3720
3721 * interp.c (mips16_entry): Add support for floating point cases.
3722 (SignalException): Pass floating point cases to mips16_entry.
3723 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3724 registers.
3725 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3726 or fmt_word.
3727 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3728 and then set the state to fmt_uninterpreted.
3729 (COP_SW): Temporarily set the state to fmt_word while calling
3730 ValueFPR.
3731
3732Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3733
3734 * gencode.c (build_instruction): The high order may be set in the
3735 comparison flags at any ISA level, not just ISA 4.
3736
3737Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3738
3739 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3740 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3741 * configure.in: sinclude ../common/aclocal.m4.
3742 * configure: Regenerated.
3743
3744Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3745
3746 * configure: Rebuild after change to aclocal.m4.
3747
3748Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3749
3750 * configure configure.in Makefile.in: Update to new configure
3751 scheme which is more compatible with WinGDB builds.
3752 * configure.in: Improve comment on how to run autoconf.
3753 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3754 * Makefile.in: Use autoconf substitution to install common
3755 makefile fragment.
3756
3757Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3758
3759 * gencode.c (build_instruction): Use BigEndianCPU instead of
3760 ByteSwapMem.
3761
3762Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3763
3764 * interp.c (sim_monitor): Make output to stdout visible in
3765 wingdb's I/O log window.
3766
3767Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3768
3769 * support.h: Undo previous change to SIGTRAP
3770 and SIGQUIT values.
3771
3772Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3773
3774 * interp.c (store_word, load_word): New static functions.
3775 (mips16_entry): New static function.
3776 (SignalException): Look for mips16 entry and exit instructions.
3777 (simulate): Use the correct index when setting fpr_state after
3778 doing a pending move.
3779
3780Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3781
3782 * interp.c: Fix byte-swapping code throughout to work on
3783 both little- and big-endian hosts.
3784
3785Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3786
3787 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3788 with gdb/config/i386/xm-windows.h.
3789
3790Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3791
3792 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3793 that messes up arithmetic shifts.
3794
3795Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3796
3797 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3798 SIGTRAP and SIGQUIT for _WIN32.
3799
3800Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3801
3802 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3803 force a 64 bit multiplication.
3804 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3805 destination register is 0, since that is the default mips16 nop
3806 instruction.
3807
3808Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3809
3810 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3811 (build_endian_shift): Don't check proc64.
3812 (build_instruction): Always set memval to uword64. Cast op2 to
3813 uword64 when shifting it left in memory instructions. Always use
3814 the same code for stores--don't special case proc64.
3815
3816 * gencode.c (build_mips16_operands): Fix base PC value for PC
3817 relative operands.
3818 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3819 jal instruction.
3820 * interp.c (simJALDELAYSLOT): Define.
3821 (JALDELAYSLOT): Define.
3822 (INDELAYSLOT, INJALDELAYSLOT): Define.
3823 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3824
3825Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3826
3827 * interp.c (sim_open): add flush_cache as a PMON routine
3828 (sim_monitor): handle flush_cache by ignoring it
3829
3830Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3831
3832 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3833 BigEndianMem.
3834 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3835 (BigEndianMem): Rename to ByteSwapMem and change sense.
3836 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3837 BigEndianMem references to !ByteSwapMem.
3838 (set_endianness): New function, with prototype.
3839 (sim_open): Call set_endianness.
3840 (sim_info): Use simBE instead of BigEndianMem.
3841 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3842 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3843 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3844 ifdefs, keeping the prototype declaration.
3845 (swap_word): Rewrite correctly.
3846 (ColdReset): Delete references to CONFIG. Delete endianness related
3847 code; moved to set_endianness.
72f4393d 3848
c906108c
SS		 3849Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3850
3851 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3852 * interp.c (CHECKHILO): Define away.
3853 (simSIGINT): New macro.
3854 (membank_size): Increase from 1MB to 2MB.
3855 (control_c): New function.
3856 (sim_resume): Rename parameter signal to signal_number. Add local
3857 variable prev. Call signal before and after simulate.
3858 (sim_stop_reason): Add simSIGINT support.
3859 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3860 functions always.
3861 (sim_warning): Delete call to SignalException. Do call printf_filtered
3862 if logfh is NULL.
3863 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3864 a call to sim_warning.
3865
3866Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3867
3868 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3869 16 bit instructions.
3870
3871Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3872
3873 Add support for mips16 (16 bit MIPS implementation):
3874 * gencode.c (inst_type): Add mips16 instruction encoding types.
3875 (GETDATASIZEINSN): Define.
3876 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3877 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3878 mtlo.
3879 (MIPS16_DECODE): New table, for mips16 instructions.
3880 (bitmap_val): New static function.
3881 (struct mips16_op): Define.
3882 (mips16_op_table): New table, for mips16 operands.
3883 (build_mips16_operands): New static function.
3884 (process_instructions): If PC is odd, decode a mips16
3885 instruction. Break out instruction handling into new
3886 build_instruction function.
3887 (build_instruction): New static function, broken out of
3888 process_instructions. Check modifiers rather than flags for SHIFT
3889 bit count and m[ft]{hi,lo} direction.
3890 (usage): Pass program name to fprintf.
3891 (main): Remove unused variable this_option_optind. Change
3892 ``*loptarg++'' to ``loptarg++''.
3893 (my_strtoul): Parenthesize && within ||.
3894 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3895 (simulate): If PC is odd, fetch a 16 bit instruction, and
3896 increment PC by 2 rather than 4.
3897 * configure.in: Add case for mips16*-*-*.
3898 * configure: Rebuild.
3899
3900Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3901
3902 * interp.c: Allow -t to enable tracing in standalone simulator.
3903 Fix garbage output in trace file and error messages.
3904
3905Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3906
3907 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3908 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3909 * configure.in: Simplify using macros in ../common/aclocal.m4.
3910 * configure: Regenerated.
3911 * tconfig.in: New file.
3912
3913Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3914
3915 * interp.c: Fix bugs in 64-bit port.
3916 Use ansi function declarations for msvc compiler.
3917 Initialize and test file pointer in trace code.
3918 Prevent duplicate definition of LAST_EMED_REGNUM.
3919
3920Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3921
3922 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3923
3924Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3925
3926 * interp.c (SignalException): Check for explicit terminating
3927 breakpoint value.
3928 * gencode.c: Pass instruction value through SignalException()
3929 calls for Trap, Breakpoint and Syscall.
3930
3931Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3932
3933 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3934 only used on those hosts that provide it.
3935 * configure.in: Add sqrt() to list of functions to be checked for.
3936 * config.in: Re-generated.
3937 * configure: Re-generated.
3938
3939Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3940
3941 * gencode.c (process_instructions): Call build_endian_shift when
3942 expanding STORE RIGHT, to fix swr.
3943 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3944 clear the high bits.
3945 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3946 Fix float to int conversions to produce signed values.
3947
3948Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3949
3950 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3951 (process_instructions): Correct handling of nor instruction.
3952 Correct shift count for 32 bit shift instructions. Correct sign
3953 extension for arithmetic shifts to not shift the number of bits in
3954 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3955 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3956 Fix madd.
3957 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3958 It's OK to have a mult follow a mult. What's not OK is to have a
3959 mult follow an mfhi.
3960 (Convert): Comment out incorrect rounding code.
3961
3962Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3963
3964 * interp.c (sim_monitor): Improved monitor printf
3965 simulation. Tidied up simulator warnings, and added "--log" option
3966 for directing warning message output.
3967 * gencode.c: Use sim_warning() rather than WARNING macro.
3968
3969Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3970
3971 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3972 getopt1.o, rather than on gencode.c. Link objects together.
3973 Don't link against -liberty.
3974 (gencode.o, getopt.o, getopt1.o): New targets.
3975 * gencode.c: Include <ctype.h> and "ansidecl.h".
3976 (AND): Undefine after including "ansidecl.h".
3977 (ULONG_MAX): Define if not defined.
3978 (OP_*): Don't define macros; now defined in opcode/mips.h.
3979 (main): Call my_strtoul rather than strtoul.
3980 (my_strtoul): New static function.
3981
3982Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3983
3984 * gencode.c (process_instructions): Generate word64 and uword64
3985 instead of `long long' and `unsigned long long' data types.
3986 * interp.c: #include sysdep.h to get signals, and define default
3987 for SIGBUS.
3988 * (Convert): Work around for Visual-C++ compiler bug with type
3989 conversion.
3990 * support.h: Make things compile under Visual-C++ by using
3991 __int64 instead of `long long'. Change many refs to long long
3992 into word64/uword64 typedefs.
3993
3994Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3995
72f4393d
L		 3996 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3997 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3998 (docdir): Removed.
3999 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
4000 (AC_PROG_INSTALL): Added.
c906108c 4001 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 4002 * configure: Rebuilt.
4003
c906108c
SS		 4004Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
4005
4006 * configure.in: Define @SIMCONF@ depending on mips target.
4007 * configure: Rebuild.
4008 * Makefile.in (run): Add @SIMCONF@ to control simulator
4009 construction.
4010 * gencode.c: Change LOADDRMASK to 64bit memory model only.
4011 * interp.c: Remove some debugging, provide more detailed error
4012 messages, update memory accesses to use LOADDRMASK.
72f4393d 4013
c906108c
SS		 4014Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
4015
4016 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
4017 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
4018 stamp-h.
4019 * configure: Rebuild.
4020 * config.in: New file, generated by autoheader.
4021 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
4022 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
4023 HAVE_ANINT and HAVE_AINT, as appropriate.
4024 * Makefile.in (run): Use @LIBS@ rather than -lm.
4025 (interp.o): Depend upon config.h.
4026 (Makefile): Just rebuild Makefile.
4027 (clean): Remove stamp-h.
4028 (mostlyclean): Make the same as clean, not as distclean.
4029 (config.h, stamp-h): New targets.
4030
4031Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
4032
4033 * interp.c (ColdReset): Fix boolean test. Make all simulator
4034 globals static.
4035
4036Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
4037
4038 * interp.c (xfer_direct_word, xfer_direct_long,
4039 swap_direct_word, swap_direct_long, xfer_big_word,
4040 xfer_big_long, xfer_little_word, xfer_little_long,
4041 swap_word,swap_long): Added.
4042 * interp.c (ColdReset): Provide function indirection to
4043 host<->simulated_target transfer routines.
4044 * interp.c (sim_store_register, sim_fetch_register): Updated to
4045 make use of indirected transfer routines.
4046
4047Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4048
4049 * gencode.c (process_instructions): Ensure FP ABS instruction
4050 recognised.
4051 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4052 system call support.
4053
4054Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4055
4056 * interp.c (sim_do_command): Complain if callback structure not
4057 initialised.
4058
4059Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4060
4061 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4062 support for Sun hosts.
4063 * Makefile.in (gencode): Ensure the host compiler and libraries
4064 used for cross-hosted build.
4065
4066Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4067
4068 * interp.c, gencode.c: Some more (TODO) tidying.
4069
4070Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4071
4072 * gencode.c, interp.c: Replaced explicit long long references with
4073 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4074 * support.h (SET64LO, SET64HI): Macros added.
4075
4076Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4077
4078 * configure: Regenerate with autoconf 2.7.
4079
4080Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4081
4082 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4083 * support.h: Remove superfluous "1" from #if.
4084 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4085
4086Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4087
4088 * interp.c (StoreFPR): Control UndefinedResult() call on
4089 WARN_RESULT manifest.
4090
4091Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4092
4093 * gencode.c: Tidied instruction decoding, and added FP instruction
4094 support.
4095
4096 * interp.c: Added dineroIII, and BSD profiling support. Also
4097 run-time FP handling.
4098
4099Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4100
4101 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4102 gencode.c, interp.c, support.h: created.
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