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sim: split sim-signal.h include out
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
1fef66b0
MF		 12021-06-18 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c: Include sim-signal.h.
4
f9a4d543
MF		 52021-06-17 Mike Frysinger <vapier@gentoo.org>
6
7 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
8 * aclocal.m4, configure: Regenerate.
9
b80d4475
MF		 102021-06-16 Mike Frysinger <vapier@gentoo.org>
11
12 * interp.c (dotrace): Make comment const.
13 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
14
6828a302
MF		 152021-06-16 Mike Frysinger <vapier@gentoo.org>
16
17 * interp.c (sim_monitor): Change ap type to address_word*.
18 (_P, P): New macros. Rewrite dynamic printf logic to use these.
19
df32b446
MF		 202021-06-16 Mike Frysinger <vapier@gentoo.org>
21
22 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
23 unsigned_1.
24
7b2298cb
MF		 252021-06-16 Mike Frysinger <vapier@gentoo.org>
26
27 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
28 register_value to 0.
29
a8a3d907
MF		 302021-06-16 Mike Frysinger <vapier@gentoo.org>
31
32 * configure: Regenerate.
33
dae666c9
MF		 342021-06-16 Mike Frysinger <vapier@gentoo.org>
35
36 * interp.c (sim_open): Change %lx to %x and PRIx macros.
37
52d37d2c
MF		 382021-06-16 Mike Frysinger <vapier@gentoo.org>
39
40 * configure: Regenerate.
41 * config.in: Removed.
42
bcaa61f7
MF		 432021-06-15 Mike Frysinger <vapier@gentoo.org>
44
45 * config.in, configure: Regenerate.
46
ba307cdd
MF		 472021-06-12 Mike Frysinger <vapier@gentoo.org>
48
49 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
50
dba333c1
MF		 512021-06-12 Mike Frysinger <vapier@gentoo.org>
52
53 * aclocal.m4, config.in, configure: Regenerate.
54
b15c5d7a
MF		 552021-06-12 Mike Frysinger <vapier@gentoo.org>
56
57 * configure.ac: Delete call to AC_CHECK_FUNCS.
58 * config.in, configure: Regenerate.
59
a55b92be
MF		 602021-06-08 Mike Frysinger <vapier@gentoo.org>
61
62 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
63 with $(IGEN).
64
8ea881d9
MF		 652021-05-29 Mike Frysinger <vapier@gentoo.org>
66
67 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
68
b312488f
FS		 692021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
70
168671c1
FS		 71 * interp.c (sim_open): Add shadow mappings from 32-bit
72 address space to 64-bit sign-extended address space.
73
742021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
75
b312488f
FS		 76 * interp.c (sim_create_inferior): Only truncate sign extension
77 bits for 32-bit target models.
78
f4fdd845
MF		 792021-05-17 Mike Frysinger <vapier@gentoo.org>
80
81 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
82
8ea7241c
MF		 832021-05-17 Mike Frysinger <vapier@gentoo.org>
84
85 * interp.c (sim_open): Switch to sim_state_alloc_extra.
86 * micromips.igen: Change SD to mips_sim_state.
87 * micromipsrun.c (sim_engine_run): Likewise.
88 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
89 (watch_options_install): Delete.
90 (struct swatch): Delete.
91 (struct sim_state): Delete.
92 (struct mips_sim_state): New struct.
93 (MIPS_SIM_STATE): Define.
94
6df01ab8
MF		 952021-05-16 Mike Frysinger <vapier@gentoo.org>
96
97 * interp.c: Replace config.h include with defs.h.
98 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
99 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
100 Include defs.h.
101
79633c12
MF		 1022021-05-16 Mike Frysinger <vapier@gentoo.org>
103
104 * config.in, configure: Regenerate.
105
df68e12b
MF		 1062021-05-14 Mike Frysinger <vapier@gentoo.org>
107
108 * interp.c: Update include path.
109
77c0fdb7
MF		 1102021-05-04 Mike Frysinger <vapier@gentoo.org>
111
112 * dv-tx3904sio.c: Include stdlib.h.
113
9b1af85c
MF		 1142021-05-04 Mike Frysinger <vapier@gentoo.org>
115
116 * configure.ac (hw_extra_devices): Inline contents into
117 SIM_AC_OPTION_HARDWARE and delete.
118 * configure: Regenerate.
119
d97ba9c6
MF		 1202021-05-04 Mike Frysinger <vapier@gentoo.org>
121
122 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
123 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
124 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
125 * configure: Regenerate.
126
4df817de
MF		 1272021-05-04 Mike Frysinger <vapier@gentoo.org>
128
129 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
130
aa0fca16
MF		 1312021-05-04 Mike Frysinger <vapier@gentoo.org>
132
133 * configure: Regenerate.
134
adbaa7b8
MF		 1352021-05-01 Mike Frysinger <vapier@gentoo.org>
136
137 * cp1.c (store_fcr): Mark static.
138
fe348617
MF		 1392021-05-01 Mike Frysinger <vapier@gentoo.org>
140
141 * config.in, configure: Regenerate.
142
9d903352
MF		 1432021-04-23 Mike Frysinger <vapier@gentoo.org>
144
145 * configure.ac (hw_enabled): Delete.
146 (SIM_AC_OPTION_HARDWARE): Delete first two args.
147 * configure: Regenerate.
148
19f6a43c
TT		 1492021-04-22 Tom Tromey <tom@tromey.com>
150
151 * configure, config.in: Rebuild.
152
e7d8f1da
TT		 1532021-04-22 Tom Tromey <tom@tromey.com>
154
155 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
156 Remove.
157 (SIM_EXTRA_DEPS): New variable.
158
efd82ac7
TT		 1592021-04-22 Tom Tromey <tom@tromey.com>
160
161 * configure: Rebuild.
162
2662c237
MF		 1632021-04-21 Mike Frysinger <vapier@gentoo.org>
164
165 * aclocal.m4: Regenerate.
166
1f195bc3
SM		 1672021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
168
169 * configure: Regenerate.
170
37e9f182
MF		 1712021-04-18 Mike Frysinger <vapier@gentoo.org>
172
173 * configure: Regenerate.
174
d5a71b11
MF		 1752021-04-12 Mike Frysinger <vapier@gentoo.org>
176
177 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
178
2b8d134b
SM		 1792021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
180
181 * Makefile.in: Set ASAN_OPTIONS when running igen.
182
5c6f091a
FS		 1832021-04-04 Steve Ellcey <sellcey@mips.com>
184 Faraz Shahbazker <fshahbazker@wavecomp.com>
185
186 * interp.c (sim_monitor): Add switch entries for unlink (13),
187 lseek (14), and stat (15).
188
b6b1c790
MF		 1892021-04-02 Mike Frysinger <vapier@gentoo.org>
190
191 * Makefile.in (../igen/igen): Delete rule.
192 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
193
c2783492
MF		 1942021-04-02 Mike Frysinger <vapier@gentoo.org>
195
196 * aclocal.m4, configure: Regenerate.
197
ebe9564b
MF		 1982021-02-28 Mike Frysinger <vapier@gentoo.org>
199
200 * configure: Regenerate.
201
f8069d55
MF		 2022021-02-27 Mike Frysinger <vapier@gentoo.org>
203
204 * Makefile.in (SIM_EXTRA_ALL): Delete.
205 (all): New target.
206
760b3e8b
MF		 2072021-02-21 Mike Frysinger <vapier@gentoo.org>
208
209 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
210 * aclocal.m4, configure: Regenerate.
211
136da8cd
MF		 2122021-02-13 Mike Frysinger <vapier@gentoo.org>
213
214 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
215 * aclocal.m4, configure: Regenerate.
216
4c0d76b9
MF		 2172021-02-06 Mike Frysinger <vapier@gentoo.org>
218
219 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
220
aa09469f
MF		 2212021-02-06 Mike Frysinger <vapier@gentoo.org>
222
223 * configure: Regenerate.
224
d4e3adda
MF		 2252021-01-30 Mike Frysinger <vapier@gentoo.org>
226
227 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
228
68ed2854
MF		 2292021-01-11 Mike Frysinger <vapier@gentoo.org>
230
231 * config.in, configure: Regenerate.
232 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
233 and strings.h include.
234
50df264d
MF		 2352021-01-09 Mike Frysinger <vapier@gentoo.org>
236
237 * configure: Regenerate.
238
bf470982
MF		 2392021-01-09 Mike Frysinger <vapier@gentoo.org>
240
241 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
242 * configure: Regenerate.
243
46f900c0
MF		 2442021-01-08 Mike Frysinger <vapier@gentoo.org>
245
246 * configure: Regenerate.
247
dfb856ba
MF		 2482021-01-04 Mike Frysinger <vapier@gentoo.org>
249
250 * configure: Regenerate.
251
382bc56b
PK		 2522020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
253
254 * sim-main.c: Include <stdlib.h>.
255
ad9675dd
PK		 2562020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
257
258 * cp1.c: Include <stdlib.h>.
259
f693213d
SM		 2602020-07-29 Simon Marchi <simon.marchi@efficios.com>
261
262 * configure: Re-generate.
263
5c887dd5
JB		 2642017-09-06 John Baldwin <jhb@FreeBSD.org>
265
266 * configure: Regenerate.
267
91588b3a
MF		 2682016-11-11 Mike Frysinger <vapier@gentoo.org>
269
6cb2202b 270 PR sim/20808
91588b3a
MF		 271 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
272 and SD to sd.
273
e04659e8
MF		 2742016-11-11 Mike Frysinger <vapier@gentoo.org>
275
6cb2202b 276 PR sim/20809
e04659e8
MF		 277 * mips.igen (check_u64): Enable for `r3900'.
278
1554f758
MF		 2792016-02-05 Mike Frysinger <vapier@gentoo.org>
280
281 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
282 STATE_PROG_BFD (sd).
283 * configure: Regenerate.
284
3d304f48
AB		 2852016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
286 Maciej W. Rozycki <macro@imgtec.com>
287
288 PR sim/19441
289 * micromips.igen (delayslot_micromips): Enable for `micromips32',
290 `micromips64' and `micromipsdsp' only.
291 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
292 (do_micromips_jalr, do_micromips_jal): Likewise.
293 (compute_movep_src_reg): Likewise.
294 (compute_andi16_imm): Likewise.
295 (convert_fmt_micromips): Likewise.
296 (convert_fmt_micromips_cvt_d): Likewise.
297 (convert_fmt_micromips_cvt_s): Likewise.
298 (FMT_MICROMIPS): Likewise.
299 (FMT_MICROMIPS_CVT_D): Likewise.
300 (FMT_MICROMIPS_CVT_S): Likewise.
301
b36d953b
MF		 3022016-01-12 Mike Frysinger <vapier@gentoo.org>
303
304 * interp.c: Include elf-bfd.h.
305 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
306 ELFCLASS32.
307
ce39bd38
MF		 3082016-01-10 Mike Frysinger <vapier@gentoo.org>
309
310 * config.in, configure: Regenerate.
311
99d8e879
MF		 3122016-01-10 Mike Frysinger <vapier@gentoo.org>
313
314 * configure: Regenerate.
315
35656e95
MF		 3162016-01-10 Mike Frysinger <vapier@gentoo.org>
317
318 * configure: Regenerate.
319
16f7876d
MF		 3202016-01-10 Mike Frysinger <vapier@gentoo.org>
321
322 * configure: Regenerate.
323
e19418e0
MF		 3242016-01-10 Mike Frysinger <vapier@gentoo.org>
325
326 * configure: Regenerate.
327
6d90347b
MF		 3282016-01-10 Mike Frysinger <vapier@gentoo.org>
329
330 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
331 * configure: Regenerate.
332
347fe5bb
MF		 3332016-01-10 Mike Frysinger <vapier@gentoo.org>
334
335 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
336 * configure: Regenerate.
337
22be3fbe
MF		 3382016-01-10 Mike Frysinger <vapier@gentoo.org>
339
340 * configure: Regenerate.
341
0dc73ef7
MF		 3422016-01-10 Mike Frysinger <vapier@gentoo.org>
343
344 * configure: Regenerate.
345
936df756
MF		 3462016-01-09 Mike Frysinger <vapier@gentoo.org>
347
348 * config.in, configure: Regenerate.
349
2e3d4f4d
MF		 3502016-01-06 Mike Frysinger <vapier@gentoo.org>
351
352 * interp.c (sim_open): Mark argv const.
353 (sim_create_inferior): Mark argv and env const.
354
9bbf6f91
MF		 3552016-01-04 Mike Frysinger <vapier@gentoo.org>
356
357 * configure: Regenerate.
358
77cf2ef5
MF		 3592016-01-03 Mike Frysinger <vapier@gentoo.org>
360
361 * interp.c (sim_open): Update sim_parse_args comment.
362
0cb8d851
MF		 3632016-01-03 Mike Frysinger <vapier@gentoo.org>
364
365 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
366 * configure: Regenerate.
367
1ac72f06
MF		 3682016-01-02 Mike Frysinger <vapier@gentoo.org>
369
370 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
371 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
372 * configure: Regenerate.
373 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
374
d47f5b30
MF		 3752016-01-02 Mike Frysinger <vapier@gentoo.org>
376
377 * dv-tx3904cpu.c (CPU, SD): Delete.
378
e1211e55
MF		 3792015-12-30 Mike Frysinger <vapier@gentoo.org>
380
381 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
382 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
383 (sim_store_register): Rename to ...
384 (mips_reg_store): ... this. Delete local cpu var.
385 Update sim_io_eprintf calls.
386 (sim_fetch_register): Rename to ...
387 (mips_reg_fetch): ... this. Delete local cpu var.
388 Update sim_io_eprintf calls.
389
5e744ef8
MF		 3902015-12-27 Mike Frysinger <vapier@gentoo.org>
391
392 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
393
1b393626
MF		 3942015-12-26 Mike Frysinger <vapier@gentoo.org>
395
396 * config.in, configure: Regenerate.
397
26f8bf63
MF		 3982015-12-26 Mike Frysinger <vapier@gentoo.org>
399
400 * interp.c (sim_write, sim_read): Delete.
401 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
402 (load_word): Likewise.
403 * micromips.igen (cache): Likewise.
404 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
405 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
406 do_store_left, do_store_right, do_load_double, do_store_double):
407 Likewise.
408 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
409 (do_prefx): Likewise.
410 * sim-main.c (address_translation, prefetch): Delete.
411 (ifetch32, ifetch16): Delete call to AddressTranslation and set
412 paddr=vaddr.
413 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
414 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
415 (LoadMemory, StoreMemory): Delete CCA arg.
416
ef04e371
MF		 4172015-12-24 Mike Frysinger <vapier@gentoo.org>
418
419 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
420 * configure: Regenerated.
421
cb379ede
MF		 4222015-12-24 Mike Frysinger <vapier@gentoo.org>
423
424 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
425 * tconfig.h: Delete.
426
26936211
MF		 4272015-12-24 Mike Frysinger <vapier@gentoo.org>
428
429 * tconfig.h (SIM_HANDLES_LMA): Delete.
430
84e8e361
MF		 4312015-12-24 Mike Frysinger <vapier@gentoo.org>
432
433 * sim-main.h (WITH_WATCHPOINTS): Delete.
434
3cabaf66
MF		 4352015-12-24 Mike Frysinger <vapier@gentoo.org>
436
437 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
438
8abe6c66
MF		 4392015-12-24 Mike Frysinger <vapier@gentoo.org>
440
441 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
442
1d19cae7
DV		 4432015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
444
445 * micromips.igen (process_isa_mode): Fix left shift of negative
446 value.
447
cdf850e9
MF		 4482015-11-17 Mike Frysinger <vapier@gentoo.org>
449
450 * sim-main.h (WITH_MODULO_MEMORY): Delete.
451
797eee42
MF		 4522015-11-15 Mike Frysinger <vapier@gentoo.org>
453
454 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
455
6e4f085c
MF		 4562015-11-14 Mike Frysinger <vapier@gentoo.org>
457
458 * interp.c (sim_close): Rename to ...
459 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
460 sim_io_shutdown.
461 * sim-main.h (mips_sim_close): Declare.
462 (SIM_CLOSE_HOOK): Define.
463
8e394ffc
AB		 4642015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
465 Ali Lown <ali.lown@imgtec.com>
466
467 * Makefile.in (tmp-micromips): New rule.
468 (tmp-mach-multi): Add support for micromips.
469 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
470 that works for both mips64 and micromips64.
471 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
472 micromips32.
473 Add build support for micromips.
474 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
475 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
476 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
477 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
478 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
479 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
480 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
481 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
482 Refactored instruction code to use these functions.
483 * dsp2.igen: Refactored instruction code to use the new functions.
484 * interp.c (decode_coproc): Refactored to work with any instruction
485 encoding.
486 (isa_mode): New variable
487 (RSVD_INSTRUCTION): Changed to 0x00000039.
488 * m16.igen (BREAK16): Refactored instruction to use do_break16.
489 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
490 * micromips.dc: New file.
491 * micromips.igen: New file.
492 * micromips16.dc: New file.
493 * micromipsdsp.igen: New file.
494 * micromipsrun.c: New file.
495 * mips.igen (do_swc1): Changed to work with any instruction encoding.
496 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
497 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
498 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
499 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
500 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
501 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
502 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
503 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
504 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
505 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
506 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
507 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
508 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
509 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
510 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
511 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
512 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
513 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
514 instructions.
515 Refactored instruction code to use these functions.
516 (RSVD): Changed to use new reserved instruction.
517 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
518 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
519 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
520 do_store_double): Added micromips32 and micromips64 models.
521 Added include for micromips.igen and micromipsdsp.igen
522 Add micromips32 and micromips64 models.
523 (DecodeCoproc): Updated to use new macro definition.
524 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
525 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
526 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
527 Refactored instruction code to use these functions.
528 * sim-main.h (CP0_operation): New enum.
529 (DecodeCoproc): Updated macro.
530 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
531 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
532 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
533 ISA_MODE_MICROMIPS): New defines.
534 (sim_state): Add isa_mode field.
535
8d0978fb
MF		 5362015-06-23 Mike Frysinger <vapier@gentoo.org>
537
538 * configure: Regenerate.
539
306f4178
MF		 5402015-06-12 Mike Frysinger <vapier@gentoo.org>
541
542 * configure.ac: Change configure.in to configure.ac.
543 * configure: Regenerate.
544
a3487082
MF		 5452015-06-12 Mike Frysinger <vapier@gentoo.org>
546
547 * configure: Regenerate.
548
29bc024d
MF		 5492015-06-12 Mike Frysinger <vapier@gentoo.org>
550
551 * interp.c [TRACE]: Delete.
552 (TRACE): Change to WITH_TRACE_ANY_P.
553 [!WITH_TRACE_ANY_P] (open_trace): Define.
554 (mips_option_handler, open_trace, sim_close, dotrace):
555 Change defined(TRACE) to WITH_TRACE_ANY_P.
556 (sim_open): Delete TRACE ifdef check.
557 * sim-main.c (load_memory): Delete TRACE ifdef check.
558 (store_memory): Likewise.
559 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
560 [!WITH_TRACE_ANY_P] (dotrace): Define.
561
3ebe2863
MF		 5622015-04-18 Mike Frysinger <vapier@gentoo.org>
563
564 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
565 comments.
566
20bca71d
MF		 5672015-04-18 Mike Frysinger <vapier@gentoo.org>
568
569 * sim-main.h (SIM_CPU): Delete.
570
7e83aa92
MF		 5712015-04-18 Mike Frysinger <vapier@gentoo.org>
572
573 * sim-main.h (sim_cia): Delete.
574
034685f9
MF		 5752015-04-17 Mike Frysinger <vapier@gentoo.org>
576
577 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
578 PU_PC_GET.
579 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
580 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
581 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
582 CIA_SET to CPU_PC_SET.
583 * sim-main.h (CIA_GET, CIA_SET): Delete.
584
78e9aa70
MF		 5852015-04-15 Mike Frysinger <vapier@gentoo.org>
586
587 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
588 * sim-main.h (STATE_CPU): Delete.
589
bf12d44e
MF		 5902015-04-13 Mike Frysinger <vapier@gentoo.org>
591
592 * configure: Regenerate.
593
7bebb329
MF		 5942015-04-13 Mike Frysinger <vapier@gentoo.org>
595
596 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
597 * interp.c (mips_pc_get, mips_pc_set): New functions.
598 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
599 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
600 (sim_pc_get): Delete.
601 * sim-main.h (SIM_CPU): Define.
602 (struct sim_state): Change cpu to an array of pointers.
603 (STATE_CPU): Drop &.
604
8ac57fbd
MF		 6052015-04-13 Mike Frysinger <vapier@gentoo.org>
606
607 * interp.c (mips_option_handler, open_trace, sim_close,
608 sim_write, sim_read, sim_store_register, sim_fetch_register,
609 sim_create_inferior, pr_addr, pr_uword64): Convert old style
610 prototypes.
611 (sim_open): Convert old style prototype. Change casts with
612 sim_write to unsigned char *.
613 (fetch_str): Change null to unsigned char, and change cast to
614 unsigned char *.
615 (sim_monitor): Change c & ch to unsigned char. Change cast to
616 unsigned char *.
617
e787f858
MF		 6182015-04-12 Mike Frysinger <vapier@gentoo.org>
619
620 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
621
122bbfb5
MF		 6222015-04-06 Mike Frysinger <vapier@gentoo.org>
623
624 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
625
0fe84f3f
MF		 6262015-04-01 Mike Frysinger <vapier@gentoo.org>
627
628 * tconfig.h (SIM_HAVE_PROFILE): Delete.
629
aadc9410
MF		 6302015-03-31 Mike Frysinger <vapier@gentoo.org>
631
632 * config.in, configure: Regenerate.
633
05f53ed6
MF		 6342015-03-24 Mike Frysinger <vapier@gentoo.org>
635
636 * interp.c (sim_pc_get): New function.
637
c0931f26
MF		 6382015-03-24 Mike Frysinger <vapier@gentoo.org>
639
640 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
641 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
642
30452bbe
MF		 6432015-03-24 Mike Frysinger <vapier@gentoo.org>
644
645 * configure: Regenerate.
646
64dd13df
MF		 6472015-03-23 Mike Frysinger <vapier@gentoo.org>
648
649 * configure: Regenerate.
650
49cd1634
MF		 6512015-03-23 Mike Frysinger <vapier@gentoo.org>
652
653 * configure: Regenerate.
654 * configure.ac (mips_extra_objs): Delete.
655 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
656 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
657
3649cb06
MF		 6582015-03-23 Mike Frysinger <vapier@gentoo.org>
659
660 * configure: Regenerate.
661 * configure.ac: Delete sim_hw checks for dv-sockser.
662
ae7d0cac
MF		 6632015-03-16 Mike Frysinger <vapier@gentoo.org>
664
665 * config.in, configure: Regenerate.
666 * tconfig.in: Rename file ...
667 * tconfig.h: ... here.
668
8406bb59
MF		 6692015-03-15 Mike Frysinger <vapier@gentoo.org>
670
671 * tconfig.in: Delete includes.
672 [HAVE_DV_SOCKSER]: Delete.
673
465fb143
MF		 6742015-03-14 Mike Frysinger <vapier@gentoo.org>
675
676 * Makefile.in (SIM_RUN_OBJS): Delete.
677
5cddc23a
MF		 6782015-03-14 Mike Frysinger <vapier@gentoo.org>
679
680 * configure.ac (AC_CHECK_HEADERS): Delete.
681 * aclocal.m4, configure: Regenerate.
682
2974be62
AM		 6832014-08-19 Alan Modra <amodra@gmail.com>
684
685 * configure: Regenerate.
686
faa743bb
RM		 6872014-08-15 Roland McGrath <mcgrathr@google.com>
688
689 * configure: Regenerate.
690 * config.in: Regenerate.
691
1a8a700e
MF		 6922014-03-04 Mike Frysinger <vapier@gentoo.org>
693
694 * configure: Regenerate.
695
bf3d9781
AM		 6962013-09-23 Alan Modra <amodra@gmail.com>
697
698 * configure: Regenerate.
699
31e6ad7d
MF		 7002013-06-03 Mike Frysinger <vapier@gentoo.org>
701
702 * aclocal.m4, configure: Regenerate.
703
d3685d60
TT		 7042013-05-10 Freddie Chopin <freddie_chopin@op.pl>
705
706 * configure: Rebuild.
707
1517bd27
MF		 7082013-03-26 Mike Frysinger <vapier@gentoo.org>
709
710 * configure: Regenerate.
711
3be31516
JS		 7122013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
713
714 * configure.ac: Address use of dv-sockser.o.
715 * tconfig.in: Conditionalize use of dv_sockser_install.
716 * configure: Regenerated.
717 * config.in: Regenerated.
718
37cb8f8e
SE		 7192012-10-04 Chao-ying Fu <fu@mips.com>
720 Steve Ellcey <sellcey@mips.com>
721
722 * mips/mips3264r2.igen (rdhwr): New.
723
87c8644f
JS		 7242012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
725
726 * configure.ac: Always link against dv-sockser.o.
727 * configure: Regenerate.
728
5f3ef9d0
JB		 7292012-06-15 Joel Brobecker <brobecker@adacore.com>
730
731 * config.in, configure: Regenerate.
732
a6ff997c
NC		 7332012-05-18 Nick Clifton <nickc@redhat.com>
734
735 PR 14072
736 * interp.c: Include config.h before system header files.
737
2232061b
MF		 7382012-03-24 Mike Frysinger <vapier@gentoo.org>
739
740 * aclocal.m4, config.in, configure: Regenerate.
741
db2e4d67
MF		 7422011-12-03 Mike Frysinger <vapier@gentoo.org>
743
744 * aclocal.m4: New file.
745 * configure: Regenerate.
746
4399a56b
MF		 7472011-10-19 Mike Frysinger <vapier@gentoo.org>
748
749 * configure: Regenerate after common/acinclude.m4 update.
750
9c082ca8
MF		 7512011-10-17 Mike Frysinger <vapier@gentoo.org>
752
753 * configure.ac: Change include to common/acinclude.m4.
754
6ffe910a
MF		 7552011-10-17 Mike Frysinger <vapier@gentoo.org>
756
757 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
758 call. Replace common.m4 include with SIM_AC_COMMON.
759 * configure: Regenerate.
760
31b28250
HPN		 7612011-07-08 Hans-Peter Nilsson <hp@axis.com>
762
3faa01e3
HPN		 763 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
764 $(SIM_EXTRA_DEPS).
765 (tmp-mach-multi): Exit early when igen fails.
31b28250 766
2419798b
MF		 7672011-07-05 Mike Frysinger <vapier@gentoo.org>
768
769 * interp.c (sim_do_command): Delete.
770
d79fe0d6
MF		 7712011-02-14 Mike Frysinger <vapier@gentoo.org>
772
773 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
774 (tx3904sio_fifo_reset): Likewise.
775 * interp.c (sim_monitor): Likewise.
776
5558e7e6
MF		 7772010-04-14 Mike Frysinger <vapier@gentoo.org>
778
779 * interp.c (sim_write): Add const to buffer arg.
780
35aafff4
JB		 7812010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
782
783 * interp.c: Don't include sysdep.h
784
3725885a
RW		 7852010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
786
787 * configure: Regenerate.
788
d6416cdc
RW		 7892009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
790
81ecdfbb
RW		 791 * config.in: Regenerate.
792 * configure: Likewise.
793
d6416cdc
RW		 794 * configure: Regenerate.
795
b5bd9624
HPN		 7962008-07-11 Hans-Peter Nilsson <hp@axis.com>
797
798 * configure: Regenerate to track ../common/common.m4 changes.
799 * config.in: Ditto.
800
6efef468 8012008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 802 Daniel Jacobowitz <dan@codesourcery.com>
803 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 804
805 * configure: Regenerate.
806
60dc88db
RS		 8072007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
808
809 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
810 that unconditionally allows fmt_ps.
811 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
812 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
813 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
814 filter from 64,f to 32,f.
815 (PREFX): Change filter from 64 to 32.
816 (LDXC1, LUXC1): Provide separate mips32r2 implementations
817 that use do_load_double instead of do_load. Make both LUXC1
818 versions unpredictable if SizeFGR () != 64.
819 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
820 instead of do_store. Remove unused variable. Make both SUXC1
821 versions unpredictable if SizeFGR () != 64.
822
599ca73e
RS		 8232007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
824
825 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
826 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
827 shifts for that case.
828
2525df03
NC		 8292007-09-04 Nick Clifton <nickc@redhat.com>
830
831 * interp.c (options enum): Add OPTION_INFO_MEMORY.
832 (display_mem_info): New static variable.
833 (mips_option_handler): Handle OPTION_INFO_MEMORY.
834 (mips_options): Add info-memory and memory-info.
835 (sim_open): After processing the command line and board
836 specification, check display_mem_info. If it is set then
837 call the real handler for the --memory-info command line
838 switch.
839
35ee6e1e
JB		 8402007-08-24 Joel Brobecker <brobecker@adacore.com>
841
842 * configure.ac: Change license of multi-run.c to GPL version 3.
843 * configure: Regenerate.
844
d5fb0879
RS		 8452007-06-28 Richard Sandiford <richard@codesourcery.com>
846
847 * configure.ac, configure: Revert last patch.
848
2a2ce21b
RS		 8492007-06-26 Richard Sandiford <richard@codesourcery.com>
850
851 * configure.ac (sim_mipsisa3264_configs): New variable.
852 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
853 every configuration support all four targets, using the triplet to
854 determine the default.
855 * configure: Regenerate.
856
efdcccc9
RS		 8572007-06-25 Richard Sandiford <richard@codesourcery.com>
858
0a7692b2 859 * Makefile.in (m16run.o): New rule.
efdcccc9 860
f532a356
TS		 8612007-05-15 Thiemo Seufer <ths@mips.com>
862
863 * mips3264r2.igen (DSHD): Fix compile warning.
864
bfe9c90b
TS		 8652007-05-14 Thiemo Seufer <ths@mips.com>
866
867 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
868 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
869 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
870 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
871 for mips32r2.
872
53f4826b
TS		 8732007-03-01 Thiemo Seufer <ths@mips.com>
874
875 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
876 and mips64.
877
8bf3ddc8
TS		 8782007-02-20 Thiemo Seufer <ths@mips.com>
879
880 * dsp.igen: Update copyright notice.
881 * dsp2.igen: Fix copyright notice.
882
8b082fb1 8832007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 884 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 885
886 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
887 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
888 Add dsp2 to sim_igen_machine.
889 * configure: Regenerate.
890 * dsp.igen (do_ph_op): Add MUL support when op = 2.
891 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
892 (mulq_rs.ph): Use do_ph_mulq.
893 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
894 * mips.igen: Add dsp2 model and include dsp2.igen.
895 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
896 for *mips32r2, *mips64r2, *dsp.
897 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
898 for *mips32r2, *mips64r2, *dsp2.
899 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
900
b1004875 9012007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 902 Nigel Stephens <nigel@mips.com>
b1004875
TS		 903
904 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
905 jumps with hazard barrier.
906
f8df4c77 9072007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 908 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 909
910 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
911 after each call to sim_io_write.
912
b1004875 9132007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 914 Nigel Stephens <nigel@mips.com>
b1004875
TS		 915
916 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
917 supported by this simulator.
07802d98
TS		 918 (decode_coproc): Recognise additional CP0 Config registers
919 correctly.
920
14fb6c5a 9212007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 922 Nigel Stephens <nigel@mips.com>
923 David Ung <davidu@mips.com>
14fb6c5a
TS		 924
925 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
926 uninterpreted formats. If fmt is one of the uninterpreted types
927 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
928 fmt_word, and fmt_uninterpreted_64 like fmt_long.
929 (store_fpr): When writing an invalid odd register, set the
930 matching even register to fmt_unknown, not the following register.
931 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
932 the the memory window at offset 0 set by --memory-size command
933 line option.
934 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
935 point register.
936 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
937 register.
938 (sim_monitor): When returning the memory size to the MIPS
939 application, use the value in STATE_MEM_SIZE, not an arbitrary
940 hardcoded value.
941 (cop_lw): Don' mess around with FPR_STATE, just pass
942 fmt_uninterpreted_32 to StoreFPR.
943 (cop_sw): Similarly.
944 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
945 (cop_sd): Similarly.
946 * mips.igen (not_word_value): Single version for mips32, mips64
947 and mips16.
948
c8847145 9492007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 950 Nigel Stephens <nigel@mips.com>
c8847145
TS		 951
952 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
953 MBytes.
954
4b5d35ee
TS		 9552007-02-17 Thiemo Seufer <ths@mips.com>
956
957 * configure.ac (mips*-sde-elf*): Move in front of generic machine
958 configuration.
959 * configure: Regenerate.
960
3669427c
TS		 9612007-02-17 Thiemo Seufer <ths@mips.com>
962
963 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
964 Add mdmx to sim_igen_machine.
965 (mipsisa64*-*-*): Likewise. Remove dsp.
966 (mipsisa32*-*-*): Remove dsp.
967 * configure: Regenerate.
968
109ad085
TS		 9692007-02-13 Thiemo Seufer <ths@mips.com>
970
971 * configure.ac: Add mips*-sde-elf* target.
972 * configure: Regenerate.
973
921d7ad3
HPN		 9742006-12-21 Hans-Peter Nilsson <hp@axis.com>
975
976 * acconfig.h: Remove.
977 * config.in, configure: Regenerate.
978
02f97da7
TS		 9792006-11-07 Thiemo Seufer <ths@mips.com>
980
981 * dsp.igen (do_w_op): Fix compiler warning.
982
2d2733fc 9832006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 984 David Ung <davidu@mips.com>
2d2733fc
TS		 985
986 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
987 sim_igen_machine.
988 * configure: Regenerate.
989 * mips.igen (model): Add smartmips.
990 (MADDU): Increment ACX if carry.
991 (do_mult): Clear ACX.
992 (ROR,RORV): Add smartmips.
72f4393d 993 (include): Include smartmips.igen.
2d2733fc
TS		 994 * sim-main.h (ACX): Set to REGISTERS[89].
995 * smartmips.igen: New file.
996
d85c3a10 9972006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 998 David Ung <davidu@mips.com>
d85c3a10
TS		 999
1000 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1001 mips3264r2.igen. Add missing dependency rules.
1002 * m16e.igen: Support for mips16e save/restore instructions.
1003
e85e3205
RE		 10042006-06-13 Richard Earnshaw <rearnsha@arm.com>
1005
1006 * configure: Regenerated.
1007
2f0122dc
DJ		 10082006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1009
1010 * configure: Regenerated.
1011
20e95c23
DJ		 10122006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1013
1014 * configure: Regenerated.
1015
69088b17
CF		 10162006-05-15 Chao-ying Fu <fu@mips.com>
1017
1018 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1019
0275de4e
NC		 10202006-04-18 Nick Clifton <nickc@redhat.com>
1021
1022 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1023 statement.
1024
b3a3ffef
HPN		 10252006-03-29 Hans-Peter Nilsson <hp@axis.com>
1026
1027 * configure: Regenerate.
1028
40a5538e
CF		 10292005-12-14 Chao-ying Fu <fu@mips.com>
1030
1031 * Makefile.in (SIM_OBJS): Add dsp.o.
1032 (dsp.o): New dependency.
1033 (IGEN_INCLUDE): Add dsp.igen.
1034 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1035 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1036 * configure: Regenerate.
1037 * mips.igen: Add dsp model and include dsp.igen.
1038 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1039 because these instructions are extended in DSP ASE.
1040 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1041 adding 6 DSP accumulator registers and 1 DSP control register.
1042 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1043 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1044 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1045 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1046 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1047 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1048 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1049 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1050 DSPCR_CCOND_SMASK): New define.
1051 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1052 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1053
21d14896
ILT		 10542005-07-08 Ian Lance Taylor <ian@airs.com>
1055
1056 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1057
b16d63da 10582005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1059 Nigel Stephens <nigel@mips.com>
1060
1061 * mips.igen: New mips16e model and include m16e.igen.
1062 (check_u64): Add mips16e tag.
1063 * m16e.igen: New file for MIPS16e instructions.
1064 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1065 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1066 models.
1067 * configure: Regenerate.
b16d63da 1068
e70cb6cd 10692005-05-26 David Ung <davidu@mips.com>
72f4393d 1070
e70cb6cd
CD		 1071 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1072 tags to all instructions which are applicable to the new ISAs.
1073 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1074 vr.igen.
1075 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1076 instructions.
e70cb6cd
CD		 1077 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1078 to mips.igen.
1079 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1080 * configure: Regenerate.
72f4393d 1081
2b193c4a
MK		 10822005-03-23 Mark Kettenis <kettenis@gnu.org>
1083
1084 * configure: Regenerate.
1085
35695fd6
AC		 10862005-01-14 Andrew Cagney <cagney@gnu.org>
1087
1088 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1089 explicit call to AC_CONFIG_HEADER.
1090 * configure: Regenerate.
1091
f0569246
AC		 10922005-01-12 Andrew Cagney <cagney@gnu.org>
1093
1094 * configure.ac: Update to use ../common/common.m4.
1095 * configure: Re-generate.
1096
38f48d72
AC		 10972005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1098
1099 * configure: Regenerated to track ../common/aclocal.m4 changes.
1100
b7026657
AC		 11012005-01-07 Andrew Cagney <cagney@gnu.org>
1102
1103 * configure.ac: Rename configure.in, require autoconf 2.59.
1104 * configure: Re-generate.
1105
379832de
HPN		 11062004-12-08 Hans-Peter Nilsson <hp@axis.com>
1107
1108 * configure: Regenerate for ../common/aclocal.m4 update.
1109
cd62154c 11102004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1111
cd62154c
AC		 1112 Committed by Andrew Cagney.
1113 * m16.igen (CMP, CMPI): Fix assembler.
1114
e5da76ec
CD		 11152004-08-18 Chris Demetriou <cgd@broadcom.com>
1116
1117 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1118 * configure: Regenerate.
1119
139181c8
CD		 11202004-06-25 Chris Demetriou <cgd@broadcom.com>
1121
1122 * configure.in (sim_m16_machine): Include mipsIII.
1123 * configure: Regenerate.
1124
1a27f959
CD		 11252004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1126
72f4393d 1127 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1128 from COP0_BADVADDR.
1129 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1130
5dbb7b5a
CD		 11312004-04-10 Chris Demetriou <cgd@broadcom.com>
1132
1133 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1134
14234056
CD		 11352004-04-09 Chris Demetriou <cgd@broadcom.com>
1136
1137 * mips.igen (check_fmt): Remove.
1138 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1139 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1140 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1141 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1142 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1143 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1144 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1145 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1146 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1147 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1148
c6f9085c
CD		 11492004-04-09 Chris Demetriou <cgd@broadcom.com>
1150
1151 * sb1.igen (check_sbx): New function.
1152 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1153
11d66e66 11542004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1155 Richard Sandiford <rsandifo@redhat.com>
1156
1157 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1158 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1159 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1160 separate implementations for mipsIV and mipsV. Use new macros to
1161 determine whether the restrictions apply.
1162
b3208fb8
CD		 11632004-01-19 Chris Demetriou <cgd@broadcom.com>
1164
1165 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1166 (check_mult_hilo): Improve comments.
1167 (check_div_hilo): Likewise. Also, fork off a new version
1168 to handle mips32/mips64 (since there are no hazards to check
1169 in MIPS32/MIPS64).
1170
9a1d84fb
CD		 11712003-06-17 Richard Sandiford <rsandifo@redhat.com>
1172
1173 * mips.igen (do_dmultx): Fix check for negative operands.
1174
ae451ac6
ILT		 11752003-05-16 Ian Lance Taylor <ian@airs.com>
1176
1177 * Makefile.in (SHELL): Make sure this is defined.
1178 (various): Use $(SHELL) whenever we invoke move-if-change.
1179
dd69d292
CD		 11802003-05-03 Chris Demetriou <cgd@broadcom.com>
1181
1182 * cp1.c: Tweak attribution slightly.
1183 * cp1.h: Likewise.
1184 * mdmx.c: Likewise.
1185 * mdmx.igen: Likewise.
1186 * mips3d.igen: Likewise.
1187 * sb1.igen: Likewise.
1188
bcd0068e
CD		 11892003-04-15 Richard Sandiford <rsandifo@redhat.com>
1190
1191 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1192 unsigned operands.
1193
6b4a8935
AC		 11942003-02-27 Andrew Cagney <cagney@redhat.com>
1195
601da316
AC		 1196 * interp.c (sim_open): Rename _bfd to bfd.
1197 (sim_create_inferior): Ditto.
6b4a8935 1198
d29e330f
CD		 11992003-01-14 Chris Demetriou <cgd@broadcom.com>
1200
1201 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1202
a2353a08
CD		 12032003-01-14 Chris Demetriou <cgd@broadcom.com>
1204
1205 * mips.igen (EI, DI): Remove.
1206
80551777
CD		 12072003-01-05 Richard Sandiford <rsandifo@redhat.com>
1208
1209 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1210
4c54fc26
CD		 12112003-01-04 Richard Sandiford <rsandifo@redhat.com>
1212 Andrew Cagney <ac131313@redhat.com>
1213 Gavin Romig-Koch <gavin@redhat.com>
1214 Graydon Hoare <graydon@redhat.com>
1215 Aldy Hernandez <aldyh@redhat.com>
1216 Dave Brolley <brolley@redhat.com>
1217 Chris Demetriou <cgd@broadcom.com>
1218
1219 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1220 (sim_mach_default): New variable.
1221 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1222 Add a new simulator generator, MULTI.
1223 * configure: Regenerate.
1224 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1225 (multi-run.o): New dependency.
1226 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1227 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1228 (tmp-multi): Combine them.
1229 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1230 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1231 (distclean-extra): New rule.
1232 * sim-main.h: Include bfd.h.
1233 (MIPS_MACH): New macro.
1234 * mips.igen (vr4120, vr5400, vr5500): New models.
1235 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1236 * vr.igen: Replace with new version.
1237
e6c674b8
CD		 12382003-01-04 Chris Demetriou <cgd@broadcom.com>
1239
1240 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1241 * configure: Regenerate.
1242
28f50ac8
CD		 12432002-12-31 Chris Demetriou <cgd@broadcom.com>
1244
1245 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1246 * mips.igen: Remove all invocations of check_branch_bug and
1247 mark_branch_bug.
1248
5071ffe6
CD		 12492002-12-16 Chris Demetriou <cgd@broadcom.com>
1250
72f4393d 1251 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1252
06e7837e
CD		 12532002-07-30 Chris Demetriou <cgd@broadcom.com>
1254
1255 * mips.igen (do_load_double, do_store_double): New functions.
1256 (LDC1, SDC1): Rename to...
1257 (LDC1b, SDC1b): respectively.
1258 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1259
2265c243
MS		 12602002-07-29 Michael Snyder <msnyder@redhat.com>
1261
1262 * cp1.c (fp_recip2): Modify initialization expression so that
1263 GCC will recognize it as constant.
1264
a2f8b4f3
CD		 12652002-06-18 Chris Demetriou <cgd@broadcom.com>
1266
1267 * mdmx.c (SD_): Delete.
1268 (Unpredictable): Re-define, for now, to directly invoke
1269 unpredictable_action().
1270 (mdmx_acc_op): Fix error in .ob immediate handling.
1271
b4b6c939
AC		 12722002-06-18 Andrew Cagney <cagney@redhat.com>
1273
1274 * interp.c (sim_firmware_command): Initialize `address'.
1275
c8cca39f
AC		 12762002-06-16 Andrew Cagney <ac131313@redhat.com>
1277
1278 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279
e7e81181 12802002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1281 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1282
1283 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1284 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1285 * mips.igen: Include mips3d.igen.
1286 (mips3d): New model name for MIPS-3D ASE instructions.
1287 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1288 instructions.
e7e81181
CD		 1289 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1290 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1291 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1292 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1293 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1294 (RSquareRoot1, RSquareRoot2): New macros.
1295 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1296 (fp_rsqrt2): New functions.
1297 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1298 * configure: Regenerate.
1299
3a2b820e 13002002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1301 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1302
1303 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1304 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1305 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1306 (convert): Note that this function is not used for paired-single
1307 format conversions.
1308 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1309 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1310 (check_fmt_p): Enable paired-single support.
1311 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1312 (PUU.PS): New instructions.
1313 (CVT.S.fmt): Don't use this instruction for paired-single format
1314 destinations.
1315 * sim-main.h (FP_formats): New value 'fmt_ps.'
1316 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1317 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1318
d18ea9c2
CD		 13192002-06-12 Chris Demetriou <cgd@broadcom.com>
1320
1321 * mips.igen: Fix formatting of function calls in
1322 many FP operations.
1323
95fd5cee
CD		 13242002-06-12 Chris Demetriou <cgd@broadcom.com>
1325
1326 * mips.igen (MOVN, MOVZ): Trace result.
1327 (TNEI): Print "tnei" as the opcode name in traces.
1328 (CEIL.W): Add disassembly string for traces.
1329 (RSQRT.fmt): Make location of disassembly string consistent
1330 with other instructions.
1331
4f0d55ae
CD		 13322002-06-12 Chris Demetriou <cgd@broadcom.com>
1333
1334 * mips.igen (X): Delete unused function.
1335
3c25f8c7
AC		 13362002-06-08 Andrew Cagney <cagney@redhat.com>
1337
1338 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1339
f3c08b7e 13402002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1341 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1342
1343 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1344 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1345 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1346 (fp_nmsub): New prototypes.
1347 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1348 (NegMultiplySub): New defines.
1349 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1350 (MADD.D, MADD.S): Replace with...
1351 (MADD.fmt): New instruction.
1352 (MSUB.D, MSUB.S): Replace with...
1353 (MSUB.fmt): New instruction.
1354 (NMADD.D, NMADD.S): Replace with...
1355 (NMADD.fmt): New instruction.
1356 (NMSUB.D, MSUB.S): Replace with...
1357 (NMSUB.fmt): New instruction.
1358
52714ff9 13592002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1360 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1361
1362 * cp1.c: Fix more comment spelling and formatting.
1363 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1364 (denorm_mode): New function.
1365 (fpu_unary, fpu_binary): Round results after operation, collect
1366 status from rounding operations, and update the FCSR.
1367 (convert): Collect status from integer conversions and rounding
1368 operations, and update the FCSR. Adjust NaN values that result
1369 from conversions. Convert to use sim_io_eprintf rather than
1370 fprintf, and remove some debugging code.
1371 * cp1.h (fenr_FS): New define.
1372
577d8c4b
CD		 13732002-06-07 Chris Demetriou <cgd@broadcom.com>
1374
1375 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1376 rounding mode to sim FP rounding mode flag conversion code into...
1377 (rounding_mode): New function.
1378
196496ed
CD		 13792002-06-07 Chris Demetriou <cgd@broadcom.com>
1380
1381 * cp1.c: Clean up formatting of a few comments.
1382 (value_fpr): Reformat switch statement.
1383
cfe9ea23 13842002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1385 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1386
1387 * cp1.h: New file.
1388 * sim-main.h: Include cp1.h.
1389 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1390 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1391 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1392 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1393 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1394 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1395 * cp1.c: Don't include sim-fpu.h; already included by
1396 sim-main.h. Clean up formatting of some comments.
1397 (NaN, Equal, Less): Remove.
1398 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1399 (fp_cmp): New functions.
1400 * mips.igen (do_c_cond_fmt): Remove.
1401 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1402 Compare. Add result tracing.
1403 (CxC1): Remove, replace with...
1404 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1405 (DMxC1): Remove, replace with...
1406 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1407 (MxC1): Remove, replace with...
1408 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1409
ee7254b0
CD		 14102002-06-04 Chris Demetriou <cgd@broadcom.com>
1411
1412 * sim-main.h (FGRIDX): Remove, replace all uses with...
1413 (FGR_BASE): New macro.
1414 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1415 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1416 (NR_FGR, FGR): Likewise.
1417 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1418 * mips.igen: Likewise.
1419
d3eb724f
CD		 14202002-06-04 Chris Demetriou <cgd@broadcom.com>
1421
1422 * cp1.c: Add an FSF Copyright notice to this file.
1423
ba46ddd0 14242002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1425 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1426
1427 * cp1.c (Infinity): Remove.
1428 * sim-main.h (Infinity): Likewise.
1429
1430 * cp1.c (fp_unary, fp_binary): New functions.
1431 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1432 (fp_sqrt): New functions, implemented in terms of the above.
1433 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1434 (Recip, SquareRoot): Remove (replaced by functions above).
1435 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1436 (fp_recip, fp_sqrt): New prototypes.
1437 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1438 (Recip, SquareRoot): Replace prototypes with #defines which
1439 invoke the functions above.
72f4393d 1440
18d8a52d
CD		 14412002-06-03 Chris Demetriou <cgd@broadcom.com>
1442
1443 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1444 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1445 file, remove PARAMS from prototypes.
1446 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1447 simulator state arguments.
1448 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1449 pass simulator state arguments.
1450 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1451 (store_fpr, convert): Remove 'sd' argument.
1452 (value_fpr): Likewise. Convert to use 'SD' instead.
1453
0f154cbd
CD		 14542002-06-03 Chris Demetriou <cgd@broadcom.com>
1455
1456 * cp1.c (Min, Max): Remove #if 0'd functions.
1457 * sim-main.h (Min, Max): Remove.
1458
e80fc152
CD		 14592002-06-03 Chris Demetriou <cgd@broadcom.com>
1460
1461 * cp1.c: fix formatting of switch case and default labels.
1462 * interp.c: Likewise.
1463 * sim-main.c: Likewise.
1464
bad673a9
CD		 14652002-06-03 Chris Demetriou <cgd@broadcom.com>
1466
1467 * cp1.c: Clean up comments which describe FP formats.
1468 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1469
7cbea089 14702002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1471 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1472
1473 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1474 Broadcom SiByte SB-1 processor configurations.
1475 * configure: Regenerate.
1476 * sb1.igen: New file.
1477 * mips.igen: Include sb1.igen.
1478 (sb1): New model.
1479 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1480 * mdmx.igen: Add "sb1" model to all appropriate functions and
1481 instructions.
1482 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1483 (ob_func, ob_acc): Reference the above.
1484 (qh_acc): Adjust to keep the same size as ob_acc.
1485 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1486 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1487
909daa82
CD		 14882002-06-03 Chris Demetriou <cgd@broadcom.com>
1489
1490 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1491
f4f1b9f1 14922002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1493 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1494
1495 * mips.igen (mdmx): New (pseudo-)model.
1496 * mdmx.c, mdmx.igen: New files.
1497 * Makefile.in (SIM_OBJS): Add mdmx.o.
1498 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1499 New typedefs.
1500 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1501 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1502 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1503 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1504 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1505 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1506 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1507 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1508 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1509 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1510 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1511 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1512 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1513 (qh_fmtsel): New macros.
1514 (_sim_cpu): New member "acc".
1515 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1516 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1517
5accf1ff
CD		 15182002-05-01 Chris Demetriou <cgd@broadcom.com>
1519
1520 * interp.c: Use 'deprecated' rather than 'depreciated.'
1521 * sim-main.h: Likewise.
1522
402586aa
CD		 15232002-05-01 Chris Demetriou <cgd@broadcom.com>
1524
1525 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1526 which wouldn't compile anyway.
1527 * sim-main.h (unpredictable_action): New function prototype.
1528 (Unpredictable): Define to call igen function unpredictable().
1529 (NotWordValue): New macro to call igen function not_word_value().
1530 (UndefinedResult): Remove.
1531 * interp.c (undefined_result): Remove.
1532 (unpredictable_action): New function.
1533 * mips.igen (not_word_value, unpredictable): New functions.
1534 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1535 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1536 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1537 NotWordValue() to check for unpredictable inputs, then
1538 Unpredictable() to handle them.
1539
c9b9995a
CD		 15402002-02-24 Chris Demetriou <cgd@broadcom.com>
1541
1542 * mips.igen: Fix formatting of calls to Unpredictable().
1543
e1015982
AC		 15442002-04-20 Andrew Cagney <ac131313@redhat.com>
1545
1546 * interp.c (sim_open): Revert previous change.
1547
b882a66b
AO		 15482002-04-18 Alexandre Oliva <aoliva@redhat.com>
1549
1550 * interp.c (sim_open): Disable chunk of code that wrote code in
1551 vector table entries.
1552
c429b7dd
CD		 15532002-03-19 Chris Demetriou <cgd@broadcom.com>
1554
1555 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1556 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1557 unused definitions.
1558
37d146fa
CD		 15592002-03-19 Chris Demetriou <cgd@broadcom.com>
1560
1561 * cp1.c: Fix many formatting issues.
1562
07892c0b
CD		 15632002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1564
1565 * cp1.c (fpu_format_name): New function to replace...
1566 (DOFMT): This. Delete, and update all callers.
1567 (fpu_rounding_mode_name): New function to replace...
1568 (RMMODE): This. Delete, and update all callers.
1569
487f79b7
CD		 15702002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1571
1572 * interp.c: Move FPU support routines from here to...
1573 * cp1.c: Here. New file.
1574 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1575 (cp1.o): New target.
1576
1e799e28
CD		 15772002-03-12 Chris Demetriou <cgd@broadcom.com>
1578
1579 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1580 * mips.igen (mips32, mips64): New models, add to all instructions
1581 and functions as appropriate.
1582 (loadstore_ea, check_u64): New variant for model mips64.
1583 (check_fmt_p): New variant for models mipsV and mips64, remove
1584 mipsV model marking fro other variant.
1585 (SLL) Rename to...
1586 (SLLa) this.
1587 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1588 for mips32 and mips64.
1589 (DCLO, DCLZ): New instructions for mips64.
1590
82f728db
CD		 15912002-03-07 Chris Demetriou <cgd@broadcom.com>
1592
1593 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1594 immediate or code as a hex value with the "%#lx" format.
1595 (ANDI): Likewise, and fix printed instruction name.
1596
b96e7ef1
CD		 15972002-03-05 Chris Demetriou <cgd@broadcom.com>
1598
1599 * sim-main.h (UndefinedResult, Unpredictable): New macros
1600 which currently do nothing.
1601
d35d4f70
CD		 16022002-03-05 Chris Demetriou <cgd@broadcom.com>
1603
1604 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1605 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1606 (status_CU3): New definitions.
1607
1608 * sim-main.h (ExceptionCause): Add new values for MIPS32
1609 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1610 for DebugBreakPoint and NMIReset to note their status in
1611 MIPS32 and MIPS64.
1612 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1613 (SignalExceptionCacheErr): New exception macros.
1614
3ad6f714
CD		 16152002-03-05 Chris Demetriou <cgd@broadcom.com>
1616
1617 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1618 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1619 is always enabled.
1620 (SignalExceptionCoProcessorUnusable): Take as argument the
1621 unusable coprocessor number.
1622
86b77b47
CD		 16232002-03-05 Chris Demetriou <cgd@broadcom.com>
1624
1625 * mips.igen: Fix formatting of all SignalException calls.
1626
97a88e93 16272002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1628
1629 * sim-main.h (SIGNEXTEND): Remove.
1630
97a88e93 16312002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1632
1633 * mips.igen: Remove gencode comment from top of file, fix
1634 spelling in another comment.
1635
97a88e93 16362002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1637
1638 * mips.igen (check_fmt, check_fmt_p): New functions to check
1639 whether specific floating point formats are usable.
1640 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1641 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1642 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1643 Use the new functions.
1644 (do_c_cond_fmt): Remove format checks...
1645 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1646
97a88e93 16472002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1648
1649 * mips.igen: Fix formatting of check_fpu calls.
1650
41774c9d
CD		 16512002-03-03 Chris Demetriou <cgd@broadcom.com>
1652
1653 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1654
4a0bd876
CD		 16552002-03-03 Chris Demetriou <cgd@broadcom.com>
1656
1657 * mips.igen: Remove whitespace at end of lines.
1658
09297648
CD		 16592002-03-02 Chris Demetriou <cgd@broadcom.com>
1660
1661 * mips.igen (loadstore_ea): New function to do effective
1662 address calculations.
1663 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1664 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1665 CACHE): Use loadstore_ea to do effective address computations.
1666
043b7057
CD		 16672002-03-02 Chris Demetriou <cgd@broadcom.com>
1668
1669 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1670 * mips.igen (LL, CxC1, MxC1): Likewise.
1671
c1e8ada4
CD		 16722002-03-02 Chris Demetriou <cgd@broadcom.com>
1673
1674 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1675 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1676 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1677 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1678 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1679 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1680 Don't split opcode fields by hand, use the opcode field values
1681 provided by igen.
1682
3e1dca16
CD		 16832002-03-01 Chris Demetriou <cgd@broadcom.com>
1684
1685 * mips.igen (do_divu): Fix spacing.
1686
1687 * mips.igen (do_dsllv): Move to be right before DSLLV,
1688 to match the rest of the do_<shift> functions.
1689
fff8d27d
CD		 16902002-03-01 Chris Demetriou <cgd@broadcom.com>
1691
1692 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1693 DSRL32, do_dsrlv): Trace inputs and results.
1694
0d3e762b
CD		 16952002-03-01 Chris Demetriou <cgd@broadcom.com>
1696
1697 * mips.igen (CACHE): Provide instruction-printing string.
1698
1699 * interp.c (signal_exception): Comment tokens after #endif.
1700
eb5fcf93
CD		 17012002-02-28 Chris Demetriou <cgd@broadcom.com>
1702
1703 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1704 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1705 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1706 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1707 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1708 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1709 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1710 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1711
bb22bd7d
CD		 17122002-02-28 Chris Demetriou <cgd@broadcom.com>
1713
1714 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1715 instruction-printing string.
1716 (LWU): Use '64' as the filter flag.
1717
91a177cf
CD		 17182002-02-28 Chris Demetriou <cgd@broadcom.com>
1719
1720 * mips.igen (SDXC1): Fix instruction-printing string.
1721
387f484a
CD		 17222002-02-28 Chris Demetriou <cgd@broadcom.com>
1723
1724 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1725 filter flags "32,f".
1726
3d81f391
CD		 17272002-02-27 Chris Demetriou <cgd@broadcom.com>
1728
1729 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1730 as the filter flag.
1731
af5107af
CD		 17322002-02-27 Chris Demetriou <cgd@broadcom.com>
1733
1734 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1735 add a comma) so that it more closely match the MIPS ISA
1736 documentation opcode partitioning.
1737 (PREF): Put useful names on opcode fields, and include
1738 instruction-printing string.
1739
ca971540
CD		 17402002-02-27 Chris Demetriou <cgd@broadcom.com>
1741
1742 * mips.igen (check_u64): New function which in the future will
1743 check whether 64-bit instructions are usable and signal an
1744 exception if not. Currently a no-op.
1745 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1746 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1747 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1748 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1749
1750 * mips.igen (check_fpu): New function which in the future will
1751 check whether FPU instructions are usable and signal an exception
1752 if not. Currently a no-op.
1753 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1754 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1755 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1756 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1757 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1758 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1759 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1760 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1761
1c47a468
CD		 17622002-02-27 Chris Demetriou <cgd@broadcom.com>
1763
1764 * mips.igen (do_load_left, do_load_right): Move to be immediately
1765 following do_load.
1766 (do_store_left, do_store_right): Move to be immediately following
1767 do_store.
1768
603a98e7
CD		 17692002-02-27 Chris Demetriou <cgd@broadcom.com>
1770
1771 * mips.igen (mipsV): New model name. Also, add it to
1772 all instructions and functions where it is appropriate.
1773
c5d00cc7
CD		 17742002-02-18 Chris Demetriou <cgd@broadcom.com>
1775
1776 * mips.igen: For all functions and instructions, list model
1777 names that support that instruction one per line.
1778
074e9cb8
CD		 17792002-02-11 Chris Demetriou <cgd@broadcom.com>
1780
1781 * mips.igen: Add some additional comments about supported
1782 models, and about which instructions go where.
1783 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1784 order as is used in the rest of the file.
1785
9805e229
CD		 17862002-02-11 Chris Demetriou <cgd@broadcom.com>
1787
1788 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1789 indicating that ALU32_END or ALU64_END are there to check
1790 for overflow.
1791 (DADD): Likewise, but also remove previous comment about
1792 overflow checking.
1793
f701dad2
CD		 17942002-02-10 Chris Demetriou <cgd@broadcom.com>
1795
1796 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1797 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1798 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1799 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1800 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1801 fields (i.e., add and move commas) so that they more closely
1802 match the MIPS ISA documentation opcode partitioning.
1803
18042002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1805
72f4393d
L		 1806 * mips.igen (ADDI): Print immediate value.
1807 (BREAK): Print code.
1808 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1809 (SLL): Print "nop" specially, and don't run the code
1810 that does the shift for the "nop" case.
20ae0098 1811
9e52972e
FF		 18122001-11-17 Fred Fish <fnf@redhat.com>
1813
1814 * sim-main.h (float_operation): Move enum declaration outside
1815 of _sim_cpu struct declaration.
1816
c0efbca4
JB		 18172001-04-12 Jim Blandy <jimb@redhat.com>
1818
1819 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1820 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1821 set of the FCSR.
1822 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1823 PENDING_FILL, and you can get the intended effect gracefully by
1824 calling PENDING_SCHED directly.
1825
fb891446
BE		 18262001-02-23 Ben Elliston <bje@redhat.com>
1827
1828 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1829 already defined elsewhere.
1830
8030f857
BE		 18312001-02-19 Ben Elliston <bje@redhat.com>
1832
1833 * sim-main.h (sim_monitor): Return an int.
1834 * interp.c (sim_monitor): Add return values.
1835 (signal_exception): Handle error conditions from sim_monitor.
1836
56b48a7a
CD		 18372001-02-08 Ben Elliston <bje@redhat.com>
1838
1839 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1840 (store_memory): Likewise, pass cia to sim_core_write*.
1841
d3ee60d9
FCE		 18422000-10-19 Frank Ch. Eigler <fche@redhat.com>
1843
1844 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1845 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1846
071da002
AC		 1847Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1850 * Makefile.in: Don't delete *.igen when cleaning directory.
1851
a28c02cd
AC		 1852Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * m16.igen (break): Call SignalException not sim_engine_halt.
1855
80ee11fa
AC		 1856Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 From Jason Eckhardt:
1859 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1860
673388c0
AC		 1861Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1862
1863 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1864
4c0deff4
NC		 18652000-05-24 Michael Hayes <mhayes@cygnus.com>
1866
1867 * mips.igen (do_dmultx): Fix typo.
1868
eb2d80b4
AC		 1869Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872
dd37a34b
AC		 1873Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1876
4c0deff4
NC		 18772000-04-12 Frank Ch. Eigler <fche@redhat.com>
1878
1879 * sim-main.h (GPR_CLEAR): Define macro.
1880
e30db738
AC		 1881Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1882
1883 * interp.c (decode_coproc): Output long using %lx and not %s.
1884
cb7450ea
FCE		 18852000-03-21 Frank Ch. Eigler <fche@redhat.com>
1886
1887 * interp.c (sim_open): Sort & extend dummy memory regions for
1888 --board=jmr3904 for eCos.
1889
a3027dd7
FCE		 18902000-03-02 Frank Ch. Eigler <fche@redhat.com>
1891
1892 * configure: Regenerated.
1893
1894Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1895
1896 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1897 calls, conditional on the simulator being in verbose mode.
1898
dfcd3bfb
JM		 1899Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1900
1901 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1902 cache don't get ReservedInstruction traps.
1903
c2d11a7d
JM		 19041999-11-29 Mark Salter <msalter@cygnus.com>
1905
1906 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1907 to clear status bits in sdisr register. This is how the hardware works.
1908
1909 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1910 being used by cygmon.
1911
4ce44c66
JM		 19121999-11-11 Andrew Haley <aph@cygnus.com>
1913
1914 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1915 instructions.
1916
cff3e48b
JM		 1917Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1918
1919 * mips.igen (MULT): Correct previous mis-applied patch.
1920
d4f3574e
SS		 1921Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1922
1923 * mips.igen (delayslot32): Handle sequence like
1924 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1925 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1926 (MULT): Actually pass the third register...
1927
19281999-09-03 Mark Salter <msalter@cygnus.com>
1929
1930 * interp.c (sim_open): Added more memory aliases for additional
1931 hardware being touched by cygmon on jmr3904 board.
1932
1933Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * configure: Regenerated to track ../common/aclocal.m4 changes.
1936
a0b3c4fd
JM		 1937Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1938
1939 * interp.c (sim_store_register): Handle case where client - GDB -
1940 specifies that a 4 byte register is 8 bytes in size.
1941 (sim_fetch_register): Ditto.
72f4393d 1942
adf40b2e
JM		 19431999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1944
1945 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1946 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1947 (idt_monitor_base): Base address for IDT monitor traps.
1948 (pmon_monitor_base): Ditto for PMON.
1949 (lsipmon_monitor_base): Ditto for LSI PMON.
1950 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1951 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1952 (sim_firmware_command): New function.
1953 (mips_option_handler): Call it for OPTION_FIRMWARE.
1954 (sim_open): Allocate memory for idt_monitor region. If "--board"
1955 option was given, add no monitor by default. Add BREAK hooks only if
1956 monitors are also there.
72f4393d 1957
43e526b9
JM		 1958Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1959
1960 * interp.c (sim_monitor): Flush output before reading input.
1961
1962Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * tconfig.in (SIM_HANDLES_LMA): Always define.
1965
1966Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 From Mark Salter <msalter@cygnus.com>:
1969 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1970 (sim_open): Add setup for BSP board.
1971
9846de1b
JM		 1972Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1975 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1976 them as unimplemented.
1977
cd0fc7c3
SS		 19781999-05-08 Felix Lee <flee@cygnus.com>
1979
1980 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1981
7a292a7a
SS		 19821999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1983
1984 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1985
1986Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1987
1988 * configure.in: Any mips64vr5*-*-* target should have
1989 -DTARGET_ENABLE_FR=1.
1990 (default_endian): Any mips64vr*el-*-* target should default to
1991 LITTLE_ENDIAN.
1992 * configure: Re-generate.
1993
19941999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1995
1996 * mips.igen (ldl): Extend from _16_, not 32.
1997
1998Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1999
2000 * interp.c (sim_store_register): Force registers written to by GDB
2001 into an un-interpreted state.
2002
c906108c
SS		 20031999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2004
2005 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2006 CPU, start periodic background I/O polls.
72f4393d 2007 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2008
20091998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2010
2011 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2012
c906108c
SS		 2013Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2014
2015 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2016 case statement.
2017
20181998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2019
2020 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2021 (load_word): Call SIM_CORE_SIGNAL hook on error.
2022 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2023 starting. For exception dispatching, pass PC instead of NULL_CIA.
2024 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2025 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2026 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2027 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2028 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2029 * mips.igen (*): Replace memory-related SignalException* calls
2030 with references to SIM_CORE_SIGNAL hook.
72f4393d 2031
c906108c
SS		 2032 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2033 fix.
2034 * sim-main.c (*): Minor warning cleanups.
72f4393d 2035
c906108c
SS		 20361998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2037
2038 * m16.igen (DADDIU5): Correct type-o.
2039
2040Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2041
2042 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2043 variables.
2044
2045Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2046
2047 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2048 to include path.
2049 (interp.o): Add dependency on itable.h
2050 (oengine.c, gencode): Delete remaining references.
2051 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2052
c906108c 20531998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2054
c906108c
SS		 2055 * vr4run.c: New.
2056 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2057 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2058 tmp-run-hack) : New.
2059 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2060 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2061 Drop the "64" qualifier to get the HACK generator working.
2062 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2063 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2064 qualifier to get the hack generator working.
2065 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2066 (DSLL): Use do_dsll.
2067 (DSLLV): Use do_dsllv.
2068 (DSRA): Use do_dsra.
2069 (DSRL): Use do_dsrl.
2070 (DSRLV): Use do_dsrlv.
2071 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2072 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2073 get the HACK generator working.
2074 (MACC) Rename to get the HACK generator working.
2075 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2076
c906108c
SS		 20771998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2078
2079 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2080 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2081
c906108c
SS		 20821998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2083
2084 * mips/interp.c (DEBUG): Cleanups.
2085
20861998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2087
2088 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2089 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2090
c906108c
SS		 20911998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2092
2093 * interp.c (sim_close): Uninstall modules.
2094
2095Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2096
2097 * sim-main.h, interp.c (sim_monitor): Change to global
2098 function.
2099
2100Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * configure.in (vr4100): Only include vr4100 instructions in
2103 simulator.
2104 * configure: Re-generate.
2105 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2106
2107Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2110 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2111 true alternative.
2112
2113 * configure.in (sim_default_gen, sim_use_gen): Replace with
2114 sim_gen.
2115 (--enable-sim-igen): Delete config option. Always using IGEN.
2116 * configure: Re-generate.
72f4393d 2117
c906108c
SS		 2118 * Makefile.in (gencode): Kill, kill, kill.
2119 * gencode.c: Ditto.
72f4393d 2120
c906108c
SS		 2121Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2122
2123 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2124 bit mips16 igen simulator.
2125 * configure: Re-generate.
2126
2127 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2128 as part of vr4100 ISA.
2129 * vr.igen: Mark all instructions as 64 bit only.
2130
2131Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2134 Pacify GCC.
2135
2136Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2139 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2140 * configure: Re-generate.
2141
2142 * m16.igen (BREAK): Define breakpoint instruction.
2143 (JALX32): Mark instruction as mips16 and not r3900.
2144 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2145
2146 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2147
2148Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2151 insn as a debug breakpoint.
2152
2153 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2154 pending.slot_size.
2155 (PENDING_SCHED): Clean up trace statement.
2156 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2157 (PENDING_FILL): Delay write by only one cycle.
2158 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2159
2160 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2161 of pending writes.
2162 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2163 32 & 64.
2164 (pending_tick): Move incrementing of index to FOR statement.
2165 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2166
c906108c
SS		 2167 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2168 build simulator.
2169 * configure: Re-generate.
72f4393d 2170
c906108c
SS		 2171 * interp.c (sim_engine_run OLD): Delete explicit call to
2172 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2173
c906108c
SS		 2174Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2175
2176 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2177 interrupt level number to match changed SignalExceptionInterrupt
2178 macro.
2179
2180Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2181
2182 * interp.c: #include "itable.h" if WITH_IGEN.
2183 (get_insn_name): New function.
2184 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2185 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2186
2187Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2188
2189 * configure: Rebuilt to inhale new common/aclocal.m4.
2190
2191Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2192
2193 * dv-tx3904sio.c: Include sim-assert.h.
2194
2195Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2196
2197 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2198 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2199 Reorganize target-specific sim-hardware checks.
2200 * configure: rebuilt.
2201 * interp.c (sim_open): For tx39 target boards, set
2202 OPERATING_ENVIRONMENT, add tx3904sio devices.
2203 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2204 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2205
c906108c
SS		 2206 * dv-tx3904irc.c: Compiler warning clean-up.
2207 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2208 frequent hw-trace messages.
2209
2210Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2211
2212 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2213
2214Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2215
2216 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2217
2218 * vr.igen: New file.
2219 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2220 * mips.igen: Define vr4100 model. Include vr.igen.
2221Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2222
2223 * mips.igen (check_mf_hilo): Correct check.
2224
2225Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * sim-main.h (interrupt_event): Add prototype.
2228
2229 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2230 register_ptr, register_value.
2231 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2232
2233 * sim-main.h (tracefh): Make extern.
2234
2235Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2236
2237 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2238 Reduce unnecessarily high timer event frequency.
c906108c 2239 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2240
c906108c
SS		 2241Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2242
2243 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2244 to allay warnings.
2245 (interrupt_event): Made non-static.
72f4393d 2246
c906108c
SS		 2247 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2248 interchange of configuration values for external vs. internal
2249 clock dividers.
72f4393d 2250
c906108c
SS		 2251Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2252
72f4393d 2253 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2254 simulator-reserved break instructions.
2255 * gencode.c (build_instruction): Ditto.
2256 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2257 reserved instructions now use exception vector, rather
c906108c
SS		 2258 than halting sim.
2259 * sim-main.h: Moved magic constants to here.
2260
2261Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2262
2263 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2264 register upon non-zero interrupt event level, clear upon zero
2265 event value.
2266 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2267 by passing zero event value.
2268 (*_io_{read,write}_buffer): Endianness fixes.
2269 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2270 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2271
2272 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2273 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2274
c906108c
SS		 2275Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2276
72f4393d 2277 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2278 and BigEndianCPU.
2279
2280Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2281
2282 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2283 parts.
2284 * configure: Update.
2285
2286Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2287
2288 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2289 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2290 * configure.in: Include tx3904tmr in hw_device list.
2291 * configure: Rebuilt.
2292 * interp.c (sim_open): Instantiate three timer instances.
2293 Fix address typo of tx3904irc instance.
2294
2295Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2296
2297 * interp.c (signal_exception): SystemCall exception now uses
2298 the exception vector.
2299
2300Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2301
2302 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2303 to allay warnings.
2304
2305Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2308
2309Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2310
2311 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2312
2313 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2314 sim-main.h. Declare a struct hw_descriptor instead of struct
2315 hw_device_descriptor.
2316
2317Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2318
2319 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2320 right bits and then re-align left hand bytes to correct byte
2321 lanes. Fix incorrect computation in do_store_left when loading
2322 bytes from second word.
2323
2324Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2327 * interp.c (sim_open): Only create a device tree when HW is
2328 enabled.
2329
2330 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2331 * interp.c (signal_exception): Ditto.
2332
2333Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2334
2335 * gencode.c: Mark BEGEZALL as LIKELY.
2336
2337Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2340 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2341
c906108c
SS		 2342Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2343
2344 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2345 modules. Recognize TX39 target with "mips*tx39" pattern.
2346 * configure: Rebuilt.
2347 * sim-main.h (*): Added many macros defining bits in
2348 TX39 control registers.
2349 (SignalInterrupt): Send actual PC instead of NULL.
2350 (SignalNMIReset): New exception type.
2351 * interp.c (board): New variable for future use to identify
2352 a particular board being simulated.
2353 (mips_option_handler,mips_options): Added "--board" option.
2354 (interrupt_event): Send actual PC.
2355 (sim_open): Make memory layout conditional on board setting.
2356 (signal_exception): Initial implementation of hardware interrupt
2357 handling. Accept another break instruction variant for simulator
2358 exit.
2359 (decode_coproc): Implement RFE instruction for TX39.
2360 (mips.igen): Decode RFE instruction as such.
2361 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2362 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2363 bbegin to implement memory map.
2364 * dv-tx3904cpu.c: New file.
2365 * dv-tx3904irc.c: New file.
2366
2367Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2368
2369 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2370
2371Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2372
2373 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2374 with calls to check_div_hilo.
2375
2376Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2377
2378 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2379 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2380 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2381 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2382 with calls to check_mult_hilo.
2383 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2384 with calls to check_div_hilo.
2385
2386Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2389 Document a replacement.
2390
2391Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2392
2393 * interp.c (sim_monitor): Make mon_printf work.
2394
2395Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2396
2397 * sim-main.h (INSN_NAME): New arg `cpu'.
2398
2399Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2400
72f4393d 2401 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2402
2403Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2404
2405 * configure: Regenerated to track ../common/aclocal.m4 changes.
2406 * config.in: Ditto.
2407
2408Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2409
2410 * acconfig.h: New file.
2411 * configure.in: Reverted change of Apr 24; use sinclude again.
2412
2413Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2414
2415 * configure: Regenerated to track ../common/aclocal.m4 changes.
2416 * config.in: Ditto.
2417
2418Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2419
2420 * configure.in: Don't call sinclude.
2421
2422Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2423
2424 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2425
2426Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2427
2428 * mips.igen (ERET): Implement.
2429
2430 * interp.c (decode_coproc): Return sign-extended EPC.
2431
2432 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2433
2434 * interp.c (signal_exception): Do not ignore Trap.
2435 (signal_exception): On TRAP, restart at exception address.
2436 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2437 (signal_exception): Update.
2438 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2439 so that TRAP instructions are caught.
2440
2441Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2442
2443 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2444 contains HI/LO access history.
2445 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2446 (HIACCESS, LOACCESS): Delete, replace with
2447 (HIHISTORY, LOHISTORY): New macros.
2448 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2449
c906108c
SS		 2450 * gencode.c (build_instruction): Do not generate checks for
2451 correct HI/LO register usage.
2452
2453 * interp.c (old_engine_run): Delete checks for correct HI/LO
2454 register usage.
2455
2456 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2457 check_mf_cycles): New functions.
2458 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2459 do_divu, domultx, do_mult, do_multu): Use.
2460
2461 * tx.igen ("madd", "maddu"): Use.
72f4393d 2462
c906108c
SS		 2463Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2464
2465 * mips.igen (DSRAV): Use function do_dsrav.
2466 (SRAV): Use new function do_srav.
2467
2468 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2469 (B): Sign extend 11 bit immediate.
2470 (EXT-B*): Shift 16 bit immediate left by 1.
2471 (ADDIU*): Don't sign extend immediate value.
2472
2473Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2474
2475 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2476
2477 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2478 functions.
2479
2480 * mips.igen (delayslot32, nullify_next_insn): New functions.
2481 (m16.igen): Always include.
2482 (do_*): Add more tracing.
2483
2484 * m16.igen (delayslot16): Add NIA argument, could be called by a
2485 32 bit MIPS16 instruction.
72f4393d 2486
c906108c
SS		 2487 * interp.c (ifetch16): Move function from here.
2488 * sim-main.c (ifetch16): To here.
72f4393d 2489
c906108c
SS		 2490 * sim-main.c (ifetch16, ifetch32): Update to match current
2491 implementations of LH, LW.
2492 (signal_exception): Don't print out incorrect hex value of illegal
2493 instruction.
2494
2495Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2496
2497 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2498 instruction.
2499
2500 * m16.igen: Implement MIPS16 instructions.
72f4393d 2501
c906108c
SS		 2502 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2503 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2504 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2505 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2506 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2507 bodies of corresponding code from 32 bit insn to these. Also used
2508 by MIPS16 versions of functions.
72f4393d 2509
c906108c
SS		 2510 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2511 (IMEM16): Drop NR argument from macro.
2512
2513Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * Makefile.in (SIM_OBJS): Add sim-main.o.
2516
2517 * sim-main.h (address_translation, load_memory, store_memory,
2518 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2519 as INLINE_SIM_MAIN.
2520 (pr_addr, pr_uword64): Declare.
2521 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2522
c906108c
SS		 2523 * interp.c (address_translation, load_memory, store_memory,
2524 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2525 from here.
2526 * sim-main.c: To here. Fix compilation problems.
72f4393d 2527
c906108c
SS		 2528 * configure.in: Enable inlining.
2529 * configure: Re-config.
2530
2531Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2532
2533 * configure: Regenerated to track ../common/aclocal.m4 changes.
2534
2535Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * mips.igen: Include tx.igen.
2538 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2539 * tx.igen: New file, contains MADD and MADDU.
2540
2541 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2542 the hardwired constant `7'.
2543 (store_memory): Ditto.
2544 (LOADDRMASK): Move definition to sim-main.h.
2545
2546 mips.igen (MTC0): Enable for r3900.
2547 (ADDU): Add trace.
2548
2549 mips.igen (do_load_byte): Delete.
2550 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2551 do_store_right): New functions.
2552 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2553
2554 configure.in: Let the tx39 use igen again.
2555 configure: Update.
72f4393d 2556
c906108c
SS		 2557Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2560 not an address sized quantity. Return zero for cache sizes.
2561
2562Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2563
2564 * mips.igen (r3900): r3900 does not support 64 bit integer
2565 operations.
2566
2567Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2568
2569 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2570 than igen one.
2571 * configure : Rebuild.
72f4393d 2572
c906108c
SS		 2573Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2574
2575 * configure: Regenerated to track ../common/aclocal.m4 changes.
2576
2577Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2578
2579 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2580
2581Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2582
2583 * configure: Regenerated to track ../common/aclocal.m4 changes.
2584 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2585
2586Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2587
2588 * configure: Regenerated to track ../common/aclocal.m4 changes.
2589
2590Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2591
2592 * interp.c (Max, Min): Comment out functions. Not yet used.
2593
2594Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2595
2596 * configure: Regenerated to track ../common/aclocal.m4 changes.
2597
2598Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2599
2600 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2601 configurable settings for stand-alone simulator.
72f4393d 2602
c906108c 2603 * configure.in: Added X11 search, just in case.
72f4393d 2604
c906108c
SS		 2605 * configure: Regenerated.
2606
2607Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2608
2609 * interp.c (sim_write, sim_read, load_memory, store_memory):
2610 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2611
2612Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2613
2614 * sim-main.h (GETFCC): Return an unsigned value.
2615
2616Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2617
2618 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2619 (DADD): Result destination is RD not RT.
2620
2621Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2622
2623 * sim-main.h (HIACCESS, LOACCESS): Always define.
2624
2625 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2626
2627 * interp.c (sim_info): Delete.
2628
2629Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2630
2631 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2632 (mips_option_handler): New argument `cpu'.
2633 (sim_open): Update call to sim_add_option_table.
2634
2635Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * mips.igen (CxC1): Add tracing.
2638
2639Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2640
2641 * sim-main.h (Max, Min): Declare.
2642
2643 * interp.c (Max, Min): New functions.
2644
2645 * mips.igen (BC1): Add tracing.
72f4393d 2646
c906108c 2647Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2648
c906108c 2649 * interp.c Added memory map for stack in vr4100
72f4393d 2650
c906108c
SS		 2651Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2652
2653 * interp.c (load_memory): Add missing "break"'s.
2654
2655Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2656
2657 * interp.c (sim_store_register, sim_fetch_register): Pass in
2658 length parameter. Return -1.
2659
2660Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2661
2662 * interp.c: Added hardware init hook, fixed warnings.
2663
2664Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2665
2666 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2667
2668Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2669
2670 * interp.c (ifetch16): New function.
2671
2672 * sim-main.h (IMEM32): Rename IMEM.
2673 (IMEM16_IMMED): Define.
2674 (IMEM16): Define.
2675 (DELAY_SLOT): Update.
72f4393d 2676
c906108c 2677 * m16run.c (sim_engine_run): New file.
72f4393d 2678
c906108c
SS		 2679 * m16.igen: All instructions except LB.
2680 (LB): Call do_load_byte.
2681 * mips.igen (do_load_byte): New function.
2682 (LB): Call do_load_byte.
2683
2684 * mips.igen: Move spec for insn bit size and high bit from here.
2685 * Makefile.in (tmp-igen, tmp-m16): To here.
2686
2687 * m16.dc: New file, decode mips16 instructions.
2688
2689 * Makefile.in (SIM_NO_ALL): Define.
2690 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2691
2692Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2693
2694 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2695 point unit to 32 bit registers.
2696 * configure: Re-generate.
2697
2698Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2699
2700 * configure.in (sim_use_gen): Make IGEN the default simulator
2701 generator for generic 32 and 64 bit mips targets.
2702 * configure: Re-generate.
2703
2704Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2705
2706 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2707 bitsize.
2708
2709 * interp.c (sim_fetch_register, sim_store_register): Read/write
2710 FGR from correct location.
2711 (sim_open): Set size of FGR's according to
2712 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2713
c906108c
SS		 2714 * sim-main.h (FGR): Store floating point registers in a separate
2715 array.
2716
2717Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * configure: Regenerated to track ../common/aclocal.m4 changes.
2720
2721Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2722
2723 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2724
2725 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2726
2727 * interp.c (pending_tick): New function. Deliver pending writes.
2728
2729 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2730 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2731 it can handle mixed sized quantites and single bits.
72f4393d 2732
c906108c
SS		 2733Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2734
2735 * interp.c (oengine.h): Do not include when building with IGEN.
2736 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2737 (sim_info): Ditto for PROCESSOR_64BIT.
2738 (sim_monitor): Replace ut_reg with unsigned_word.
2739 (*): Ditto for t_reg.
2740 (LOADDRMASK): Define.
2741 (sim_open): Remove defunct check that host FP is IEEE compliant,
2742 using software to emulate floating point.
2743 (value_fpr, ...): Always compile, was conditional on HASFPU.
2744
2745Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2746
2747 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2748 size.
2749
2750 * interp.c (SD, CPU): Define.
2751 (mips_option_handler): Set flags in each CPU.
2752 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2753 (sim_close): Do not clear STATE, deleted anyway.
2754 (sim_write, sim_read): Assume CPU zero's vm should be used for
2755 data transfers.
2756 (sim_create_inferior): Set the PC for all processors.
2757 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2758 argument.
2759 (mips16_entry): Pass correct nr of args to store_word, load_word.
2760 (ColdReset): Cold reset all cpu's.
2761 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2762 (sim_monitor, load_memory, store_memory, signal_exception): Use
2763 `CPU' instead of STATE_CPU.
2764
2765
2766 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2767 SD or CPU_.
72f4393d 2768
c906108c
SS		 2769 * sim-main.h (signal_exception): Add sim_cpu arg.
2770 (SignalException*): Pass both SD and CPU to signal_exception.
2771 * interp.c (signal_exception): Update.
72f4393d 2772
c906108c
SS		 2773 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2774 Ditto
2775 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2776 address_translation): Ditto
2777 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2778
c906108c
SS		 2779Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2780
2781 * configure: Regenerated to track ../common/aclocal.m4 changes.
2782
2783Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2784
2785 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2786
72f4393d 2787 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2788
2789 * sim-main.h (CPU_CIA): Delete.
2790 (SET_CIA, GET_CIA): Define
2791
2792Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2795 regiser.
2796
2797 * configure.in (default_endian): Configure a big-endian simulator
2798 by default.
2799 * configure: Re-generate.
72f4393d 2800
c906108c
SS		 2801Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2802
2803 * configure: Regenerated to track ../common/aclocal.m4 changes.
2804
2805Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2806
2807 * interp.c (sim_monitor): Handle Densan monitor outbyte
2808 and inbyte functions.
2809
28101997-12-29 Felix Lee <flee@cygnus.com>
2811
2812 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2813
2814Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2815
2816 * Makefile.in (tmp-igen): Arrange for $zero to always be
2817 reset to zero after every instruction.
2818
2819Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2820
2821 * configure: Regenerated to track ../common/aclocal.m4 changes.
2822 * config.in: Ditto.
2823
2824Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2825
2826 * mips.igen (MSUB): Fix to work like MADD.
2827 * gencode.c (MSUB): Similarly.
2828
2829Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2830
2831 * configure: Regenerated to track ../common/aclocal.m4 changes.
2832
2833Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2836
2837Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2838
2839 * sim-main.h (sim-fpu.h): Include.
2840
2841 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2842 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2843 using host independant sim_fpu module.
2844
2845Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2846
2847 * interp.c (signal_exception): Report internal errors with SIGABRT
2848 not SIGQUIT.
2849
2850 * sim-main.h (C0_CONFIG): New register.
2851 (signal.h): No longer include.
2852
2853 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2854
2855Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2856
2857 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2858
2859Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2860
2861 * mips.igen: Tag vr5000 instructions.
2862 (ANDI): Was missing mipsIV model, fix assembler syntax.
2863 (do_c_cond_fmt): New function.
2864 (C.cond.fmt): Handle mips I-III which do not support CC field
2865 separatly.
2866 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2867 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2868 in IV3.2 spec.
2869 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2870 vr5000 which saves LO in a GPR separatly.
72f4393d 2871
c906108c
SS		 2872 * configure.in (enable-sim-igen): For vr5000, select vr5000
2873 specific instructions.
2874 * configure: Re-generate.
72f4393d 2875
c906108c
SS		 2876Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877
2878 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2879
2880 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2881 fmt_uninterpreted_64 bit cases to switch. Convert to
2882 fmt_formatted,
2883
2884 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2885
2886 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2887 as specified in IV3.2 spec.
2888 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2889
2890Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2891
2892 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2893 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2894 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2895 PENDING_FILL versions of instructions. Simplify.
2896 (X): New function.
2897 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2898 instructions.
2899 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2900 a signed value.
2901 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2902
c906108c
SS		 2903 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2904 global.
2905 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2906
2907Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2908
2909 * gencode.c (build_mips16_operands): Replace IPC with cia.
2910
2911 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2912 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2913 IPC to `cia'.
2914 (UndefinedResult): Replace function with macro/function
2915 combination.
2916 (sim_engine_run): Don't save PC in IPC.
2917
2918 * sim-main.h (IPC): Delete.
2919
2920
2921 * interp.c (signal_exception, store_word, load_word,
2922 address_translation, load_memory, store_memory, cache_op,
2923 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2924 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2925 current instruction address - cia - argument.
2926 (sim_read, sim_write): Call address_translation directly.
2927 (sim_engine_run): Rename variable vaddr to cia.
2928 (signal_exception): Pass cia to sim_monitor
72f4393d 2929
c906108c
SS		 2930 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2931 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2932 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2933
2934 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2935 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2936 SIM_ASSERT.
72f4393d 2937
c906108c
SS		 2938 * interp.c (signal_exception): Pass restart address to
2939 sim_engine_restart.
2940
2941 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2942 idecode.o): Add dependency.
2943
2944 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2945 Delete definitions
2946 (DELAY_SLOT): Update NIA not PC with branch address.
2947 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2948
2949 * mips.igen: Use CIA not PC in branch calculations.
2950 (illegal): Call SignalException.
2951 (BEQ, ADDIU): Fix assembler.
2952
2953Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2954
2955 * m16.igen (JALX): Was missing.
2956
2957 * configure.in (enable-sim-igen): New configuration option.
2958 * configure: Re-generate.
72f4393d 2959
c906108c
SS		 2960 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2961
2962 * interp.c (load_memory, store_memory): Delete parameter RAW.
2963 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2964 bypassing {load,store}_memory.
2965
2966 * sim-main.h (ByteSwapMem): Delete definition.
2967
2968 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2969
2970 * interp.c (sim_do_command, sim_commands): Delete mips specific
2971 commands. Handled by module sim-options.
72f4393d 2972
c906108c
SS		 2973 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2974 (WITH_MODULO_MEMORY): Define.
2975
2976 * interp.c (sim_info): Delete code printing memory size.
2977
2978 * interp.c (mips_size): Nee sim_size, delete function.
2979 (power2): Delete.
2980 (monitor, monitor_base, monitor_size): Delete global variables.
2981 (sim_open, sim_close): Delete code creating monitor and other
2982 memory regions. Use sim-memopts module, via sim_do_commandf, to
2983 manage memory regions.
2984 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2985
c906108c
SS		 2986 * interp.c (address_translation): Delete all memory map code
2987 except line forcing 32 bit addresses.
2988
2989Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2992 trace options.
2993
2994 * interp.c (logfh, logfile): Delete globals.
2995 (sim_open, sim_close): Delete code opening & closing log file.
2996 (mips_option_handler): Delete -l and -n options.
2997 (OPTION mips_options): Ditto.
2998
2999 * interp.c (OPTION mips_options): Rename option trace to dinero.
3000 (mips_option_handler): Update.
3001
3002Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3003
3004 * interp.c (fetch_str): New function.
3005 (sim_monitor): Rewrite using sim_read & sim_write.
3006 (sim_open): Check magic number.
3007 (sim_open): Write monitor vectors into memory using sim_write.
3008 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3009 (sim_read, sim_write): Simplify - transfer data one byte at a
3010 time.
3011 (load_memory, store_memory): Clarify meaning of parameter RAW.
3012
3013 * sim-main.h (isHOST): Defete definition.
3014 (isTARGET): Mark as depreciated.
3015 (address_translation): Delete parameter HOST.
3016
3017 * interp.c (address_translation): Delete parameter HOST.
3018
3019Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3020
72f4393d 3021 * mips.igen:
c906108c
SS		 3022
3023 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3024 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3025
3026Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3027
3028 * mips.igen: Add model filter field to records.
3029
3030Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3031
3032 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3033
c906108c
SS		 3034 interp.c (sim_engine_run): Do not compile function sim_engine_run
3035 when WITH_IGEN == 1.
3036
3037 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3038 target architecture.
3039
3040 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3041 igen. Replace with configuration variables sim_igen_flags /
3042 sim_m16_flags.
3043
3044 * m16.igen: New file. Copy mips16 insns here.
3045 * mips.igen: From here.
3046
3047Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3048
3049 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3050 to top.
3051 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3052
3053Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3054
3055 * gencode.c (build_instruction): Follow sim_write's lead in using
3056 BigEndianMem instead of !ByteSwapMem.
3057
3058Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3059
3060 * configure.in (sim_gen): Dependent on target, select type of
3061 generator. Always select old style generator.
3062
3063 configure: Re-generate.
3064
3065 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3066 targets.
3067 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3068 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3069 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3070 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3071 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3072
c906108c
SS		 3073Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3076
3077 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3078 CURRENT_FLOATING_POINT instead.
3079
3080 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3081 (address_translation): Raise exception InstructionFetch when
3082 translation fails and isINSTRUCTION.
72f4393d 3083
c906108c
SS		 3084 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3085 sim_engine_run): Change type of of vaddr and paddr to
3086 address_word.
3087 (address_translation, prefetch, load_memory, store_memory,
3088 cache_op): Change type of vAddr and pAddr to address_word.
3089
3090 * gencode.c (build_instruction): Change type of vaddr and paddr to
3091 address_word.
3092
3093Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3096 macro to obtain result of ALU op.
3097
3098Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3099
3100 * interp.c (sim_info): Call profile_print.
3101
3102Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3103
3104 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3105
3106 * sim-main.h (WITH_PROFILE): Do not define, defined in
3107 common/sim-config.h. Use sim-profile module.
3108 (simPROFILE): Delete defintion.
3109
3110 * interp.c (PROFILE): Delete definition.
3111 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3112 (sim_close): Delete code writing profile histogram.
3113 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3114 Delete.
3115 (sim_engine_run): Delete code profiling the PC.
3116
3117Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3118
3119 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3120
3121 * interp.c (sim_monitor): Make register pointers of type
3122 unsigned_word*.
3123
3124 * sim-main.h: Make registers of type unsigned_word not
3125 signed_word.
3126
3127Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * interp.c (sync_operation): Rename from SyncOperation, make
3130 global, add SD argument.
3131 (prefetch): Rename from Prefetch, make global, add SD argument.
3132 (decode_coproc): Make global.
3133
3134 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3135
3136 * gencode.c (build_instruction): Generate DecodeCoproc not
3137 decode_coproc calls.
3138
3139 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3140 (SizeFGR): Move to sim-main.h
3141 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3142 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3143 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3144 sim-main.h.
3145 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3146 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3147 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3148 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3149 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3150 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3151
c906108c
SS		 3152 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3153 exception.
3154 (sim-alu.h): Include.
3155 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3156 (sim_cia): Typedef to instruction_address.
72f4393d 3157
c906108c
SS		 3158Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * Makefile.in (interp.o): Rename generated file engine.c to
3161 oengine.c.
72f4393d 3162
c906108c 3163 * interp.c: Update.
72f4393d 3164
c906108c
SS		 3165Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3166
3167 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3168
c906108c
SS		 3169Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3170
3171 * gencode.c (build_instruction): For "FPSQRT", output correct
3172 number of arguments to Recip.
72f4393d 3173
c906108c
SS		 3174Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3175
3176 * Makefile.in (interp.o): Depends on sim-main.h
3177
3178 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3179
3180 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3181 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3182 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3183 STATE, DSSTATE): Define
3184 (GPR, FGRIDX, ..): Define.
3185
3186 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3187 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3188 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3189
c906108c 3190 * interp.c: Update names to match defines from sim-main.h
72f4393d 3191
c906108c
SS		 3192Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3193
3194 * interp.c (sim_monitor): Add SD argument.
3195 (sim_warning): Delete. Replace calls with calls to
3196 sim_io_eprintf.
3197 (sim_error): Delete. Replace calls with sim_io_error.
3198 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3199 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3200 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3201 argument.
3202 (mips_size): Rename from sim_size. Add SD argument.
3203
3204 * interp.c (simulator): Delete global variable.
3205 (callback): Delete global variable.
3206 (mips_option_handler, sim_open, sim_write, sim_read,
3207 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3208 sim_size,sim_monitor): Use sim_io_* not callback->*.
3209 (sim_open): ZALLOC simulator struct.
3210 (PROFILE): Do not define.
3211
3212Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3213
3214 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3215 support.h with corresponding code.
3216
3217 * sim-main.h (word64, uword64), support.h: Move definition to
3218 sim-main.h.
3219 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3220
3221 * support.h: Delete
3222 * Makefile.in: Update dependencies
3223 * interp.c: Do not include.
72f4393d 3224
c906108c
SS		 3225Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3226
3227 * interp.c (address_translation, load_memory, store_memory,
3228 cache_op): Rename to from AddressTranslation et.al., make global,
3229 add SD argument
72f4393d 3230
c906108c
SS		 3231 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3232 CacheOp): Define.
72f4393d 3233
c906108c
SS		 3234 * interp.c (SignalException): Rename to signal_exception, make
3235 global.
3236
3237 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3238
c906108c
SS		 3239 * sim-main.h (SignalException, SignalExceptionInterrupt,
3240 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3241 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3242 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3243 Define.
72f4393d 3244
c906108c 3245 * interp.c, support.h: Use.
72f4393d 3246
c906108c
SS		 3247Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3248
3249 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3250 to value_fpr / store_fpr. Add SD argument.
3251 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3252 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3253
3254 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3255
c906108c
SS		 3256Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3257
3258 * interp.c (sim_engine_run): Check consistency between configure
3259 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3260 and HASFPU.
3261
3262 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3263 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3264 (mips_endian): Configure WITH_TARGET_ENDIAN.
3265 * configure: Update.
3266
3267Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3268
3269 * configure: Regenerated to track ../common/aclocal.m4 changes.
3270
3271Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3272
3273 * configure: Regenerated.
3274
3275Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3276
3277 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3278
3279Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3280
3281 * gencode.c (print_igen_insn_models): Assume certain architectures
3282 include all mips* instructions.
3283 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3284 instruction.
3285
3286 * Makefile.in (tmp.igen): Add target. Generate igen input from
3287 gencode file.
3288
3289 * gencode.c (FEATURE_IGEN): Define.
3290 (main): Add --igen option. Generate output in igen format.
3291 (process_instructions): Format output according to igen option.
3292 (print_igen_insn_format): New function.
3293 (print_igen_insn_models): New function.
3294 (process_instructions): Only issue warnings and ignore
3295 instructions when no FEATURE_IGEN.
3296
3297Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3298
3299 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3300 MIPS targets.
3301
3302Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3303
3304 * configure: Regenerated to track ../common/aclocal.m4 changes.
3305
3306Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3307
3308 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3309 SIM_RESERVED_BITS): Delete, moved to common.
3310 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3311
c906108c
SS		 3312Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3313
3314 * configure.in: Configure non-strict memory alignment.
3315 * configure: Regenerated to track ../common/aclocal.m4 changes.
3316
3317Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3318
3319 * configure: Regenerated to track ../common/aclocal.m4 changes.
3320
3321Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3322
3323 * gencode.c (SDBBP,DERET): Added (3900) insns.
3324 (RFE): Turn on for 3900.
3325 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3326 (dsstate): Made global.
3327 (SUBTARGET_R3900): Added.
3328 (CANCELDELAYSLOT): New.
3329 (SignalException): Ignore SystemCall rather than ignore and
3330 terminate. Add DebugBreakPoint handling.
3331 (decode_coproc): New insns RFE, DERET; and new registers Debug
3332 and DEPC protected by SUBTARGET_R3900.
3333 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3334 bits explicitly.
3335 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3336 * configure: Update.
c906108c
SS		 3337
3338Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3339
3340 * gencode.c: Add r3900 (tx39).
72f4393d 3341
c906108c
SS		 3342
3343Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3344
3345 * gencode.c (build_instruction): Don't need to subtract 4 for
3346 JALR, just 2.
3347
3348Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3349
3350 * interp.c: Correct some HASFPU problems.
3351
3352Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3353
3354 * configure: Regenerated to track ../common/aclocal.m4 changes.
3355
3356Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3357
3358 * interp.c (mips_options): Fix samples option short form, should
3359 be `x'.
3360
3361Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3362
3363 * interp.c (sim_info): Enable info code. Was just returning.
3364
3365Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3366
3367 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3368 MFC0.
3369
3370Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3371
3372 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3373 constants.
3374 (build_instruction): Ditto for LL.
3375
3376Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3377
3378 * configure: Regenerated to track ../common/aclocal.m4 changes.
3379
3380Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3381
3382 * configure: Regenerated to track ../common/aclocal.m4 changes.
3383 * config.in: Ditto.
3384
3385Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3386
3387 * interp.c (sim_open): Add call to sim_analyze_program, update
3388 call to sim_config.
3389
3390Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3391
3392 * interp.c (sim_kill): Delete.
3393 (sim_create_inferior): Add ABFD argument. Set PC from same.
3394 (sim_load): Move code initializing trap handlers from here.
3395 (sim_open): To here.
3396 (sim_load): Delete, use sim-hload.c.
3397
3398 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3399
3400Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * configure: Regenerated to track ../common/aclocal.m4 changes.
3403 * config.in: Ditto.
3404
3405Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * interp.c (sim_open): Add ABFD argument.
3408 (sim_load): Move call to sim_config from here.
3409 (sim_open): To here. Check return status.
3410
3411Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3412
c906108c
SS		 3413 * gencode.c (build_instruction): Two arg MADD should
3414 not assign result to $0.
72f4393d 3415
c906108c
SS		 3416Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3417
3418 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3419 * sim/mips/configure.in: Regenerate.
3420
3421Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3422
3423 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3424 signed8, unsigned8 et.al. types.
3425
3426 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3427 hosts when selecting subreg.
3428
3429Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3430
3431 * interp.c (sim_engine_run): Reset the ZERO register to zero
3432 regardless of FEATURE_WARN_ZERO.
3433 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3434
3435Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3436
3437 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3438 (SignalException): For BreakPoints ignore any mode bits and just
3439 save the PC.
3440 (SignalException): Always set the CAUSE register.
3441
3442Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3443
3444 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3445 exception has been taken.
3446
3447 * interp.c: Implement the ERET and mt/f sr instructions.
3448
3449Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3450
3451 * interp.c (SignalException): Don't bother restarting an
3452 interrupt.
3453
3454Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3455
3456 * interp.c (SignalException): Really take an interrupt.
3457 (interrupt_event): Only deliver interrupts when enabled.
3458
3459Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3460
3461 * interp.c (sim_info): Only print info when verbose.
3462 (sim_info) Use sim_io_printf for output.
72f4393d 3463
c906108c
SS		 3464Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3465
3466 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3467 mips architectures.
3468
3469Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3470
3471 * interp.c (sim_do_command): Check for common commands if a
3472 simulator specific command fails.
3473
3474Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3475
3476 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3477 and simBE when DEBUG is defined.
3478
3479Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3480
3481 * interp.c (interrupt_event): New function. Pass exception event
3482 onto exception handler.
3483
3484 * configure.in: Check for stdlib.h.
3485 * configure: Regenerate.
3486
3487 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3488 variable declaration.
3489 (build_instruction): Initialize memval1.
3490 (build_instruction): Add UNUSED attribute to byte, bigend,
3491 reverse.
3492 (build_operands): Ditto.
3493
3494 * interp.c: Fix GCC warnings.
3495 (sim_get_quit_code): Delete.
3496
3497 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3498 * Makefile.in: Ditto.
3499 * configure: Re-generate.
72f4393d 3500
c906108c
SS		 3501 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3502
3503Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3504
3505 * interp.c (mips_option_handler): New function parse argumes using
3506 sim-options.
3507 (myname): Replace with STATE_MY_NAME.
3508 (sim_open): Delete check for host endianness - performed by
3509 sim_config.
3510 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3511 (sim_open): Move much of the initialization from here.
3512 (sim_load): To here. After the image has been loaded and
3513 endianness set.
3514 (sim_open): Move ColdReset from here.
3515 (sim_create_inferior): To here.
3516 (sim_open): Make FP check less dependant on host endianness.
3517
3518 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3519 run.
3520 * interp.c (sim_set_callbacks): Delete.
3521
3522 * interp.c (membank, membank_base, membank_size): Replace with
3523 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3524 (sim_open): Remove call to callback->init. gdb/run do this.
3525
3526 * interp.c: Update
3527
3528 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3529
3530 * interp.c (big_endian_p): Delete, replaced by
3531 current_target_byte_order.
3532
3533Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3534
3535 * interp.c (host_read_long, host_read_word, host_swap_word,
3536 host_swap_long): Delete. Using common sim-endian.
3537 (sim_fetch_register, sim_store_register): Use H2T.
3538 (pipeline_ticks): Delete. Handled by sim-events.
3539 (sim_info): Update.
3540 (sim_engine_run): Update.
3541
3542Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3543
3544 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3545 reason from here.
3546 (SignalException): To here. Signal using sim_engine_halt.
3547 (sim_stop_reason): Delete, moved to common.
72f4393d 3548
c906108c
SS		 3549Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3550
3551 * interp.c (sim_open): Add callback argument.
3552 (sim_set_callbacks): Delete SIM_DESC argument.
3553 (sim_size): Ditto.
3554
3555Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3556
3557 * Makefile.in (SIM_OBJS): Add common modules.
3558
3559 * interp.c (sim_set_callbacks): Also set SD callback.
3560 (set_endianness, xfer_*, swap_*): Delete.
3561 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3562 Change to functions using sim-endian macros.
3563 (control_c, sim_stop): Delete, use common version.
3564 (simulate): Convert into.
3565 (sim_engine_run): This function.
3566 (sim_resume): Delete.
72f4393d 3567
c906108c
SS		 3568 * interp.c (simulation): New variable - the simulator object.
3569 (sim_kind): Delete global - merged into simulation.
3570 (sim_load): Cleanup. Move PC assignment from here.
3571 (sim_create_inferior): To here.
3572
3573 * sim-main.h: New file.
3574 * interp.c (sim-main.h): Include.
72f4393d 3575
c906108c
SS		 3576Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3577
3578 * configure: Regenerated to track ../common/aclocal.m4 changes.
3579
3580Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3581
3582 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3583
3584Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3585
72f4393d
L		 3586 * gencode.c (build_instruction): DIV instructions: check
3587 for division by zero and integer overflow before using
c906108c
SS		 3588 host's division operation.
3589
3590Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3591
3592 * Makefile.in (SIM_OBJS): Add sim-load.o.
3593 * interp.c: #include bfd.h.
3594 (target_byte_order): Delete.
3595 (sim_kind, myname, big_endian_p): New static locals.
3596 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3597 after argument parsing. Recognize -E arg, set endianness accordingly.
3598 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3599 load file into simulator. Set PC from bfd.
3600 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3601 (set_endianness): Use big_endian_p instead of target_byte_order.
3602
3603Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3604
3605 * interp.c (sim_size): Delete prototype - conflicts with
3606 definition in remote-sim.h. Correct definition.
3607
3608Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3609
3610 * configure: Regenerated to track ../common/aclocal.m4 changes.
3611 * config.in: Ditto.
3612
3613Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3614
3615 * interp.c (sim_open): New arg `kind'.
3616
3617 * configure: Regenerated to track ../common/aclocal.m4 changes.
3618
3619Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3620
3621 * configure: Regenerated to track ../common/aclocal.m4 changes.
3622
3623Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3624
3625 * interp.c (sim_open): Set optind to 0 before calling getopt.
3626
3627Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3628
3629 * configure: Regenerated to track ../common/aclocal.m4 changes.
3630
3631Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3632
3633 * interp.c : Replace uses of pr_addr with pr_uword64
3634 where the bit length is always 64 independent of SIM_ADDR.
3635 (pr_uword64) : added.
3636
3637Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3638
3639 * configure: Re-generate.
3640
3641Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3642
3643 * configure: Regenerate to track ../common/aclocal.m4 changes.
3644
3645Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3646
3647 * interp.c (sim_open): New SIM_DESC result. Argument is now
3648 in argv form.
3649 (other sim_*): New SIM_DESC argument.
3650
3651Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3652
3653 * interp.c: Fix printing of addresses for non-64-bit targets.
3654 (pr_addr): Add function to print address based on size.
3655
3656Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3657
3658 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3659
3660Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3661
3662 * gencode.c (build_mips16_operands): Correct computation of base
3663 address for extended PC relative instruction.
3664
3665Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3666
3667 * interp.c (mips16_entry): Add support for floating point cases.
3668 (SignalException): Pass floating point cases to mips16_entry.
3669 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3670 registers.
3671 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3672 or fmt_word.
3673 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3674 and then set the state to fmt_uninterpreted.
3675 (COP_SW): Temporarily set the state to fmt_word while calling
3676 ValueFPR.
3677
3678Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3679
3680 * gencode.c (build_instruction): The high order may be set in the
3681 comparison flags at any ISA level, not just ISA 4.
3682
3683Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3684
3685 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3686 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3687 * configure.in: sinclude ../common/aclocal.m4.
3688 * configure: Regenerated.
3689
3690Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3691
3692 * configure: Rebuild after change to aclocal.m4.
3693
3694Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3695
3696 * configure configure.in Makefile.in: Update to new configure
3697 scheme which is more compatible with WinGDB builds.
3698 * configure.in: Improve comment on how to run autoconf.
3699 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3700 * Makefile.in: Use autoconf substitution to install common
3701 makefile fragment.
3702
3703Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3704
3705 * gencode.c (build_instruction): Use BigEndianCPU instead of
3706 ByteSwapMem.
3707
3708Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3709
3710 * interp.c (sim_monitor): Make output to stdout visible in
3711 wingdb's I/O log window.
3712
3713Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3714
3715 * support.h: Undo previous change to SIGTRAP
3716 and SIGQUIT values.
3717
3718Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3719
3720 * interp.c (store_word, load_word): New static functions.
3721 (mips16_entry): New static function.
3722 (SignalException): Look for mips16 entry and exit instructions.
3723 (simulate): Use the correct index when setting fpr_state after
3724 doing a pending move.
3725
3726Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3727
3728 * interp.c: Fix byte-swapping code throughout to work on
3729 both little- and big-endian hosts.
3730
3731Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3732
3733 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3734 with gdb/config/i386/xm-windows.h.
3735
3736Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3737
3738 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3739 that messes up arithmetic shifts.
3740
3741Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3742
3743 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3744 SIGTRAP and SIGQUIT for _WIN32.
3745
3746Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3747
3748 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3749 force a 64 bit multiplication.
3750 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3751 destination register is 0, since that is the default mips16 nop
3752 instruction.
3753
3754Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3755
3756 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3757 (build_endian_shift): Don't check proc64.
3758 (build_instruction): Always set memval to uword64. Cast op2 to
3759 uword64 when shifting it left in memory instructions. Always use
3760 the same code for stores--don't special case proc64.
3761
3762 * gencode.c (build_mips16_operands): Fix base PC value for PC
3763 relative operands.
3764 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3765 jal instruction.
3766 * interp.c (simJALDELAYSLOT): Define.
3767 (JALDELAYSLOT): Define.
3768 (INDELAYSLOT, INJALDELAYSLOT): Define.
3769 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3770
3771Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3772
3773 * interp.c (sim_open): add flush_cache as a PMON routine
3774 (sim_monitor): handle flush_cache by ignoring it
3775
3776Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3777
3778 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3779 BigEndianMem.
3780 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3781 (BigEndianMem): Rename to ByteSwapMem and change sense.
3782 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3783 BigEndianMem references to !ByteSwapMem.
3784 (set_endianness): New function, with prototype.
3785 (sim_open): Call set_endianness.
3786 (sim_info): Use simBE instead of BigEndianMem.
3787 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3788 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3789 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3790 ifdefs, keeping the prototype declaration.
3791 (swap_word): Rewrite correctly.
3792 (ColdReset): Delete references to CONFIG. Delete endianness related
3793 code; moved to set_endianness.
72f4393d 3794
c906108c
SS		 3795Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3796
3797 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3798 * interp.c (CHECKHILO): Define away.
3799 (simSIGINT): New macro.
3800 (membank_size): Increase from 1MB to 2MB.
3801 (control_c): New function.
3802 (sim_resume): Rename parameter signal to signal_number. Add local
3803 variable prev. Call signal before and after simulate.
3804 (sim_stop_reason): Add simSIGINT support.
3805 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3806 functions always.
3807 (sim_warning): Delete call to SignalException. Do call printf_filtered
3808 if logfh is NULL.
3809 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3810 a call to sim_warning.
3811
3812Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3813
3814 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3815 16 bit instructions.
3816
3817Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3818
3819 Add support for mips16 (16 bit MIPS implementation):
3820 * gencode.c (inst_type): Add mips16 instruction encoding types.
3821 (GETDATASIZEINSN): Define.
3822 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3823 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3824 mtlo.
3825 (MIPS16_DECODE): New table, for mips16 instructions.
3826 (bitmap_val): New static function.
3827 (struct mips16_op): Define.
3828 (mips16_op_table): New table, for mips16 operands.
3829 (build_mips16_operands): New static function.
3830 (process_instructions): If PC is odd, decode a mips16
3831 instruction. Break out instruction handling into new
3832 build_instruction function.
3833 (build_instruction): New static function, broken out of
3834 process_instructions. Check modifiers rather than flags for SHIFT
3835 bit count and m[ft]{hi,lo} direction.
3836 (usage): Pass program name to fprintf.
3837 (main): Remove unused variable this_option_optind. Change
3838 ``*loptarg++'' to ``loptarg++''.
3839 (my_strtoul): Parenthesize && within ||.
3840 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3841 (simulate): If PC is odd, fetch a 16 bit instruction, and
3842 increment PC by 2 rather than 4.
3843 * configure.in: Add case for mips16*-*-*.
3844 * configure: Rebuild.
3845
3846Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3847
3848 * interp.c: Allow -t to enable tracing in standalone simulator.
3849 Fix garbage output in trace file and error messages.
3850
3851Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3852
3853 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3854 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3855 * configure.in: Simplify using macros in ../common/aclocal.m4.
3856 * configure: Regenerated.
3857 * tconfig.in: New file.
3858
3859Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3860
3861 * interp.c: Fix bugs in 64-bit port.
3862 Use ansi function declarations for msvc compiler.
3863 Initialize and test file pointer in trace code.
3864 Prevent duplicate definition of LAST_EMED_REGNUM.
3865
3866Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3867
3868 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3869
3870Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3871
3872 * interp.c (SignalException): Check for explicit terminating
3873 breakpoint value.
3874 * gencode.c: Pass instruction value through SignalException()
3875 calls for Trap, Breakpoint and Syscall.
3876
3877Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3878
3879 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3880 only used on those hosts that provide it.
3881 * configure.in: Add sqrt() to list of functions to be checked for.
3882 * config.in: Re-generated.
3883 * configure: Re-generated.
3884
3885Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3886
3887 * gencode.c (process_instructions): Call build_endian_shift when
3888 expanding STORE RIGHT, to fix swr.
3889 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3890 clear the high bits.
3891 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3892 Fix float to int conversions to produce signed values.
3893
3894Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3895
3896 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3897 (process_instructions): Correct handling of nor instruction.
3898 Correct shift count for 32 bit shift instructions. Correct sign
3899 extension for arithmetic shifts to not shift the number of bits in
3900 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3901 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3902 Fix madd.
3903 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3904 It's OK to have a mult follow a mult. What's not OK is to have a
3905 mult follow an mfhi.
3906 (Convert): Comment out incorrect rounding code.
3907
3908Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3909
3910 * interp.c (sim_monitor): Improved monitor printf
3911 simulation. Tidied up simulator warnings, and added "--log" option
3912 for directing warning message output.
3913 * gencode.c: Use sim_warning() rather than WARNING macro.
3914
3915Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3916
3917 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3918 getopt1.o, rather than on gencode.c. Link objects together.
3919 Don't link against -liberty.
3920 (gencode.o, getopt.o, getopt1.o): New targets.
3921 * gencode.c: Include <ctype.h> and "ansidecl.h".
3922 (AND): Undefine after including "ansidecl.h".
3923 (ULONG_MAX): Define if not defined.
3924 (OP_*): Don't define macros; now defined in opcode/mips.h.
3925 (main): Call my_strtoul rather than strtoul.
3926 (my_strtoul): New static function.
3927
3928Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3929
3930 * gencode.c (process_instructions): Generate word64 and uword64
3931 instead of `long long' and `unsigned long long' data types.
3932 * interp.c: #include sysdep.h to get signals, and define default
3933 for SIGBUS.
3934 * (Convert): Work around for Visual-C++ compiler bug with type
3935 conversion.
3936 * support.h: Make things compile under Visual-C++ by using
3937 __int64 instead of `long long'. Change many refs to long long
3938 into word64/uword64 typedefs.
3939
3940Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3941
72f4393d
L		 3942 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3943 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3944 (docdir): Removed.
3945 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3946 (AC_PROG_INSTALL): Added.
c906108c 3947 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3948 * configure: Rebuilt.
3949
c906108c
SS		 3950Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3951
3952 * configure.in: Define @SIMCONF@ depending on mips target.
3953 * configure: Rebuild.
3954 * Makefile.in (run): Add @SIMCONF@ to control simulator
3955 construction.
3956 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3957 * interp.c: Remove some debugging, provide more detailed error
3958 messages, update memory accesses to use LOADDRMASK.
72f4393d 3959
c906108c
SS		 3960Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3961
3962 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3963 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3964 stamp-h.
3965 * configure: Rebuild.
3966 * config.in: New file, generated by autoheader.
3967 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3968 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3969 HAVE_ANINT and HAVE_AINT, as appropriate.
3970 * Makefile.in (run): Use @LIBS@ rather than -lm.
3971 (interp.o): Depend upon config.h.
3972 (Makefile): Just rebuild Makefile.
3973 (clean): Remove stamp-h.
3974 (mostlyclean): Make the same as clean, not as distclean.
3975 (config.h, stamp-h): New targets.
3976
3977Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3978
3979 * interp.c (ColdReset): Fix boolean test. Make all simulator
3980 globals static.
3981
3982Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3983
3984 * interp.c (xfer_direct_word, xfer_direct_long,
3985 swap_direct_word, swap_direct_long, xfer_big_word,
3986 xfer_big_long, xfer_little_word, xfer_little_long,
3987 swap_word,swap_long): Added.
3988 * interp.c (ColdReset): Provide function indirection to
3989 host<->simulated_target transfer routines.
3990 * interp.c (sim_store_register, sim_fetch_register): Updated to
3991 make use of indirected transfer routines.
3992
3993Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3994
3995 * gencode.c (process_instructions): Ensure FP ABS instruction
3996 recognised.
3997 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3998 system call support.
3999
4000Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4001
4002 * interp.c (sim_do_command): Complain if callback structure not
4003 initialised.
4004
4005Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4006
4007 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4008 support for Sun hosts.
4009 * Makefile.in (gencode): Ensure the host compiler and libraries
4010 used for cross-hosted build.
4011
4012Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4013
4014 * interp.c, gencode.c: Some more (TODO) tidying.
4015
4016Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4017
4018 * gencode.c, interp.c: Replaced explicit long long references with
4019 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4020 * support.h (SET64LO, SET64HI): Macros added.
4021
4022Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4023
4024 * configure: Regenerate with autoconf 2.7.
4025
4026Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4027
4028 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4029 * support.h: Remove superfluous "1" from #if.
4030 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4031
4032Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4033
4034 * interp.c (StoreFPR): Control UndefinedResult() call on
4035 WARN_RESULT manifest.
4036
4037Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4038
4039 * gencode.c: Tidied instruction decoding, and added FP instruction
4040 support.
4041
4042 * interp.c: Added dineroIII, and BSD profiling support. Also
4043 run-time FP handling.
4044
4045Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4046
4047 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4048 gencode.c, interp.c, support.h: created.
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