Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Markus Klotzbuecher <mk@denx.de>
+Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Ricardo Ribalda <ricardo.ribalda@uam.es>
--- /dev/null
+Copyright (c) 2014, Renesas Electronics Corporation
+All rights reserved.
+
+Redistribution and use in binary form, without modification, are permitted
+provided that the following conditions are met:
+
+1. Redistribution in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+2. The name of Renesas Electronics Corporation may not be used to endorse or
+ promote products derived from this software without specific prior written
+ permission.
+3. Reverse engineering, decompilation, or disassembly of this software is
+ not permitted.
+
+THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS ELECTRONICS CORPORATION DISCLAIMS
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND
+NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL RENESAS ELECTRONICS
+CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
T: git git://git.denx.de/u-boot-arc.git
F: arch/arc/
+ARC HSDK CREG GPIO
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: drivers/gpio/hsdk-creg-gpio.c
+
+ARC HSDK CGU CLOCK
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: drivers/clk/clk-hsdk-cgu.c
+F: include/dt-bindings/clock/snps,hsdk-cgu.h
+F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
+
ARM
M: Albert Aribaud <albert.u.boot@aribaud.net>
S: Maintained
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/arm/mach-rmobile/
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
S: Maintained
T: git git://git.denx.de/u-boot-rockchip.git
+F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
F: board/rockchip/
+F: drivers/clk/rockchip/
+F: drivers/gpio/rk_gpio.c
+F: drivers/misc/rockchip-efuse.c
+F: drivers/pinctrl/rockchip/
+F: drivers/ram/rockchip/
+F: drivers/sysreset/sysreset_rockchip.c
+F: tools/rkcommon.c
+F: tools/rkcommon.h
+F: tools/rkimage.c
+F: tools/rksd.c
+F: tools/rkspi.c
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
T: git git://git.denx.de/u-boot-i2c.git
F: drivers/i2c/
+LOGGING
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git git://git.denx.de/u-boot.git
+F: common/log.c
+F: cmd/log.c
+F: test/log/log_test.c
+F: test/py/tests/test_log.py
+
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
T: git git://git.denx.de/u-boot-usb.git
F: drivers/usb/
+USB xHCI
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-usb.git topic-xhci
+F: drivers/usb/host/xhci*
+
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
# SPDX-License-Identifier: GPL-2.0+
#
-VERSION = 2017
-PATCHLEVEL = 11
+VERSION = 2018
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
endif
ifneq ($(CONFIG_TEGRA),)
+ifneq ($(CONFIG_BINMAN),)
+u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin: \
+ spl/u-boot-spl u-boot.bin FORCE
+ $(call if_changed,binman)
+else
OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE
$(call if_changed,pad_cat)
u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE
$(call if_changed,copy)
+endif # binman
endif
OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
the bootcounter.
CONFIG_BOOTCOUNT_ALEN = address len
+ CONFIG_BOOTCOUNT_EXT
+ enable support for the bootcounter in EXT filesystem
+ CONFIG_SYS_BOOTCOUNT_ADDR = RAM address used for read
+ and write.
+ CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE = interface
+ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART = device and part
+ CONFIG_SYS_BOOTCOUNT_EXT_NAME = filename
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
-----------------
All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory.
+coding style; see the kernel coding style guide at
+https://www.kernel.org/doc/html/latest/process/coding-style.html, and the
+script "scripts/Lindent" in your Linux kernel source directory.
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
+#define AUX_AUX_CACHE_LIMIT 0x5D
+#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
+
+/* ICCM and DCCM auxiliary registers */
+#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
+#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val) \
__builtin_arc_sr((unsigned int)val, reg_immed)
+
+/* ARCNUM [15:8] - field to identify each core in a multi-core system */
+#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
--- /dev/null
+#include <asm-generic/gpio.h>
r2 = (unsigned int)env_get("bootargs");
}
- smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
- smp_kick_all_cpus();
-
- if (!fake)
+ if (!fake) {
+ smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+ smp_kick_all_cpus();
kernel_entry(r0, 0, r2);
+ }
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
* relocation but will be used after being zeroed.
*/
int l1_line_sz __section(".data");
-int dcache_exists __section(".data");
-int icache_exists __section(".data");
+bool dcache_exists __section(".data") = false;
+bool icache_exists __section(".data") = false;
#define CACHE_LINE_MASK (~(l1_line_sz - 1))
#ifdef CONFIG_ISA_ARCV2
int slc_line_sz __section(".data");
-int slc_exists __section(".data");
-int ioc_exists __section(".data");
+bool slc_exists __section(".data") = false;
+bool ioc_exists __section(".data") = false;
static unsigned int __before_slc_op(const int op)
{
sbcr.word = read_aux_reg(ARC_BCR_SLC);
if (sbcr.fields.ver) {
slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
- slc_exists = 1;
+ slc_exists = true;
slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
}
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
if (cbcr.fields.c)
- ioc_exists = 1;
+ ioc_exists = true;
}
#endif
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
if (ibcr.fields.ver) {
- icache_exists = 1;
+ icache_exists = true;
l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
if (!ic_line_sz)
panic("Instruction exists but line length is 0\n");
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
if (dbcr.fields.ver){
- dcache_exists = 1;
+ dcache_exists = true;
l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
panic("Data cache exists but line length is 0\n");
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
if (icache_status()) {
write_aux_reg(ARC_AUX_IC_IVIC, 1);
+ /*
+ * As per ARC HS databook (see chapter 5.3.3.2)
+ * it is required to add 3 NOPs after each write to IC_IVIC.
+ */
+ __builtin_arc_nop();
+ __builtin_arc_nop();
+ __builtin_arc_nop();
read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
}
}
imply NAND
config ARCH_ZYNQ
- bool "Xilinx Zynq Platform"
+ bool "Xilinx Zynq based platform"
select BOARD_LATE_INIT
select CPU_V7
select SUPPORT_SPL
imply CMD_SPL
config ARCH_ZYNQMP
- bool "Support Xilinx ZynqMP Platform"
+ bool "Xilinx ZynqMP based platform"
select ARM64
select BOARD_LATE_INIT
select DM
select SUPPORT_SPL
select CLK
select SPL_BOARD_INIT if SPL
- select SPL_CLK
+ select SPL_CLK if SPL
select DM_USB if USB
imply FAT_WRITE
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS2080ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
select ARM64
select BOARD_LATE_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS1012ARDB platform.
The LS1012A Reference design board (RDB) is a high-performance
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
+ select ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
checkgcc6:
@if test "$(call cc-name)" = "gcc" -a \
"$(call cc-version)" -lt "0600"; then \
- echo -n '*** Your GCC is older than 6.0 and will not be '; \
- echo 'supported starting in v2018.01.'; \
+ echo '*** Your GCC is older than 6.0 and is not supported'; \
+ false; \
fi
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
- -j .u_boot_list -j .rela.dyn -j .got -j .got.plt
+ -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+ -j .binman_sym_table
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
- -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
+ -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+ -j .binman_sym_table
endif
# if a dtb section exists we always have to include it
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
imply SCSI
+ imply SCSI_AHCI
imply CMD_PCI
menu "LS102xA architecture"
.globl reset
.globl save_boot_params_ret
+ .type save_boot_params_ret,%function
#ifdef CONFIG_ARMV7_LPAE
.global switch_to_hypervisor_ret
#endif
/* Page fits, create block PTE */
debug("Setting PTE %p to block virt=%llx\n",
pte, virt);
- *pte = phys | attrs;
+ if (level == 3)
+ *pte = phys | attrs | PTE_TYPE_PAGE;
+ else
+ *pte = phys | attrs;
virt += blocksize;
phys += blocksize;
size -= blocksize;
#include <asm/macro.h>
#include <linux/linkage.h>
+/*
+ * Exception vectors.
+ */
+ .align 11
+ .globl vectors
+vectors:
+ .align 7 /* Current EL Synchronous Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_sync
+ b exception_exit
+
+ .align 7 /* Current EL IRQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_irq
+ b exception_exit
+
+ .align 7 /* Current EL FIQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_fiq
+ b exception_exit
+
+ .align 7 /* Current EL Error Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_error
+ b exception_exit
+
+ .align 7 /* Current EL Synchronous Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_sync
+ b exception_exit
+
+ .align 7 /* Current EL IRQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_irq
+ b exception_exit
+
+ .align 7 /* Current EL FIQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_fiq
+ b exception_exit
+
+ .align 7 /* Current EL Error Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_error
+ b exception_exit
+
/*
* Enter Exception.
* This will save the processor state that is ELR/X0~X30
* to the stack frame.
*/
-.macro exception_entry
- stp x29, x30, [sp, #-16]!
+_exception_entry:
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
0:
stp x2, x0, [sp, #-16]!
mov x0, sp
-.endm
+ ret
-/*
- * Exception vectors.
- */
- .align 11
- .globl vectors
-vectors:
- .align 7
- b _do_bad_sync /* Current EL Synchronous Thread */
-
- .align 7
- b _do_bad_irq /* Current EL IRQ Thread */
-
- .align 7
- b _do_bad_fiq /* Current EL FIQ Thread */
-
- .align 7
- b _do_bad_error /* Current EL Error Thread */
-
- .align 7
- b _do_sync /* Current EL Synchronous Handler */
-
- .align 7
- b _do_irq /* Current EL IRQ Handler */
-
- .align 7
- b _do_fiq /* Current EL FIQ Handler */
-
- .align 7
- b _do_error /* Current EL Error Handler */
-
-
-_do_bad_sync:
- exception_entry
- bl do_bad_sync
- b exception_exit
-
-_do_bad_irq:
- exception_entry
- bl do_bad_irq
- b exception_exit
-
-_do_bad_fiq:
- exception_entry
- bl do_bad_fiq
- b exception_exit
-
-_do_bad_error:
- exception_entry
- bl do_bad_error
- b exception_exit
-
-_do_sync:
- exception_entry
- bl do_sync
- b exception_exit
-
-_do_irq:
- exception_entry
- bl do_irq
- b exception_exit
-
-_do_fiq:
- exception_entry
- bl do_fiq
- b exception_exit
-
-_do_error:
- exception_entry
- bl do_error
- b exception_exit
exception_exit:
ldp x2, x0, [sp],#16
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
+ imply SCSI_AHCI
imply CMD_PCI
config ARCH_LS1046A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
+ imply SCSI_AHCI
config ARCH_LS1088A
bool
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+ default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x680000 if SYS_LS_PPA_FW_IN_MMC
default 0x680000 if SYS_LS_PPA_FW_IN_NAND
help
#include <fsl_ddr.h>
#endif
#include <asm/arch/clock.h>
+#include <hwconfig.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+static void config_core_prefetch(void)
+{
+ char *buf = NULL;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ const char *prefetch_arg = NULL;
+ size_t arglen;
+ unsigned int mask;
+ struct pt_regs regs;
+
+ if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ buf = buffer;
+
+ prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
+ &arglen, buf);
+
+ if (prefetch_arg) {
+ mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
+ if (mask & 0x1) {
+ printf("Core0 prefetch can't be disabled\n");
+ return;
+ }
+
+#define SIP_PREFETCH_DISABLE_64 0xC200FF13
+ regs.regs[0] = SIP_PREFETCH_DISABLE_64;
+ regs.regs[1] = mask;
+ smc_call(®s);
+
+ if (regs.regs[0])
+ printf("Prefetch disable config failed for mask ");
+ else
+ printf("Prefetch disable config passed for mask ");
+ printf("0x%x\n", mask);
+ }
+}
+
int arch_early_init_r(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
* erratum A009635 is valid only for LS2080A SoC and
* its personalitiesi
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
erratum_a009635();
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
fsl_rgmii_init();
#endif
+ config_core_prefetch();
+
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
* For LS2080A SoC and its personalities, timer controller
* offset is different
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
#endif
--- /dev/null
+Core instruction prefetch disable
+---------------------------------
+To disable instruction prefetch of core; hwconfig needs to be updated.
+for e.g.
+setenv hwconfig 'fsl_ddr:bank_intlv=auto;core_prefetch:disable=0x02'
+
+Here 0x02 can be replaced with any valid value except Mask[0] bit. It
+represents 64 bit mask. The 64-bit Mask has one bit for each core.
+Mask[0] = core0
+Mask[1] = core1
+Mask[2] = core2
+etc
+If the bit is set ('b1) in the mask, then prefetch is disabled for
+that core when it is released from reset.
+
+core0 prefetch should not be disabled i.e. Mask[0] should never be set.
+Setting Mask[0] may lead to undefined behavior.
+
+Once disabled, prefetch remains disabled until the next reset.
+There is no function to re-enable prefetch.
-------------------
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
+command sequence. Below is one example for PBI commands for LS2085AQDS which
+uses NAND device with 2KB/page, block size 128KB.
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
With these two images in NAND device, the board can boot from NAND.
-Another example for RDB boards,
+Another example for LS2085ARDB boards,
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
to match board NAND device with 4KB/page, block size 512KB.
+Note, LS2088A and LS1088A don't support booting from NAND.
+
Booting from SD/eMMC
-------------------
Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+ u32 mask = cpu_pos_mask();
+ int off_prev = -1;
+
+ off = fdt_path_offset(blob, "/cpus");
+ if (off < 0) {
+ puts("couldn't find /cpus node\n");
+ return;
+ }
+
+ fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
+
+ off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+ "cpu", 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+ if (reg) {
+ core_id = fdt_read_number(reg, addr_cells);
+ if (!test_bit(id_to_core(core_id), &mask)) {
+ fdt_del_node(blob, off);
+ off = off_prev;
+ }
+ }
+ off_prev = off;
+ off = fdt_node_offset_by_prop_value(blob, off_prev,
+ "device_type", "cpu", 4);
+ }
+
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
val = gur_in32(&gur->svr);
- if (SVR_SOC_VER(val) != SVR_LS1043A) {
+ if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
rev = gur_in32(&gur->svr);
- if (SVR_SOC_VER(rev) != SVR_LS1043A)
+ if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
return;
rev = SVR_REV(rev);
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
- mov w3, w2
- ands w3, w3, #SVR_WO_E << 8
- mov w4, #SVR_LS1043A << 8
+ lsr w3, w2, #16
+ ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
+#endif
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#endif
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
{
scfg_clrsetbits32(scfg + offset / 4,
static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
#endif
+#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
static void erratum_a009007(void)
{
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1012A)
void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
-
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
usb_phy = (void __iomem *)SCFG_USB_PHY2;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
usb_phy = (void __iomem *)SCFG_USB_PHY3;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#endif
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
+config SYS_MEM_RSVD_FOR_MMU
+ bool "Reserve memory for MMU Table"
+ help
+ If defined this option is used to setup different space for
+ MMU table than the one which will be allocated during
+ relocation.
+
config BOOT_INIT_FILE
string "boot.bin init register filename"
depends on SPL
Add register writes to boot.bin format (max 256 pairs).
Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
+config PMUFW_INIT_FILE
+ string "PMU firmware"
+ depends on SPL
+ default ""
+ help
+ Include external PMUFW (Platform Management Unit FirmWare) to
+ a Xilinx bootable image (boot.bin).
+
config ZYNQMP_USB
bool "Configure ZynqMP USB"
config DEFINE_TCM_OCM_MMAP
bool "Define TCM and OCM memory in MMU Table"
+ default y if MP
help
This option if enabled defines the TCM and OCM memory and its
memory attributes in MMU table entry.
default 0x7 if USB_MODE
default 0xa if SW_USBHOST_MODE
default 0xb if SW_SATA_MODE
+ default 0xe if SD1_LSHFT_MODE
choice
prompt "Boot mode"
config SW_SATA_MODE
bool "SW SATA_MODE"
+config SD1_LSHFT_MODE
+ bool "SD1_LSHFT_MODE"
+
endchoice
endif
obj-y += clk.o
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
-obj-y += slcr.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
return 0x14000;
}
+#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
+int reserve_mmu(void)
+{
+ initialize_tcm(TCM_LOCK);
+ memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
+
+ return 0;
+}
+#endif
+
static unsigned int zynqmp_get_silicon_version_secure(void)
{
u32 ver;
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawwrite(address, mask, value);
- else if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ else
return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
value, 0, NULL);
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
ret = zynqmp_mmio_rawread(address, value);
- } else if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ } else {
ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
0, ret_payload);
*value = ret_payload[1];
boot_addr = ZYNQMP_R5_LOVEC_ADDR;
}
+ /*
+ * Since we don't know where the user may have loaded the image
+ * for an R5 we have to flush all the data cache to ensure
+ * the R5 sees it.
+ */
+ flush_dcache_all();
+
if (!strncmp(argv[1], "lockstep", 8)) {
printf("R5 lockstep mode\n");
+ set_r5_reset(LOCK);
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(HALT, LOCK);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(LOCK);
+ dcache_disable();
write_tcm_boot_trampoline(boot_addr_uniq);
+ dcache_enable();
set_r5_halt_mode(RELEASE, LOCK);
} else if (!strncmp(argv[1], "split", 5)) {
printf("R5 split mode\n");
+ set_r5_reset(SPLIT);
set_r5_tcm_mode(SPLIT);
set_r5_halt_mode(HALT, SPLIT);
+ set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(SPLIT);
+ dcache_disable();
write_tcm_boot_trampoline(boot_addr_uniq);
+ dcache_enable();
set_r5_halt_mode(RELEASE, SPLIT);
} else {
printf("Unsupported mode\n");
+++ /dev/null
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
-
-/*
- * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
- *
- * @peri_name: Name of the peripheral for checking MIO status
- * @get_pins: Pointer to array of get pin for this peripheral
- * @num_pins: Number of pins for this peripheral
- * @mask: Mask value
- * @check_val: Required check value to get the status of periph
- */
-struct zynq_slcr_mio_get_status {
- const char *peri_name;
- const int *get_pins;
- int num_pins;
- u32 mask;
- u32 check_val;
-};
-
-static const struct zynq_slcr_mio_get_status mio_periphs[] = {
-};
-
-/*
- * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
- *
- * @periph: Name of the peripheral
- *
- * Returns count to indicate the number of pins configured for the
- * given @periph.
- */
-int zynq_slcr_get_mio_pin_status(const char *periph)
-{
- const struct zynq_slcr_mio_get_status *mio_ptr;
- int val, i, j;
- int mio = 0;
-
- for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
- if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
- mio_ptr = &mio_periphs[i];
- for (j = 0; j < mio_ptr->num_pins; j++) {
- val = readl(&slcr_base->mio_pin
- [mio_ptr->get_pins[j]]);
- if ((val & mio_ptr->mask) == mio_ptr->check_val)
- mio++;
- }
- break;
- }
- }
-
- return mio;
-}
#ifdef CONFIG_SPL_SATA_SUPPORT
case SW_SATA_MODE:
return BOOT_DEVICE_SATA;
+#endif
+#ifdef CONFIG_SPL_SPI_SUPPORT
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ return BOOT_DEVICE_SPI;
#endif
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
KEEP(*(SORT(.u_boot_list*)));
}
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
. = ALIGN(4);
__image_copy_end = .;
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+ rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rv1108-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb \
- meson-gxl-s905x-p212.dtb
+ meson-gxl-s905x-p212.dtb \
+ meson-gxl-s905x-libretech-cc.dtb \
+ meson-gxl-s905x-khadas-vim.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
- zynq-zc706.dtb \
- zynq-zed.dtb \
- zynq-zybo.dtb \
+dtb-$(CONFIG_ARCH_ZYNQ) += \
+ zynq-cc108.dtb \
+ zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
+ zynq-syzygy-hub.dtb \
zynq-topic-miami.dtb \
zynq-topic-miamilite.dtb \
zynq-topic-miamiplus.dtb \
- zynq-zturn-myir.dtb \
+ zynq-zc702.dtb \
+ zynq-zc706.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
- zynq-zc770-xm013.dtb
+ zynq-zc770-xm013.dtb \
+ zynq-zed.dtb \
+ zynq-zturn-myir.dtb \
+ zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
+ zynqmp-zcu102-rev1.0.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-bananapi-m3.dtb \
- sun8i-a83t-cubietruck-plus.dtb
+ sun8i-a83t-cubietruck-plus.dtb \
+ sun8i-a83t-tbs-a711.dts
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-nanopi-neo2.dtb \
+ sun50i-h5-nanopi-neo-plus2.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
r8a7796-m3ulcb.dtb \
- r8a7796-salvator-x.dtb
+ r8a7796-salvator-x.dtb \
+ r8a77970-eagle.dtb \
+ r8a77995-draak.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
logicpd-torpedo-37xx-devkit.dtb \
logicpd-som-lv-37xx-devkit.dtb
+dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
+ at91-sama5d2_ptc_ek.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
marvell,function = "i2c0";
};
+ nand_pins: nand-pins {
+ marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+ "mpp38", "mpp28", "mpp40", "mpp42",
+ "mpp35", "mpp36", "mpp25", "mpp30",
+ "mpp32";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp41";
+ marvell,function = "nand";
+ };
+
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
};
flash@d0000 {
- compatible = "marvell,armada370-nand";
+ compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+/*
+ * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
+ *
+ * Copyright (C) 2017 Microchip Technology Inc,
+ * Ludovic Desroches <ludovic.desroches@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Atmel SAMA5D2 PTC EK";
+ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart0;
+ };
+
+ ahb {
+ usb0: gadget@00300000 {
+ atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci@00400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PB12 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@00500000 {
+ status = "okay";
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
+ status = "disabled"; /* conflicts with nand and qspi0*/
+ u-boot,dm-pre-reloc;
+ };
+
+ apb {
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+
+ uart0: serial@f801c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c1: i2c@fc028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ i2c_eeprom: i2c_eeprom@50 {
+ compatible = "atmel,24mac402";
+ reg = <0x50>;
+ };
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PC6__TWD1>,
+ <PIN_PC7__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rmii: macb0_rmii {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA10__SDMMC0_RSTN>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB12__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PB11__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9512.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+ model = "Raspberry Pi Zero W";
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
reg = <0x10440000 0x1000>;
};
- serial@13800000 {
+ gic: interrupt-controller@10490000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ cpu-offset = <0x4000>;
+ reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+ };
+
+ serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x3c>;
id = <0>;
};
- serial@13810000 {
+ serail_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x3c>;
id = <1>;
};
- serial@13820000 {
+ serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x3c>;
id = <2>;
};
- serial@13830000 {
+ serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x3c>;
id = <3>;
};
- serial@13840000 {
+ serial_4: serial@13840000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13840000 0x3c>;
id = <4>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <0 56 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <1 57 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <2 58 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <3 59 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138a0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <4 60 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138b0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <5 61 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138c0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <6 62 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138d0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <7 63 0>;
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12510000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 75 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12520000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 76 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12530000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 77 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12540000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 78 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 131 0>;
status = "disabled";
};
cpu-offset = <0x8000>;
};
- combiner: interrupt-controller@10440000 {
- samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
- };
-
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
};
};
};
+
+&combiner {
+ samsung,combiner-nr = <16>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+};
compatible = "samsung,odroid", "samsung,exynos4412";
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc0 = &mshc_0;
mmc1 = &sdhci2;
};
- i2c@13860000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_VM1M2_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDDQ_MMC2_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDDQ_MMC0/1/3_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VMPLL_1.0V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VPLL_1.1V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD_MIPI/HDMI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD_MIPI/HDMI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD_ABB1_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD_UOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDD_C2C_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDD_ABB02_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDD_HSIC/OTG_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDD_HSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "VDDQ_CAM_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VDDQ_EMMC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "TFLASH_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "VDDQ_EMMC_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "VDDQ_LCD_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "VDD_MIF_1.0V";
- regulator-min-microvolt = <8500000>;
- regulator-max-microvolt = <1100000>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "VDD_ARM_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "VDD_INT_1.1V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "VDD_G3D_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VDDQ_AP_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VCC_INL1/7_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VCC_INL2/3/5_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VCC_P3V3_2.85V";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
-
serial@13810000 {
status = "okay";
};
};
};
+&i2c_0 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx3>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_VM1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_MMC2_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDDQ_MMC0/1/3_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VMPLL_1.0V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD_MIPI/HDMI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD_MIPI/HDMI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD_ABB1_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD_UOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDD_C2C_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD_ABB02_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD_HSIC/OTG_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD_HSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDQ_CAM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDDQ_EMMC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "TFLASH_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDQ_EMMC_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "VDDQ_LCD_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "VDD_MIF_1.0V";
+ regulator-min-microvolt = <8500000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "VDD_ARM_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VDD_INT_1.1V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VDD_G3D_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VDDQ_AP_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VCC_INL1/7_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VCC_INL2/3/5_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VCC_P3V3_2.85V";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
&sdhci2 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
};
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
i2c8 = &i2c_fg;
i2c9 = &i2c_max77693;
serial0 = "/serial@13800000";
status = "okay";
};
- i2c@138d0000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-compatible = "LDO1";
- regulator-name = "VALIVE_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-compatible = "LDO2";
- regulator-name = "VM1M2_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-compatible = "LDO3";
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-compatible = "LDO4";
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo5_reg: LDO5 {
- regulator-compatible = "LDO5";
- regulator-name = "VCC_1.8V_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-compatible = "LDO6";
- regulator-name = "VMPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo7_reg: LDO7 {
- regulator-compatible = "LDO7";
- regulator-name = "VPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo8_reg: LDO8 {
- regulator-compatible = "LDO8";
- regulator-name = "VMIPI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo9_reg: LDO9 {
- regulator-compatible = "LDO9";
- regulator-name = "CAM_ISP_MIPI_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo10_reg: LDO10 {
- regulator-compatible = "LDO10";
- regulator-name = "VMIPI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo11_reg: LDO11 {
- regulator-compatible = "LDO11";
- regulator-name = "VABB1_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo12_reg: LDO12 {
- regulator-compatible = "LDO12";
- regulator-name = "VUOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-off;
- };
-
- ldo13_reg: LDO13 {
- regulator-compatible = "LDO13";
- regulator-name = "NFC_AVDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo14_reg: LDO14 {
- regulator-compatible = "LDO14";
- regulator-name = "VABB2_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo15_reg: LDO15 {
- regulator-compatible = "LDO15";
- regulator-name = "VHSIC_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo16_reg: LDO16 {
- regulator-compatible = "LDO16";
- regulator-name = "VHSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo17_reg: LDO17 {
- regulator-compatible = "LDO17";
- regulator-name = "CAM_SENSOR_CORE_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo18_reg: LDO18 {
- regulator-compatible = "LDO18";
- regulator-name = "CAM_ISP_SEN_IO_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo19_reg: LDO19 {
- regulator-compatible = "LDO19";
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo20_reg: LDO20 {
- regulator-compatible = "LDO20";
- regulator-name = "VDDQ_PRE_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo21_reg: LDO21 {
- regulator-compatible = "LDO21";
- regulator-name = "VTF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo22_reg: LDO22 {
- regulator-compatible = "LDO22";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo23_reg: LDO23 {
- regulator-compatible = "LDO23";
- regulator-name = "TSP_AVDD_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-mem-idle;
- };
-
- ldo24_reg: LDO24 {
- regulator-compatible = "LDO24";
- regulator-name = "TSP_VDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "LCD_VCC_3.3V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo26_reg: LDO26 {
- regulator-compatible = "LDO26";
- regulator-name = "MOTOR_VCC_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-idle;
- };
-
- buck1_reg: BUCK1 {
- regulator-compatible = "BUCK1";
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck2_reg: BUCK2 {
- regulator-compatible = "BUCK2";
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck3_reg: BUCK3 {
- regulator-compatible = "BUCK3";
- regulator-name = "vdd_int";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck4_reg: BUCK4 {
- regulator-compatible = "BUCK4";
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck5_reg: BUCK5 {
- regulator-compatible = "BUCK5";
- regulator-name = "VMEM_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- regulator-compatible = "BUCK6";
- regulator-name = "VCC_SUB_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- buck7_reg: BUCK7 {
- regulator-compatible = "BUCK7";
- regulator-name = "VCC_SUB_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-compatible = "BUCK8";
- regulator-name = "VMEM_VDDF_3.0V";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- buck9_reg: BUCK9 {
- regulator-compatible = "BUCK9";
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-off;
- };
- };
- };
- };
-
fimd@11c00000 {
compatible = "samsung,exynos-fimd";
reg = <0x11c00000 0xa4>;
};
};
+&i2c_7 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+};
+
&sdhci0 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
/ {
compatible = "samsung,exynos4412";
+};
- gic: interrupt-controller@10490000 {
- cpu-offset = <0x4000>;
- };
-
- interrupt-controller@10440000 {
- samsung,combiner-nr = <20>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
- };
-
+&combiner {
+ samsung,combiner-nr = <20>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
pinctrl_3: pinctrl@106E0000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 72 0>;
};
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
#include <dt-bindings/clock/imx6qdl-clock.h>
/ {
+ aliases {
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ };
+
memory {
reg = <0x10000000 0x80000000>;
};
};
&usdhc3 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
pinctrl_usdhc3: usdhc3grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
+ u-boot,dm-spl;
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
+ u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
+ u-boot,dm-spl;
};
ldb: ldb@020e0008 {
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
+ u-boot,dm-spl;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
};
&usdhc2 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
+ u-boot,dm-spl;
pmu {
compatible = "arm,cortex-a7-pmu";
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
+ u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
+ u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
+ u-boot,dm-spl;
};
gpio5: gpio@020ac000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
+ u-boot,dm-spl;
};
gpr: iomuxc-gpr@020e4000 {
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
+ u-boot,dm-spl;
usbotg1: usb@02184000 {
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
*/
/ {
+ model = "LogicPD Zoom OMAP3 Development Kit";
+
chosen {
stdout-path = &uart1;
};
--- /dev/null
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "meson-gxl-s905x-p212.dtsi"
+
+/ {
+ compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "Khadas VIM";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Function";
+ linux,code = <KEY_FN>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ aliases {
+ serial2 = &uart_AO_B;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ button@0 {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ power {
+ label = "vim:red:power";
+ pwms = <&pwm_AO_ab 1 7812500 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c_B {
+ status = "okay";
+ pinctrl-0 = <&i2c_b_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ /* has to be enabled manually when a battery is connected: */
+ status = "disabled";
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-geekbox";
+};
+
+&pwm_AO_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal> , <&xtal>;
+ clock-names = "clkin0", "clkin1" ;
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
+};
+
+&sd_emmc_a {
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
+&uart_AO {
+ status = "okay";
+};
+
+/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>;
+ pinctrl-names = "default";
+};
--- /dev/null
+/*
+ * Copyright (c) 2017 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "Libre Technology CC";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ system {
+ label = "librecomputer:system-status";
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+
+ blue {
+ label = "librecomputer:blue";
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_card: regulator-vcc-card {
+ compatible = "regulator-gpio";
+
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_card>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <50000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
--- /dev/null
+/*
+ * Device Tree Source for the Eagle board
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+
+/ {
+ model = "Renesas Eagle board based on r8a77970";
+ compatible = "renesas,eagle", "renesas,r8a77970";
+
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+
+ avb_pins: avb {
+ groups = "avb0_mdc";
+ function = "avb0";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a77970 SoC
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+ compatible = "renesas,r8a77970";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0>;
+ clocks = <&cpg CPG_CORE 0>;
+ power-domains = <&sysc 5>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller {
+ compatible = "cache";
+ power-domains = <&sysc 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1010000 0 0x1000>,
+ <0 0xf1020000 0 0x20000>,
+ <0 0xf1040000 0 0x20000>,
+ <0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77970-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77970-rst";
+ reg = <0 0xe6160000 0 0x200>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77970-sysc";
+ reg = <0 0xe6180000 0 0x440>;
+ #power-domain-cells = <1>;
+ };
+
+ pfc: pfc@e6060000 {
+ compatible = "renesas,pfc-r8a77970";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77970",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77970",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 96>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe66a0000 0 96>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ <&dmac2 0x37>, <&dmac2 0x36>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ <&dmac2 0x57>, <&dmac2 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ <&dmac2 0x59>, <&dmac2 0x58>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77970",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii-id";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77995.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Renesas Draak board based on r8a77995";
+ compatible = "renesas,draak", "renesas,r8a77995";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x18000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&pfc {
+ avb0_pins: avb {
+ mux {
+ groups = "avb0_link", "avb0_mdc", "avb0_mii";
+ function = "avb0";
+ };
+ };
+
+ pwm0_pins: pwm0 {
+ groups = "pwm0_c";
+ function = "pwm0";
+ };
+
+ pwm1_pins: pwm1 {
+ groups = "pwm1_c";
+ function = "pwm1";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&avb {
+ pinctrl-0 = <&avb0_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a77995 SoC
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77995-sysc.h>
+
+/ {
+ compatible = "renesas,r8a77995";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A77995_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77995-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77995-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77995-rst";
+ reg = <0 0xe6160000 0 0x0200>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77995";
+ reg = <0 0xe6060000 0 0x508>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77995-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 9>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 14>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 906>;
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77995",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii-txid";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ ehci0: usb@ee080100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ ohci0: usb@ee080000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a77995",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "rk3128.dtsi"
+
+/ {
+ model = "Rockchip RK3128 Evaluation board";
+ compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ vbus-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&emmc {
+ fifo-mode;
+ status = "okay";
+};
+
+&pinctrl {
+ usb_otg {
+ otg_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3128-cru.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3128";
+ rockchip,sram = <&sram>;
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ spi0 = &spi0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3128-smp";
+
+ cpu0:cpu@0x000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x000>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1:cpu@0x001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x001>;
+ };
+
+ cpu2:cpu@0x002 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x002>;
+ };
+
+ cpu3:cpu@0x003 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x003>;
+ };
+ };
+
+ cpu_axi_bus: cpu_axi_bus {
+ compatible = "rockchip,cpu_axi_bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ qos {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ crypto {
+ reg = <0x10128080 0x20>;
+ };
+
+ core {
+ reg = <0x1012a000 0x20>;
+ };
+
+ peri {
+ reg = <0x1012c000 0x20>;
+ };
+
+ gpu {
+ reg = <0x1012d000 0x20>;
+ };
+
+ vpu {
+ reg = <0x1012e000 0x20>;
+ };
+
+ rga {
+ reg = <0x1012f000 0x20>;
+ };
+ ebc {
+ reg = <0x1012f080 0x20>;
+ };
+
+ iep {
+ reg = <0x1012f100 0x20>;
+ };
+
+ lcdc {
+ reg = <0x1012f180 0x20>;
+ rockchip,priority = <3 3>;
+ };
+
+ vip {
+ reg = <0x1012f200 0x20>;
+ rockchip,priority = <3 3>;
+ };
+ };
+
+ msch {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ msch@10128000 {
+ reg = <0x10128000 0x20>;
+ rockchip,read-latency = <0x3f>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ migrate = <0x84000005>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma: pdma@20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ arm,pl330-broken-no-flushp;//2
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin12m: xin12m {
+ compatible = "fixed-clock";
+ clocks = <&xin24m>;
+ clock-frequency = <12000000>;
+ clock-output-names = "xin12m";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ timer@20044000 {
+ compatible = "arm,armv7-timer";
+ reg = <0x20044000 0xb8>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,broadcast = <1>;
+ };
+
+ watchdog: wdt@2004c000 {
+ compatible = "rockchip,watch dog";
+ reg = <0x2004c000 0x100>;
+ clock-names = "pclk_wdt";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,irq = <1>;
+ rockchip,timeout = <60>;
+ rockchip,atboot = <1>;
+ rockchip,debug = <0>;
+ };
+
+ reset: reset@20000110 {
+ compatible = "rockchip,reset";
+ reg = <0x20000110 0x24>;
+ #reset-cells = <1>;
+ };
+
+ nandc: nandc@10500000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x10500000 0x4000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
+ nandc_id = <0>;
+ clocks = <&cru SCLK_NANDC>,
+ <&cru HCLK_NANDC>,
+ <&cru SRST_NANDC>;
+ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
+ };
+
+ dmc: dmc@20004000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-dmc", "syscon";
+ reg = <0x0 0x20004000 0x0 0x1000>;
+ };
+
+ cru: clock-controller@20000000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ uart0: serial0@20060000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20060000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ dmas = <&pdma 2>, <&pdma 3>;
+ #dma-cells = <2>;
+ };
+
+ uart1: serial1@20064000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20064000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ dmas = <&pdma 4>, <&pdma 5>;
+ #dma-cells = <2>;
+ };
+
+ uart2: serial2@20068000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ dmas = <&pdma 6>, <&pdma 7>;
+ #dma-cells = <2>;
+ };
+
+ saradc: saradc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ pwm0: pwm0@20050000 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050000 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm1: pwm1@20050010 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050010 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm2: pwm2@20050020 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050020 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ pwm3: pwm3@20050030 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050030 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ };
+
+ sram: sram@10080400 {
+ compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
+ reg = <0x10080400 0x1C00>;
+ map-exec;
+ map-cacheable;
+ };
+
+ pmu: syscon@100a0000 {
+ compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
+ reg = <0x100a0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ gic: interrupt-controller@10139000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ reg = <0x10139000 0x1000>,
+ <0x1013a000 0x1000>,
+ <0x1013c000 0x2000>,
+ <0x1013e000 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
+ };
+
+ u2phy: usb2-phy {
+ compatible = "rockchip,rk3128-usb2phy";
+ reg = <0x017c 0x0c>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ #phy-cells = <1>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+
+ usb_otg: usb@10180000 {
+ compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
+ "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ g-use-dma;
+ hnp-srp-disable;
+ phys = <&u2phy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@101c0000 {
+ compatible = "generic-ehci";
+ reg = <0x101c0000 0x20000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@101e0000 {
+ compatible = "generic-ohci";
+ reg = <0x101e0000 0x20000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@10214000 {
+ compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10214000 0x4000>;
+ max-frequency = <150000000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ emmc: dwmmc@1021c000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x1021c000 0x4000>;
+ max-frequency = <150000000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ bus-width = <8>;
+ default-sample-phase = <158>;
+ num-slots = <1>;
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ i2c0: i2c0@20072000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <20072000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ };
+
+ i2c1: i2c1@20056000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ };
+
+ i2c2: i2c2@2005a000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005a000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ };
+
+ i2c3: i2c3@2005e000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005e000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ };
+
+ spi0: spi@20074000 {
+ compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
+ rockchip,spi-src-clk = <0>;
+ num-cs = <2>;
+ clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
+ clock-names = "spi","pclk_spi0";
+ dmas = <&pdma 8>, <&pdma 9>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ };
+
+ grf: syscon@20008000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3128-grf", "syscon";
+ reg = <0x20008000 0x1000>;
+ };
+
+ pinctrl: pinctrl@20008000 {
+ compatible = "rockchip,rk3128-pinctrl";
+ reg = <0x20008000 0xA8>,
+ <0x200080A8 0x4C>,
+ <0x20008118 0x20>,
+ <0x20008100 0x04>;
+ reg-names = "base", "mux", "pull", "drv";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@2007c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2007c000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio2@20088000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20088000 0x100>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ emmc {
+ /*
+ * We run eMMC at max speed; bump up drive strength.
+ * We also have external pulls, so disable the internal ones.
+ */
+
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_pwren: emmc-pwren {
+ rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
+ <1 25 RK_FUNC_2 &pcfg_pull_none>,
+ <1 26 RK_FUNC_2 &pcfg_pull_none>,
+ <1 27 RK_FUNC_2 &pcfg_pull_none>,
+ <1 28 RK_FUNC_2 &pcfg_pull_none>,
+ <1 29 RK_FUNC_2 &pcfg_pull_none>,
+ <1 30 RK_FUNC_2 &pcfg_pull_none>,
+ <1 31 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ nandc{
+ nandc_ale:nandc-ale {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_cle:nandc-cle {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_wrn:nandc-wrn {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_rdn:nandc-rdn {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_rdy:nandc-rdy {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_cs0:nandc-cs0 {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ nandc_data: nandc-data {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
+ <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
+ <1 19 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_wp: sdmmc-wp {
+ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
+ <1 RK_PC3 1 &pcfg_pull_up>,
+ <1 RK_PC4 1 &pcfg_pull_up>,
+ <1 RK_PC5 1 &pcfg_pull_up>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
+ <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
+ <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 20 3 &pcfg_pull_none>,
+ <2 21 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_txd_mux0:spi0-txd-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_rxd_mux0:spi0-rxd-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_clk_mux0:spi0-clk-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_cs0_mux0:spi0-cs0-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ spi0_cs1_mux0:spi0-cs1-mux0 {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ };
+};
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
+ sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
};
chosen {
&dwc3_typec1 {
status = "okay";
+ tsd,usb-port-power = "usbhub_enable";
};
&vopb {
status = "okay";
};
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
&gpio3 {
u-boot,dm-pre-reloc;
};
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 83000000>;
+ u-boot,dm-pre-reloc;
};
uart1_clk: uart1_clk@25 {
#clock-cells = <0>;
reg = <26>;
atmel,clk-output-range = <0 83000000>;
+ u-boot,dm-pre-reloc;
};
uart3_clk: uart3_clk@27 {
status = "disabled";
};
+ uart0: serial@f801c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf801c000 0x100>;
+ clocks = <&uart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
uart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x100>;
status = "disabled";
};
+ uart2: serial@f8024000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf8024000 0x100>;
+ clocks = <&uart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
i2c0: i2c@f8028000 {
compatible = "atmel,sama5d2-i2c";
reg = <0xf8028000 0x100>;
u-boot,dm-pre-reloc;
};
};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
status = "disabled";
u-boot,dm-pre-reloc;
};
+
+ pwrcfg: power-config@58024800 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
u-boot,dm-pre-reloc;
};
--- /dev/null
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO Plus 2";
+ compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
};
};
+&ehci1 {
+ status = "okay";
+};
+
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
&usbphy {
status = "okay";
};
-
-&ohci1 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
};
};
+&ccu {
+ compatible = "allwinner,sun50i-h5-ccu";
+};
+
&gic {
compatible = "arm,gic-400";
};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc1 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc2 {
+ compatible = "allwinner,sun50i-h5-emmc",
+ "allwinner,sun50i-a64-emmc";
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+};
+
+&pio {
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "allwinner,sun50i-h5-pinctrl";
+};
--- /dev/null
+/*
+ * Copyright 2017 Ondřej Jirman
+ * Ondřej Jirman <megous@megous.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+ model = "TBS A711 Tablet";
+ compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
--- /dev/null
+#include <config.h>
+
+/ {
+ binman {
+ multiple-images;
+ image1 {
+ filename = "u-boot-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+
+ /* Same as image1 - some tools still expect the -dtb suffix */
+ image2 {
+ filename = "u-boot-dtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+
+ image3 {
+ filename = "u-boot-nodtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot-nodtb {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+ };
+};
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "tegra-u-boot.dtsi"
+
/ {
host1x@50000000 {
u-boot,dm-pre-reloc;
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
-/ {
- host1x@50000000 {
- u-boot,dm-pre-reloc;
- dc@54200000 {
- u-boot,dm-pre-reloc;
- };
- };
-};
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
stdout-path = "serial0:115200n8";
};
+ cpld {
+ compatible = "renesas,ulcb-cpld";
+ status = "okay";
+ gpio-sck = <&gpio6 8 0>;
+ gpio-mosi = <&gpio6 7 0>;
+ gpio-miso = <&gpio6 10 0>;
+ gpio-sstbz = <&gpio2 3 0>;
+ };
+
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
};
};
+&i2c_dvfs {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
- power-source = <3300>;
+ power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
};
ðsc {
- interrupts = <0 48 4>;
+ interrupts = <0 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq0 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/uniphier-gpio.h>
+
/memreserve/ 0x80000000 0x02000000;
/ {
};
};
- cluster0_opp: opp_table {
+ cluster0_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
};
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
+ resets = <&peri_rst 8>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
+ resets = <&sys_rst 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
+ <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
+ <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
+ <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-ld11-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x68>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-ld11-aidet";
reg = <0x5fc20000 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
ðsc {
- interrupts = <0 48 4>;
+ interrupts = <0 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq0 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
/memreserve/ 0x80000000 0x02000000;
/ {
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
};
cpu3: cpu@101 {
};
};
- cluster0_opp: opp_table0 {
+ cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cluster1_opp: opp_table1 {
+ cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
};
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 10 4>;
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+ thermal-sensors = <&pvtctl>;
+
+ trips {
+ cpu_crit: cpu-crit {
+ temperature = <110000>; /* 110C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu-alert {
+ temperature = <100000>; /* 100C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0
+ THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu2
+ THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
+ resets = <&peri_rst 8>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
+ resets = <&sys_rst 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-ld20-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x68>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-ld20-aidet";
reg = <0x5fc20000 0x200>;
watchdog {
compatible = "socionext,uniphier-wdt";
};
+
+ pvtctl: pvtctl {
+ compatible = "socionext,uniphier-ld20-thermal";
+ interrupts = <0 3 4>;
+ #thermal-sensor-cells = <0>;
+ socionext,tmod-calibration = <0x0f22 0x68ee>;
+ };
};
usb: usb@65b00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
ðsc {
- interrupts = <0 49 4>;
+ interrupts = <1 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq1 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/uniphier-gpio.h>
+
/ {
compatible = "socionext,uniphier-ld4";
#address-cells = <1>;
clock-frequency = <24576000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <36864000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <36864000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <36864000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <36864000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <136>;
+ socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
};
i2c0: i2c@58400000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
+ <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
+ <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
+ <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
ðsc {
- interrupts = <0 52 4>;
+ interrupts = <4 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq4 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
*/
&pinctrl {
- pinctrl_aout: aout_grp {
+ pinctrl_aout: aout {
groups = "aout";
function = "aout";
};
- pinctrl_emmc: emmc_grp {
+ pinctrl_emmc: emmc {
groups = "emmc", "emmc_dat8";
function = "emmc";
};
- pinctrl_emmc_1v8: emmc_grp_1v8 {
+ pinctrl_emmc_1v8: emmc-1v8 {
groups = "emmc", "emmc_dat8";
function = "emmc";
};
- pinctrl_ether_mii: ether_mii_grp {
+ pinctrl_ether_mii: ether-mii {
groups = "ether_mii";
function = "ether_mii";
};
- pinctrl_ether_rgmii: ether_rgmii_grp {
+ pinctrl_ether_rgmii: ether-rgmii {
groups = "ether_rgmii";
function = "ether_rgmii";
};
- pinctrl_ether_rmii: ether_rmii_grp {
+ pinctrl_ether_rmii: ether-rmii {
groups = "ether_rmii";
function = "ether_rmii";
};
- pinctrl_i2c0: i2c0_grp {
+ pinctrl_i2c0: i2c0 {
groups = "i2c0";
function = "i2c0";
};
- pinctrl_i2c1: i2c1_grp {
+ pinctrl_i2c1: i2c1 {
groups = "i2c1";
function = "i2c1";
};
- pinctrl_i2c2: i2c2_grp {
+ pinctrl_i2c2: i2c2 {
groups = "i2c2";
function = "i2c2";
};
- pinctrl_i2c3: i2c3_grp {
+ pinctrl_i2c3: i2c3 {
groups = "i2c3";
function = "i2c3";
};
- pinctrl_i2c4: i2c4_grp {
+ pinctrl_i2c4: i2c4 {
groups = "i2c4";
function = "i2c4";
};
- pinctrl_nand: nand_grp {
+ pinctrl_nand: nand {
groups = "nand";
function = "nand";
};
- pinctrl_nand2cs: nand2cs_grp {
+ pinctrl_nand2cs: nand2cs {
groups = "nand", "nand_cs1";
function = "nand";
};
- pinctrl_sd: sd_grp {
+ pinctrl_sd: sd {
groups = "sd";
function = "sd";
};
- pinctrl_sd_1v8: sd_grp_1v8 {
+ pinctrl_sd_1v8: sd-1v8 {
groups = "sd";
function = "sd";
};
- pinctrl_sd1: sd1_grp {
+ pinctrl_sd1: sd1 {
groups = "sd1";
function = "sd1";
};
- pinctrl_sd1_1v8: sd1_grp_1v8 {
+ pinctrl_sd1_1v8: sd1-1v8 {
groups = "sd1";
function = "sd1";
};
- pinctrl_system_bus: system_bus_grp {
+ pinctrl_system_bus: system-bus {
groups = "system_bus", "system_bus_cs1";
function = "system_bus";
};
- pinctrl_uart0: uart0_grp {
+ pinctrl_uart0: uart0 {
groups = "uart0";
function = "uart0";
};
- pinctrl_uart1: uart1_grp {
+ pinctrl_uart1: uart1 {
groups = "uart1";
function = "uart1";
};
- pinctrl_uart2: uart2_grp {
+ pinctrl_uart2: uart2 {
groups = "uart2";
function = "uart2";
};
- pinctrl_uart3: uart3_grp {
+ pinctrl_uart3: uart3 {
groups = "uart3";
function = "uart3";
};
- pinctrl_usb0: usb0_grp {
+ pinctrl_usb0: usb0 {
groups = "usb0";
function = "usb0";
};
- pinctrl_usb1: usb1_grp {
+ pinctrl_usb1: usb1 {
groups = "usb1";
function = "usb1";
};
- pinctrl_usb2: usb2_grp {
+ pinctrl_usb2: usb2 {
groups = "usb2";
function = "usb2";
};
- pinctrl_usb3: usb3_grp {
+ pinctrl_usb3: usb3 {
groups = "usb3";
function = "usb3";
};
};
ðsc {
- interrupts = <0 50 4>;
+ interrupts = <2 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq2 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/uniphier-gpio.h>
+
/ {
compatible = "socionext,uniphier-pro4";
#address-cells = <1>;
clock-frequency = <25000000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <248>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
};
i2c0: i2c@58780000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
clock-frequency = <400000>;
};
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
+ <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
+ <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
};
- cpu_opp: opp_table {
+ cpu_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
clock-frequency = <20000000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <248>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
};
i2c0: i2c@58780000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
emmc: sdhc@68400000 {
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
/ {
compatible = "socionext,uniphier-pxs2";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
operating-points-v2 = <&cpu_opp>;
};
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
operating-points-v2 = <&cpu_opp>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
};
};
- cpu_opp: opp_table {
+ cpu_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
clock-frequency = <25000000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+ thermal-sensors = <&pvtctl>;
+
+ trips {
+ cpu_crit: cpu-crit {
+ temperature = <95000>; /* 95C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu-alert {
+ temperature = <85000>; /* 85C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0
+ THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <88900000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <88900000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <88900000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <88900000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
gpio-ranges-group-names = "gpio_range0",
"gpio_range1";
ngpios = <232>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+ <21 217 3>;
};
i2c0: i2c@58780000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 45 4>;
clocks = <&peri_clk 8>;
+ resets = <&peri_rst 8>;
clock-frequency = <400000>;
};
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
clock-frequency = <400000>;
};
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
+
+ pvtctl: pvtctl {
+ compatible = "socionext,uniphier-pxs2-thermal";
+ interrupts = <0 3 4>;
+ #thermal-sensor-cells = <0>;
+ socionext,tmod-calibration = <0x0f86 0x6844>;
+ };
};
usb0: usb@65b00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
ðsc {
- interrupts = <0 52 4>;
+ interrupts = <4 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq4 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/uniphier-gpio.h>
+
/memreserve/ 0x80000000 0x02000000;
/ {
};
};
- cluster0_opp: opp_table {
+ cluster0_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
};
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
"gpio_range1",
"gpio_range2";
ngpios = <286>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+ <21 217 3>;
};
i2c0: i2c@58780000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
+ resets = <&sys_rst 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
};
};
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pxs3-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x68>;
+ };
+ };
+
aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pxs3-aidet";
reg = <0x5fc20000 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
};
ðsc {
- interrupts = <0 48 4>;
+ interrupts = <0 8>;
};
&serial0 {
status = "okay";
};
+&gpio {
+ xirq0 {
+ gpio-hog;
+ gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
+ input;
+ };
+};
+
&i2c0 {
status = "okay";
};
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/uniphier-gpio.h>
+
/ {
compatible = "socionext,uniphier-sld8";
#address-cells = <1>;
clock-frequency = <25000000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <80000000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <80000000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <80000000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <80000000>;
+ resets = <&peri_rst 3>;
};
gpio: gpio@55000000 {
"gpio_range1",
"gpio_range2";
ngpios = <136>;
+ socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
};
i2c0: i2c@58400000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <400000>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
+ <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>;
};
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
+ <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>;
};
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
+ <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
+ resets = <&sys_rst 2>;
};
};
};
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
- support_card: support_card@1,1f00000 {
+ support_card: support-card@1,1f00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 1 0x01f00000 0x00100000>;
+ interrupt-parent = <&gpio>;
ethsc: ethernet@0 {
compatible = "smsc,lan9118", "smsc,lan9115";
pinctrl {
u-boot,dm-pre-reloc;
- emmc_grp {
+ emmc {
u-boot,dm-pre-reloc;
};
- uart0_grp {
+ uart0 {
u-boot,dm-pre-reloc;
};
- uart1_grp {
+ uart1 {
u-boot,dm-pre-reloc;
};
- uart2_grp {
+ uart2 {
u-boot,dm-pre-reloc;
};
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
- #interrupt-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
--- /dev/null
+/*
+ * Xilinx CC108 board DTS
+ *
+ * (C) Copyright 2007-2013 Xilinx, Inc.
+ * (C) Copyright 2007-2013 Michal Simek
+ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <0>;
+ num-cs = <1>;
+ flash@0 { /* 16 MB */
+ compatible = "n25q128a11";
+ reg = <0x0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot-bs";
+ reg = <0x0 0x400000>; /* 4MB */
+ };
+ partition@0x400000 {
+ label = "qspi-linux";
+ reg = <0x400000 0x400000>; /* 4MB */
+ };
+ partition@0x800000 {
+ label = "qspi-rootfs";
+ reg = <0x800000 0x400000>; /* 4MB */
+ };
+ partition@0xc00000 {
+ label = "qspi-devicetree";
+ reg = <0xc00000 0x100000>; /* 1MB */
+ };
+ partition@0xd00000 {
+ label = "qspi-scratch";
+ reg = <0xd00000 0x200000>; /* 2MB */
+ };
+ partition@0xf00000 {
+ label = "qspi-uboot-env";
+ reg = <0xf00000 0x100000>; /* 1MB */
+ };
+ };
+};
+
+&sdhci1 {
+ status = "okay";
+ broken-cd ;
+ wp-inverted ;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy1>;
+};
--- /dev/null
+/*
+ * Xilinx CSE QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+/*
+ * Xilinx CSE QSPI board DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE QSPI Board";
+ compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
+
+ aliases {
+ spi0 = &qspi;
+ serial0 = &dcc;
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0xFFFC0000 0x40000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ qspi: spi@e000d000 {
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clkc 10>, <&clkc 43>;
+ compatible = "xlnx,zynq-qspi-1.0";
+ status = "okay";
+ interrupt-parent = <&intc>;
+ interrupts = <0 19 4>;
+ reg = <0xe000d000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ flash@0 {
+ compatible = "n25q128a11";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@qspi-fsbl-uboot {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ partition@qspi-bitstream {
+ label = "qspi-bitstream";
+ reg = <0xC00000 0x400000>;
+ };
+ };
+ };
+
+ slcr: slcr@f8000000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF8000000 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ u-boot,dm-pre-reloc;
+ clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+ "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+ "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper", "sdio1_aper",
+ "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+ "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+ "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+ "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+&dcc {
+ status = "okay";
+};
--- /dev/null
+/*
+ * SYZYGY Hub DTS
+ *
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2017 Opal Kelly Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "SYZYGY Hub";
+ compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart0;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 47 1>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "otg";
+ usb-phy = <&usb_phy0>;
+};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio0 50 0>;
+ sda-gpios = <&gpio0 51 0>;
i2cswitch@74 {
compatible = "nxp,pca9548";
};
};
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_50_grp", "gpio0_51_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_50_grp", "gpio0_51_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_2_grp";
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
+ device_type = "ethernet-phy";
};
};
};
usb_phy0: phy0 {
- compatible = "usb-nop-xceiv";
#phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
reset-gpios = <&gpio0 46 1>;
};
};
ethernet_phy: ethernet-phy@0 {
reg = <0>;
+ device_type = "ethernet-phy";
};
};
* SPDX-License-Identifier: GPL-2.0+
*/
-&amba {
+/ {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
* SPDX-License-Identifier: GPL-2.0+
*/
-&amba {
+/ {
misc_clk: misc_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
model = "ZynqMP EP108";
aliases {
+ ethernet0 = &gem0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
serial0 = &uart0;
status = "okay";
clock-frequency = <400000>;
eeprom@54 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x54>;
};
};
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x55>;
};
};
spi-max-frequency = <50000000>;
reg = <0>;
- spi0_flash0@00000000 {
+ spi0_flash0@0 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
spi-max-frequency = <50000000>;
reg = <0>;
- spi1_flash0@00000000 {
+ spi1_flash0@0 {
label = "spi1_flash0";
reg = <0x0 0x100000>;
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem2 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
spi-max-frequency = <50000000>;
reg = <0>;
- spi0_flash0@00000000 {
+ spi0_flash0@0 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
spi-max-frequency = <20000000>;
reg = <0>;
- spi1_flash0@00000000 {
+ spi1_flash0@0 {
label = "spi1_flash0";
reg = <0x0 0x84000>;
};
*
* Michal Simek <michal.simek@xilinx.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&lpd_dma_chan1 {
&gem0 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
&gem1 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 91];
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy7>;
};
&gem2 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 92];
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy3>;
};
&gem3 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 93];
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy8>;
};
};
chosen {
- bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+ bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem1 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+ model = "ZynqMP ZCU102 Rev1.0";
+ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ board_sn: board_sn@0 {
+ reg = <0x0 0x14>;
+ };
+
+ eth_mac: eth_mac@20 {
+ reg = <0x20 0x6>;
+ };
+
+ board_name: board_name@d0 {
+ reg = <0xd0 0x6>;
+ };
+
+ board_revision: board_revision@e0 {
+ reg = <0xe0 0x3>;
+ };
+};
/*
- * dts file for Xilinx ZynqMP ZCU102
+ * dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015, Xilinx, Inc.
*
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
compatible = "gpio-leds";
heartbeat_led {
label = "heartbeat";
- gpios = <&gpio 23 0>;
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
/*
gtr_sel0 {
gpio-hog;
gpios = <0 0>;
- output-high; /* PCIE = 0, DP = 1 */
+ output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr_sel1 {
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
/* FIXME PL i2c via PCA9306 - u45 */
/* FIXME MSP430 - u41 - not detected */
i2cswitch@74 { /* u34 */
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
- eeprom@54 { /* u23 */
+ eeprom: eeprom@54 { /* u23 */
compatible = "at,24c08";
reg = <0x54>;
};
si5328: clock-generator4@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
};
};
/* 5 - 7 unconnected */
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_0_cd_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_0_cd_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_0_wp_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_0_wp_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22", "MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&pcie {
-/* status = "okay"; */
+ status = "okay";
};
&qspi {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
no-1-8-v; /* for 1.0 silicon */
xlnx,mio_bank = <1>;
};
+&serdes {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+ maximum-speed = "super-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
};
&xilinx_drm {
/ {
model = "ZynqMP ZCU102 RevB";
+ compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
&gem3 {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
+ operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
idle-states {
- entry-mehod = "arm,psci";
+ entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <600>;
- min-residency-us = <800000>;
+ min-residency-us = <10000>;
};
};
};
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <1199999988>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <599999994>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <399999996>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <299999997>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
};
pd_dp: pd-dp {
- /* fixme: what to attach to */
#power-domain-cells = <0x0>;
pd-id = <0x29>;
};
method = "smc";
};
- firmware {
+ pmufw: firmware {
compatible = "xlnx,zynqmp-pm";
method = "smc";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
- interrupts = <1 13 0xf01>,
- <1 14 0xf01>,
- <1 11 0xf01>,
- <1 10 0xf01>;
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
};
edac {
compatible = "arm,cortex-a53-edac";
};
- pcap {
+ fpga_full: fpga-full {
+ compatible = "fpga-region";
+ fpga-mgr = <&pcap>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc_revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
+
+ pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
+ rst: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+
+ xlnx_dp_snd_card: dp_snd_card {
+ compatible = "xlnx,dp-snd-card";
+ status = "disabled";
+ xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
+ xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
+ };
+
+ xlnx_dp_snd_codec0: dp_snd_codec0 {
+ compatible = "xlnx,dp-snd-codec";
+ status = "disabled";
+ clock-names = "aud_clk";
+ };
+
+ xlnx_dp_snd_pcm0: dp_snd_pcm0 {
+ compatible = "xlnx,dp-snd-pcm";
+ status = "disabled";
+ dmas = <&xlnx_dpdma 4>;
+ dma-names = "tx";
+ };
+
+ xlnx_dp_snd_pcm1: dp_snd_pcm1 {
+ compatible = "xlnx,dp-snd-pcm";
+ status = "disabled";
+ dmas = <&xlnx_dpdma 5>;
+ dma-names = "tx";
+ };
+
+ xilinx_drm: xilinx_drm {
+ compatible = "xlnx,drm";
+ status = "disabled";
+ xlnx,encoder-slave = <&xlnx_dp>;
+ xlnx,connector-type = "DisplayPort";
+ xlnx,dp-sub = <&xlnx_dp_sub>;
+ planes {
+ xlnx,pixel-format = "rgb565";
+ plane0 {
+ dmas = <&xlnx_dpdma 3>;
+ dma-names = "dma0";
+ };
+ plane1 {
+ dmas = <&xlnx_dpdma 0>,
+ <&xlnx_dpdma 1>,
+ <&xlnx_dpdma 2>;
+ dma-names = "dma0", "dma1", "dma2";
+ };
+ };
+ };
+
amba_apu: amba_apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "arm,mali-400", "arm,mali-utgard";
- reg = <0x0 0xfd4b0000 0x0 0x30000>;
+ reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+ clock-names = "gpu", "gpu_pp0", "gpu_pp1";
power-domains = <&pd_gpu>;
};
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
+ gpio-controller;
power-domains = <&pd_gpio>;
};
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
};
qspi: spi@ff0f0000 {
+ u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
+ calibration = <0x8000>;
};
serdes: zynqmp_phy@fd400000 {
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>,
- <0x0 0xfd1a0000 0x0 0x1000>,
<0x0 0xff5e0000 0x0 0x1000>;
- reg-names = "serdes", "siou", "fpd", "lpd";
- xlnx,tx_termination_fix;
+ reg-names = "serdes", "siou", "lpd";
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
+ resets = <&rst 16>, <&rst 59>, <&rst 60>,
+ <&rst 61>, <&rst 62>, <&rst 63>,
+ <&rst 64>, <&rst 3>, <&rst 29>,
+ <&rst 30>, <&rst 31>, <&rst 32>;
+ reset-names = "sata_rst", "usb0_crst", "usb1_crst",
+ "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
+ "usb1_apbrst", "dp_rst", "gem0_rst",
+ "gem1_rst", "gem2_rst", "gem3_rst";
lane0: lane0 {
#phy-cells = <4>;
};
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
+ #stream-id-cells = <4>;
+ iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
+ <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* dma-coherent; */
};
sdhci0: sdhci@ff160000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
power-domains = <&pd_sd0>;
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
};
sdhci1: sdhci@ff170000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
power-domains = <&pd_sd1>;
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
+ };
+
+ pinctrl0: pinctrl@ff180000 {
+ compatible = "xlnx,pinctrl-zynqmp";
+ status = "disabled";
+ reg = <0x0 0xff180000 0x0 0x1000>;
};
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
#iommu-cells = <1>;
+ status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
- mmu-masters = < &gem0 0x874
- &gem1 0x875
- &gem2 0x876
- &gem3 0x877
- &usb0 0x860
- &usb1 0x861
- &qspi 0x873
- &lpd_dma_chan1 0x868
- &lpd_dma_chan2 0x869
- &lpd_dma_chan3 0x86a
- &lpd_dma_chan4 0x86b
- &lpd_dma_chan5 0x86c
- &lpd_dma_chan6 0x86d
- &lpd_dma_chan7 0x86e
- &lpd_dma_chan8 0x86f
- &fpd_dma_chan1 0x14e8
- &fpd_dma_chan2 0x14e9
- &fpd_dma_chan3 0x14ea
- &fpd_dma_chan4 0x14eb
- &fpd_dma_chan5 0x14ec
- &fpd_dma_chan6 0x14ed
- &fpd_dma_chan7 0x14ee
- &fpd_dma_chan8 0x14ef
- &sdhci0 0x870
- &sdhci1 0x871
- &nand0 0x872>;
};
spi0: spi@ff040000 {
power-domains = <&pd_uart1>;
};
- usb0: usb0 {
+ usb0: usb0@ff9d0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
+ reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
- clocks = <&clk125>, <&clk125>;
- #stream-id-cells = <1>;
- iommus = <&smmu 0x860>;
power-domains = <&pd_usb0>;
ranges;
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
dwc3_0: dwc3@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupts = <0 65 4>;
- /* snps,quirk-frame-length-adjustment = <0x20>; */
+ interrupts = <0 65 4>, <0 69 4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x860>;
+ snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
+ /* dma-coherent; */
};
};
- usb1: usb1 {
+ usb1: usb1@ff9e0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
+ reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
- clocks = <&clk125>, <&clk125>;
- #stream-id-cells = <1>;
- iommus = <&smmu 0x861>;
power-domains = <&pd_usb1>;
ranges;
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
dwc3_1: dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupts = <0 70 4>;
- /* snps,quirk-frame-length-adjustment = <0x20>; */
+ interrupts = <0 70 4>, <0 74 4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x861>;
+ snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
+ /* dma-coherent; */
};
};
timeout-sec = <10>;
};
- xilinx_drm: xilinx_drm {
- compatible = "xlnx,drm";
+ xilinx_ams: ams@ffa50000 {
+ compatible = "xlnx,zynqmp-ams";
status = "disabled";
- xlnx,encoder-slave = <&xlnx_dp>;
- xlnx,connector-type = "DisplayPort";
- xlnx,dp-sub = <&xlnx_dp_sub>;
- planes {
- xlnx,pixel-format = "rgb565";
- plane0 {
- dmas = <&xlnx_dpdma 3>;
- dma-names = "dma0";
- };
- plane1 {
- dmas = <&xlnx_dpdma 0>,
- <&xlnx_dpdma 1>,
- <&xlnx_dpdma 2>;
- dma-names = "dma0", "dma1", "dma2";
- };
+ interrupt-parent = <&gic>;
+ interrupts = <0 56 4>;
+ interrupt-names = "ams-irq";
+ reg = <0x0 0xffa50000 0x0 0x800>;
+ reg-names = "ams-base";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #io-channel-cells = <1>;
+ ranges;
+
+ ams_ps: ams_ps@ffa50800 {
+ compatible = "xlnx,zynqmp-ams-ps";
+ status = "disabled";
+ reg = <0x0 0xffa50800 0x0 0x400>;
+ };
+
+ ams_pl: ams_pl@ffa50c00 {
+ compatible = "xlnx,zynqmp-ams-pl";
+ status = "disabled";
+ reg = <0x0 0xffa50c00 0x0 0x400>;
};
};
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
+ power-domains = <&pd_dp>;
xlnx,dp-version = "v1.2";
xlnx,max-lanes = <2>;
xlnx,max-link-rate = <540000>;
xlnx,max-pclock-frequency = <300000>;
};
- xlnx_dp_snd_card: dp_snd_card {
- compatible = "xlnx,dp-snd-card";
- status = "disabled";
- xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
- xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
- };
-
- xlnx_dp_snd_codec0: dp_snd_codec0 {
- compatible = "xlnx,dp-snd-codec";
- status = "disabled";
- clock-names = "aud_clk";
- };
-
- xlnx_dp_snd_pcm0: dp_snd_pcm0 {
- compatible = "xlnx,dp-snd-pcm";
- status = "disabled";
- dmas = <&xlnx_dpdma 4>;
- dma-names = "tx";
- };
-
- xlnx_dp_snd_pcm1: dp_snd_pcm1 {
- compatible = "xlnx,dp-snd-pcm";
- status = "disabled";
- dmas = <&xlnx_dpdma 5>;
- dma-names = "tx";
- };
-
xlnx_dp_sub: dp_sub@fd4aa000 {
compatible = "xlnx,dp-sub";
status = "disabled";
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
+ power-domains = <&pd_dp>;
};
xlnx_dpdma: dma@fd4c0000 {
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
+ power-domains = <&pd_dp>;
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel {
*/
/* BOOT0 header information */
+_start:
+ ARM_VECTORS
.word 0xbabeface
.word _end - _start
*/
/* BOOT0 header information */
+_start:
+ ARM_VECTORS
.word 0xbabeface
.word _end - _start
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
-#define SVR_DEV_LS2080A 0x8701
-
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr) ((svr) >> 8)
+#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
--- /dev/null
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_ETH_H__
+#define __MESON_ETH_H__
+
+#include <phy.h>
+
+enum {
+ /* Use GXL Internal RMII PHY */
+ MESON_GXL_USE_INTERNAL_RMII_PHY = 1,
+};
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_gx_eth_init(phy_interface_t mode, unsigned int flags);
+
+#endif /* __MESON_ETH_H__ */
#ifndef __GXBB_H__
#define __GXBB_H__
+#define GXBB_FIRMWARE_MEM_SIZE 0x1000000
+
+#define GXBB_AOBUS_BASE 0xc8100000
#define GXBB_PERIPHS_BASE 0xc8834400
#define GXBB_HIU_BASE 0xc883c000
#define GXBB_ETH_BASE 0xc9410000
+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000
+#define GXBB_AO_MEM_SIZE_SHIFT 16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
+
/* Peripherals registers */
#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
--- /dev/null
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_MEM_H__
+#define __MESON_MEM_H__
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_gx_init_reserved_memory(void *fdt);
+
+#endif /* __MESON_MEM_H__ */
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
};
#endif
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
+ IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
+ IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
+ IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
+ IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
};
#endif
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
#include <asm/types.h>
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
+#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
MX6SLL_LCDIF_BASE_ADDR : \
#endif
-
-/*
- * Implementation specifics
- */
-
-#ifdef CONFIG_ARCH_LUBBOCK
-#include "lubbock.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-#include "idp.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_CERF
-#include "cerf.h"
-#endif
-
-#ifdef CONFIG_ARCH_CSB226
-#include "csb226.h"
-#endif
-
-#ifdef CONFIG_ARCH_INNOKOM
-#include "innokom.h"
-#endif
-
-#ifdef CONFIG_ARCH_PLEB
-#include "pleb.h"
-#endif
-
#endif /* _ASM_ARCH_HARDWARE_H */
-
/*
* Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
/*
* Execution starts on the instruction following this 4-byte header
- * (containing the magic 'RK33').
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
*
* To make life easier for everyone, we build the SPL binary with
* space for this 4-byte header already included in the binary.
*/
-
#ifdef CONFIG_SPL_BUILD
/*
* We need to add 4 bytes of space for the 'RK33' at the
* beginning of the executable. However, as we want to keep
* this generic and make it applicable to builds that are like
* the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
- * TPL, but extra space needed in the SPL), we simply repeat
- * the 'b reset' with the expectation that the first one will
- * be overwritten, if this is the first stage contained in the
- * final image created with mkimage)...
+ * TPL, but extra space needed in the SPL), we simply insert
+ * a branch-to-next-instruction-word with the expectation that
+ * the first one may be overwritten, if this is the first stage
+ * contained in the final image created with mkimage)...
*/
- b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+ adr r3, entry_counter
+ ldr r0, [r3]
+ cmp r0, #1 /* check if entry_counter == 1 */
+ beq reset /* regular bootup */
+ add r0, #1
+ str r0, [r3] /* increment the entry_counter in memory */
+ mov r0, #0 /* return 0 to the BROM to signal 'OK' */
+ bx lr /* return control to the BROM */
+entry_counter:
+ .word 0
#endif
+
+#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
+ /* U-Boot proper of armv7 do not need this */
b reset
+#endif
+
+#if !defined(CONFIG_ARM64)
+ /*
+ * For armv7, the addr '_start' will used as vector start address
+ * and write to VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
+#endif
-#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
#endif
#define BOOT_CHARGING (REBOOT_FLAG + 11)
/* enter usb mass storage mode */
#define BOOT_UMS (REBOOT_FLAG + 12)
+/* enter bootrom download mode */
+#define BOOT_BROM_DOWNLOAD 0xEF08A53C
+
+#ifndef __ASSEMBLY__
+int setup_boot_mode(void);
+#endif
#endif
/*
* (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
extern u32 SAVE_SP_ADDR;
/**
- * Hand control back to the bootrom to load another
- * boot stage.
+ * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
+ * result code
+ *
+ * Transfer control back to the Rockchip BROM, restoring necessary
+ * register context and passing a command/result code to the BROM
+ * to instruct its next actions (e.g. continue boot sequence, enter
+ * download mode, ...).
+ *
+ * This function does not return.
+ *
+ * @brom_cmd: indicates how the bootrom should continue the boot
+ * sequence (e.g. load the next stage)
*/
-void back_to_bootrom(void);
+enum rockchip_bootrom_cmd {
+ /*
+ * These can not start at 0, as 0 has a special meaning
+ * for setjmp().
+ */
-/**
- * Assembler component for the above (do not call this directly)
- */
-void _back_to_bootrom_s(void);
+ BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */
+ BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */
+};
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd);
/**
* Boot-device identifiers as used by the BROM
return clk_id - 1;
}
+struct sysreset_reg {
+ unsigned int glb_srst_fst_value;
+ unsigned int glb_srst_snd_value;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*
--- /dev/null
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3128_H
+#define _ASM_ARCH_CRU_RK3128_H
+
+#include <common.h>
+
+#define MHz 1000000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (594 * MHz)
+
+#define CORE_PERI_HZ 150000000
+#define CORE_ACLK_HZ 300000000
+
+#define BUS_ACLK_HZ 148500000
+#define BUS_HCLK_HZ 148500000
+#define BUS_PCLK_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3128_clk_priv {
+ struct rk3128_cru *cru;
+};
+
+struct rk3128_cru {
+ struct rk3128_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ } pll[4];
+ unsigned int cru_mode_con;
+ unsigned int cru_clksel_con[35];
+ unsigned int cru_clkgate_con[11];
+ unsigned int reserved;
+ unsigned int cru_glb_srst_fst_value;
+ unsigned int cru_glb_srst_snd_value;
+ unsigned int reserved1[2];
+ unsigned int cru_softrst_con[9];
+ unsigned int cru_misc_con;
+ unsigned int reserved2[2];
+ unsigned int cru_glb_cnt_th;
+ unsigned int reserved3[3];
+ unsigned int cru_glb_rst_st;
+ unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
+ unsigned int cru_sdmmc_con[2];
+ unsigned int cru_sdio_con[2];
+ unsigned int reserved5[2];
+ unsigned int cru_emmc_con[2];
+ unsigned int reserved6[4];
+ unsigned int cru_pll_prg_en;
+};
+check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
+
+enum {
+ /* PLLCON0*/
+ PLL_POSTDIV1_SHIFT = 12,
+ PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
+ PLL_FBDIV_SHIFT = 0,
+ PLL_FBDIV_MASK = 0xfff,
+
+ /* PLLCON1 */
+ PLL_RST_SHIFT = 14,
+ PLL_PD_SHIFT = 13,
+ PLL_PD_MASK = 1 << PLL_PD_SHIFT,
+ PLL_DSMPD_SHIFT = 12,
+ PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
+ PLL_LOCK_STATUS_SHIFT = 10,
+ PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
+ PLL_POSTDIV2_SHIFT = 6,
+ PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
+ PLL_REFDIV_SHIFT = 0,
+ PLL_REFDIV_MASK = 0x3f,
+
+ /* CRU_MODE */
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORM,
+ GPLL_MODE_DEEP,
+ CPLL_MODE_SHIFT = 8,
+ CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
+ CPLL_MODE_SLOW = 0,
+ CPLL_MODE_NORM,
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORM,
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORM,
+
+ /* CRU_CLK_SEL0_CON */
+ BUS_ACLK_PLL_SEL_SHIFT = 14,
+ BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
+ BUS_ACLK_PLL_SEL_CPLL = 0,
+ BUS_ACLK_PLL_SEL_GPLL,
+ BUS_ACLK_PLL_SEL_GPLL_DIV2,
+ BUS_ACLK_PLL_SEL_GPLL_DIV3,
+ BUS_ACLK_DIV_SHIFT = 8,
+ BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
+ CORE_CLK_PLL_SEL_SHIFT = 7,
+ CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
+ CORE_CLK_PLL_SEL_APLL = 0,
+ CORE_CLK_PLL_SEL_GPLL_DIV2,
+ CORE_DIV_CON_SHIFT = 0,
+ CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL1_CON */
+ BUS_PCLK_DIV_SHIFT = 12,
+ BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
+ BUS_HCLK_DIV_SHIFT = 8,
+ BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
+ CORE_ACLK_DIV_SHIFT = 4,
+ CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
+ CORE_PERI_DIV_SHIFT = 0,
+ CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
+
+ /* CRU_CLK_SEL2_CON */
+ NANDC_PLL_SEL_SHIFT = 14,
+ NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
+ NANDC_PLL_SEL_CPLL = 0,
+ NANDC_PLL_SEL_GPLL,
+ NANDC_CLK_DIV_SHIFT = 8,
+ NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
+ PVTM_CLK_DIV_SHIFT = 0,
+ PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
+
+ /* CRU_CLKSEL10_CON */
+ PERI_PLL_SEL_SHIFT = 14,
+ PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
+ PERI_PLL_APLL = 0,
+ PERI_PLL_DPLL,
+ PERI_PLL_GPLL,
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
+ PERI_ACLK_DIV_SHIFT = 0,
+ PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
+
+ /* CRU_CLKSEL11_CON */
+ MMC0_PLL_SHIFT = 6,
+ MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
+ MMC0_SEL_APLL = 0,
+ MMC0_SEL_GPLL,
+ MMC0_SEL_GPLL_DIV2,
+ MMC0_SEL_24M,
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL12_CON */
+ EMMC_PLL_SHIFT = 14,
+ EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
+ EMMC_SEL_APLL = 0,
+ EMMC_SEL_GPLL,
+ EMMC_SEL_GPLL_DIV2,
+ EMMC_SEL_24M,
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
+
+ /* CLKSEL_CON24 */
+ SARADC_DIV_CON_SHIFT = 8,
+ SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ SARADC_DIV_CON_WIDTH = 8,
+
+ /* CRU_CLKSEL27_CON*/
+ DCLK_VOP_SEL_SHIFT = 0,
+ DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
+ DCLK_VOP_PLL_SEL_CPLL = 0,
+ DCLK_VOP_DIV_CON_SHIFT = 8,
+ DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
+
+ /* CRU_CLKSEL31_CON */
+ VIO0_PLL_SHIFT = 5,
+ VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
+ VI00_SEL_CPLL = 0,
+ VIO0_SEL_GPLL,
+ VIO0_DIV_SHIFT = 0,
+ VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
+ VIO1_PLL_SHIFT = 13,
+ VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
+ VI01_SEL_CPLL = 0,
+ VIO1_SEL_GPLL,
+ VIO1_DIV_SHIFT = 8,
+ VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
+
+ /* CRU_SOFTRST5_CON */
+ DDRCTRL_PSRST_SHIFT = 11,
+ DDRCTRL_SRST_SHIFT = 10,
+ DDRPHY_PSRST_SHIFT = 9,
+ DDRPHY_SRST_SHIFT = 8,
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3128_H
+#define _ASM_ARCH_GRF_RK3128_H
+
+#include <common.h>
+
+struct rk3128_grf {
+ unsigned int reserved[0x2a];
+ unsigned int gpio0a_iomux;
+ unsigned int gpio0b_iomux;
+ unsigned int gpio0c_iomux;
+ unsigned int gpio0d_iomux;
+ unsigned int gpio1a_iomux;
+ unsigned int gpio1b_iomux;
+ unsigned int gpio1c_iomux;
+ unsigned int gpio1d_iomux;
+ unsigned int gpio2a_iomux;
+ unsigned int gpio2b_iomux;
+ unsigned int gpio2c_iomux;
+ unsigned int gpio2d_iomux;
+ unsigned int gpio3a_iomux;
+ unsigned int gpio3b_iomux;
+ unsigned int gpio3c_iomux;
+ unsigned int gpio3d_iomux;
+ unsigned int gpio2c_iomux2;
+ unsigned int grf_cif_iomux;
+ unsigned int grf_cif_iomux1;
+ unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
+ unsigned int gpio0l_pull;
+ unsigned int gpio0h_pull;
+ unsigned int gpio1l_pull;
+ unsigned int gpio1h_pull;
+ unsigned int gpio2l_pull;
+ unsigned int gpio2h_pull;
+ unsigned int gpio3l_pull;
+ unsigned int gpio3h_pull;
+ unsigned int reserved2;
+ unsigned int soc_con0;
+ unsigned int soc_con1;
+ unsigned int soc_con2;
+ unsigned int soc_status0;
+ unsigned int reserved3[6];
+ unsigned int mac_con0;
+ unsigned int mac_con1;
+ unsigned int reserved4[4];
+ unsigned int uoc0_con0;
+ unsigned int reserved5;
+ unsigned int uoc1_con1;
+ unsigned int uoc1_con2;
+ unsigned int uoc1_con3;
+ unsigned int uoc1_con4;
+ unsigned int uoc1_con5;
+ unsigned int reserved6;
+ unsigned int ddrc_stat;
+ unsigned int reserved9;
+ unsigned int soc_status1;
+ unsigned int cpu_con0;
+ unsigned int cpu_con1;
+ unsigned int cpu_con2;
+ unsigned int cpu_con3;
+ unsigned int reserved10;
+ unsigned int reserved11;
+ unsigned int cpu_status0;
+ unsigned int cpu_status1;
+ unsigned int os_reg[8];
+ unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
+ unsigned int usbphy0_con[8];
+ unsigned int usbphy1_con[8];
+ unsigned int uoc_status0;
+ unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
+ unsigned int chip_tag;
+ unsigned int sdmmc_det_cnt;
+};
+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
+
+struct rk3128_pmu {
+ unsigned int wakeup_cfg;
+ unsigned int pwrdn_con;
+ unsigned int pwrdn_st;
+ unsigned int idle_req;
+ unsigned int idle_st;
+ unsigned int pwrmode_con;
+ unsigned int pwr_state;
+ unsigned int osc_cnt;
+ unsigned int core_pwrdwn_cnt;
+ unsigned int core_pwrup_cnt;
+ unsigned int sft_con;
+ unsigned int ddr_sref_st;
+ unsigned int int_con;
+ unsigned int int_st;
+ unsigned int sys_reg[4];
+};
+check_member(rk3128_pmu, int_st, 0x34);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A7_SHIFT = 14,
+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
+ GPIO0A7_GPIO = 0,
+ GPIO0A7_I2C3_SDA,
+
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_I2C3_SCL,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 1 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 1 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_I2S_SDI,
+ GPIO0B6_SPI_CSN0,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_I2S_SDO,
+ GPIO0B5_SPI_RXD,
+
+ GPIO0B4_SHIFT = 8,
+ GPIO0B4_MASK = 1 << GPIO0B4_SHIFT,
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_I2S_LRCKTX,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_I2S_LRCKRX,
+ GPIO0B3_SPI_TXD,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_I2S_SCLK,
+ GPIO0B1_SPI_CLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_I2S1_MCLK,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_PWM2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM1,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = 1 << GPIO0D1_SHIFT,
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_UART2_CTSN,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_UART2_RTSN,
+ GPIO0D0_PMIC_SLEEP,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_I2S_SDI,
+ GPIO1A5_SDMMC_DATA3,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 3 << GPIO1A4_SHIFT,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_I2S_SD0,
+ GPIO1A4_SDMMC_DATA2,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_I2S_LRCKTX,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_I2S_LRCKRX,
+ GPIO1A2_SDMMC_DATA1,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 3 << GPIO1A1_SHIFT,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_I2S_SCLK,
+ GPIO1A1_SDMMC_DATA0,
+ GPIO1A1_PMIC_SLEEP,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 3,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_I2S_MCLK,
+ GPIO1A0_SDMMC_CLKOUT,
+ GPIO1A0_XIN32K,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_MMC0_CMD,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 1 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_MMC_PWREN,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_SPI_RXD,
+ GPIO1B2_UART1_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_SPI_TXD,
+ GPIO1B1_UART1_SOUT,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3 << GPIO1B0_SHIFT,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_SPI_CLK,
+ GPIO1B0_UART1_CTSN
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_NAND_CS2,
+ GPIO1C6_EMMC_CMD,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_MMC0_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_MMC0_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_MMC0_D1,
+ GPIO1C3_UART2_RX,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_MMC0_D0,
+ GPIO1C2_UART2_TX,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_MMC0_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+ GPIO1D7_SPI_CSN1,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+ GPIO1D6_SPI_CSN0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+ GPIO1D5_SPI_TXD1,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+ GPIO1D4_SPI_RXD1,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+ GPIO1D3_SFC_SIO3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+ GPIO1D2_SFC_SIO2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+ GPIO1D1_SFC_SIO1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+ GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_NAND_DQS,
+ GPIO2A7_EMMC_CLKOUT,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_NAND_CS0,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_NAND_WP,
+ GPIO2A5_EMMC_PWREN,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+ GPIO2A3_SFC_CLK,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SFC_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SFC_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_EMMC_CLKOUT,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_LCDC0_D13,
+ GPIO2B7_EBC_SDCE5,
+ GPIO2B7_GMAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_LCDC0_D12,
+ GPIO2B6_EBC_SDCE4,
+ GPIO2B6_GMAC_CLK,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_LCDC0_D11,
+ GPIO2B5_EBC_SDCE3,
+ GPIO2B5_GMAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_LCDC0_D10,
+ GPIO2B4_EBC_SDCE2,
+ GPIO2B4_GMAC_MDIO,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_LCDC0_DEN,
+ GPIO2B3_EBC_GDCLK,
+ GPIO2B3_GMAC_RXCLK,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_LCDC0_VSYNC,
+ GPIO2B2_EBC_SDOE,
+ GPIO2B2_GMAC_CRS,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_LCDC0_HSYNC,
+ GPIO2B1_EBC_SDLE,
+ GPIO2B1_GMAC_TXCLK,
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_LCDC0_DCLK,
+ GPIO2B0_EBC_SDCLK,
+ GPIO2B0_GMAC_RXDV,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_LCDC0_D17,
+ GPIO2C3_EBC_GDPWR0,
+ GPIO2C3_GMAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_LCDC0_D16,
+ GPIO2C2_EBC_GDSP,
+ GPIO2C2_GMAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_LCDC0_D15,
+ GPIO2C1_EBC_GDOE,
+ GPIO2C1_GMAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_LCDC0_D14,
+ GPIO2C0_EBC_VCOM,
+ GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_LCDC0_D22,
+ GPIO2D6_GMAC_COL = 4,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_GMAC_MDC = 3,
+};
+
+/* GRF_GPIO2C_IOMUX2 */
+enum {
+ GPIO2C7_SHIFT = 12,
+ GPIO2C7_MASK = 7 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_GMAC_TXD3 = 4,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 7 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_GMAC_TXD2 = 4,
+
+ GPIO2C5_SHIFT = 4,
+ GPIO2C5_MASK = 7 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL = 3,
+ GPIO2C5_GMAC_RXD2,
+
+ GPIO2C4_SHIFT = 0,
+ GPIO2C4_MASK = 7 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA = 3,
+ GPIO2C4_GMAC_RXD2,
+};
+#endif
PMUGRF_GPIO1C3_SEL_SHIFT = 6,
PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
PMUGRF_PWM_2 = 1,
-
+ PMUGRF_GPIO1C4_SEL_SHIFT = 8,
+ PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
+ PMUGRF_I2C8PMU_SDA = 1,
+ PMUGRF_GPIO1C5_SEL_SHIFT = 10,
+ PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
+ PMUGRF_I2C8PMU_SCL = 1,
};
/* GRF_SOC_CON5 */
PERIPH_ID_I2C3,
PERIPH_ID_I2C4,
PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
u32 u_id_high;
};
-struct stm32_rcc_regs {
- u32 cr; /* RCC clock control */
- u32 pllcfgr; /* RCC PLL configuration */
- u32 cfgr; /* RCC clock configuration */
- u32 cir; /* RCC clock interrupt */
- u32 ahb1rstr; /* RCC AHB1 peripheral reset */
- u32 ahb2rstr; /* RCC AHB2 peripheral reset */
- u32 ahb3rstr; /* RCC AHB3 peripheral reset */
- u32 rsv0;
- u32 apb1rstr; /* RCC APB1 peripheral reset */
- u32 apb2rstr; /* RCC APB2 peripheral reset */
- u32 rsv1[2];
- u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
- u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
- u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
- u32 rsv2;
- u32 apb1enr; /* RCC APB1 peripheral clock enable */
- u32 apb2enr; /* RCC APB2 peripheral clock enable */
- u32 rsv3[2];
- u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
- u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
- u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
- u32 rsv4;
- u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
- u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
- u32 rsv5[2];
- u32 bdcr; /* RCC Backup domain control */
- u32 csr; /* RCC clock control & status */
- u32 rsv6[2];
- u32 sscgr; /* RCC spread spectrum clock generation */
- u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr;
- u32 dckcfgr;
-};
-
struct stm32_pwr_regs {
u32 cr;
u32 csr;
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_RCC_H
-#define _STM32_RCC_H
-
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/*
- * RCC AHB1ENR specific definitions
- */
-#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
-#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
-#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
-
-/*
- * RCC APB1ENR specific definitions
- */
-#define RCC_APB1ENR_TIM2EN BIT(0)
-#define RCC_APB1ENR_PWREN BIT(28)
-
-/*
- * RCC APB2ENR specific definitions
- */
-#define RCC_APB2ENR_SYSCFGEN BIT(14)
-
-#endif
#define STM32_BUS_MASK GENMASK(31, 16)
-struct stm32_rcc_regs {
- u32 cr; /* RCC clock control */
- u32 pllcfgr; /* RCC PLL configuration */
- u32 cfgr; /* RCC clock configuration */
- u32 cir; /* RCC clock interrupt */
- u32 ahb1rstr; /* RCC AHB1 peripheral reset */
- u32 ahb2rstr; /* RCC AHB2 peripheral reset */
- u32 ahb3rstr; /* RCC AHB3 peripheral reset */
- u32 rsv0;
- u32 apb1rstr; /* RCC APB1 peripheral reset */
- u32 apb2rstr; /* RCC APB2 peripheral reset */
- u32 rsv1[2];
- u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
- u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
- u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
- u32 rsv2;
- u32 apb1enr; /* RCC APB1 peripheral clock enable */
- u32 apb2enr; /* RCC APB2 peripheral clock enable */
- u32 rsv3[2];
- u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
- u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
- u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
- u32 rsv4;
- u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
- u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
- u32 rsv5[2];
- u32 bdcr; /* RCC Backup domain control */
- u32 csr; /* RCC clock control & status */
- u32 rsv6[2];
- u32 sscgr; /* RCC spread spectrum clock generation */
- u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr; /* PLLSAI configuration */
- u32 dckcfgr; /* dedicated clocks configuration register */
-};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-struct stm32_pwr_regs {
- u32 cr1; /* power control register 1 */
- u32 csr1; /* power control/status register 2 */
- u32 cr2; /* power control register 2 */
- u32 csr2; /* power control/status register 2 */
-};
-#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
void stm32_flash_latency_cfg(int latency);
--- /dev/null
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+ u32 cr2; /* power control register 2 */
+ u32 csr2; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
#ifndef _SUNXI_DRAM_SUN8I_H3_H
#define _SUNXI_DRAM_SUN8I_H3_H
+#include <linux/bitops.h>
+
struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
* the 32-bit wide access consists of. Also three control signals can be
* adjusted individually.
*/
-#define BITS_PER_BYTE 8
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS and DQSN */
#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
+#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
+#define ZYNQMP_TCM_SIZE 0x40000
+
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
#define ZYNQMP_CSU_VERSION_VELOCE 0x2
#define ZYNQMP_CSU_VERSION_QEMU 0x3
+#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
+
#define ZYNQMP_SILICON_VER_MASK 0xF000
#define ZYNQMP_SILICON_VER_SHIFT 12
enum {
IDCODE,
VERSION,
+ IDCODE2,
};
enum {
TCM_SPLIT,
};
-int zynq_slcr_get_mio_pin_status(const char *periph);
-
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
void psu_init(void);
#define PTE_TYPE_MASK (3 << 0)
#define PTE_TYPE_FAULT (0 << 0)
#define PTE_TYPE_TABLE (3 << 0)
+#define PTE_TYPE_PAGE (3 << 0)
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
void init_aips(void);
void init_src(void);
-void imx_set_wdog_powerdown(bool enable);
+void imx_wdog_disable_powerdown(void);
int board_mmc_get_env_dev(int devno);
/*
- * (C) Copyright 2016
- * Alexander Graf <agraf@suse.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
(C) Copyright 2016 Alexander Graf <agraf@suse.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SETJMP_H_
#define _SETJMP_H_ 1
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
struct jmp_buf_data {
- ulong target;
- ulong regs[5];
- int ret;
-};
-
-typedef struct jmp_buf_data jmp_buf[1];
-
-static inline int setjmp(jmp_buf jmp)
-{
- jmp->ret = 0;
-
-#ifdef CONFIG_ARM64
- asm volatile(
- "adr x1, jmp_target\n"
- "str x1, %0\n"
- "stp x26, x27, %1\n"
- "stp x28, x29, %2\n"
- "mov x1, sp\n"
- "str x1, %3\n"
- "jmp_target: "
- : "=m" (jmp->target), "=m" (jmp->regs[0]),
- "=m" (jmp->regs[2]), "=m" (jmp->regs[4])
- :
- : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
- "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
- "x16", "x17", "x18", "x19", "x20", "x21", "x22",
- "x23", "x24", "x25", /* x26, x27, x28, x29, sp */
- "x30", "cc", "memory");
-#else
- asm volatile(
-#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
- ".align 2\n"
- "adr r0, jmp_target\n"
- "add r0, r0, $1\n"
+#if defined(__aarch64__)
+ u64 regs[13];
#else
- "adr r0, jmp_target\n"
-#endif
- "mov r1, %0\n"
- "mov r2, sp\n"
- "stm r1!, {r0, r2, r4, r5, r6, r7}\n"
- ".align 2\n"
- "jmp_target: \n"
- :
- : "l" (&jmp->target)
- : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
- "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
- "cc", "memory");
-#endif
-
- return jmp->ret;
-}
-
-static inline __noreturn void longjmp(jmp_buf jmp, int ret)
-{
- jmp->ret = ret;
-
-#ifdef CONFIG_ARM64
- asm volatile(
- "ldr x0, %0\n"
- "ldr x1, %3\n"
- "mov sp, x1\n"
- "ldp x26, x27, %1\n"
- "ldp x28, x25, %2\n"
- "mov x29, x25\n"
- "br x0\n"
- :
- : "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]),
- "m" (jmp->regs[4])
- : "x0", "x1", "x25", "x26", "x27", "x28");
-#else
- asm volatile(
- "mov r1, %0\n"
- "ldm r1!, {r0, r2, r4, r5, r6, r7}\n"
- "mov sp, r2\n"
- "bx r0\n"
- :
- : "l" (&jmp->target)
- : "r1");
+ u32 regs[10]; /* r4-r9, sl, fp, sp, lr */
#endif
+};
- while (1) { }
-}
+typedef struct jmp_buf_data jmp_buf[1];
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
#endif /* _SETJMP_H_ */
#ifndef __ASSEMBLY__
-/**
- * save_boot_params() - Save boot parameters before starting reset sequence
- *
- * If you provide this function it will be called immediately U-Boot starts,
- * both for SPL and U-Boot proper.
- *
- * All registers are unchanged from U-Boot entry. No registers need be
- * preserved.
- *
- * This is not a normal C function. There is no stack. Return by branching to
- * save_boot_params_ret.
- *
- * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
- */
-
-/**
- * save_boot_params_ret() - Return from save_boot_params()
- *
- * If you provide save_boot_params(), then you should jump back to this
- * function when done. Try to preserve all registers.
- *
- * If your implementation of save_boot_params() is in C then it is acceptable
- * to simply call save_boot_params_ret() at the end of your function. Since
- * there is no link register set up, you cannot just exit the function. U-Boot
- * will return to the (initialised) value of lr, and likely crash/hang.
- *
- * If your implementation of save_boot_params() is in assembler then you
- * should use 'b' or 'bx' to return to save_boot_params_ret.
- */
-void save_boot_params_ret(void);
-
#ifdef CONFIG_ARMV7_LPAE
void switch_to_hypervisor_ret(void);
#endif
#endif /* CONFIG_ARM64 */
#ifndef __ASSEMBLY__
+/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
+/**
+ * save_boot_params_ret() - Return from save_boot_params()
+ *
+ * If you provide save_boot_params(), then you should jump back to this
+ * function when done. Try to preserve all registers.
+ *
+ * If your implementation of save_boot_params() is in C then it is acceptable
+ * to simply call save_boot_params_ret() at the end of your function. Since
+ * there is no link register set up, you cannot just exit the function. U-Boot
+ * will return to the (initialised) value of lr, and likely crash/hang.
+ *
+ * If your implementation of save_boot_params() is in assembler then you
+ * should use 'b' or 'bx' to return to save_boot_params_ret.
+ */
+void save_boot_params_ret(void);
+
/**
* Change the cache settings for a region.
*
#ifndef _DAVINCI_NAND_H_
#define _DAVINCI_NAND_H_
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/arch/hardware.h>
#define NAND_READ_START 0x00
obj-y += vectors.o crt0.o
endif
+ifdef CONFIG_ARM64
+obj-y += setjmp_aarch64.o
+else
+obj-y += setjmp.o
+endif
+
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARM64
obj-y += relocate_64.o
#endif /* !CONFIG_SPL_BUILD */
#if defined(CONFIG_SPL_BUILD)
bl spl_relocate_stack_gd /* may return NULL */
- /* set up gd here, outside any C code */
- mov x18, x0
+ /* set up gd here, outside any C code, if new stack is returned */
+ cmp x0, #0
+ csel x18, x0, x18, ne
/*
* Perform 'sp = (x0 != NULL) ? x0 : sp' while working
* around the constraint that conditional moves can not
.rel.data : { *(.rel.data) *(.rel.data*) }
_data_size = . - _etext;
- . = ALIGN(4096);
- .dynsym : { *(.dynsym) }
- . = ALIGN(4096);
- .dynstr : { *(.dynstr) }
- . = ALIGN(4096);
- .note.gnu.build-id : { *(.note.gnu.build-id) }
/DISCARD/ : {
*(.rel.reloc)
*(.eh_frame)
*(.note.GNU-stack)
+ *(.dynsym)
+ *(.dynstr)
+ *(.note.gnu.build-id)
+ *(.comment)
}
- .comment 0 : { *(.comment) }
}
#include <linux/compiler.h>
#include <efi_loader.h>
+DECLARE_GLOBAL_DATA_PTR;
int interrupt_init(void)
{
{
int i;
- printf("ELR: %lx\n", regs->elr);
- printf("LR: %lx\n", regs->regs[30]);
+ if (gd->flags & GD_FLG_RELOC) {
+ printf("ELR: %lx\n", regs->elr - gd->reloc_off);
+ printf("LR: %lx\n", regs->regs[30] - gd->reloc_off);
+ } else {
+ printf("ELR: %lx\n", regs->elr);
+ printf("LR: %lx\n", regs->regs[30]);
+ }
for (i = 0; i < 29; i += 2)
printf("x%-2d: %016lx x%-2d: %016lx\n",
i, regs->regs[i], i+1, regs->regs[i+1]);
--- /dev/null
+/*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+
+.pushsection .text.setjmp, "ax"
+ENTRY(setjmp)
+ /*
+ * A subroutine must preserve the contents of the registers
+ * r4-r8, r10, r11 (v1-v5, v7 and v8) and SP (and r9 in PCS
+ * variants that designate r9 as v6).
+ */
+ mov ip, sp
+ stm a1, {v1-v8, ip, lr}
+ mov a1, #0
+ bx lr
+ENDPROC(setjmp)
+.popsection
+
+.pushsection .text.longjmp, "ax"
+ENTRY(longjmp)
+ ldm a1, {v1-v8, ip, lr}
+ mov sp, ip
+ mov a1, a2
+ /* If we were passed a return value of zero, return one instead */
+ cmp a1, #0
+ bne 1f
+ mov a1, #1
+1:
+ bx lr
+ENDPROC(longjmp)
+.popsection
--- /dev/null
+/*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+.pushsection .text.setjmp, "ax"
+ENTRY(setjmp)
+ /* Preserve all callee-saved registers and the SP */
+ stp x19, x20, [x0,#0]
+ stp x21, x22, [x0,#16]
+ stp x23, x24, [x0,#32]
+ stp x25, x26, [x0,#48]
+ stp x27, x28, [x0,#64]
+ stp x29, x30, [x0,#80]
+ mov x2, sp
+ str x2, [x0, #96]
+ mov x0, #0
+ ret
+ENDPROC(setjmp)
+.popsection
+
+.pushsection .text.longjmp, "ax"
+ENTRY(longjmp)
+ ldp x19, x20, [x0,#0]
+ ldp x21, x22, [x0,#16]
+ ldp x23, x24, [x0,#32]
+ ldp x25, x26, [x0,#48]
+ ldp x27, x28, [x0,#64]
+ ldp x29, x30, [x0,#80]
+ ldr x2, [x0,#96]
+ mov sp, x2
+ /* Move the return value in place, but return 1 if passed 0. */
+ adds x0, xzr, x1
+ csinc x0, x0, xzr, ne
+ ret
+ENDPROC(longjmp)
+.popsection
#include <config.h>
+/*
+ * A macro to allow insertion of an ARM exception vector either
+ * for the non-boot0 case or by a boot0-header.
+ */
+ .macro ARM_VECTORS
+ b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+ .endm
+
+
/*
*************************************************************************
*
.section ".vectors", "ax"
+#if defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ *
+ * To allow a boot0 hook to insert a 'special' sequence after the vector
+ * table (e.g. for the socfpga), the presence of a boot0 hook supresses
+ * the below vector table and assumes that the vector table is filled in
+ * by the boot0 hook. The requirements for a boot0 hook thus are:
+ * (1) defines '_start:' as appropriate
+ * (2) inserts the vector table using ARM_VECTORS as appropriate
+ */
+#include <asm/arch/boot0.h>
+
+#else
+
/*
*************************************************************************
*
*/
_start:
-
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#endif
-
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
-/*
- * Various SoCs need something special and SoC-specific up front in
- * order to boot, allow them to set that in their boot0.h file and then
- * use it here.
- */
-#include <asm/arch/boot0.h>
-#endif
+ ARM_VECTORS
+#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
/*
*************************************************************************
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
-config TARGET_SAMA5D2_PTC
- bool "SAMA5D2 PTC board"
+config TARGET_SAMA5D2_PTC_EK
+ bool "SAMA5D2 PTC EK board"
select SAMA5D2
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D2_XPLAINED
select SAMA5D4
select SUPPORT_SPL
+config TARGET_WB45N
+ bool "Support Laird WB45N"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_WB50N
+ bool "Support Laird WB50N"
+ select BOARD_LATE_INIT
+ select CPU_V7
+ select SUPPORT_SPL
+ select BOARD_EARLY_INIT_F
+
endchoice
config SYS_SOC
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
-source "board/atmel/sama5d2_ptc/Kconfig"
+source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
+source "board/laird/wb45n/Kconfig"
+source "board/laird/wb50n/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_deglitch(x, y) \
+ at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_output(x, y) \
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_input(x, y) \
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D2 datasheet.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef SAMA5D2_SMC_H
+#define SAMA5D2_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700)
+#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704)
+#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708)
+#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c)
+#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710)
+#else
+struct at91_cs {
+ u32 setup; /* 0x600 SMC Setup Register */
+ u32 pulse; /* 0x604 SMC Pulse Register */
+ u32 cycle; /* 0x608 SMC Cycle Register */
+ u32 timings; /* 0x60C SMC Cycle Register */
+ u32 mode; /* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+ struct at91_cs cs[4];
+};
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x) (x & 0x7f)
+#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8)
+#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS 0x00000000
+#define AT91_SMC_MODE_RM_NRD 0x00000001
+#define AT91_SMC_MODE_WM_NCS 0x00000000
+#define AT91_SMC_MODE_WM_NWE 0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
+#define AT91_SMC_MODE_EXNW_READY 0x00000030
+
+#define AT91_SMC_MODE_BAT 0x00000100
+#define AT91_SMC_MODE_DBW_8 0x00000000
+#define AT91_SMC_MODE_DBW_16 0x00001000
+#define AT91_SMC_MODE_DBW_32 0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF 0x00100000
+#define AT91_SMC_MODE_PMEN 0x01000000
+#define AT91_SMC_MODE_PS_4 0x00000000
+#define AT91_SMC_MODE_PS_8 0x10000000
+#define AT91_SMC_MODE_PS_16 0x20000000
+#define AT91_SMC_MODE_PS_32 0x30000000
+
+#endif
This option creates a build targetting the ARM1176 ISA.
select BCM2835
+config TARGET_RPI_0_W
+ bool "Raspberry Pi Zero W"
+ help
+ Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
+ the RPi Zero model W.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi Zero W. To enable the UART console, the following
+ non-default option must be present in config.txt: enable_uart=1.
+ This is required for U-Boot to operate correctly, even if you only
+ care about the HDMI/usbkbd console.
+
+ This option creates a build targetting the ARMv7/AArch32 ISA.
+ select BCM2835
+
config TARGET_RPI_2
bool "Raspberry Pi 2"
help
}
}
-void imx_set_wdog_powerdown(bool enable)
+void imx_wdog_disable_powerdown(void)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
#endif
/* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
+ writew(0, &wdog1->wmcr);
+ writew(0, &wdog2->wmcr);
- if (is_mx6sx() || is_mx6ul() || is_mx7())
- writew(enable, &wdog3->wmcr);
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
+ writew(0, &wdog3->wmcr);
#ifdef CONFIG_MX7D
- writew(enable, &wdog4->wmcr);
+ writew(0, &wdog4->wmcr);
#endif
}
select BOARD_LATE_INIT
select MX53
+config TARGET_MX53PPD
+ bool "Support mx53ppd"
+ select MX53
+ help
+ Enable support for the GE Healthcare PPD.
+
config TARGET_MX53SMD
bool "Support mx53smd"
select MX53
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
+source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/technologic/ts4800/Kconfig"
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
config TARGET_CM_FX6
bool "CM-FX6"
select SUPPORT_SPL
+ select MX6QDL
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_DHCOMIMX6
bool "dh_imx6"
+ select MX6QDL
select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_GW_VENTANA
bool "gw_ventana"
+ select MX6QDL
select SUPPORT_SPL
imply CMD_SATA
imply CMD_SPL
config TARGET_MCCMON6
bool "mccmon6"
+ select MX6QDL
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
-config TARGET_MX6Q_ICORE
- bool "Support Engicam i.Core"
- select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
- select SPL_LOAD_FIT
-
-config TARGET_MX6Q_ICORE_RQS
- bool "Support Engicam i.Core RQS"
+config TARGET_MX6Q_ENGICAM
+ bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_PINCTRL if SPL
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
config TARGET_MX6SABRESD
bool "mx6sabresd"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
select DM_THERMAL
select SUPPORT_SPL
-config TARGET_MX6UL_GEAM
- bool "Support Engicam GEAM6UL"
- select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
-config TARGET_MX6UL_ISIOT
- bool "Support Engicam Is.IoT MX6UL"
+config TARGET_MX6UL_ENGICAM
+ bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_PINCTRL if SPL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_UDOO
bool "udoo"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_WANDBOARD
bool "wandboard"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
source "board/dhelectronics/dh_imx6/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/engicam/geam6ul/Kconfig"
-source "board/engicam/icorem6/Kconfig"
-source "board/engicam/icorem6_rqs/Kconfig"
-source "board/engicam/isiotmx6ul/Kconfig"
+source "board/engicam/imx6q/Kconfig"
+source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
if (is_mx6sl())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
- imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+ imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
if (is_mx6sx())
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
init_csu();
/* Disable PDE bit of WMCR register */
- imx_set_wdog_powerdown(false);
+ imx_wdog_disable_powerdown();
imx_enet_mdio_fixup();
*/
#ifdef CONFIG_IDE
#define __io
-#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#ifndef __KIRKWOOD_GPIO_H
#define __KIRKWOOD_GPIO_H
-/* got from kernel include/linux/bitops.h */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
-
#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
+config TARGET_LIBRETECH_CC
+ bool "LIBRETECH-CC"
+ help
+ LibreTech CC is a single board computer based on Meson GXL
+ with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
+ eMMC, IR receiver and a 40-pin GPIO header.
+
+config TARGET_KHADAS_VIM
+ bool "KHADAS-VIM"
+ help
+ Khadas VIM is a single board computer based on Meson GXL
+ with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
+ eMMC, IR receiver and a 40-pin GPIO header.
+
endif
config SYS_SOC
source "board/amlogic/p212/Kconfig"
+source "board/amlogic/libretech-cc/Kconfig"
+
+source "board/amlogic/khadas-vim/Kconfig"
+
endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o sm.o
+obj-y += board.o sm.o eth.o
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>
+#include <linux/sizes.h>
+#include <efi_loader.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-int dram_init_banksize(void)
+phys_size_t get_effective_memsize(void)
{
- /* Reserve first 16 MiB of RAM for firmware */
- gd->bd->bi_dram[0].start = 0x1000000;
- gd->bd->bi_dram[0].size = 0xf000000;
- /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
- gd->bd->bi_dram[1].start = 0x10000000;
- gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
- return 0;
+ /* Size is reported in MiB, convert it in bytes */
+ return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
+ >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
+{
+ int ret;
+
+ ret = fdt_add_mem_rsv(fdt, start, size);
+ if (ret)
+ printf("Could not reserve zone @ 0x%llx\n", start);
+
+ if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+ efi_add_memory_map(start,
+ ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+ }
+}
+
+void meson_gx_init_reserved_memory(void *fdt)
+{
+ u64 bl31_size, bl31_start;
+ u64 bl32_size, bl32_start;
+ u32 reg;
+
+ /*
+ * Get ARM Trusted Firmware reserved memory zones in :
+ * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+ * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+ * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+ */
+
+ reg = readl(GXBB_AO_SEC_GP_CFG3);
+
+ bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
+ >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+ bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+ bl31_start = readl(GXBB_AO_SEC_GP_CFG5);
+ bl32_start = readl(GXBB_AO_SEC_GP_CFG4);
+
+ /*
+ * Early Meson GXBB Firmware revisions did not provide the reserved
+ * memory zones in the registers, keep fixed memory zone handling.
+ */
+ if (IS_ENABLED(CONFIG_MESON_GXBB) &&
+ !reg && !bl31_start && !bl32_start) {
+ bl31_start = 0x10000000;
+ bl31_size = 0x200000;
+ }
+
+ /* Add first 16MiB reserved zone */
+ meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
+
+ /* Add BL31 reserved zone */
+ if (bl31_start && bl31_size)
+ meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
+
+ /* Add BL32 reserved zone */
+ if (bl32_start && bl32_size)
+ meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}
void reset_cpu(ulong addr)
--- /dev/null
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/eth.h>
+#include <phy.h>
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
+{
+ switch (mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+ GXBB_ETH_REG_0_TX_PHASE(1) |
+ GXBB_ETH_REG_0_TX_RATIO(4) |
+ GXBB_ETH_REG_0_PHY_CLK_EN |
+ GXBB_ETH_REG_0_CLK_EN);
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
+ GXBB_ETH_REG_0_CLK_EN);
+
+ /* Use GXL RMII Internal PHY */
+ if (IS_ENABLED(CONFIG_MESON_GXL) &&
+ (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
+ writel(0x10110181, GXBB_ETH_REG_2);
+ writel(0xe40908ff, GXBB_ETH_REG_3);
+ }
+
+ break;
+
+ default:
+ printf("Invalid Ethernet interface mode\n");
+ return;
+ }
+
+ /* Enable power and clock gate */
+ setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+ clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+}
#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
+#if defined(CONFIG_ARMADA_38X)
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS 0
+#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
+#else
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
+#endif
#if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */
#define BOOT_DEV_SEL_OFFS 4
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+#define BOOT_FROM_NAND 0x0A
#define BOOT_FROM_UART 0x28
#define BOOT_FROM_UART_ALT 0x3f
#define BOOT_FROM_SPI 0x32
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+#if defined(CONFIG_ARMADA_38X)
+ /*
+ * If the bootrom error register contains any else than zeros
+ * in the first 8 bits it's an error condition. And in that case
+ * try to boot from UART.
+ */
+ if (boot_device)
+#else
if (boot_device == BOOTROM_ERR_MODE_UART)
+#endif
return BOOT_DEVICE_UART;
/*
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
+#if defined(CONFIG_ARMADA_38X)
+ case BOOT_FROM_NAND:
+ return BOOT_DEVICE_NAND;
+#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
* SPL has no chance to receive this information. So we
* need to return to the BootROM to enable this xmodem
* UART download.
+ *
+ * If booting from NAND lets let the BootROM load the
+ * rest of the bootloader.
*/
- if (get_boot_device() == BOOT_DEVICE_UART)
- return_to_bootrom();
+ switch (get_boot_device()) {
+ case BOOT_DEVICE_UART:
+#if defined(CONFIG_ARMADA_38X)
+ case BOOT_DEVICE_NAND:
+#endif
+ return_to_bootrom();
+ }
}
#include <common.h>
#include <jffs2/load_kernel.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/omap_gpmc.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
mac[5] = (die_id[0] >> 8) & 0xff;
eth_env_set_enetaddr("usbethaddr", mac);
+
+ if (!env_get("ethaddr"))
+ eth_env_set_enetaddr("ethaddr", mac);
}
}
config R8A7796
bool "Renesas SoC R8A7796"
+config R8A77970
+ bool "Renesas SoC R8A77970"
+
+config R8A77995
+ bool "Renesas SoC R8A77995"
+
endchoice
choice
prompt "Renesus ARM64 SoCs board select"
optional
+config TARGET_DRAAK
+ bool "Draak board"
+ help
+ Support for Renesas R-Car Gen3 Draak platform
+
+config TARGET_EAGLE
+ bool "Eagle board"
+ help
+ Support for Renesas R-Car Gen3 Eagle platform
+
config TARGET_SALVATOR_X
bool "Salvator-X board"
help
config SYS_SOC
default "rmobile"
+source "board/renesas/draak/Kconfig"
+source "board/renesas/eagle/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
-obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
-obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o
+obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#ifndef CONFIG_RCAR_GEN3
int checkboard(void)
{
printf("Board: %s\n", sysinfo.board_string);
return 0;
}
+#endif
#include <common.h>
#include <asm/io.h>
-#define PRR 0xFF000044
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
+static u32 rmobile_get_prr(void);
+
u32 rmobile_get_cpu_type(void)
{
- return (readl(PRR) & 0x00007F00) >> 8;
+ return (rmobile_get_prr() & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
{
- const u32 prr = readl(PRR);
+ const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
u32 rmobile_get_cpu_rev_fraction(void)
{
- const u32 prr = readl(PRR);
+ const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
else
return prr & 0x0000000F;
}
+
+#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON)
+static u32 rmobile_get_prr(void)
+{
+ /*
+ * On RCar/RMobile Gen2 and older systems, the PRR is always
+ * located at the address below. On newer systems, the PRR
+ * may be located at different address, but that information
+ * is obtained from DT. This code will be removed when all
+ * of the older systems get converted to DM and OF control.
+ */
+ return readl(0xFF000044);
+}
+#else
+
+#include <dm.h>
+#include <syscon.h>
+#include <regmap.h>
+
+struct renesas_prr_priv {
+ fdt_addr_t regs;
+};
+
+enum {
+ PRR_RCAR,
+};
+
+static u32 rmobile_get_prr(void)
+{
+ struct regmap *map;
+
+ map = syscon_get_regmap_by_driver_data(PRR_RCAR);
+ if (!map) {
+ printf("PRR regmap failed!\n");
+ hang();
+ }
+
+ return readl(map->base);
+}
+
+static const struct udevice_id renesas_prr_ids[] = {
+ { .compatible = "renesas,prr", .data = PRR_RCAR },
+ { }
+};
+
+U_BOOT_DRIVER(renesas_prr) = {
+ .name = "renesas_prr",
+ .id = UCLASS_SYSCON,
+ .of_match = renesas_prr_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+#if defined(CONFIG_RCAR_GEN3)
+ rcar_gen3_memmap_fixup();
+#endif
dcache_enable();
}
#endif
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
- { 0x37, "SH73A0" },
- { 0x40, "R8A7740" },
- { 0x45, "R8A7790" },
- { 0x47, "R8A7791" },
- { 0x4A, "R8A7792" },
- { 0x4B, "R8A7793" },
- { 0x4C, "R8A7794" },
- { 0x4F, "R8A7795" },
- { 0x52, "R8A7796" },
+ { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
+ { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+ { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
+ { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
+ { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
+ { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
+ { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
+ { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
+ { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
+ { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+ { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
};
#elif defined(CONFIG_R8A7794)
#include "r8a7794-gpio.h"
void r8a7794_pinmux_init(void);
-#elif defined(CONFIG_R8A7795)
-#include "r8a7795-gpio.h"
-void r8a7795_pinmux_init(void);
-#elif defined(CONFIG_R8A7796)
-#include "r8a7796-gpio.h"
-void r8a7796_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */
+++ /dev/null
-/*
- * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h
- * This file defines pin function control of gpio.
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_R8A7795_GPIO_H__
-#define __ASM_R8A7795_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-
-/* V2(ES2.0) */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
- GPIO_GP_1_28,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
- GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
- GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
- GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
-
- GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
-
- /* GPSR0 */
- GPIO_GFN_D15,
- GPIO_GFN_D14,
- GPIO_GFN_D13,
- GPIO_GFN_D12,
- GPIO_GFN_D11,
- GPIO_GFN_D10,
- GPIO_GFN_D9,
- GPIO_GFN_D8,
- GPIO_GFN_D7,
- GPIO_GFN_D6,
- GPIO_GFN_D5,
- GPIO_GFN_D4,
- GPIO_GFN_D3,
- GPIO_GFN_D2,
- GPIO_GFN_D1,
- GPIO_GFN_D0,
-
- /* GPSR1 */
- GPIO_GFN_CLKOUT,
- GPIO_GFN_EX_WAIT0_A,
- GPIO_GFN_WE1x,
- GPIO_GFN_WE0x,
- GPIO_GFN_RD_WRx,
- GPIO_GFN_RDx,
- GPIO_GFN_BSx,
- GPIO_GFN_CS1x_A26,
- GPIO_GFN_CS0x,
- GPIO_GFN_A19,
- GPIO_GFN_A18,
- GPIO_GFN_A17,
- GPIO_GFN_A16,
- GPIO_GFN_A15,
- GPIO_GFN_A14,
- GPIO_GFN_A13,
- GPIO_GFN_A12,
- GPIO_GFN_A11,
- GPIO_GFN_A10,
- GPIO_GFN_A9,
- GPIO_GFN_A8,
- GPIO_GFN_A7,
- GPIO_GFN_A6,
- GPIO_GFN_A5,
- GPIO_GFN_A4,
- GPIO_GFN_A3,
- GPIO_GFN_A2,
- GPIO_GFN_A1,
- GPIO_GFN_A0,
-
- /* GPSR2 */
- GPIO_GFN_AVB_AVTP_CAPTURE_A,
- GPIO_GFN_AVB_AVTP_MATCH_A,
- GPIO_GFN_AVB_LINK,
- GPIO_GFN_AVB_PHY_INT,
- GPIO_GFN_AVB_MAGIC,
- GPIO_GFN_AVB_MDC,
- GPIO_GFN_PWM2_A,
- GPIO_GFN_PWM1_A,
- GPIO_GFN_PWM0,
- GPIO_GFN_IRQ5,
- GPIO_GFN_IRQ4,
- GPIO_GFN_IRQ3,
- GPIO_GFN_IRQ2,
- GPIO_GFN_IRQ1,
- GPIO_GFN_IRQ0,
-
- /* GPSR3 */
- GPIO_GFN_SD1_WP,
- GPIO_GFN_SD1_CD,
- GPIO_GFN_SD0_WP,
- GPIO_GFN_SD0_CD,
- GPIO_GFN_SD1_DAT3,
- GPIO_GFN_SD1_DAT2,
- GPIO_GFN_SD1_DAT1,
- GPIO_GFN_SD1_DAT0,
- GPIO_GFN_SD1_CMD,
- GPIO_GFN_SD1_CLK,
- GPIO_GFN_SD0_DAT3,
- GPIO_GFN_SD0_DAT2,
- GPIO_GFN_SD0_DAT1,
- GPIO_GFN_SD0_DAT0,
- GPIO_GFN_SD0_CMD,
- GPIO_GFN_SD0_CLK,
-
- /* GPSR4 */
- GPIO_GFN_SD3_DS,
- GPIO_GFN_SD3_DAT7,
- GPIO_GFN_SD3_DAT6,
- GPIO_GFN_SD3_DAT5,
- GPIO_GFN_SD3_DAT4,
- GPIO_GFN_SD3_DAT3,
- GPIO_GFN_SD3_DAT2,
- GPIO_GFN_SD3_DAT1,
- GPIO_GFN_SD3_DAT0,
- GPIO_GFN_SD3_CMD,
- GPIO_GFN_SD3_CLK,
- GPIO_GFN_SD2_DS,
- GPIO_GFN_SD2_DAT3,
- GPIO_GFN_SD2_DAT2,
- GPIO_GFN_SD2_DAT1,
- GPIO_GFN_SD2_DAT0,
- GPIO_GFN_SD2_CMD,
- GPIO_GFN_SD2_CLK,
-
- /* GPSR5 */
- GPIO_GFN_MLB_DAT,
- GPIO_GFN_MLB_SIG,
- GPIO_GFN_MLB_CLK,
- GPIO_FN_MSIOF0_RXD,
- GPIO_GFN_MSIOF0_SS2,
- GPIO_FN_MSIOF0_TXD,
- GPIO_GFN_MSIOF0_SS1,
- GPIO_GFN_MSIOF0_SYNC,
- GPIO_FN_MSIOF0_SCK,
- GPIO_GFN_HRTS0x,
- GPIO_GFN_HCTS0x,
- GPIO_GFN_HTX0,
- GPIO_GFN_HRX0,
- GPIO_GFN_HSCK0,
- GPIO_GFN_RX2_A,
- GPIO_GFN_TX2_A,
- GPIO_GFN_SCK2,
- GPIO_GFN_RTS1x_TANS,
- GPIO_GFN_CTS1x,
- GPIO_GFN_TX1_A,
- GPIO_GFN_RX1_A,
- GPIO_GFN_RTS0x_TANS,
- GPIO_GFN_CTS0x,
- GPIO_GFN_TX0,
- GPIO_GFN_RX0,
- GPIO_GFN_SCK0,
-
- /* GPSR6 */
- GPIO_GFN_USB3_OVC,
- GPIO_GFN_USB3_PWEN,
- GPIO_GFN_USB30_OVC,
- GPIO_GFN_USB30_PWEN,
- GPIO_GFN_USB1_OVC,
- GPIO_GFN_USB1_PWEN,
- GPIO_GFN_USB0_OVC,
- GPIO_GFN_USB0_PWEN,
- GPIO_GFN_AUDIO_CLKB_B,
- GPIO_GFN_AUDIO_CLKA_A,
- GPIO_GFN_SSI_SDATA9_A,
- GPIO_GFN_SSI_SDATA8,
- GPIO_GFN_SSI_SDATA7,
- GPIO_GFN_SSI_WS78,
- GPIO_GFN_SSI_SCK78,
- GPIO_GFN_SSI_SDATA6,
- GPIO_GFN_SSI_WS6,
- GPIO_GFN_SSI_SCK6,
- GPIO_FN_SSI_SDATA5,
- GPIO_FN_SSI_WS5,
- GPIO_FN_SSI_SCK5,
- GPIO_GFN_SSI_SDATA4,
- GPIO_GFN_SSI_WS4,
- GPIO_GFN_SSI_SCK4,
- GPIO_GFN_SSI_SDATA3,
- GPIO_GFN_SSI_WS34,
- GPIO_GFN_SSI_SCK34,
- GPIO_GFN_SSI_SDATA2_A,
- GPIO_GFN_SSI_SDATA1_A,
- GPIO_GFN_SSI_SDATA0,
- GPIO_GFN_SSI_WS01239,
- GPIO_GFN_SSI_SCK01239,
-
- /* GPSR7 */
- GPIO_FN_HDMI1_CEC,
- GPIO_FN_HDMI0_CEC,
- GPIO_FN_AVS2,
- GPIO_FN_AVS1,
-
- /* IPSR0 */
- GPIO_IFN_AVB_MDC,
- GPIO_FN_MSIOF2_SS2_C,
- GPIO_IFN_AVB_MAGIC,
- GPIO_FN_MSIOF2_SS1_C,
- GPIO_FN_SCK4_A,
- GPIO_IFN_AVB_PHY_INT,
- GPIO_FN_MSIOF2_SYNC_C,
- GPIO_FN_RX4_A,
- GPIO_IFN_AVB_LINK,
- GPIO_FN_MSIOF2_SCK_C,
- GPIO_FN_TX4_A,
- GPIO_IFN_AVB_AVTP_MATCH_A,
- GPIO_FN_MSIOF2_RXD_C,
- GPIO_FN_CTS4x_A,
- GPIO_FN_FSCLKST2x_A,
- GPIO_IFN_AVB_AVTP_CAPTURE_A,
- GPIO_FN_MSIOF2_TXD_C,
- GPIO_FN_RTS4x_TANS_A,
- GPIO_IFN_IRQ0,
- GPIO_FN_QPOLB,
- GPIO_FN_DU_CDE,
- GPIO_FN_VI4_DATA0_B,
- GPIO_FN_CAN0_TX_B,
- GPIO_FN_CANFD0_TX_B,
- GPIO_FN_MSIOF3_SS2_E,
- GPIO_IFN_IRQ1,
- GPIO_FN_QPOLA,
- GPIO_FN_DU_DISP,
- GPIO_FN_VI4_DATA1_B,
- GPIO_FN_CAN0_RX_B,
- GPIO_FN_CANFD0_RX_B,
- GPIO_FN_MSIOF3_SS1_E,
-
- /* IPSR1 */
- GPIO_IFN_IRQ2,
- GPIO_FN_QCPV_QDE,
- GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- GPIO_FN_VI4_DATA2_B,
- GPIO_FN_MSIOF3_SYNC_E,
- GPIO_FN_PWM3_B,
- GPIO_IFN_IRQ3,
- GPIO_FN_QSTVB_QVE,
- GPIO_FN_A25,
- GPIO_FN_DU_DOTCLKOUT1,
- GPIO_FN_VI4_DATA3_B,
- GPIO_FN_MSIOF3_SCK_E,
- GPIO_FN_PWM4_B,
- GPIO_IFN_IRQ4,
- GPIO_FN_QSTH_QHS,
- GPIO_FN_A24,
- GPIO_FN_DU_EXHSYNC_DU_HSYNC,
- GPIO_FN_VI4_DATA4_B,
- GPIO_FN_MSIOF3_RXD_E,
- GPIO_FN_PWM5_B,
- GPIO_IFN_IRQ5,
- GPIO_FN_QSTB_QHE,
- GPIO_FN_A23,
- GPIO_FN_DU_EXVSYNC_DU_VSYNC,
- GPIO_FN_VI4_DATA5_B,
- GPIO_FN_FSCLKST2x_B,
- GPIO_FN_MSIOF3_TXD_E,
- GPIO_FN_PWM6_B,
- GPIO_IFN_PWM0,
- GPIO_FN_AVB_AVTP_PPS,
- GPIO_FN_VI4_DATA6_B,
- GPIO_FN_IECLK_B,
- GPIO_IFN_PWM1_A,
- GPIO_FN_HRX3_D,
- GPIO_FN_VI4_DATA7_B,
- GPIO_FN_IERX_B,
- GPIO_IFN_PWM2_A,
- GPIO_FN_HTX3_D,
- GPIO_FN_IETX_B,
- GPIO_IFN_A0,
- GPIO_FN_LCDOUT16,
- GPIO_FN_MSIOF3_SYNC_B,
- GPIO_FN_VI4_DATA8,
- GPIO_FN_DU_DB0,
- GPIO_FN_PWM3_A,
-
- /* IPSR2 */
- GPIO_IFN_A1,
- GPIO_FN_LCDOUT17,
- GPIO_FN_MSIOF3_TXD_B,
- GPIO_FN_VI4_DATA9,
- GPIO_FN_DU_DB1,
- GPIO_FN_PWM4_A,
- GPIO_IFN_A2,
- GPIO_FN_LCDOUT18,
- GPIO_FN_MSIOF3_SCK_B,
- GPIO_FN_VI4_DATA10,
- GPIO_FN_DU_DB2,
- GPIO_FN_PWM5_A,
- GPIO_IFN_A3,
- GPIO_FN_LCDOUT19,
- GPIO_FN_MSIOF3_RXD_B,
- GPIO_FN_VI4_DATA11,
- GPIO_FN_DU_DB3,
- GPIO_FN_PWM6_A,
- GPIO_IFN_A4,
- GPIO_FN_LCDOUT20,
- GPIO_FN_MSIOF3_SS1_B,
- GPIO_FN_VI4_DATA12,
- GPIO_FN_VI5_DATA12,
- GPIO_FN_DU_DB4,
- GPIO_IFN_A5,
- GPIO_FN_LCDOUT21,
- GPIO_FN_MSIOF3_SS2_B,
- GPIO_FN_SCK4_B,
- GPIO_FN_VI4_DATA13,
- GPIO_FN_VI5_DATA13,
- GPIO_FN_DU_DB5,
- GPIO_IFN_A6,
- GPIO_FN_LCDOUT22,
- GPIO_FN_MSIOF2_SS1_A,
- GPIO_FN_RX4_B,
- GPIO_FN_VI4_DATA14,
- GPIO_FN_VI5_DATA14,
- GPIO_FN_DU_DB6,
- GPIO_IFN_A7,
- GPIO_FN_LCDOUT23,
- GPIO_FN_MSIOF2_SS2_A,
- GPIO_FN_TX4_B,
- GPIO_FN_VI4_DATA15,
- GPIO_FN_V15_DATA15,
- GPIO_FN_DU_DB7,
- GPIO_IFN_A8,
- GPIO_FN_RX3_B,
- GPIO_FN_MSIOF2_SYNC_A,
- GPIO_FN_HRX4_B,
- GPIO_FN_SDA6_A,
- GPIO_FN_AVB_AVTP_MATCH_B,
- GPIO_FN_PWM1_B,
-
- /* IPSR3 */
- GPIO_IFN_A9,
- GPIO_FN_MSIOF2_SCK_A,
- GPIO_FN_CTS4x_B,
- GPIO_FN_VI5_VSYNCx,
- GPIO_IFN_A10,
- GPIO_FN_MSIOF2_RXD_A,
- GPIO_FN_RTS4n_TANS_B,
- GPIO_FN_VI5_HSYNCx,
- GPIO_IFN_A11,
- GPIO_FN_TX3_B,
- GPIO_FN_MSIOF2_TXD_A,
- GPIO_FN_HTX4_B,
- GPIO_FN_HSCK4,
- GPIO_FN_VI5_FIELD,
- GPIO_FN_SCL6_A,
- GPIO_FN_AVB_AVTP_CAPTURE_B,
- GPIO_FN_PWM2_B,
- GPIO_IFN_A12,
- GPIO_FN_LCDOUT12,
- GPIO_FN_MSIOF3_SCK_C,
- GPIO_FN_HRX4_A,
- GPIO_FN_VI5_DATA8,
- GPIO_FN_DU_DG4,
- GPIO_IFN_A13,
- GPIO_FN_LCDOUT13,
- GPIO_FN_MSIOF3_SYNC_C,
- GPIO_FN_HTX4_A,
- GPIO_FN_VI5_DATA9,
- GPIO_FN_DU_DG5,
- GPIO_IFN_A14,
- GPIO_FN_LCDOUT14,
- GPIO_FN_MSIOF3_RXD_C,
- GPIO_FN_HCTS4x,
- GPIO_FN_VI5_DATA10,
- GPIO_FN_DU_DG6,
- GPIO_IFN_A15,
- GPIO_FN_LCDOUT15,
- GPIO_FN_MSIOF3_TXD_C,
- GPIO_FN_HRTS4x,
- GPIO_FN_VI5_DATA11,
- GPIO_FN_DU_DG7,
- GPIO_IFN_A16,
- GPIO_FN_LCDOUT8,
- GPIO_FN_VI4_FIELD,
- GPIO_FN_DU_DG0,
-
- /* IPSR4 */
- GPIO_IFN_A17,
- GPIO_FN_LCDOUT9,
- GPIO_FN_VI4_VSYNCx,
- GPIO_FN_DU_DG1,
- GPIO_IFN_A18,
- GPIO_FN_LCDOUT10,
- GPIO_FN_VI4_HSYNCx,
- GPIO_FN_DU_DG2,
- GPIO_IFN_A19,
- GPIO_FN_LCDOUT11,
- GPIO_FN_VI4_CLKENB,
- GPIO_FN_DU_DG3,
- GPIO_IFN_CS0x,
- GPIO_FN_VI5_CLKENB,
- GPIO_IFN_CS1x_A26,
- GPIO_FN_VI5_CLK,
- GPIO_FN_EX_WAIT0_B,
- GPIO_IFN_BSx,
- GPIO_FN_QSTVA_QVS,
- GPIO_FN_MSIOF3_SCK_D,
- GPIO_FN_SCK3,
- GPIO_FN_HSCK3,
- GPIO_FN_CAN1_TX,
- GPIO_FN_CANFD1_TX,
- GPIO_FN_IETX_A,
- GPIO_IFN_RDx,
- GPIO_FN_MSIOF3_SYNC_D,
- GPIO_FN_RX3_A,
- GPIO_FN_HRX3_A,
- GPIO_FN_CAN0_TX_A,
- GPIO_FN_CANFD0_TX_A,
- GPIO_IFN_RD_WRx,
- GPIO_FN_MSIOF3_RXD_D,
- GPIO_FN_TX3_A,
- GPIO_FN_HTX3_A,
- GPIO_FN_CAN0_RX_A,
- GPIO_FN_CANFD0_RX_A,
-
- /* IPSR5 */
- GPIO_IFN_WE0x,
- GPIO_FN_MSIIOF3_TXD_D,
- GPIO_FN_CTS3x,
- GPIO_FN_HCTS3x,
- GPIO_FN_SCL6_B,
- GPIO_FN_CAN_CLK,
- GPIO_FN_IECLK_A,
- GPIO_IFN_WE1x,
- GPIO_FN_MSIOF3_SS1_D,
- GPIO_FN_RTS3x_TANS,
- GPIO_FN_HRTS3x,
- GPIO_FN_SDA6_B,
- GPIO_FN_CAN1_RX,
- GPIO_FN_CANFD1_RX,
- GPIO_FN_IERX_A,
- GPIO_IFN_EX_WAIT0_A,
- GPIO_FN_QCLK,
- GPIO_FN_VI4_CLK,
- GPIO_FN_DU_DOTCLKOUT0,
- GPIO_IFN_D0,
- GPIO_FN_MSIOF2_SS1_B,
- GPIO_FN_MSIOF3_SCK_A,
- GPIO_FN_VI4_DATA16,
- GPIO_FN_VI5_DATA0,
- GPIO_IFN_D1,
- GPIO_FN_MSIOF2_SS2_B,
- GPIO_FN_MSIOF3_SYNC_A,
- GPIO_FN_VI4_DATA17,
- GPIO_FN_VI5_DATA1,
- GPIO_IFN_D2,
- GPIO_FN_MSIOF3_RXD_A,
- GPIO_FN_VI4_DATA18,
- GPIO_FN_VI5_DATA2,
- GPIO_IFN_D3,
- GPIO_FN_MSIOF3_TXD_A,
- GPIO_FN_VI4_DATA19,
- GPIO_FN_VI5_DATA3,
- GPIO_IFN_D4,
- GPIO_FN_MSIOF2_SCK_B,
- GPIO_FN_VI4_DATA20,
- GPIO_FN_VI5_DATA4,
-
- /* IPSR6 */
- GPIO_IFN_D5,
- GPIO_FN_MSIOF2_SYNC_B,
- GPIO_FN_VI4_DATA21,
- GPIO_FN_VI5_DATA5,
- GPIO_IFN_D6,
- GPIO_FN_MSIOF2_RXD_B,
- GPIO_FN_VI4_DATA22,
- GPIO_FN_VI5_DATA6,
- GPIO_IFN_D7,
- GPIO_FN_MSIOF2_TXD_B,
- GPIO_FN_VI4_DATA23,
- GPIO_FN_VI5_DATA7,
- GPIO_IFN_D8,
- GPIO_FN_LCDOUT0,
- GPIO_FN_MSIOF2_SCK_D,
- GPIO_FN_SCK4_C,
- GPIO_FN_VI4_DATA0_A,
- GPIO_FN_DU_DR0,
- GPIO_IFN_D9,
- GPIO_FN_LCDOUT1,
- GPIO_FN_MSIOF2_SYNC_D,
- GPIO_FN_VI4_DATA1_A,
- GPIO_FN_DU_DR1,
- GPIO_IFN_D10,
- GPIO_FN_LCDOUT2,
- GPIO_FN_MSIOF2_RXD_D,
- GPIO_FN_HRX3_B,
- GPIO_FN_VI4_DATA2_A,
- GPIO_FN_CTS4x_C,
- GPIO_FN_DU_DR2,
- GPIO_IFN_D11,
- GPIO_FN_LCDOUT3,
- GPIO_FN_MSIOF2_TXD_D,
- GPIO_FN_HTX3_B,
- GPIO_FN_VI4_DATA3_A,
- GPIO_FN_RTS4x_TANS_C,
- GPIO_FN_DU_DR3,
- GPIO_IFN_D12,
- GPIO_FN_LCDOUT4,
- GPIO_FN_MSIOF2_SS1_D,
- GPIO_FN_RX4_C,
- GPIO_FN_VI4_DATA4_A,
- GPIO_FN_DU_DR4,
-
- /* IPSR7 */
- GPIO_IFN_D13,
- GPIO_FN_LCDOUT5,
- GPIO_FN_MSIOF2_SS2_D,
- GPIO_FN_TX4_C,
- GPIO_FN_VI4_DATA5_A,
- GPIO_FN_DU_DR5,
- GPIO_IFN_D14,
- GPIO_FN_LCDOUT6,
- GPIO_FN_MSIOF3_SS1_A,
- GPIO_FN_HRX3_C,
- GPIO_FN_VI4_DATA6_A,
- GPIO_FN_DU_DR6,
- GPIO_FN_SCL6_C,
- GPIO_IFN_D15,
- GPIO_FN_LCDOUT7,
- GPIO_FN_MSIOF3_SS2_A,
- GPIO_FN_HTX3_C,
- GPIO_FN_VI4_DATA7_A,
- GPIO_FN_DU_DR7,
- GPIO_FN_SDA6_C,
- GPIO_FN_FSCLKST,
- GPIO_IFN_SD0_CLK,
- GPIO_FN_MSIOF1_SCK_E,
- GPIO_FN_STP_OPWM_0_B,
- GPIO_IFN_SD0_CMD,
- GPIO_FN_MSIOF1_SYNC_E,
- GPIO_FN_STP_IVCXO27_0_B,
- GPIO_IFN_SD0_DAT0,
- GPIO_FN_MSIOF1_RXD_E,
- GPIO_FN_TS_SCK0_B,
- GPIO_FN_STP_ISCLK_0_B,
- GPIO_IFN_SD0_DAT1,
- GPIO_FN_MSIOF1_TXD_E,
- GPIO_FN_TS_SPSYNC0_B,
- GPIO_FN_STP_ISSYNC_0_B,
-
- /* IPSR8 */
- GPIO_IFN_SD0_DAT2,
- GPIO_FN_MSIOF1_SS1_E,
- GPIO_FN_TS_SDAT0_B,
- GPIO_FN_STP_ISD_0_B,
- GPIO_IFN_SD0_DAT3,
- GPIO_FN_MSIOF1_SS2_E,
- GPIO_FN_TS_SDEN0_B,
- GPIO_FN_STP_ISEN_0_B,
- GPIO_IFN_SD1_CLK,
- GPIO_FN_MSIOF1_SCK_G,
- GPIO_FN_SIM0_CLK_A,
- GPIO_IFN_SD1_CMD,
- GPIO_FN_MSIOF1_SYNC_G,
- GPIO_FN_NFCEx_B,
- GPIO_FN_SIM0_D_A,
- GPIO_FN_STP_IVCXO27_1_B,
- GPIO_IFN_SD1_DAT0,
- GPIO_FN_SD2_DAT4,
- GPIO_FN_MSIOF1_RXD_G,
- GPIO_FN_NFWPx_B,
- GPIO_FN_TS_SCK1_B,
- GPIO_FN_STP_ISCLK_1_B,
- GPIO_IFN_SD1_DAT1,
- GPIO_FN_SD2_DAT5,
- GPIO_FN_MSIOF1_TXD_G,
- GPIO_FN_NFDATA14_B,
- GPIO_FN_TS_SPSYNC1_B,
- GPIO_FN_STP_ISSYNC_1_B,
- GPIO_IFN_SD1_DAT2,
- GPIO_FN_SD2_DAT6,
- GPIO_FN_MSIOF1_SS1_G,
- GPIO_FN_NFDATA15_B,
- GPIO_FN_TS_SDAT1_B,
- GPIO_FN_STP_IOD_1_B,
- GPIO_IFN_SD1_DAT3,
- GPIO_FN_SD2_DAT7,
- GPIO_FN_MSIOF1_SS2_G,
- GPIO_FN_NFRBx_B,
- GPIO_FN_TS_SDEN1_B,
- GPIO_FN_STP_ISEN_1_B,
-
- /* IPSR9 */
- GPIO_IFN_SD2_CLK,
- GPIO_FN_NFDATA8,
- GPIO_IFN_SD2_CMD,
- GPIO_FN_NFDATA9,
- GPIO_IFN_SD2_DAT0,
- GPIO_FN_NFDATA10,
- GPIO_IFN_SD2_DAT1,
- GPIO_FN_NFDATA11,
- GPIO_IFN_SD2_DAT2,
- GPIO_FN_NFDATA12,
- GPIO_IFN_SD2_DAT3,
- GPIO_FN_NFDATA13,
- GPIO_IFN_SD2_DS,
- GPIO_FN_NFALE,
- GPIO_FN_SATA_DEVSLP_B,
- GPIO_IFN_SD3_CLK,
- GPIO_FN_NFWEx,
-
- /* IPSR10 */
- GPIO_IFN_SD3_CMD,
- GPIO_FN_NFREx,
- GPIO_IFN_SD3_DAT0,
- GPIO_FN_NFDATA0,
- GPIO_IFN_SD3_DAT1,
- GPIO_FN_NFDATA1,
- GPIO_IFN_SD3_DAT2,
- GPIO_FN_NFDATA2,
- GPIO_IFN_SD3_DAT3,
- GPIO_FN_NFDATA3,
- GPIO_IFN_SD3_DAT4,
- GPIO_FN_SD2_CD_A,
- GPIO_FN_NFDATA4,
- GPIO_IFN_SD3_DAT5,
- GPIO_FN_SD2_WP_A,
- GPIO_FN_NFDATA5,
- GPIO_IFN_SD3_DAT6,
- GPIO_FN_SD3_CD,
- GPIO_FN_NFDATA6,
-
- /* IPSR11 */
- GPIO_IFN_SD3_DAT7,
- GPIO_FN_SD3_WP,
- GPIO_FN_NFDATA7,
- GPIO_IFN_SD3_DS,
- GPIO_FN_NFCLE,
- GPIO_IFN_SD0_CD,
- GPIO_FN_NFDATA14_A,
- GPIO_FN_SCL2_B,
- GPIO_FN_SIM0_RST_A,
- GPIO_IFN_SD0_WP,
- GPIO_FN_NFDATA15_A,
- GPIO_FN_SDA2_B,
- GPIO_IFN_SD1_CD,
- GPIO_FN_NFRBx_A,
- GPIO_FN_SIM0_CLK_B,
- GPIO_IFN_SD1_WP,
- GPIO_FN_NFCEx_A,
- GPIO_FN_SIM0_D_B,
- GPIO_IFN_SCK0,
- GPIO_FN_HSCK1_B,
- GPIO_FN_MSIOF1_SS2_B,
- GPIO_FN_AUDIO_CLKC_B,
- GPIO_FN_SDA2_A,
- GPIO_FN_SIM0_RST_B,
- GPIO_FN_STP_OPWM_0_C,
- GPIO_FN_RIF0_CLK_B,
- GPIO_FN_ADICHS2,
- GPIO_FN_SCK5_B,
- GPIO_IFN_RX0,
- GPIO_FN_HRX1_B,
- GPIO_FN_TS_SCK0_C,
- GPIO_FN_STP_ISCLK_0_C,
- GPIO_FN_RIF0_D0_B,
-
- /* IPSR12 */
- GPIO_IFN_TX0,
- GPIO_FN_HTX1_B,
- GPIO_FN_TS_SPSYNC0_C,
- GPIO_FN_STP_ISSYNC_0_C,
- GPIO_FN_RIF0_D1_B,
- GPIO_IFN_CTS0x,
- GPIO_FN_HCTS1x_B,
- GPIO_FN_MSIOF1_SYNC_B,
- GPIO_FN_TS_SPSYNC1_C,
- GPIO_FN_STP_ISSYNC_1_C,
- GPIO_FN_RIF1_SYNC_B,
- GPIO_FN_AUDIO_CLKOUT_C,
- GPIO_FN_ADICS_SAMP,
- GPIO_IFN_RTS0x_TANS,
- GPIO_FN_HRTS1x_B,
- GPIO_FN_MSIOF1_SS1_B,
- GPIO_FN_AUDIO_CLKA_B,
- GPIO_FN_SCL2_A,
- GPIO_FN_STP_IVCXO27_1_C,
- GPIO_FN_RIF0_SYNC_B,
- GPIO_FN_ADICHS1,
- GPIO_IFN_RX1_A,
- GPIO_FN_HRX1_A,
- GPIO_FN_TS_SDAT0_C,
- GPIO_FN_STP_ISD_0_C,
- GPIO_FN_RIF1_CLK_C,
- GPIO_IFN_TX1_A,
- GPIO_FN_HTX1_A,
- GPIO_FN_TS_SDEN0_C,
- GPIO_FN_STP_ISEN_0_C,
- GPIO_FN_RIF1_D0_C,
- GPIO_IFN_CTS1x,
- GPIO_FN_HCTS1x_A,
- GPIO_FN_MSIOF1_RXD_B,
- GPIO_FN_TS_SDEN1_C,
- GPIO_FN_STP_ISEN_1_C,
- GPIO_FN_RIF1_D0_B,
- GPIO_FN_ADIDATA,
- GPIO_IFN_RTS1x_TANS,
- GPIO_FN_HRTS1x_A,
- GPIO_FN_MSIOF1_TXD_B,
- GPIO_FN_TS_SDAT1_C,
- GPIO_FN_STP_ISD_1_C,
- GPIO_FN_RIF1_D1_B,
- GPIO_FN_ADICHS0,
- GPIO_IFN_SCK2,
- GPIO_FN_SCIF_CLK_B,
- GPIO_FN_MSIOF1_SCK_B,
- GPIO_FN_TS_SCK1_C,
- GPIO_FN_STP_ISCLK_1_C,
- GPIO_FN_RIF1_CLK_B,
- GPIO_FN_ADICLK,
-
- /* IPSR13 */
- GPIO_IFN_TX2_A,
- GPIO_FN_SD2_CD_B,
- GPIO_FN_SCL1_A,
- GPIO_FN_FMCLK_A,
- GPIO_FN_RIF1_D1_C,
- GPIO_FN_FSO_CFE_0x,
- GPIO_IFN_RX2_A,
- GPIO_FN_SD2_WP_B,
- GPIO_FN_SDA1_A,
- GPIO_FN_FMIN_A,
- GPIO_FN_RIF1_SYNC_C,
- GPIO_FN_FSO_CFE_1x,
- GPIO_IFN_HSCK0,
- GPIO_FN_MSIOF1_SCK_D,
- GPIO_FN_AUDIO_CLKB_A,
- GPIO_FN_SSI_SDATA1_B,
- GPIO_FN_TS_SCK0_D,
- GPIO_FN_STP_ISCLK_0_D,
- GPIO_FN_RIF0_CLK_C,
- GPIO_FN_RX5_B,
- GPIO_IFN_HRX0,
- GPIO_FN_MSIOF1_RXD_D,
- GPIO_FN_SSI_SDATA2_B,
- GPIO_FN_TS_SDEN0_D,
- GPIO_FN_STP_ISEN_0_D,
- GPIO_FN_RIF0_D0_C,
- GPIO_IFN_HTX0,
- GPIO_FN_MSIOF1_TXD_D,
- GPIO_FN_SSI_SDATA9_B,
- GPIO_FN_TS_SDAT0_D,
- GPIO_FN_STP_ISD_0_D,
- GPIO_FN_RIF0_D1_C,
- GPIO_IFN_HCTS0x,
- GPIO_FN_RX2_B,
- GPIO_FN_MSIOF1_SYNC_D,
- GPIO_FN_SSI_SCK9_A,
- GPIO_FN_TS_SPSYNC0_D,
- GPIO_FN_STP_ISSYNC_0_D,
- GPIO_FN_RIF0_SYNC_C,
- GPIO_FN_AUDIO_CLKOUT1_A,
- GPIO_IFN_HRTS0x,
- GPIO_FN_TX2_B,
- GPIO_FN_MSIOF1_SS1_D,
- GPIO_FN_SSI_WS9_A,
- GPIO_FN_STP_IVCXO27_0_D,
- GPIO_FN_BPFCLK_A,
- GPIO_FN_AUDIO_CLKOUT2_A,
- GPIO_IFN_MSIOF0_SYNC,
- GPIO_FN_AUDIO_CLKOUT_A,
- GPIO_FN_TX5_B,
- GPIO_FN_BPFCLK_D,
-
- /* IPSR14 */
- GPIO_IFN_MSIOF0_SS1,
- GPIO_FN_RX5_A,
- GPIO_FN_NFWPx_A,
- GPIO_FN_AUDIO_CLKA_C,
- GPIO_FN_SSI_SCK2_A,
- GPIO_FN_STP_IVCXO27_0_C,
- GPIO_FN_AUDIO_CLKOUT3_A,
- GPIO_FN_TCLK1_B,
- GPIO_IFN_MSIOF0_SS2,
- GPIO_FN_TX5_A,
- GPIO_FN_MSIOF1_SS2_D,
- GPIO_FN_AUDIO_CLKC_A,
- GPIO_FN_SSI_WS2_A,
- GPIO_FN_STP_OPWM_0_D,
- GPIO_FN_AUDIO_CLKOUT_D,
- GPIO_FN_SPEEDIN_B,
- GPIO_IFN_MLB_CLK,
- GPIO_FN_MSIOF1_SCK_F,
- GPIO_FN_SCL1_B,
- GPIO_IFN_MLB_SIG,
- GPIO_FN_RX1_B,
- GPIO_FN_MSIOF1_SYNC_F,
- GPIO_FN_SDA1_B,
- GPIO_IFN_MLB_DAT,
- GPIO_FN_TX1_B,
- GPIO_FN_MSIOF1_RXD_F,
- GPIO_IFN_SSI_SCK01239,
- GPIO_FN_MSIOF1_TXD_F,
- GPIO_FN_MOUT0,
- GPIO_IFN_SSI_WS01239,
- GPIO_FN_MSIOF1_SS1_F,
- GPIO_FN_MOUT1,
- GPIO_IFN_SSI_SDATA0,
- GPIO_FN_MSIOF1_SS2_F,
- GPIO_FN_MOUT2,
-
- /* IPSR15 */
- GPIO_IFN_SSI_SDATA1_A,
- GPIO_FN_MOUT5,
- GPIO_IFN_SSI_SDATA2_A,
- GPIO_FN_SSI_SCK1_B,
- GPIO_FN_MOUT6,
- GPIO_IFN_SSI_SCK34,
- GPIO_FN_MSIOF1_SS1_A,
- GPIO_FN_STP_OPWM_0_A,
- GPIO_IFN_SSI_WS34,
- GPIO_FN_HCTS2x_A,
- GPIO_FN_MSIOF1_SS2_A,
- GPIO_FN_STP_IVCXO27_0_A,
- GPIO_IFN_SSI_SDATA3,
- GPIO_FN_HRTS2x_A,
- GPIO_FN_MSIOF1_TXD_A,
- GPIO_FN_TS_SCK0_A,
- GPIO_FN_STP_ISCLK_0_A,
- GPIO_FN_RIF0_D1_A,
- GPIO_FN_RIF2_D0_A,
- GPIO_IFN_SSI_SCK4,
- GPIO_FN_HRX2_A,
- GPIO_FN_MSIOF1_SCK_A,
- GPIO_FN_TS_SDAT0_A,
- GPIO_FN_STP_ISD_0_A,
- GPIO_FN_RIF0_CLK_A,
- GPIO_FN_RIF2_CLK_A,
- GPIO_IFN_SSI_WS4,
- GPIO_FN_HTX2_A,
- GPIO_FN_MSIOF1_SYNC_A,
- GPIO_FN_TS_SDEN0_A,
- GPIO_FN_STP_ISEN_0_A,
- GPIO_FN_RIF0_SYNC_A,
- GPIO_FN_RIF2_SYNC_A,
- GPIO_IFN_SSI_SDATA4,
- GPIO_FN_HSCK2_A,
- GPIO_FN_MSIOF1_RXD_A,
- GPIO_FN_TS_SPSYNC0_A,
- GPIO_FN_STP_ISSYNC_0_A,
- GPIO_FN_RIF0_D0_A,
- GPIO_FN_RIF2_D1_A,
-
- /* IPSR16 */
- GPIO_IFN_SSI_SCK6,
- GPIO_FN_SIM0_RST_D,
- GPIO_IFN_SSI_WS6,
- GPIO_FN_SIM0_D_D,
- GPIO_IFN_SSI_SDATA6,
- GPIO_FN_SIM0_CLK_D,
- GPIO_FN_SATA_DEVSLP_A,
- GPIO_IFN_SSI_SCK78,
- GPIO_FN_HRX2_B,
- GPIO_FN_MSIOF1_SCK_C,
- GPIO_FN_TS_SCK1_A,
- GPIO_FN_STP_ISCLK_1_A,
- GPIO_FN_RIF1_CLK_A,
- GPIO_FN_RIF3_CLK_A,
- GPIO_IFN_SSI_WS78,
- GPIO_FN_HTX2_B,
- GPIO_FN_MSIOF1_SYNC_C,
- GPIO_FN_TS_SDAT1_A,
- GPIO_FN_STP_ISD_1_A,
- GPIO_FN_RIF1_SYNC_A,
- GPIO_FN_RIF3_SYNC_A,
- GPIO_IFN_SSI_SDATA7,
- GPIO_FN_HCTS2x_B,
- GPIO_FN_MSIOF1_RXD_C,
- GPIO_FN_TS_SDEN1_A,
- GPIO_FN_STP_ISEN_1_A,
- GPIO_FN_RIF1_D0_A,
- GPIO_FN_RIF3_D0_A,
- GPIO_FN_TCLK2_A,
- GPIO_IFN_SSI_SDATA8,
- GPIO_FN_HRTS2x_B,
- GPIO_FN_MSIOF1_TXD_C,
- GPIO_FN_TS_SPSYNC1_A,
- GPIO_FN_STP_ISSYNC_1_A,
- GPIO_FN_RIF1_D1_A,
- GPIO_FN_RIF3_D1_A,
- GPIO_IFN_SSI_SDATA9_A,
- GPIO_FN_HSCK2_B,
- GPIO_FN_MSIOF1_SS1_C,
- GPIO_FN_HSCK1_A,
- GPIO_FN_SSI_WS1_B,
- GPIO_FN_SCK1,
- GPIO_FN_STP_IVCXO27_1_A,
- GPIO_FN_SCK5_A,
-
- /* IPSR17 */
- GPIO_IFN_AUDIO_CLKA_A,
- GPIO_FN_CC5_OSCOUT,
- GPIO_IFN_AUDIO_CLKB_B,
- GPIO_FN_SCIF_CLK_A,
- GPIO_FN_STP_IVCXO27_1_D,
- GPIO_FN_REMOCON_A,
- GPIO_FN_TCLK1_A,
- GPIO_IFN_USB0_PWEN,
- GPIO_FN_SIM0_RST_C,
- GPIO_FN_TS_SCK1_D,
- GPIO_FN_STP_ISCLK_1_D,
- GPIO_FN_BPFCLK_B,
- GPIO_FN_RIF3_CLK_B,
- GPIO_FN_HSCK2_C,
- GPIO_IFN_USB0_OVC,
- GPIO_FN_SIM0_D_C,
- GPIO_FN_TS_SDAT1_D,
- GPIO_FN_STP_ISD_1_D,
- GPIO_FN_RIF3_SYNC_B,
- GPIO_FN_HRX2_C,
- GPIO_IFN_USB1_PWEN,
- GPIO_FN_SIM0_CLK_C,
- GPIO_FN_SSI_SCK1_A,
- GPIO_FN_TS_SCK0_E,
- GPIO_FN_STP_ISCLK_0_E,
- GPIO_FN_FMCLK_B,
- GPIO_FN_RIF2_CLK_B,
- GPIO_FN_SPEEDIN_A,
- GPIO_FN_HTX2_C,
- GPIO_IFN_USB1_OVC,
- GPIO_FN_MSIOF1_SS2_C,
- GPIO_FN_SSI_WS1_A,
- GPIO_FN_TS_SDAT0_E,
- GPIO_FN_STP_ISD_0_E,
- GPIO_FN_FMIN_B,
- GPIO_FN_RIF2_SYNC_B,
- GPIO_FN_REMOCON_B,
- GPIO_FN_HCTS2x_C,
- GPIO_IFN_USB30_PWEN,
- GPIO_FN_AUDIO_CLKOUT_B,
- GPIO_FN_SSI_SCK2_B,
- GPIO_FN_TS_SDEN1_D,
- GPIO_FN_STP_ISEN_1_D,
- GPIO_FN_STP_OPWM_0_E,
- GPIO_FN_RIF3_D0_B,
- GPIO_FN_TCLK2_B,
- GPIO_FN_TPU0TO0,
- GPIO_FN_BPFCLK_C,
- GPIO_FN_HRTS2x_C,
- GPIO_IFN_USB30_OVC,
- GPIO_FN_AUDIO_CLKOUT1_B,
- GPIO_FN_SSI_WS2_B,
- GPIO_FN_TS_SPSYNC1_D,
- GPIO_FN_STP_ISSYNC_1_D,
- GPIO_FN_STP_IVCXO27_0_E,
- GPIO_FN_RIF3_D1_B,
- GPIO_FN_FSO_TOEx,
- GPIO_FN_TPU0TO1,
-
- /* IPSR18 */
- GPIO_IFN_USB3_PWEN,
- GPIO_FN_AUDIO_CLKOUT2_B,
- GPIO_FN_SSI_SCK9_B,
- GPIO_FN_TS_SDEN0_E,
- GPIO_FN_STP_ISEN_0_E,
- GPIO_FN_RIF2_D0_B,
- GPIO_FN_TPU0TO2,
- GPIO_FN_FMCLK_C,
- GPIO_FN_FMCLK_D,
- GPIO_IFN_USB3_OVC,
- GPIO_FN_AUDIO_CLKOUT3_B,
- GPIO_FN_SSI_WS9_B,
- GPIO_FN_TS_SPSYNC0_E,
- GPIO_FN_STP_ISSYNC_0_E,
- GPIO_FN_RIF2_D1_B,
- GPIO_FN_TPU0TO3,
- GPIO_FN_FMIN_C,
- GPIO_FN_FMIN_D,
-};
-
-#endif /* __ASM_R8A7795_GPIO_H__ */
+++ /dev/null
-/*
- * arch/arm/mach-rmobile/include/mach/r8a7795.h
- * This file defines registers and value for r8a7795.
- *
- * Copyright (C) 2015 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_R8A7795_H
-#define __ASM_ARCH_R8A7795_H
-
-#include "rcar-gen3-base.h"
-
-/* Module stop control/status register bits */
-#define MSTP0_BITS 0x00640800
-#define MSTP1_BITS 0xF3EE9390
-#define MSTP2_BITS 0x340FAFDC
-#define MSTP3_BITS 0xD80C7CDF
-#define MSTP4_BITS 0x80000184
-#define MSTP5_BITS 0x40BFFF46
-#define MSTP6_BITS 0xE5FBEECF
-#define MSTP7_BITS 0x39FFFF0E
-#define MSTP8_BITS 0x01F19FF4
-#define MSTP9_BITS 0xFFDFFFFF
-#define MSTP10_BITS 0xFFFEFFE0
-#define MSTP11_BITS 0x00000000
-
-/* SDHI */
-#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
-#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
-
-#endif /* __ASM_ARCH_R8A7795_H */
+++ /dev/null
-/*
- * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h
- * This file defines pin function control of gpio.
- *
- * Copyright (C) 2016 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_R8A7796_GPIO_H__
-#define __ASM_R8A7796_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
- GPIO_GP_1_28,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
- GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
- GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
- GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
-
- GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
-
- /* GPSR0 */
- GPIO_GFN_D15,
- GPIO_GFN_D14,
- GPIO_GFN_D13,
- GPIO_GFN_D12,
- GPIO_GFN_D11,
- GPIO_GFN_D10,
- GPIO_GFN_D9,
- GPIO_GFN_D8,
- GPIO_GFN_D7,
- GPIO_GFN_D6,
- GPIO_GFN_D5,
- GPIO_GFN_D4,
- GPIO_GFN_D3,
- GPIO_GFN_D2,
- GPIO_GFN_D1,
- GPIO_GFN_D0,
-
- /* GPSR1 */
- GPIO_GFN_CLKOUT,
- GPIO_GFN_EX_WAIT0_A,
- GPIO_GFN_WE1x,
- GPIO_GFN_WE0x,
- GPIO_GFN_RD_WRx,
- GPIO_GFN_RDx,
- GPIO_GFN_BSx,
- GPIO_GFN_CS1x_A26,
- GPIO_GFN_CS0x,
- GPIO_GFN_A19,
- GPIO_GFN_A18,
- GPIO_GFN_A17,
- GPIO_GFN_A16,
- GPIO_GFN_A15,
- GPIO_GFN_A14,
- GPIO_GFN_A13,
- GPIO_GFN_A12,
- GPIO_GFN_A11,
- GPIO_GFN_A10,
- GPIO_GFN_A9,
- GPIO_GFN_A8,
- GPIO_GFN_A7,
- GPIO_GFN_A6,
- GPIO_GFN_A5,
- GPIO_GFN_A4,
- GPIO_GFN_A3,
- GPIO_GFN_A2,
- GPIO_GFN_A1,
- GPIO_GFN_A0,
-
- /* GPSR2 */
- GPIO_GFN_AVB_AVTP_CAPTURE_A,
- GPIO_GFN_AVB_AVTP_MATCH_A,
- GPIO_GFN_AVB_LINK,
- GPIO_GFN_AVB_PHY_INT,
- GPIO_GFN_AVB_MAGIC,
- GPIO_GFN_AVB_MDC,
- GPIO_GFN_PWM2_A,
- GPIO_GFN_PWM1_A,
- GPIO_GFN_PWM0,
- GPIO_GFN_IRQ5,
- GPIO_GFN_IRQ4,
- GPIO_GFN_IRQ3,
- GPIO_GFN_IRQ2,
- GPIO_GFN_IRQ1,
- GPIO_GFN_IRQ0,
-
- /* GPSR3 */
- GPIO_GFN_SD1_WP,
- GPIO_GFN_SD1_CD,
- GPIO_GFN_SD0_WP,
- GPIO_GFN_SD0_CD,
- GPIO_GFN_SD1_DAT3,
- GPIO_GFN_SD1_DAT2,
- GPIO_GFN_SD1_DAT1,
- GPIO_GFN_SD1_DAT0,
- GPIO_GFN_SD1_CMD,
- GPIO_GFN_SD1_CLK,
- GPIO_GFN_SD0_DAT3,
- GPIO_GFN_SD0_DAT2,
- GPIO_GFN_SD0_DAT1,
- GPIO_GFN_SD0_DAT0,
- GPIO_GFN_SD0_CMD,
- GPIO_GFN_SD0_CLK,
-
- /* GPSR4 */
- GPIO_GFN_SD3_DS,
- GPIO_GFN_SD3_DAT7,
- GPIO_GFN_SD3_DAT6,
- GPIO_GFN_SD3_DAT5,
- GPIO_GFN_SD3_DAT4,
- GPIO_FN_SD3_DAT3,
- GPIO_FN_SD3_DAT2,
- GPIO_FN_SD3_DAT1,
- GPIO_FN_SD3_DAT0,
- GPIO_FN_SD3_CMD,
- GPIO_FN_SD3_CLK,
- GPIO_GFN_SD2_DS,
- GPIO_GFN_SD2_DAT3,
- GPIO_GFN_SD2_DAT2,
- GPIO_GFN_SD2_DAT1,
- GPIO_GFN_SD2_DAT0,
- GPIO_FN_SD2_CMD,
- GPIO_GFN_SD2_CLK,
-
- /* GPSR5 */
- GPIO_GFN_MLB_DAT,
- GPIO_GFN_MLB_SIG,
- GPIO_GFN_MLB_CLK,
- GPIO_FN_MSIOF0_RXD,
- GPIO_GFN_MSIOF0_SS2,
- GPIO_FN_MSIOF0_TXD,
- GPIO_GFN_MSIOF0_SS1,
- GPIO_GFN_MSIOF0_SYNC,
- GPIO_FN_MSIOF0_SCK,
- GPIO_GFN_HRTS0x,
- GPIO_GFN_HCTS0x,
- GPIO_GFN_HTX0,
- GPIO_GFN_HRX0,
- GPIO_GFN_HSCK0,
- GPIO_GFN_RX2_A,
- GPIO_GFN_TX2_A,
- GPIO_GFN_SCK2,
- GPIO_GFN_RTS1x_TANS,
- GPIO_GFN_CTS1x,
- GPIO_GFN_TX1_A,
- GPIO_GFN_RX1_A,
- GPIO_GFN_RTS0x_TANS,
- GPIO_GFN_CTS0x,
- GPIO_GFN_TX0,
- GPIO_GFN_RX0,
- GPIO_GFN_SCK0,
-
- /* GPSR6 */
- GPIO_GFN_GP6_31,
- GPIO_GFN_GP6_30,
- GPIO_GFN_USB30_OVC,
- GPIO_GFN_USB30_PWEN,
- GPIO_GFN_USB1_OVC,
- GPIO_GFN_USB1_PWEN,
- GPIO_GFN_USB0_OVC,
- GPIO_GFN_USB0_PWEN,
- GPIO_GFN_AUDIO_CLKB_B,
- GPIO_GFN_AUDIO_CLKA_A,
- GPIO_GFN_SSI_SDATA9_A,
- GPIO_GFN_SSI_SDATA8,
- GPIO_GFN_SSI_SDATA7,
- GPIO_GFN_SSI_WS78,
- GPIO_GFN_SSI_SCK78,
- GPIO_GFN_SSI_SDATA6,
- GPIO_GFN_SSI_WS6,
- GPIO_GFN_SSI_SCK6,
- GPIO_FN_SSI_SDATA5,
- GPIO_FN_SSI_WS5,
- GPIO_FN_SSI_SCK5,
- GPIO_GFN_SSI_SDATA4,
- GPIO_GFN_SSI_WS4,
- GPIO_GFN_SSI_SCK4,
- GPIO_GFN_SSI_SDATA3,
- GPIO_GFN_SSI_WS34,
- GPIO_GFN_SSI_SCK34,
- GPIO_GFN_SSI_SDATA2_A,
- GPIO_GFN_SSI_SDATA1_A,
- GPIO_GFN_SSI_SDATA0,
- GPIO_GFN_SSI_WS01239,
- GPIO_GFN_SSI_SCK01239,
-
- /* GPSR7 */
- GPIO_FN_HDMI1_CEC,
- GPIO_FN_HDMI0_CEC,
- GPIO_FN_AVS2,
- GPIO_FN_AVS1,
-
- /* IPSR0 */
- GPIO_IFN_AVB_MDC,
- GPIO_FN_MSIOF2_SS2_C,
- GPIO_IFN_AVB_MAGIC,
- GPIO_FN_MSIOF2_SS1_C,
- GPIO_FN_SCK4_A,
- GPIO_IFN_AVB_PHY_INT,
- GPIO_FN_MSIOF2_SYNC_C,
- GPIO_FN_RX4_A,
- GPIO_IFN_AVB_LINK,
- GPIO_FN_MSIOF2_SCK_C,
- GPIO_FN_TX4_A,
- GPIO_IFN_AVB_AVTP_MATCH_A,
- GPIO_FN_MSIOF2_RXD_C,
- GPIO_FN_CTS4x_A,
- GPIO_IFN_AVB_AVTP_CAPTURE_A,
- GPIO_FN_MSIOF2_TXD_C,
- GPIO_FN_RTS4x_TANS_A,
- GPIO_IFN_IRQ0,
- GPIO_FN_QPOLB,
- GPIO_FN_DU_CDE,
- GPIO_FN_VI4_DATA0_B,
- GPIO_FN_CAN0_TX_B,
- GPIO_FN_CANFD0_TX_B,
- GPIO_FN_MSIOF3_SS2_E,
- GPIO_IFN_IRQ1,
- GPIO_FN_QPOLA,
- GPIO_FN_DU_DISP,
- GPIO_FN_VI4_DATA1_B,
- GPIO_FN_CAN0_RX_B,
- GPIO_FN_CANFD0_RX_B,
- GPIO_FN_MSIOF3_SS1_E,
-
- /* IPSR1 */
- GPIO_IFN_IRQ2,
- GPIO_FN_QCPV_QDE,
- GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- GPIO_FN_VI4_DATA2_B,
- GPIO_FN_MSIOF3_SYNC_E,
- GPIO_FN_PWM3_B,
- GPIO_IFN_IRQ3,
- GPIO_FN_QSTVB_QVE,
- GPIO_FN_DU_DOTCLKOUT1,
- GPIO_FN_VI4_DATA3_B,
- GPIO_FN_MSIOF3_SCK_E,
- GPIO_FN_PWM4_B,
- GPIO_IFN_IRQ4,
- GPIO_FN_QSTH_QHS,
- GPIO_FN_DU_EXHSYNC_DU_HSYNC,
- GPIO_FN_VI4_DATA4_B,
- GPIO_FN_MSIOF3_RXD_E,
- GPIO_FN_PWM5_B,
- GPIO_IFN_IRQ5,
- GPIO_FN_QSTB_QHE,
- GPIO_FN_DU_EXVSYNC_DU_VSYNC,
- GPIO_FN_VI4_DATA5_B,
- GPIO_FN_MSIOF3_TXD_E,
- GPIO_FN_PWM6_B,
- GPIO_IFN_PWM0,
- GPIO_FN_AVB_AVTP_PPS,
- GPIO_FN_VI4_DATA6_B,
- GPIO_FN_IECLK_B,
- GPIO_IFN_PWM1_A,
- GPIO_FN_HRX3_D,
- GPIO_FN_VI4_DATA7_B,
- GPIO_FN_IERX_B,
- GPIO_IFN_PWM2_A,
- GPIO_FN_PWMFSW0,
- GPIO_FN_HTX3_D,
- GPIO_FN_IETX_B,
- GPIO_IFN_A0,
- GPIO_FN_LCDOUT16,
- GPIO_FN_MSIOF3_SYNC_B,
- GPIO_FN_VI4_DATA8,
- GPIO_FN_DU_DB0,
- GPIO_FN_PWM3_A,
-
- /* IPSR2 */
- GPIO_IFN_A1,
- GPIO_FN_LCDOUT17,
- GPIO_FN_MSIOF3_TXD_B,
- GPIO_FN_VI4_DATA9,
- GPIO_FN_DU_DB1,
- GPIO_FN_PWM4_A,
- GPIO_IFN_A2,
- GPIO_FN_LCDOUT18,
- GPIO_FN_MSIOF3_SCK_B,
- GPIO_FN_VI4_DATA10,
- GPIO_FN_DU_DB2,
- GPIO_FN_PWM5_A,
- GPIO_IFN_A3,
- GPIO_FN_LCDOUT19,
- GPIO_FN_MSIOF3_RXD_B,
- GPIO_FN_VI4_DATA11,
- GPIO_FN_DU_DB3,
- GPIO_FN_PWM6_A,
- GPIO_IFN_A4,
- GPIO_FN_LCDOUT20,
- GPIO_FN_MSIOF3_SS1_B,
- GPIO_FN_VI4_DATA12,
- GPIO_FN_VI5_DATA12,
- GPIO_FN_DU_DB4,
- GPIO_IFN_A5,
- GPIO_FN_LCDOUT21,
- GPIO_FN_MSIOF3_SS2_B,
- GPIO_FN_SCK4_B,
- GPIO_FN_VI4_DATA13,
- GPIO_FN_VI5_DATA13,
- GPIO_FN_DU_DB5,
- GPIO_IFN_A6,
- GPIO_FN_LCDOUT22,
- GPIO_FN_MSIOF2_SS1_A,
- GPIO_FN_RX4_B,
- GPIO_FN_VI4_DATA14,
- GPIO_FN_VI5_DATA14,
- GPIO_FN_DU_DB6,
- GPIO_IFN_A7,
- GPIO_FN_LCDOUT23,
- GPIO_FN_MSIOF2_SS2_A,
- GPIO_FN_TX4_B,
- GPIO_FN_VI4_DATA15,
- GPIO_FN_V15_DATA15,
- GPIO_FN_DU_DB7,
- GPIO_IFN_A8,
- GPIO_FN_RX3_B,
- GPIO_FN_MSIOF2_SYNC_A,
- GPIO_FN_HRX4_B,
- GPIO_FN_SDA6_A,
- GPIO_FN_AVB_AVTP_MATCH_B,
- GPIO_FN_PWM1_B,
-
- /* IPSR3 */
- GPIO_IFN_A9,
- GPIO_FN_MSIOF2_SCK_A,
- GPIO_FN_CTS4x_B,
- GPIO_FN_VI5_VSYNCx,
- GPIO_IFN_A10,
- GPIO_FN_MSIOF2_RXD_A,
- GPIO_FN_RTS4n_TANS_B,
- GPIO_FN_VI5_HSYNCx,
- GPIO_IFN_A11,
- GPIO_FN_TX3_B,
- GPIO_FN_MSIOF2_TXD_A,
- GPIO_FN_HTX4_B,
- GPIO_FN_HSCK4,
- GPIO_FN_VI5_FIELD,
- GPIO_FN_SCL6_A,
- GPIO_FN_AVB_AVTP_CAPTURE_B,
- GPIO_FN_PWM2_B,
- GPIO_FN_SPV_EVEN,
- GPIO_IFN_A12,
- GPIO_FN_LCDOUT12,
- GPIO_FN_MSIOF3_SCK_C,
- GPIO_FN_HRX4_A,
- GPIO_FN_VI5_DATA8,
- GPIO_FN_DU_DG4,
- GPIO_IFN_A13,
- GPIO_FN_LCDOUT13,
- GPIO_FN_MSIOF3_SYNC_C,
- GPIO_FN_HTX4_A,
- GPIO_FN_VI5_DATA9,
- GPIO_FN_DU_DG5,
- GPIO_IFN_A14,
- GPIO_FN_LCDOUT14,
- GPIO_FN_MSIOF3_RXD_C,
- GPIO_FN_HCTS4x,
- GPIO_FN_VI5_DATA10,
- GPIO_FN_DU_DG6,
- GPIO_IFN_A15,
- GPIO_FN_LCDOUT15,
- GPIO_FN_MSIOF3_TXD_C,
- GPIO_FN_HRTS4x,
- GPIO_FN_VI5_DATA11,
- GPIO_FN_DU_DG7,
- GPIO_IFN_A16,
- GPIO_FN_LCDOUT8,
- GPIO_FN_VI4_FIELD,
- GPIO_FN_DU_DG0,
-
- /* IPSR4 */
- GPIO_IFN_A17,
- GPIO_FN_LCDOUT9,
- GPIO_FN_VI4_VSYNCx,
- GPIO_FN_DU_DG1,
- GPIO_IFN_A18,
- GPIO_FN_LCDOUT10,
- GPIO_FN_VI4_HSYNCx,
- GPIO_FN_DU_DG2,
- GPIO_IFN_A19,
- GPIO_FN_LCDOUT11,
- GPIO_FN_VI4_CLKENB,
- GPIO_FN_DU_DG3,
- GPIO_IFN_CS0x,
- GPIO_FN_VI5_CLKENB,
- GPIO_IFN_CS1x_A26,
- GPIO_FN_VI5_CLK,
- GPIO_FN_EX_WAIT0_B,
- GPIO_IFN_BSx,
- GPIO_FN_QSTVA_QVS,
- GPIO_FN_MSIOF3_SCK_D,
- GPIO_FN_SCK3,
- GPIO_FN_HSCK3,
- GPIO_FN_CAN1_TX,
- GPIO_FN_CANFD1_TX,
- GPIO_FN_IETX_A,
- GPIO_IFN_RDx,
- GPIO_FN_MSIOF3_SYNC_D,
- GPIO_FN_RX3_A,
- GPIO_FN_HRX3_A,
- GPIO_FN_CAN0_TX_A,
- GPIO_FN_CANFD0_TX_A,
- GPIO_IFN_RD_WRx,
- GPIO_FN_MSIOF3_RXD_D,
- GPIO_FN_TX3_A,
- GPIO_FN_HTX3_A,
- GPIO_FN_CAN0_RX_A,
- GPIO_FN_CANFD0_RX_A,
-
- /* IPSR5 */
- GPIO_IFN_WE0x,
- GPIO_FN_MSIIOF3_TXD_D,
- GPIO_FN_CTS3x,
- GPIO_FN_HCTS3x,
- GPIO_FN_SCL6_B,
- GPIO_FN_CAN_CLK,
- GPIO_FN_IECLK_A,
- GPIO_IFN_WE1x,
- GPIO_FN_MSIOF3_SS1_D,
- GPIO_FN_RTS3x_TANS,
- GPIO_FN_HRTS3x,
- GPIO_FN_SDA6_B,
- GPIO_FN_CAN1_RX,
- GPIO_FN_CANFD1_RX,
- GPIO_FN_IERX_A,
- GPIO_IFN_EX_WAIT0_A,
- GPIO_FN_QCLK,
- GPIO_FN_VI4_CLK,
- GPIO_FN_DU_DOTCLKOUT0,
- GPIO_IFN_D0,
- GPIO_FN_MSIOF2_SS1_B,
- GPIO_FN_MSIOF3_SCK_A,
- GPIO_FN_VI4_DATA16,
- GPIO_FN_VI5_DATA0,
- GPIO_IFN_D1,
- GPIO_FN_MSIOF2_SS2_B,
- GPIO_FN_MSIOF3_SYNC_A,
- GPIO_FN_VI4_DATA17,
- GPIO_FN_VI5_DATA1,
- GPIO_IFN_D2,
- GPIO_FN_MSIOF3_RXD_A,
- GPIO_FN_VI4_DATA18,
- GPIO_FN_VI5_DATA2,
- GPIO_IFN_D3,
- GPIO_FN_MSIOF3_TXD_A,
- GPIO_FN_VI4_DATA19,
- GPIO_FN_VI5_DATA3,
- GPIO_IFN_D4,
- GPIO_FN_MSIOF2_SCK_B,
- GPIO_FN_VI4_DATA20,
- GPIO_FN_VI5_DATA4,
-
- /* IPSR6 */
- GPIO_IFN_D5,
- GPIO_FN_MSIOF2_SYNC_B,
- GPIO_FN_VI4_DATA21,
- GPIO_FN_VI5_DATA5,
- GPIO_IFN_D6,
- GPIO_FN_MSIOF2_RXD_B,
- GPIO_FN_VI4_DATA22,
- GPIO_FN_VI5_DATA6,
- GPIO_IFN_D7,
- GPIO_FN_MSIOF2_TXD_B,
- GPIO_FN_VI4_DATA23,
- GPIO_FN_VI5_DATA7,
- GPIO_IFN_D8,
- GPIO_FN_LCDOUT0,
- GPIO_FN_MSIOF2_SCK_D,
- GPIO_FN_SCK4_C,
- GPIO_FN_VI4_DATA0_A,
- GPIO_FN_DU_DR0,
- GPIO_IFN_D9,
- GPIO_FN_LCDOUT1,
- GPIO_FN_MSIOF2_SYNC_D,
- GPIO_FN_VI4_DATA1_A,
- GPIO_FN_DU_DR1,
- GPIO_IFN_D10,
- GPIO_FN_LCDOUT2,
- GPIO_FN_MSIOF2_RXD_D,
- GPIO_FN_HRX3_B,
- GPIO_FN_VI4_DATA2_A,
- GPIO_FN_CTS4x_C,
- GPIO_FN_DU_DR2,
- GPIO_IFN_D11,
- GPIO_FN_LCDOUT3,
- GPIO_FN_MSIOF2_TXD_D,
- GPIO_FN_HTX3_B,
- GPIO_FN_VI4_DATA3_A,
- GPIO_FN_RTS4x_TANS_C,
- GPIO_FN_DU_DR3,
- GPIO_IFN_D12,
- GPIO_FN_LCDOUT4,
- GPIO_FN_MSIOF2_SS1_D,
- GPIO_FN_RX4_C,
- GPIO_FN_VI4_DATA4_A,
- GPIO_FN_DU_DR4,
-
- /* IPSR7 */
- GPIO_IFN_D13,
- GPIO_FN_LCDOUT5,
- GPIO_FN_MSIOF2_SS2_D,
- GPIO_FN_TX4_C,
- GPIO_FN_VI4_DATA5_A,
- GPIO_FN_DU_DR5,
- GPIO_IFN_D14,
- GPIO_FN_LCDOUT6,
- GPIO_FN_MSIOF3_SS1_A,
- GPIO_FN_HRX3_C,
- GPIO_FN_VI4_DATA6_A,
- GPIO_FN_DU_DR6,
- GPIO_FN_SCL6_C,
- GPIO_IFN_D15,
- GPIO_FN_LCDOUT7,
- GPIO_FN_MSIOF3_SS2_A,
- GPIO_FN_HTX3_C,
- GPIO_FN_VI4_DATA7_A,
- GPIO_FN_DU_DR7,
- GPIO_FN_SDA6_C,
- GPIO_FN_FSCLKST,
- GPIO_IFN_SD0_CLK,
- GPIO_FN_MSIOF1_SCK_E,
- GPIO_FN_STP_OPWM_0_B,
- GPIO_IFN_SD0_CMD,
- GPIO_FN_MSIOF1_SYNC_E,
- GPIO_FN_STP_IVCXO27_0_B,
- GPIO_IFN_SD0_DAT0,
- GPIO_FN_MSIOF1_RXD_E,
- GPIO_FN_TS_SCK0_B,
- GPIO_FN_STP_ISCLK_0_B,
- GPIO_IFN_SD0_DAT1,
- GPIO_FN_MSIOF1_TXD_E,
- GPIO_FN_TS_SPSYNC0_B,
- GPIO_FN_STP_ISSYNC_0_B,
-
- /* IPSR8 */
- GPIO_IFN_SD0_DAT2,
- GPIO_FN_MSIOF1_SS1_E,
- GPIO_FN_TS_SDAT0_B,
- GPIO_FN_STP_ISD_0_B,
-
- GPIO_IFN_SD0_DAT3,
- GPIO_FN_MSIOF1_SS2_E,
- GPIO_FN_TS_SDEN0_B,
- GPIO_FN_STP_ISEN_0_B,
-
- GPIO_IFN_SD1_CLK,
- GPIO_FN_MSIOF1_SCK_G,
- GPIO_FN_SIM0_CLK_A,
-
- GPIO_IFN_SD1_CMD,
- GPIO_FN_MSIOF1_SYNC_G,
- GPIO_FN_NFCEx_B,
- GPIO_FN_SIM0_D_A,
- GPIO_FN_STP_IVCXO27_1_B,
-
- GPIO_IFN_SD1_DAT0,
- GPIO_FN_SD2_DAT4,
- GPIO_FN_MSIOF1_RXD_G,
- GPIO_FN_NFWPx_B,
- GPIO_FN_TS_SCK1_B,
- GPIO_FN_STP_ISCLK_1_B,
-
- GPIO_IFN_SD1_DAT1,
- GPIO_FN_SD2_DAT5,
- GPIO_FN_MSIOF1_TXD_G,
- GPIO_FN_NFDATA14_B,
- GPIO_FN_TS_SPSYNC1_B,
- GPIO_FN_STP_ISSYNC_1_B,
-
- GPIO_IFN_SD1_DAT2,
- GPIO_FN_SD2_DAT6,
- GPIO_FN_MSIOF1_SS1_G,
- GPIO_FN_NFDATA15_B,
- GPIO_FN_TS_SDAT1_B,
- GPIO_FN_STP_IOD_1_B,
-
- GPIO_IFN_SD1_DAT3,
- GPIO_FN_SD2_DAT7,
- GPIO_FN_MSIOF1_SS2_G,
- GPIO_FN_NFRBx_B,
- GPIO_FN_TS_SDEN1_B,
- GPIO_FN_STP_ISEN_1_B,
-
- /* IPSR9 */
- GPIO_IFN_SD2_CLK,
- GPIO_FN_NFDATA8,
-
- GPIO_IFN_SD2_CMD,
- GPIO_FN_NFDATA9,
-
- GPIO_IFN_SD2_DAT0,
- GPIO_FN_NFDATA10,
-
- GPIO_IFN_SD2_DAT1,
- GPIO_FN_NFDATA11,
-
- GPIO_IFN_SD2_DAT2,
- GPIO_FN_NFDATA12,
-
- GPIO_IFN_SD2_DAT3,
- GPIO_FN_NFDATA13,
-
- GPIO_IFN_SD2_DS,
- GPIO_FN_NFALE,
-
- GPIO_IFN_SD3_CLK,
- GPIO_FN_NFWEx,
-
- /* IPSR10 */
- GPIO_IFN_SD3_CMD,
- GPIO_FN_NFREx,
-
- GPIO_IFN_SD3_DAT0,
- GPIO_FN_NFDATA0,
-
- GPIO_IFN_SD3_DAT1,
- GPIO_FN_NFDATA1,
-
- GPIO_IFN_SD3_DAT2,
- GPIO_FN_NFDATA2,
-
- GPIO_IFN_SD3_DAT3,
- GPIO_FN_NFDATA3,
-
- GPIO_IFN_SD3_DAT4,
- GPIO_FN_SD2_CD_A,
- GPIO_FN_NFDATA4,
-
- GPIO_IFN_SD3_DAT5,
- GPIO_FN_SD2_WP_A,
- GPIO_FN_NFDATA5,
-
- GPIO_IFN_SD3_DAT6,
- GPIO_FN_SD3_CD,
- GPIO_FN_NFDATA6,
-
- /* IPSR11 */
- GPIO_IFN_SD3_DAT7,
- GPIO_FN_SD3_WP,
- GPIO_FN_NFDATA7,
-
- GPIO_IFN_SD3_DS,
- GPIO_FN_NFCLE,
-
- GPIO_IFN_SD0_CD,
- GPIO_FN_NFDATA14_A,
- GPIO_FN_SCL2_B,
- GPIO_FN_SIM0_RST_A,
-
- GPIO_IFN_SD0_WP,
- GPIO_FN_NFDATA15_A,
- GPIO_FN_SDA2_B,
-
- GPIO_IFN_SD1_CD,
- GPIO_FN_NFRBx_A,
- GPIO_FN_SIM0_CLK_B,
-
- GPIO_IFN_SD1_WP,
- GPIO_FN_NFCEx_A,
- GPIO_FN_SIM0_D_B,
-
- GPIO_IFN_SCK0,
- GPIO_FN_HSCK1_B,
- GPIO_FN_MSIOF1_SS2_B,
- GPIO_FN_AUDIO_CLKC_B,
- GPIO_FN_SDA2_A,
- GPIO_FN_SIM0_RST_B,
- GPIO_FN_STP_OPWM_0_C,
- GPIO_FN_RIF0_CLK_B,
- GPIO_FN_ADICHS2,
- GPIO_FN_SCK5_B,
-
- GPIO_IFN_RX0,
- GPIO_FN_HRX1_B,
- GPIO_FN_TS_SCK0_C,
- GPIO_FN_STP_ISCLK_0_C,
- GPIO_FN_RIF0_D0_B,
-
- /* IPSR12 */
- GPIO_IFN_TX0,
- GPIO_FN_HTX1_B,
- GPIO_FN_TS_SPSYNC0_C,
- GPIO_FN_STP_ISSYNC_0_C,
- GPIO_FN_RIF0_D1_B,
-
- GPIO_IFN_CTS0x,
- GPIO_FN_HCTS1x_B,
- GPIO_FN_MSIOF1_SYNC_B,
- GPIO_FN_TS_SPSYNC1_C,
- GPIO_FN_STP_ISSYNC_1_C,
- GPIO_FN_RIF1_SYNC_B,
- GPIO_FN_AUDIO_CLKOUT_C,
- GPIO_FN_ADICS_SAMP,
-
- GPIO_IFN_RTS0x_TANS,
- GPIO_FN_HRTS1x_B,
- GPIO_FN_MSIOF1_SS1_B,
- GPIO_FN_AUDIO_CLKA_B,
- GPIO_FN_SCL2_A,
- GPIO_FN_STP_IVCXO27_1_C,
- GPIO_FN_RIF0_SYNC_B,
- GPIO_FN_ADICHS1,
-
- GPIO_IFN_RX1_A,
- GPIO_FN_HRX1_A,
- GPIO_FN_TS_SDAT0_C,
- GPIO_FN_STP_ISD_0_C,
- GPIO_FN_RIF1_CLK_C,
-
- GPIO_IFN_TX1_A,
- GPIO_FN_HTX1_A,
- GPIO_FN_TS_SDEN0_C,
- GPIO_FN_STP_ISEN_0_C,
- GPIO_FN_RIF1_D0_C,
-
- GPIO_IFN_CTS1x,
- GPIO_FN_HCTS1x_A,
- GPIO_FN_MSIOF1_RXD_B,
- GPIO_FN_TS_SDEN1_C,
- GPIO_FN_STP_ISEN_1_C,
- GPIO_FN_RIF1_D0_B,
- GPIO_FN_ADIDATA,
-
- GPIO_IFN_RTS1x_TANS,
- GPIO_FN_HRTS1x_A,
- GPIO_FN_MSIOF1_TXD_B,
- GPIO_FN_TS_SDAT1_C,
- GPIO_FN_STP_ISD_1_C,
- GPIO_FN_RIF1_D1_B,
- GPIO_FN_ADICHS0,
-
- GPIO_IFN_SCK2,
- GPIO_FN_SCIF_CLK_B,
- GPIO_FN_MSIOF1_SCK_B,
- GPIO_FN_TS_SCK1_C,
- GPIO_FN_STP_ISCLK_1_C,
- GPIO_FN_RIF1_CLK_B,
- GPIO_FN_ADICLK,
-
- /* IPSR13 */
- GPIO_IFN_TX2_A,
- GPIO_FN_SD2_CD_B,
- GPIO_FN_SCL1_A,
- GPIO_FN_FMCLK_A,
- GPIO_FN_RIF1_D1_C,
- GPIO_FN_FSO_CFE_0_B,
-
- GPIO_IFN_RX2_A,
- GPIO_FN_SD2_WP_B,
- GPIO_FN_SDA1_A,
- GPIO_FN_FMIN_A,
- GPIO_FN_RIF1_SYNC_C,
- GPIO_FN_FSO_CEF_1_B,
-
- GPIO_IFN_HSCK0,
- GPIO_FN_MSIOF1_SCK_D,
- GPIO_FN_AUDIO_CLKB_A,
- GPIO_FN_SSI_SDATA1_B,
- GPIO_FN_TS_SCK0_D,
- GPIO_FN_STP_ISCLK_0_D,
- GPIO_FN_RIF0_CLK_C,
- GPIO_FN_RX5_B,
-
- GPIO_IFN_HRX0,
- GPIO_FN_MSIOF1_RXD_D,
- GPIO_FN_SS1_SDATA2_B,
- GPIO_FN_TS_SDEN0_D,
- GPIO_FN_STP_ISEN_0_D,
- GPIO_FN_RIF0_D0_C,
-
- GPIO_IFN_HTX0,
- GPIO_FN_MSIOF1_TXD_D,
- GPIO_FN_SSI_SDATA9_B,
- GPIO_FN_TS_SDAT0_D,
- GPIO_FN_STP_ISD_0_D,
- GPIO_FN_RIF0_D1_C,
-
- GPIO_IFN_HCTS0x,
- GPIO_FN_RX2_B,
- GPIO_FN_MSIOF1_SYNC_D,
- GPIO_FN_SSI_SCK9_A,
- GPIO_FN_TS_SPSYNC0_D,
- GPIO_FN_STP_ISSYNC_0_D,
- GPIO_FN_RIF0_SYNC_C,
- GPIO_FN_AUDIO_CLKOUT1_A,
-
- GPIO_IFN_HRTS0x,
- GPIO_FN_TX2_B,
- GPIO_FN_MSIOF1_SS1_D,
- GPIO_FN_SSI_WS9_A,
- GPIO_FN_STP_IVCXO27_0_D,
- GPIO_FN_BPFCLK_A,
- GPIO_FN_AUDIO_CLKOUT2_A,
-
- GPIO_IFN_MSIOF0_SYNC,
- GPIO_FN_AUDIO_CLKOUT_A,
- GPIO_FN_TX5_B,
- GPIO_FN_BPFCLK_D,
-
- /* IPSR14 */
- GPIO_IFN_MSIOF0_SS1,
- GPIO_FN_RX5_A,
- GPIO_FN_NFWPx_A,
- GPIO_FN_AUDIO_CLKA_C,
- GPIO_FN_SSI_SCK2_A,
- GPIO_FN_STP_IVCXO27_0_C,
- GPIO_FN_AUDIO_CLKOUT3_A,
- GPIO_FN_TCLK1_B,
-
- GPIO_IFN_MSIOF0_SS2,
- GPIO_FN_TX5_A,
- GPIO_FN_MSIOF1_SS2_D,
- GPIO_FN_AUDIO_CLKC_A,
- GPIO_FN_SSI_WS2_A,
- GPIO_FN_STP_OPWM_0_D,
- GPIO_FN_AUDIO_CLKOUT_D,
- GPIO_FN_SPEEDIN_B,
-
- GPIO_IFN_MLB_CLK,
- GPIO_FN_MSIOF1_SCK_F,
- GPIO_FN_SCL1_B,
-
- GPIO_IFN_MLB_SIG,
- GPIO_FN_RX1_B,
- GPIO_FN_MSIOF1_SYNC_F,
- GPIO_FN_SDA1_B,
-
- GPIO_IFN_MLB_DAT,
- GPIO_FN_TX1_B,
- GPIO_FN_MSIOF1_RXD_F,
-
- GPIO_IFN_SSI_SCK0129,
- GPIO_FN_MSIOF1_TXD_F,
- GPIO_FN_MOUT0,
-
- GPIO_IFN_SSI_WS0129,
- GPIO_FN_MSIOF1_SS1_F,
- GPIO_FN_MOUT1,
-
- GPIO_IFN_SSI_SDATA0,
- GPIO_FN_MSIOF1_SS2_F,
- GPIO_FN_MOUT2,
-
- /* IPSR15 */
- GPIO_IFN_SSI_SDATA1_A,
- GPIO_FN_MOUT5,
-
- GPIO_IFN_SSI_SDATA2_A,
- GPIO_FN_SSI_SCK1_B,
- GPIO_FN_MOUT6,
-
- GPIO_IFN_SSI_SCK34,
- GPIO_FN_MSIOF1_SS1_A,
- GPIO_FN_STP_OPWM_0_A,
-
- GPIO_IFN_SSI_WS34,
- GPIO_FN_HCTS2x_A,
- GPIO_FN_MSIOF1_SS2_A,
- GPIO_FN_STP_IVCXO27_0_A,
-
- GPIO_IFN_SSI_SDATA3,
- GPIO_FN_HRTS2x_A,
- GPIO_FN_MSIOF1_TXD_A,
- GPIO_FN_TS_SCK0_A,
- GPIO_FN_STP_ISCLK_0_A,
- GPIO_FN_RIF0_D1_A,
- GPIO_FN_RIF2_D0_A,
-
- GPIO_IFN_SSI_SCK4,
- GPIO_FN_HRX2_A,
- GPIO_FN_MSIOF1_SCK_A,
- GPIO_FN_TS_SDAT0_A,
- GPIO_FN_STP_ISD_0_A,
- GPIO_FN_RIF0_CLK_A,
- GPIO_FN_RIF2_CLK_A,
-
- GPIO_IFN_SSI_WS4,
- GPIO_FN_HTX2_A,
- GPIO_FN_MSIOF1_SYNC_A,
- GPIO_FN_TS_SDEN0_A,
- GPIO_FN_STP_ISEN_0_A,
- GPIO_FN_RIF0_SYNC_A,
- GPIO_FN_RIF2_SYNC_A,
-
- GPIO_IFN_SSI_SDATA4,
- GPIO_FN_HSCK2_A,
- GPIO_FN_MSIOF1_RXD_A,
- GPIO_FN_TS_SPSYNC0_A,
- GPIO_FN_STP_ISSYNC_0_A,
- GPIO_FN_RIF0_D0_A,
- GPIO_FN_RIF2_D1_A,
-
- /* IPSR16 */
- GPIO_IFN_SSI_SCK6,
- GPIO_FN_SIM0_RST_D,
- GPIO_FN_FSO_TOE_A,
-
- GPIO_IFN_SSI_WS6,
- GPIO_FN_SIM0_D_D,
-
- GPIO_IFN_SSI_SDATA6,
- GPIO_FN_SIM0_CLK_D,
-
- GPIO_IFN_SSI_SCK78,
- GPIO_FN_HRX2_B,
- GPIO_FN_MSIOF1_SCK_C,
- GPIO_FN_TS_SCK1_A,
- GPIO_FN_STP_ISCLK_1_A,
- GPIO_FN_RIF1_CLK_A,
- GPIO_FN_RIF3_CLK_A,
-
- GPIO_IFN_SSI_WS78,
- GPIO_FN_HTX2_B,
- GPIO_FN_MSIOF1_SYNC_C,
- GPIO_FN_TS_SDAT1_A,
- GPIO_FN_STP_ISD_1_A,
- GPIO_FN_RIF1_SYNC_A,
- GPIO_FN_RIF3_SYNC_A,
-
- GPIO_IFN_SSI_SDATA7,
- GPIO_FN_HCTS2x_B,
- GPIO_FN_MSIOF1_RXD_C,
- GPIO_FN_TS_SDEN1_A,
- GPIO_FN_STP_IEN_1_A,
- GPIO_FN_RIF1_D0_A,
- GPIO_FN_RIF3_D0_A,
- GPIO_FN_TCLK2_A,
-
- GPIO_IFN_SSI_SDATA8,
- GPIO_FN_HRTS2x_B,
- GPIO_FN_MSIOF1_TXD_C,
- GPIO_FN_TS_SPSYNC1_A,
- GPIO_FN_STP_ISSYNC_1_A,
- GPIO_FN_RIF1_D1_A,
- GPIO_FN_EIF3_D1_A,
-
- GPIO_IFN_SSI_SDATA9_A,
- GPIO_FN_HSCK2_B,
- GPIO_FN_MSIOF1_SS1_C,
- GPIO_FN_HSCK1_A,
- GPIO_FN_SSI_WS1_B,
- GPIO_FN_SCK1,
- GPIO_FN_STP_IVCXO27_1_A,
- GPIO_FN_SCK5,
-
- /* IPSR17 */
- GPIO_IFN_AUDIO_CLKA_A,
- GPIO_FN_CC5_OSCOUT,
-
- GPIO_IFN_AUDIO_CLKB_B,
- GPIO_FN_SCIF_CLK_A,
- GPIO_FN_STP_IVCXO27_1_D,
- GPIO_FN_REMOCON_A,
- GPIO_FN_TCLK1_A,
-
- GPIO_IFN_USB0_PWEN,
- GPIO_FN_SIM0_RST_C,
- GPIO_FN_TS_SCK1_D,
- GPIO_FN_STP_ISCLK_1_D,
- GPIO_FN_BPFCLK_B,
- GPIO_FN_RIF3_CLK_B,
- GPIO_FN_FSO_CFE_1_A,
- GPIO_FN_HSCK2_C,
-
- GPIO_IFN_USB0_OVC,
- GPIO_FN_SIM0_D_C,
- GPIO_FN_TS_SDAT1_D,
- GPIO_FN_STP_ISD_1_D,
- GPIO_FN_RIF3_SYNC_B,
- GPIO_FN_HRX2_C,
-
- GPIO_IFN_USB1_PWEN,
- GPIO_FN_SIM0_CLK_C,
- GPIO_FN_SSI_SCK1_A,
- GPIO_FN_TS_SCK0_E,
- GPIO_FN_STP_ISCLK_0_E,
- GPIO_FN_FMCLK_B,
- GPIO_FN_RIF2_CLK_B,
- GPIO_FN_SPEEDIN_A,
- GPIO_FN_HTX2_C,
-
- GPIO_IFN_USB1_OVC,
- GPIO_FN_MSIOF1_SS2_C,
- GPIO_FN_SSI_WS1_A,
- GPIO_FN_TS_SDAT0_E,
- GPIO_FN_STP_ISD_0_E,
- GPIO_FN_FMIN_B,
- GPIO_FN_RIF2_SYNC_B,
- GPIO_FN_REMOCON_B,
- GPIO_FN_HCTS2x_C,
-
- GPIO_IFN_USB30_PWEN,
- GPIO_FN_AUDIO_CLKOUT_B,
- GPIO_FN_SSI_SCK2_B,
- GPIO_FN_TS_SDEN1_D,
- GPIO_FN_STP_ISEN_1_D,
- GPIO_FN_STP_OPWM_0_E,
- GPIO_FN_RIF3_D0_B,
- GPIO_FN_TCLK2_B,
- GPIO_FN_TPU0TO0,
- GPIO_FN_BPFCLK_C,
- GPIO_FN_HRTS2x_C,
-
- GPIO_IFN_USB30_OVC,
- GPIO_FN_AUDIO_CLKOUT1_B,
- GPIO_FN_SSI_WS2_B,
- GPIO_FN_TS_SPSYNC1_D,
- GPIO_FN_STP_ISSYNC_1_D,
- GPIO_FN_STP_IVCXO27_0_E,
- GPIO_FN_RIF3_D1_B,
- GPIO_FN_FSO_TOE_B,
- GPIO_FN_TPU0TO1,
-
- /* IPSR18 */
- GPIO_IFN_GP6_30,
- GPIO_FN_AUDIO_CLKOUT2_B,
- GPIO_FN_SSI_SCK9_B,
- GPIO_FN_TS_SDEN0_E,
- GPIO_FN_STP_ISEN_0_E,
- GPIO_FN_RIF2_D0_B,
- GPIO_FN_FSO_CFE_0_A,
- GPIO_FN_TPU0TO2,
- GPIO_FN_FMCLK_C,
- GPIO_FN_FMCLK_D,
-
- GPIO_IFN_GP6_31,
- GPIO_FN_AUDIO_CLKOUT3_B,
- GPIO_FN_SSI_WS9_B,
- GPIO_FN_TS_SPSYNC0_E,
- GPIO_FN_STP_ISSYNC_0_E,
- GPIO_FN_RIF2_D1_B,
- GPIO_FN_TPU0TO3,
- GPIO_FN_FMIN_C,
- GPIO_FN_FMIN_D,
-
-};
-
-#endif /* __ASM_R8A7796_GPIO_H__ */
+++ /dev/null
-/*
- * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h
- * This file defines registers and value for r8a7796.
- *
- * Copyright (C) 2016 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_R8A7796_H
-#define __ASM_ARCH_R8A7796_H
-
-#include "rcar-gen3-base.h"
-
-/* Module stop control/status register bits */
-#define MSTP0_BITS 0x00200000
-#define MSTP1_BITS 0xFFFFFFFF
-#define MSTP2_BITS 0x340E2FDC
-#define MSTP3_BITS 0xFFFFFFDF
-#define MSTP4_BITS 0x80000184
-#define MSTP5_BITS 0xC3FFFFFF
-#define MSTP6_BITS 0xFFFFFFFF
-#define MSTP7_BITS 0xFFFFFFFF
-#define MSTP8_BITS 0x01F1FFF7
-#define MSTP9_BITS 0xFFFFFFFE
-#define MSTP10_BITS 0xFFFEFFE0
-#define MSTP11_BITS 0x000000B7
-
-/* SDHI */
-#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
-#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
-
-#endif /* __ASM_ARCH_R8A7796_H */
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
-/* SDHI */
-#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
-#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
-
/* PFC */
#define PFC_PUEN5 0xE6060414
#define PUEN_SSI_SDATA4 BIT(17)
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
-#elif defined(CONFIG_R8A7795)
-#include <asm/arch/r8a7795.h>
-#elif defined(CONFIG_R8A7796)
-#include <asm/arch/r8a7796.h>
+#elif defined(CONFIG_RCAR_GEN3)
+#include <asm/arch/rcar-gen3-base.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_ARCH_RMOBILE */
+/* PRR CPU IDs */
+#define RMOBILE_CPU_TYPE_SH73A0 0x37
+#define RMOBILE_CPU_TYPE_R8A7740 0x40
+#define RMOBILE_CPU_TYPE_R8A7790 0x45
+#define RMOBILE_CPU_TYPE_R8A7791 0x47
+#define RMOBILE_CPU_TYPE_R8A7792 0x4A
+#define RMOBILE_CPU_TYPE_R8A7793 0x4B
+#define RMOBILE_CPU_TYPE_R8A7794 0x4C
+#define RMOBILE_CPU_TYPE_R8A7795 0x4F
+#define RMOBILE_CPU_TYPE_R8A7796 0x52
+#define RMOBILE_CPU_TYPE_R8A77970 0x54
+#define RMOBILE_CPU_TYPE_R8A77995 0x58
+
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
+void rcar_gen3_memmap_fixup(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */
--- /dev/null
+/*
+ * Renesas RCar Gen3 memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region r8a7795_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+static struct mm_region r8a7796_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+static struct mm_region r8a77970_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+static struct mm_region r8a77995_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = r8a7795_mem_map;
+
+void rcar_gen3_memmap_fixup(void)
+{
+ u32 cpu_type = rmobile_get_cpu_type();
+
+ switch (cpu_type) {
+ case RMOBILE_CPU_TYPE_R8A7795:
+ mem_map = r8a7795_mem_map;
+ break;
+ case RMOBILE_CPU_TYPE_R8A7796:
+ mem_map = r8a7796_mem_map;
+ break;
+ case RMOBILE_CPU_TYPE_R8A77970:
+ mem_map = r8a77970_mem_map;
+ break;
+ case RMOBILE_CPU_TYPE_R8A77995:
+ mem_map = r8a77995_mem_map;
+ break;
+ }
+}
+++ /dev/null
-/*
- * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region r8a7795_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = r8a7795_mem_map;
+++ /dev/null
-/*
- * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region r8a7796_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe0000000UL,
- .phys = 0xe0000000UL,
- .size = 0xe0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = r8a7796_mem_map;
+++ /dev/null
-/*
- * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c
- * This file is r8a7795 processor support - PFC hardware block.
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx)
-
-#define CPU_32_PORT2(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx)
-
-#define CPU_32_PORT_29(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), \
- PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), \
- PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), \
- PORT_1(fn, pfx##25, sfx), \
- PORT_1(fn, pfx##26, sfx), \
- PORT_1(fn, pfx##27, sfx), \
- PORT_1(fn, pfx##28, sfx)
-
-#define CPU_32_PORT_28(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), \
- PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), \
- PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), \
- PORT_1(fn, pfx##25, sfx), \
- PORT_1(fn, pfx##26, sfx), \
- PORT_1(fn, pfx##27, sfx)
-
-#define CPU_32_PORT_26(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), \
- PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), \
- PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), \
- PORT_1(fn, pfx##25, sfx)
-
-#define CPU_32_PORT_18(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx), \
- PORT_1(fn, pfx##15, sfx), \
- PORT_1(fn, pfx##16, sfx), \
- PORT_1(fn, pfx##17, sfx)
-
-#define CPU_32_PORT_16(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx), \
- PORT_1(fn, pfx##15, sfx)
-
-#define CPU_32_PORT_15(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx)
-
-#define CPU_32_PORT_4(fn, pfx, sfx) \
- PORT_1(fn, pfx##0, sfx), \
- PORT_1(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##3, sfx)
-
-
-/* --gen3-- */
-/* GP_0_0_DATA -> GP_7_4_DATA */
-/* except for GP0[16] - [31],
- GP1[28] - [31],
- GP2[15] - [31],
- GP3[16] - [31],
- GP4[18] - [31],
- GP5[26] - [31],
- GP7[4] - [31] */
-
-#define ES_CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT_16(fn, pfx##_0_, sfx), \
- CPU_32_PORT_28(fn, pfx##_1_, sfx), \
- CPU_32_PORT_15(fn, pfx##_2_, sfx), \
- CPU_32_PORT_16(fn, pfx##_3_, sfx), \
- CPU_32_PORT_18(fn, pfx##_4_, sfx), \
- CPU_32_PORT_26(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT_4(fn, pfx##_7_, sfx)
-
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT_16(fn, pfx##_0_, sfx), \
- CPU_32_PORT_29(fn, pfx##_1_, sfx), \
- CPU_32_PORT_15(fn, pfx##_2_, sfx), \
- CPU_32_PORT_16(fn, pfx##_3_, sfx), \
- CPU_32_PORT_18(fn, pfx##_4_, sfx), \
- CPU_32_PORT_26(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT_4(fn, pfx##_7_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- GFN_D15,
- GFN_D14,
- GFN_D13,
- GFN_D12,
- GFN_D11,
- GFN_D10,
- GFN_D9,
- GFN_D8,
- GFN_D7,
- GFN_D6,
- GFN_D5,
- GFN_D4,
- GFN_D3,
- GFN_D2,
- GFN_D1,
- GFN_D0,
-
- /* GPSR1 */
- GFN_CLKOUT,
- GFN_EX_WAIT0_A,
- GFN_WE1x,
- GFN_WE0x,
- GFN_RD_WRx,
- GFN_RDx,
- GFN_BSx,
- GFN_CS1x_A26,
- GFN_CS0x,
- GFN_A19,
- GFN_A18,
- GFN_A17,
- GFN_A16,
- GFN_A15,
- GFN_A14,
- GFN_A13,
- GFN_A12,
- GFN_A11,
- GFN_A10,
- GFN_A9,
- GFN_A8,
- GFN_A7,
- GFN_A6,
- GFN_A5,
- GFN_A4,
- GFN_A3,
- GFN_A2,
- GFN_A1,
- GFN_A0,
-
- /* GPSR2 */
- GFN_AVB_AVTP_CAPTURE_A,
- GFN_AVB_AVTP_MATCH_A,
- GFN_AVB_LINK,
- GFN_AVB_PHY_INT,
- GFN_AVB_MAGIC,
- GFN_AVB_MDC,
- GFN_PWM2_A,
- GFN_PWM1_A,
- GFN_PWM0,
- GFN_IRQ5,
- GFN_IRQ4,
- GFN_IRQ3,
- GFN_IRQ2,
- GFN_IRQ1,
- GFN_IRQ0,
-
- /* GPSR3 */
- GFN_SD1_WP,
- GFN_SD1_CD,
- GFN_SD0_WP,
- GFN_SD0_CD,
- GFN_SD1_DAT3,
- GFN_SD1_DAT2,
- GFN_SD1_DAT1,
- GFN_SD1_DAT0,
- GFN_SD1_CMD,
- GFN_SD1_CLK,
- GFN_SD0_DAT3,
- GFN_SD0_DAT2,
- GFN_SD0_DAT1,
- GFN_SD0_DAT0,
- GFN_SD0_CMD,
- GFN_SD0_CLK,
-
- /* GPSR4 */
- GFN_SD3_DS,
- GFN_SD3_DAT7,
- GFN_SD3_DAT6,
- GFN_SD3_DAT5,
- GFN_SD3_DAT4,
- GFN_SD3_DAT3,
- GFN_SD3_DAT2,
- GFN_SD3_DAT1,
- GFN_SD3_DAT0,
- GFN_SD3_CMD,
- GFN_SD3_CLK,
- GFN_SD2_DS,
- GFN_SD2_DAT3,
- GFN_SD2_DAT2,
- GFN_SD2_DAT1,
- GFN_SD2_DAT0,
- GFN_SD2_CMD,
- GFN_SD2_CLK,
-
- /* GPSR5 */
- GFN_MLB_DAT,
- GFN_MLB_SIG,
- GFN_MLB_CLK,
- FN_MSIOF0_RXD,
- GFN_MSIOF0_SS2,
- FN_MSIOF0_TXD,
- GFN_MSIOF0_SS1,
- GFN_MSIOF0_SYNC,
- FN_MSIOF0_SCK,
- GFN_HRTS0x,
- GFN_HCTS0x,
- GFN_HTX0,
- GFN_HRX0,
- GFN_HSCK0,
- GFN_RX2_A,
- GFN_TX2_A,
- GFN_SCK2,
- GFN_RTS1x_TANS,
- GFN_CTS1x,
- GFN_TX1_A,
- GFN_RX1_A,
- GFN_RTS0x_TANS,
- GFN_CTS0x,
- GFN_TX0,
- GFN_RX0,
- GFN_SCK0,
-
- /* GPSR6 */
- GFN_USB3_OVC,
- GFN_USB3_PWEN,
- GFN_USB30_OVC,
- GFN_USB30_PWEN,
- GFN_USB1_OVC,
- GFN_USB1_PWEN,
- GFN_USB0_OVC,
- GFN_USB0_PWEN,
- GFN_AUDIO_CLKB_B,
- GFN_AUDIO_CLKA_A,
- GFN_SSI_SDATA9_A,
- GFN_SSI_SDATA8,
- GFN_SSI_SDATA7,
- GFN_SSI_WS78,
- GFN_SSI_SCK78,
- GFN_SSI_SDATA6,
- GFN_SSI_WS6,
- GFN_SSI_SCK6,
- FN_SSI_SDATA5,
- FN_SSI_WS5,
- FN_SSI_SCK5,
- GFN_SSI_SDATA4,
- GFN_SSI_WS4,
- GFN_SSI_SCK4,
- GFN_SSI_SDATA3,
- GFN_SSI_WS34,
- GFN_SSI_SCK34,
- GFN_SSI_SDATA2_A,
- GFN_SSI_SDATA1_A,
- GFN_SSI_SDATA0,
- GFN_SSI_WS01239,
- GFN_SSI_SCK01239,
-
- /* GPSR7 */
- FN_HDMI1_CEC,
- FN_HDMI0_CEC,
- FN_AVS2,
- FN_AVS1,
-
- /* IPSR0 */
- IFN_AVB_MDC,
- FN_MSIOF2_SS2_C,
- IFN_AVB_MAGIC,
- FN_MSIOF2_SS1_C,
- FN_SCK4_A,
- IFN_AVB_PHY_INT,
- FN_MSIOF2_SYNC_C,
- FN_RX4_A,
- IFN_AVB_LINK,
- FN_MSIOF2_SCK_C,
- FN_TX4_A,
- IFN_AVB_AVTP_MATCH_A,
- FN_MSIOF2_RXD_C,
- FN_CTS4x_A,
- FN_FSCLKST2x_A,
- IFN_AVB_AVTP_CAPTURE_A,
- FN_MSIOF2_TXD_C,
- FN_RTS4x_TANS_A,
- IFN_IRQ0,
- FN_QPOLB,
- FN_DU_CDE,
- FN_VI4_DATA0_B,
- FN_CAN0_TX_B,
- FN_CANFD0_TX_B,
- FN_MSIOF3_SS2_E,
- IFN_IRQ1,
- FN_QPOLA,
- FN_DU_DISP,
- FN_VI4_DATA1_B,
- FN_CAN0_RX_B,
- FN_CANFD0_RX_B,
- FN_MSIOF3_SS1_E,
-
- /* IPSR1 */
- IFN_IRQ2,
- FN_QCPV_QDE,
- FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- FN_VI4_DATA2_B,
- FN_MSIOF3_SYNC_E,
- FN_PWM3_B,
- IFN_IRQ3,
- FN_QSTVB_QVE,
- FN_DU_DOTCLKOUT1,
- FN_VI4_DATA3_B,
- FN_MSIOF3_SCK_E,
- FN_PWM4_B,
- IFN_IRQ4,
- FN_QSTH_QHS,
- FN_DU_EXHSYNC_DU_HSYNC,
- FN_VI4_DATA4_B,
- FN_MSIOF3_RXD_E,
- FN_PWM5_B,
- IFN_IRQ5,
- FN_QSTB_QHE,
- FN_DU_EXVSYNC_DU_VSYNC,
- FN_VI4_DATA5_B,
- FN_FSCLKST2x_B,
- FN_MSIOF3_TXD_E,
- FN_PWM6_B,
- IFN_PWM0,
- FN_AVB_AVTP_PPS,
- FN_VI4_DATA6_B,
- FN_IECLK_B,
- IFN_PWM1_A,
- FN_HRX3_D,
- FN_VI4_DATA7_B,
- FN_IERX_B,
- IFN_PWM2_A,
- FN_HTX3_D,
- FN_IETX_B,
- IFN_A0,
- FN_LCDOUT16,
- FN_MSIOF3_SYNC_B,
- FN_VI4_DATA8,
- FN_DU_DB0,
- FN_PWM3_A,
-
- /* IPSR2 */
- IFN_A1,
- FN_LCDOUT17,
- FN_MSIOF3_TXD_B,
- FN_VI4_DATA9,
- FN_DU_DB1,
- FN_PWM4_A,
- IFN_A2,
- FN_LCDOUT18,
- FN_MSIOF3_SCK_B,
- FN_VI4_DATA10,
- FN_DU_DB2,
- FN_PWM5_A,
- IFN_A3,
- FN_LCDOUT19,
- FN_MSIOF3_RXD_B,
- FN_VI4_DATA11,
- FN_DU_DB3,
- FN_PWM6_A,
- IFN_A4,
- FN_LCDOUT20,
- FN_MSIOF3_SS1_B,
- FN_VI4_DATA12,
- FN_VI5_DATA12,
- FN_DU_DB4,
- IFN_A5,
- FN_LCDOUT21,
- FN_MSIOF3_SS2_B,
- FN_SCK4_B,
- FN_VI4_DATA13,
- FN_VI5_DATA13,
- FN_DU_DB5,
- IFN_A6,
- FN_LCDOUT22,
- FN_MSIOF2_SS1_A,
- FN_RX4_B,
- FN_VI4_DATA14,
- FN_VI5_DATA14,
- FN_DU_DB6,
- IFN_A7,
- FN_LCDOUT23,
- FN_MSIOF2_SS2_A,
- FN_TX4_B,
- FN_VI4_DATA15,
- FN_V15_DATA15,
- FN_DU_DB7,
- IFN_A8,
- FN_RX3_B,
- FN_MSIOF2_SYNC_A,
- FN_HRX4_B,
- FN_SDA6_A,
- FN_AVB_AVTP_MATCH_B,
- FN_PWM1_B,
-
- /* IPSR3 */
- IFN_A9,
- FN_MSIOF2_SCK_A,
- FN_CTS4x_B,
- FN_VI5_VSYNCx,
- IFN_A10,
- FN_MSIOF2_RXD_A,
- FN_RTS4n_TANS_B,
- FN_VI5_HSYNCx,
- IFN_A11,
- FN_TX3_B,
- FN_MSIOF2_TXD_A,
- FN_HTX4_B,
- FN_HSCK4,
- FN_VI5_FIELD,
- FN_SCL6_A,
- FN_AVB_AVTP_CAPTURE_B,
- FN_PWM2_B,
- IFN_A12,
- FN_LCDOUT12,
- FN_MSIOF3_SCK_C,
- FN_HRX4_A,
- FN_VI5_DATA8,
- FN_DU_DG4,
- IFN_A13,
- FN_LCDOUT13,
- FN_MSIOF3_SYNC_C,
- FN_HTX4_A,
- FN_VI5_DATA9,
- FN_DU_DG5,
- IFN_A14,
- FN_LCDOUT14,
- FN_MSIOF3_RXD_C,
- FN_HCTS4x,
- FN_VI5_DATA10,
- FN_DU_DG6,
- IFN_A15,
- FN_LCDOUT15,
- FN_MSIOF3_TXD_C,
- FN_HRTS4x,
- FN_VI5_DATA11,
- FN_DU_DG7,
- IFN_A16,
- FN_LCDOUT8,
- FN_VI4_FIELD,
- FN_DU_DG0,
-
- /* IPSR4 */
- IFN_A17,
- FN_LCDOUT9,
- FN_VI4_VSYNCx,
- FN_DU_DG1,
- IFN_A18,
- FN_LCDOUT10,
- FN_VI4_HSYNCx,
- FN_DU_DG2,
- IFN_A19,
- FN_LCDOUT11,
- FN_VI4_CLKENB,
- FN_DU_DG3,
- IFN_CS0x,
- FN_VI5_CLKENB,
- IFN_CS1x_A26,
- FN_VI5_CLK,
- FN_EX_WAIT0_B,
- IFN_BSx,
- FN_QSTVA_QVS,
- FN_MSIOF3_SCK_D,
- FN_SCK3,
- FN_HSCK3,
- FN_CAN1_TX,
- FN_CANFD1_TX,
- FN_IETX_A,
- IFN_RDx,
- FN_MSIOF3_SYNC_D,
- FN_RX3_A,
- FN_HRX3_A,
- FN_CAN0_TX_A,
- FN_CANFD0_TX_A,
- IFN_RD_WRx,
- FN_MSIOF3_RXD_D,
- FN_TX3_A,
- FN_HTX3_A,
- FN_CAN0_RX_A,
- FN_CANFD0_RX_A,
-
- /* IPSR5 */
- IFN_WE0x,
- FN_MSIIOF3_TXD_D,
- FN_CTS3x,
- FN_HCTS3x,
- FN_SCL6_B,
- FN_CAN_CLK,
- FN_IECLK_A,
- IFN_WE1x,
- FN_MSIOF3_SS1_D,
- FN_RTS3x_TANS,
- FN_HRTS3x,
- FN_SDA6_B,
- FN_CAN1_RX,
- FN_CANFD1_RX,
- FN_IERX_A,
- IFN_EX_WAIT0_A,
- FN_QCLK,
- FN_VI4_CLK,
- FN_DU_DOTCLKOUT0,
- IFN_D0,
- FN_MSIOF2_SS1_B,
- FN_MSIOF3_SCK_A,
- FN_VI4_DATA16,
- FN_VI5_DATA0,
- IFN_D1,
- FN_MSIOF2_SS2_B,
- FN_MSIOF3_SYNC_A,
- FN_VI4_DATA17,
- FN_VI5_DATA1,
- IFN_D2,
- FN_MSIOF3_RXD_A,
- FN_VI4_DATA18,
- FN_VI5_DATA2,
- IFN_D3,
- FN_MSIOF3_TXD_A,
- FN_VI4_DATA19,
- FN_VI5_DATA3,
- IFN_D4,
- FN_MSIOF2_SCK_B,
- FN_VI4_DATA20,
- FN_VI5_DATA4,
-
- /* IPSR6 */
- IFN_D5,
- FN_MSIOF2_SYNC_B,
- FN_VI4_DATA21,
- FN_VI5_DATA5,
- IFN_D6,
- FN_MSIOF2_RXD_B,
- FN_VI4_DATA22,
- FN_VI5_DATA6,
- IFN_D7,
- FN_MSIOF2_TXD_B,
- FN_VI4_DATA23,
- FN_VI5_DATA7,
- IFN_D8,
- FN_LCDOUT0,
- FN_MSIOF2_SCK_D,
- FN_SCK4_C,
- FN_VI4_DATA0_A,
- FN_DU_DR0,
- IFN_D9,
- FN_LCDOUT1,
- FN_MSIOF2_SYNC_D,
- FN_VI4_DATA1_A,
- FN_DU_DR1,
- IFN_D10,
- FN_LCDOUT2,
- FN_MSIOF2_RXD_D,
- FN_HRX3_B,
- FN_VI4_DATA2_A,
- FN_CTS4x_C,
- FN_DU_DR2,
- IFN_D11,
- FN_LCDOUT3,
- FN_MSIOF2_TXD_D,
- FN_HTX3_B,
- FN_VI4_DATA3_A,
- FN_RTS4x_TANS_C,
- FN_DU_DR3,
- IFN_D12,
- FN_LCDOUT4,
- FN_MSIOF2_SS1_D,
- FN_RX4_C,
- FN_VI4_DATA4_A,
- FN_DU_DR4,
-
- /* IPSR7 */
- IFN_D13,
- FN_LCDOUT5,
- FN_MSIOF2_SS2_D,
- FN_TX4_C,
- FN_VI4_DATA5_A,
- FN_DU_DR5,
- IFN_D14,
- FN_LCDOUT6,
- FN_MSIOF3_SS1_A,
- FN_HRX3_C,
- FN_VI4_DATA6_A,
- FN_DU_DR6,
- FN_SCL6_C,
- IFN_D15,
- FN_LCDOUT7,
- FN_MSIOF3_SS2_A,
- FN_HTX3_C,
- FN_VI4_DATA7_A,
- FN_DU_DR7,
- FN_SDA6_C,
- FN_FSCLKST,
- IFN_SD0_CLK,
- FN_MSIOF1_SCK_E,
- FN_STP_OPWM_0_B,
- IFN_SD0_CMD,
- FN_MSIOF1_SYNC_E,
- FN_STP_IVCXO27_0_B,
- IFN_SD0_DAT0,
- FN_MSIOF1_RXD_E,
- FN_TS_SCK0_B,
- FN_STP_ISCLK_0_B,
- IFN_SD0_DAT1,
- FN_MSIOF1_TXD_E,
- FN_TS_SPSYNC0_B,
- FN_STP_ISSYNC_0_B,
-
- /* IPSR8 */
- IFN_SD0_DAT2,
- FN_MSIOF1_SS1_E,
- FN_TS_SDAT0_B,
- FN_STP_ISD_0_B,
- IFN_SD0_DAT3,
- FN_MSIOF1_SS2_E,
- FN_TS_SDEN0_B,
- FN_STP_ISEN_0_B,
- IFN_SD1_CLK,
- FN_MSIOF1_SCK_G,
- FN_SIM0_CLK_A,
- IFN_SD1_CMD,
- FN_MSIOF1_SYNC_G,
- FN_NFCEx_B,
- FN_SIM0_D_A,
- FN_STP_IVCXO27_1_B,
- IFN_SD1_DAT0,
- FN_SD2_DAT4,
- FN_MSIOF1_RXD_G,
- FN_NFWPx_B,
- FN_TS_SCK1_B,
- FN_STP_ISCLK_1_B,
- IFN_SD1_DAT1,
- FN_SD2_DAT5,
- FN_MSIOF1_TXD_G,
- FN_NFDATA14_B,
- FN_TS_SPSYNC1_B,
- FN_STP_ISSYNC_1_B,
- IFN_SD1_DAT2,
- FN_SD2_DAT6,
- FN_MSIOF1_SS1_G,
- FN_NFDATA15_B,
- FN_TS_SDAT1_B,
- FN_STP_IOD_1_B,
- IFN_SD1_DAT3,
- FN_SD2_DAT7,
- FN_MSIOF1_SS2_G,
- FN_NFRBx_B,
- FN_TS_SDEN1_B,
- FN_STP_ISEN_1_B,
-
- /* IPSR9 */
- IFN_SD2_CLK,
- FN_NFDATA8,
- IFN_SD2_CMD,
- FN_NFDATA9,
- IFN_SD2_DAT0,
- FN_NFDATA10,
- IFN_SD2_DAT1,
- FN_NFDATA11,
- IFN_SD2_DAT2,
- FN_NFDATA12,
- IFN_SD2_DAT3,
- FN_NFDATA13,
- IFN_SD2_DS,
- FN_NFALE,
- FN_SATA_DEVSLP_B,
- IFN_SD3_CLK,
- FN_NFWEx,
-
- /* IPSR10 */
- IFN_SD3_CMD,
- FN_NFREx,
- IFN_SD3_DAT0,
- FN_NFDATA0,
- IFN_SD3_DAT1,
- FN_NFDATA1,
- IFN_SD3_DAT2,
- FN_NFDATA2,
- IFN_SD3_DAT3,
- FN_NFDATA3,
- IFN_SD3_DAT4,
- FN_SD2_CD_A,
- FN_NFDATA4,
- IFN_SD3_DAT5,
- FN_SD2_WP_A,
- FN_NFDATA5,
- IFN_SD3_DAT6,
- FN_SD3_CD,
- FN_NFDATA6,
-
- /* IPSR11 */
- IFN_SD3_DAT7,
- FN_SD3_WP,
- FN_NFDATA7,
- IFN_SD3_DS,
- FN_NFCLE,
- IFN_SD0_CD,
- FN_NFDATA14_A,
- FN_SCL2_B,
- FN_SIM0_RST_A,
- IFN_SD0_WP,
- FN_NFDATA15_A,
- FN_SDA2_B,
- IFN_SD1_CD,
- FN_NFRBx_A,
- FN_SIM0_CLK_B,
- IFN_SD1_WP,
- FN_NFCEx_A,
- FN_SIM0_D_B,
- IFN_SCK0,
- FN_HSCK1_B,
- FN_MSIOF1_SS2_B,
- FN_AUDIO_CLKC_B,
- FN_SDA2_A,
- FN_SIM0_RST_B,
- FN_STP_OPWM_0_C,
- FN_RIF0_CLK_B,
- FN_ADICHS2,
- FN_SCK5_B,
- IFN_RX0,
- FN_HRX1_B,
- FN_TS_SCK0_C,
- FN_STP_ISCLK_0_C,
- FN_RIF0_D0_B,
-
- /* IPSR12 */
- IFN_TX0,
- FN_HTX1_B,
- FN_TS_SPSYNC0_C,
- FN_STP_ISSYNC_0_C,
- FN_RIF0_D1_B,
- IFN_CTS0x,
- FN_HCTS1x_B,
- FN_MSIOF1_SYNC_B,
- FN_TS_SPSYNC1_C,
- FN_STP_ISSYNC_1_C,
- FN_RIF1_SYNC_B,
- FN_AUDIO_CLKOUT_C,
- FN_ADICS_SAMP,
- IFN_RTS0x_TANS,
- FN_HRTS1x_B,
- FN_MSIOF1_SS1_B,
- FN_AUDIO_CLKA_B,
- FN_SCL2_A,
- FN_STP_IVCXO27_1_C,
- FN_RIF0_SYNC_B,
- FN_ADICHS1,
- IFN_RX1_A,
- FN_HRX1_A,
- FN_TS_SDAT0_C,
- FN_STP_ISD_0_C,
- FN_RIF1_CLK_C,
- IFN_TX1_A,
- FN_HTX1_A,
- FN_TS_SDEN0_C,
- FN_STP_ISEN_0_C,
- FN_RIF1_D0_C,
- IFN_CTS1x,
- FN_HCTS1x_A,
- FN_MSIOF1_RXD_B,
- FN_TS_SDEN1_C,
- FN_STP_ISEN_1_C,
- FN_RIF1_D0_B,
- FN_ADIDATA,
- IFN_RTS1x_TANS,
- FN_HRTS1x_A,
- FN_MSIOF1_TXD_B,
- FN_TS_SDAT1_C,
- FN_STP_ISD_1_C,
- FN_RIF1_D1_B,
- FN_ADICHS0,
- IFN_SCK2,
- FN_SCIF_CLK_B,
- FN_MSIOF1_SCK_B,
- FN_TS_SCK1_C,
- FN_STP_ISCLK_1_C,
- FN_RIF1_CLK_B,
- FN_ADICLK,
-
- /* IPSR13 */
- IFN_TX2_A,
- FN_SD2_CD_B,
- FN_SCL1_A,
- FN_FMCLK_A,
- FN_RIF1_D1_C,
- FN_FSO_CFE_0x,
- IFN_RX2_A,
- FN_SD2_WP_B,
- FN_SDA1_A,
- FN_FMIN_A,
- FN_RIF1_SYNC_C,
- FN_FSO_CFE_1x,
- IFN_HSCK0,
- FN_MSIOF1_SCK_D,
- FN_AUDIO_CLKB_A,
- FN_SSI_SDATA1_B,
- FN_TS_SCK0_D,
- FN_STP_ISCLK_0_D,
- FN_RIF0_CLK_C,
- FN_RX5_B,
- IFN_HRX0,
- FN_MSIOF1_RXD_D,
- FN_SSI_SDATA2_B,
- FN_TS_SDEN0_D,
- FN_STP_ISEN_0_D,
- FN_RIF0_D0_C,
- IFN_HTX0,
- FN_MSIOF1_TXD_D,
- FN_SSI_SDATA9_B,
- FN_TS_SDAT0_D,
- FN_STP_ISD_0_D,
- FN_RIF0_D1_C,
- IFN_HCTS0x,
- FN_RX2_B,
- FN_MSIOF1_SYNC_D,
- FN_SSI_SCK9_A,
- FN_TS_SPSYNC0_D,
- FN_STP_ISSYNC_0_D,
- FN_RIF0_SYNC_C,
- FN_AUDIO_CLKOUT1_A,
- IFN_HRTS0x,
- FN_TX2_B,
- FN_MSIOF1_SS1_D,
- FN_SSI_WS9_A,
- FN_STP_IVCXO27_0_D,
- FN_BPFCLK_A,
- FN_AUDIO_CLKOUT2_A,
- IFN_MSIOF0_SYNC,
- FN_AUDIO_CLKOUT_A,
- FN_TX5_B,
- FN_BPFCLK_D,
-
- /* IPSR14 */
- IFN_MSIOF0_SS1,
- FN_RX5_A,
- FN_NFWPx_A,
- FN_AUDIO_CLKA_C,
- FN_SSI_SCK2_A,
- FN_STP_IVCXO27_0_C,
- FN_AUDIO_CLKOUT3_A,
- FN_TCLK1_B,
- IFN_MSIOF0_SS2,
- FN_TX5_A,
- FN_MSIOF1_SS2_D,
- FN_AUDIO_CLKC_A,
- FN_SSI_WS2_A,
- FN_STP_OPWM_0_D,
- FN_AUDIO_CLKOUT_D,
- FN_SPEEDIN_B,
- IFN_MLB_CLK,
- FN_MSIOF1_SCK_F,
- FN_SCL1_B,
- IFN_MLB_SIG,
- FN_RX1_B,
- FN_MSIOF1_SYNC_F,
- FN_SDA1_B,
- IFN_MLB_DAT,
- FN_TX1_B,
- FN_MSIOF1_RXD_F,
- IFN_SSI_SCK01239,
- FN_MSIOF1_TXD_F,
- FN_MOUT0,
- IFN_SSI_WS01239,
- FN_MSIOF1_SS1_F,
- FN_MOUT1,
- IFN_SSI_SDATA0,
- FN_MSIOF1_SS2_F,
- FN_MOUT2,
-
- /* IPSR15 */
- IFN_SSI_SDATA1_A,
- FN_MOUT5,
- IFN_SSI_SDATA2_A,
- FN_SSI_SCK1_B,
- FN_MOUT6,
- IFN_SSI_SCK34,
- FN_MSIOF1_SS1_A,
- FN_STP_OPWM_0_A,
- IFN_SSI_WS34,
- FN_HCTS2x_A,
- FN_MSIOF1_SS2_A,
- FN_STP_IVCXO27_0_A,
- IFN_SSI_SDATA3,
- FN_HRTS2x_A,
- FN_MSIOF1_TXD_A,
- FN_TS_SCK0_A,
- FN_STP_ISCLK_0_A,
- FN_RIF0_D1_A,
- FN_RIF2_D0_A,
- IFN_SSI_SCK4,
- FN_HRX2_A,
- FN_MSIOF1_SCK_A,
- FN_TS_SDAT0_A,
- FN_STP_ISD_0_A,
- FN_RIF0_CLK_A,
- FN_RIF2_CLK_A,
- IFN_SSI_WS4,
- FN_HTX2_A,
- FN_MSIOF1_SYNC_A,
- FN_TS_SDEN0_A,
- FN_STP_ISEN_0_A,
- FN_RIF0_SYNC_A,
- FN_RIF2_SYNC_A,
- IFN_SSI_SDATA4,
- FN_HSCK2_A,
- FN_MSIOF1_RXD_A,
- FN_TS_SPSYNC0_A,
- FN_STP_ISSYNC_0_A,
- FN_RIF0_D0_A,
- FN_RIF2_D1_A,
-
- /* IPSR16 */
- IFN_SSI_SCK6,
- FN_SIM0_RST_D,
- IFN_SSI_WS6,
- FN_SIM0_D_D,
- IFN_SSI_SDATA6,
- FN_SIM0_CLK_D,
- FN_SATA_DEVSLP_A,
- IFN_SSI_SCK78,
- FN_HRX2_B,
- FN_MSIOF1_SCK_C,
- FN_TS_SCK1_A,
- FN_STP_ISCLK_1_A,
- FN_RIF1_CLK_A,
- FN_RIF3_CLK_A,
- IFN_SSI_WS78,
- FN_HTX2_B,
- FN_MSIOF1_SYNC_C,
- FN_TS_SDAT1_A,
- FN_STP_ISD_1_A,
- FN_RIF1_SYNC_A,
- FN_RIF3_SYNC_A,
- IFN_SSI_SDATA7,
- FN_HCTS2x_B,
- FN_MSIOF1_RXD_C,
- FN_TS_SDEN1_A,
- FN_STP_ISEN_1_A,
- FN_RIF1_D0_A,
- FN_RIF3_D0_A,
- FN_TCLK2_A,
- IFN_SSI_SDATA8,
- FN_HRTS2x_B,
- FN_MSIOF1_TXD_C,
- FN_TS_SPSYNC1_A,
- FN_STP_ISSYNC_1_A,
- FN_RIF1_D1_A,
- FN_RIF3_D1_A,
- IFN_SSI_SDATA9_A,
- FN_HSCK2_B,
- FN_MSIOF1_SS1_C,
- FN_HSCK1_A,
- FN_SSI_WS1_B,
- FN_SCK1,
- FN_STP_IVCXO27_1_A,
- FN_SCK5_A,
-
- /* IPSR17 */
- IFN_AUDIO_CLKA_A,
- FN_CC5_OSCOUT,
- IFN_AUDIO_CLKB_B,
- FN_SCIF_CLK_A,
- FN_STP_IVCXO27_1_D,
- FN_REMOCON_A,
- FN_TCLK1_A,
- IFN_USB0_PWEN,
- FN_SIM0_RST_C,
- FN_TS_SCK1_D,
- FN_STP_ISCLK_1_D,
- FN_BPFCLK_B,
- FN_RIF3_CLK_B,
- FN_HSCK2_C,
- IFN_USB0_OVC,
- FN_SIM0_D_C,
- FN_TS_SDAT1_D,
- FN_STP_ISD_1_D,
- FN_RIF3_SYNC_B,
- FN_HRX2_C,
- IFN_USB1_PWEN,
- FN_SIM0_CLK_C,
- FN_SSI_SCK1_A,
- FN_TS_SCK0_E,
- FN_STP_ISCLK_0_E,
- FN_FMCLK_B,
- FN_RIF2_CLK_B,
- FN_SPEEDIN_A,
- FN_HTX2_C,
- IFN_USB1_OVC,
- FN_MSIOF1_SS2_C,
- FN_SSI_WS1_A,
- FN_TS_SDAT0_E,
- FN_STP_ISD_0_E,
- FN_FMIN_B,
- FN_RIF2_SYNC_B,
- FN_REMOCON_B,
- FN_HCTS2x_C,
- IFN_USB30_PWEN,
- FN_AUDIO_CLKOUT_B,
- FN_SSI_SCK2_B,
- FN_TS_SDEN1_D,
- FN_STP_ISEN_1_D,
- FN_STP_OPWM_0_E,
- FN_RIF3_D0_B,
- FN_TCLK2_B,
- FN_TPU0TO0,
- FN_BPFCLK_C,
- FN_HRTS2x_C,
- IFN_USB30_OVC,
- FN_AUDIO_CLKOUT1_B,
- FN_SSI_WS2_B,
- FN_TS_SPSYNC1_D,
- FN_STP_ISSYNC_1_D,
- FN_STP_IVCXO27_0_E,
- FN_RIF3_D1_B,
- FN_FSO_TOEx,
- FN_TPU0TO1,
-
- /* IPSR18 */
- IFN_USB3_PWEN,
- FN_AUDIO_CLKOUT2_B,
- FN_SSI_SCK9_B,
- FN_TS_SDEN0_E,
- FN_STP_ISEN_0_E,
- FN_RIF2_D0_B,
- FN_TPU0TO2,
- FN_FMCLK_C,
- FN_FMCLK_D,
- IFN_USB3_OVC,
- FN_AUDIO_CLKOUT3_B,
- FN_SSI_WS9_B,
- FN_TS_SPSYNC0_E,
- FN_STP_ISSYNC_0_E,
- FN_RIF2_D1_B,
- FN_TPU0TO3,
- FN_FMIN_C,
- FN_FMIN_D,
-
- /* MOD_SEL0 */
- /* sel_msiof3[3](0,1,2,3,4) */
- FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
- FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
- FN_SEL_MSIOF3_4,
- /* sel_msiof2[2](0,1,2,3) */
- FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
- FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
- /* sel_msiof1[3](0,1,2,3,4,5,6) */
- FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
- FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
- FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
- FN_SEL_MSIOF1_6,
- /* sel_lbsc[1](0,1) */
- FN_SEL_LBSC_0, FN_SEL_LBSC_1,
- /* sel_iebus[1](0,1) */
- FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
- /* sel_i2c2[1](0,1) */
- FN_SEL_I2C2_0, FN_SEL_I2C2_1,
- /* sel_i2c1[1](0,1) */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1,
- /* sel_hscif4[1](0,1) */
- FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
- /* sel_hscif3[2](0,1,2,3) */
- FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
- FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
- /* sel_hscif1[1](0,1) */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* reserved[1] */
- /* sel_hscif2[2](0,1,2) */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2,
- /* sel_etheravb[1](0,1) */
- FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
- /* sel_drif3[1](0,1) */
- FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
- /* sel_drif2[1](0,1) */
- FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
- /* sel_drif1[2](0,1,2) */
- FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
- FN_SEL_DRIF1_2,
- /* sel_drif0[2](0,1,2) */
- FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
- FN_SEL_DRIF0_2,
- /* sel_canfd0[1](0,1) */
- FN_SEL_CANFD_0, FN_SEL_CANFD_1,
- /* sel_adg_a[2](0,1,2) */
- FN_SEL_ADG_A_0, FN_SEL_ADG_A_1,
- FN_SEL_ADG_A_2,
- /* reserved[3]*/
-
- /* MOD_SEL1 */
- /* sel_tsif1[2](0,1,2,3) */
- FN_SEL_TSIF1_0, FN_SEL_TSIF1_1,
- FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
- /* sel_tsif0[3](0,1,2,3,4) */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_TSIF0_4,
- /* sel_timer_tmu1[1](0,1) */
- FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,
- /* sel_ssp1_1[2](0,1,2,3) */
- FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,
- FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,
- /* sel_ssp1_0[3](0,1,2,3,4) */
- FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
- FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,
- FN_SEL_SSP1_0_4,
- /* sel_ssi1[1](0,1) */
- FN_SEL_SSI_0, FN_SEL_SSI_1,
- /* sel_speed_pulse_if[1](0,1) */
- FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
- /* sel_simcard[2](0,1,2,3) */
- FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,
- FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
- /* sel_sdhi2[1](0,1) */
- FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
- /* sel_scif4[2](0,1,2) */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
- FN_SEL_SCIF4_2,
- /* sel_scif3[1](0,1) */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- /* sel_scif2[1](0,1) */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
- /* sel_scif1[1](0,1) */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
- /* sel_scif[1](0,1) */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* sel_remocon[1](0,1) */
- FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
- /* reserved[8..7] */
- /* sel_rcan0[1](0,1) */
- FN_SEL_RCAN_0, FN_SEL_RCAN_1,
- /* sel_pwm6[1](0,1) */
- FN_SEL_PWM6_0, FN_SEL_PWM6_1,
- /* sel_pwm5[1](0,1) */
- FN_SEL_PWM5_0, FN_SEL_PWM5_1,
- /* sel_pwm4[1](0,1) */
- FN_SEL_PWM4_0, FN_SEL_PWM4_1,
- /* sel_pwm3[1](0,1) */
- FN_SEL_PWM3_0, FN_SEL_PWM3_1,
- /* sel_pwm2[1](0,1) */
- FN_SEL_PWM2_0, FN_SEL_PWM2_1,
- /* sel_pwm1[1](0,1) */
- FN_SEL_PWM1_0, FN_SEL_PWM1_1,
-
- /* MOD_SEL2 */
- /* i2c_sel_5[1](0,1) */
- FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
- /* i2c_sel_3[1](0,1) */
- FN_I2C_SEL_3_0, FN_I2C_SEL_3_1,
- /* i2c_sel_0[1](0,1) */
- FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
- /* sel_fm[2](0,1,2,3) */
- FN_SEL_FM_0, FN_SEL_FM_1,
- FN_SEL_FM_2, FN_SEL_FM_3,
- /* sel_scif5[1](0,1) */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* sel_i2c6[3](0,1,2) */
- FN_SEL_I2C6_0, FN_SEL_I2C6_1,
- FN_SEL_I2C6_2,
- /* sel_ndfc[1](0,1) */
- FN_SEL_NDFC_0, FN_SEL_NDFC_1,
- /* sel_ssi2[1](0,1) */
- FN_SEL_SSI2_0, FN_SEL_SSI2_1,
- /* sel_ssi9[1](0,1) */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* sel_timer_tmu2[1](0,1) */
- FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,
- /* sel_adg_b[1](0,1) */
- FN_SEL_ADG_B_0, FN_SEL_ADG_B_1,
- /* sel_adg_c[1](0,1) */
- FN_SEL_ADG_C_0, FN_SEL_ADG_C_1,
- /* reserved[16..16] */
- /* reserved[15..8] */
- /* reserved[7..1] */
- /* sel_vin4[1](0,1) */
- FN_SEL_VIN4_0, FN_SEL_VIN4_1,
-
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- /* GPSR0 */
- D15_GMARK,
- D14_GMARK,
- D13_GMARK,
- D12_GMARK,
- D11_GMARK,
- D10_GMARK,
- D9_GMARK,
- D8_GMARK,
- D7_GMARK,
- D6_GMARK,
- D5_GMARK,
- D4_GMARK,
- D3_GMARK,
- D2_GMARK,
- D1_GMARK,
- D0_GMARK,
-
- /* GPSR1 */
- CLKOUT_GMARK,
- EX_WAIT0_A_GMARK,
- WE1x_GMARK,
- WE0x_GMARK,
- RD_WRx_GMARK,
- RDx_GMARK,
- BSx_GMARK,
- CS1x_A26_GMARK,
- CS0x_GMARK,
- A19_GMARK,
- A18_GMARK,
- A17_GMARK,
- A16_GMARK,
- A15_GMARK,
- A14_GMARK,
- A13_GMARK,
- A12_GMARK,
- A11_GMARK,
- A10_GMARK,
- A9_GMARK,
- A8_GMARK,
- A7_GMARK,
- A6_GMARK,
- A5_GMARK,
- A4_GMARK,
- A3_GMARK,
- A2_GMARK,
- A1_GMARK,
- A0_GMARK,
-
- /* GPSR2 */
- AVB_AVTP_CAPTURE_A_GMARK,
- AVB_AVTP_MATCH_A_GMARK,
- AVB_LINK_GMARK,
- AVB_PHY_INT_GMARK,
- AVB_MAGIC_GMARK,
- AVB_MDC_GMARK,
- PWM2_A_GMARK,
- PWM1_A_GMARK,
- PWM0_GMARK,
- IRQ5_GMARK,
- IRQ4_GMARK,
- IRQ3_GMARK,
- IRQ2_GMARK,
- IRQ1_GMARK,
- IRQ0_GMARK,
-
- /* GPSR3 */
- SD1_WP_GMARK,
- SD1_CD_GMARK,
- SD0_WP_GMARK,
- SD0_CD_GMARK,
- SD1_DAT3_GMARK,
- SD1_DAT2_GMARK,
- SD1_DAT1_GMARK,
- SD1_DAT0_GMARK,
- SD1_CMD_GMARK,
- SD1_CLK_GMARK,
- SD0_DAT3_GMARK,
- SD0_DAT2_GMARK,
- SD0_DAT1_GMARK,
- SD0_DAT0_GMARK,
- SD0_CMD_GMARK,
- SD0_CLK_GMARK,
-
- /* GPSR4 */
- SD3_DS_GMARK,
- SD3_DAT7_GMARK,
- SD3_DAT6_GMARK,
- SD3_DAT5_GMARK,
- SD3_DAT4_GMARK,
- SD3_DAT3_GMARK,
- SD3_DAT2_GMARK,
- SD3_DAT1_GMARK,
- SD3_DAT0_GMARK,
- SD3_CMD_GMARK,
- SD3_CLK_GMARK,
- SD2_DS_GMARK,
- SD2_DAT3_GMARK,
- SD2_DAT2_GMARK,
- SD2_DAT1_GMARK,
- SD2_DAT0_GMARK,
- SD2_CMD_GMARK,
- SD2_CLK_GMARK,
-
- /* GPSR5 */
- MLB_DAT_GMARK,
- MLB_SIG_GMARK,
- MLB_CLK_GMARK,
- MSIOF0_RXD_MARK,
- MSIOF0_SS2_GMARK,
- MSIOF0_TXD_MARK,
- MSIOF0_SS1_GMARK,
- MSIOF0_SYNC_GMARK,
- MSIOF0_SCK_MARK,
- HRTS0x_GMARK,
- HCTS0x_GMARK,
- HTX0_GMARK,
- HRX0_GMARK,
- HSCK0_GMARK,
- RX2_A_GMARK,
- TX2_A_GMARK,
- SCK2_GMARK,
- RTS1x_TANS_GMARK,
- CTS1x_GMARK,
- TX1_A_GMARK,
- RX1_A_GMARK,
- RTS0x_TANS_GMARK,
- CTS0x_GMARK,
- TX0_GMARK,
- RX0_GMARK,
- SCK0_GMARK,
-
- /* GPSR6 */
- USB3_OVC_GMARK,
- USB3_PWEN_GMARK,
- USB30_OVC_GMARK,
- USB30_PWEN_GMARK,
- USB1_OVC_GMARK,
- USB1_PWEN_GMARK,
- USB0_OVC_GMARK,
- USB0_PWEN_GMARK,
- AUDIO_CLKB_B_GMARK,
- AUDIO_CLKA_A_GMARK,
- SSI_SDATA9_A_GMARK,
- SSI_SDATA8_GMARK,
- SSI_SDATA7_GMARK,
- SSI_WS78_GMARK,
- SSI_SCK78_GMARK,
- SSI_SDATA6_GMARK,
- SSI_WS6_GMARK,
- SSI_SCK6_GMARK,
- SSI_SDATA5_MARK,
- SSI_WS5_MARK,
- SSI_SCK5_MARK,
- SSI_SDATA4_GMARK,
- SSI_WS4_GMARK,
- SSI_SCK4_GMARK,
- SSI_SDATA3_GMARK,
- SSI_WS34_GMARK,
- SSI_SCK34_GMARK,
- SSI_SDATA2_A_GMARK,
- SSI_SDATA1_A_GMARK,
- SSI_SDATA0_GMARK,
- SSI_WS01239_GMARK,
- SSI_SCK01239_GMARK,
-
- /* GPSR7 */
- HDMI1_CEC_MARK,
- HDMI0_CEC_MARK,
- AVS2_MARK,
- AVS1_MARK,
-
- /* IPSR0 */
- AVB_MDC_IMARK,
- MSIOF2_SS2_C_MARK,
- AVB_MAGIC_IMARK,
- MSIOF2_SS1_C_MARK,
- SCK4_A_MARK,
- AVB_PHY_INT_IMARK,
- MSIOF2_SYNC_C_MARK,
- RX4_A_MARK,
- AVB_LINK_IMARK,
- MSIOF2_SCK_C_MARK,
- TX4_A_MARK,
- AVB_AVTP_MATCH_A_IMARK,
- MSIOF2_RXD_C_MARK,
- CTS4x_A_MARK,
- FSCLKST2x_A_MARK,
- AVB_AVTP_CAPTURE_A_IMARK,
- MSIOF2_TXD_C_MARK,
- RTS4x_TANS_A_MARK,
- IRQ0_IMARK,
- QPOLB_MARK,
- DU_CDE_MARK,
- VI4_DATA0_B_MARK,
- CAN0_TX_B_MARK,
- CANFD0_TX_B_MARK,
- MSIOF3_SS2_E_MARK,
- IRQ1_IMARK,
- QPOLA_MARK,
- DU_DISP_MARK,
- VI4_DATA1_B_MARK,
- CAN0_RX_B_MARK,
- CANFD0_RX_B_MARK,
- MSIOF3_SS1_E_MARK,
-
- /* IPSR1 */
- IRQ2_IMARK,
- QCPV_QDE_MARK,
- DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
- VI4_DATA2_B_MARK,
- MSIOF3_SYNC_E_MARK,
- PWM3_B_MARK,
- IRQ3_IMARK,
- QSTVB_QVE_MARK,
- DU_DOTCLKOUT1_MARK,
- VI4_DATA3_B_MARK,
- MSIOF3_SCK_E_MARK,
- PWM4_B_MARK,
- IRQ4_IMARK,
- QSTH_QHS_MARK,
- DU_EXHSYNC_DU_HSYNC_MARK,
- VI4_DATA4_B_MARK,
- MSIOF3_RXD_E_MARK,
- PWM5_B_MARK,
- IRQ5_IMARK,
- QSTB_QHE_MARK,
- DU_EXVSYNC_DU_VSYNC_MARK,
- VI4_DATA5_B_MARK,
- FSCLKST2x_B_MARK,
- MSIOF3_TXD_E_MARK,
- PWM6_B_MARK,
- PWM0_IMARK,
- AVB_AVTP_PPS_MARK,
- VI4_DATA6_B_MARK,
- IECLK_B_MARK,
- PWM1_A_IMARK,
- HRX3_D_MARK,
- VI4_DATA7_B_MARK,
- IERX_B_MARK,
- PWM2_A_IMARK,
- PWMFSW0_MARK,
- HTX3_D_MARK,
- IETX_B_MARK,
- A0_IMARK,
- LCDOUT16_MARK,
- MSIOF3_SYNC_B_MARK,
- VI4_DATA8_MARK,
- DU_DB0_MARK,
- PWM3_A_MARK,
-
- /* IPSR2 */
- A1_IMARK,
- LCDOUT17_MARK,
- MSIOF3_TXD_B_MARK,
- VI4_DATA9_MARK,
- DU_DB1_MARK,
- PWM4_A_MARK,
- A2_IMARK,
- LCDOUT18_MARK,
- MSIOF3_SCK_B_MARK,
- VI4_DATA10_MARK,
- DU_DB2_MARK,
- PWM5_A_MARK,
- A3_IMARK,
- LCDOUT19_MARK,
- MSIOF3_RXD_B_MARK,
- VI4_DATA11_MARK,
- DU_DB3_MARK,
- PWM6_A_MARK,
- A4_IMARK,
- LCDOUT20_MARK,
- MSIOF3_SS1_B_MARK,
- VI4_DATA12_MARK,
- VI5_DATA12_MARK,
- DU_DB4_MARK,
- A5_IMARK,
- LCDOUT21_MARK,
- MSIOF3_SS2_B_MARK,
- SCK4_B_MARK,
- VI4_DATA13_MARK,
- VI5_DATA13_MARK,
- DU_DB5_MARK,
- A6_IMARK,
- LCDOUT22_MARK,
- MSIOF2_SS1_A_MARK,
- RX4_B_MARK,
- VI4_DATA14_MARK,
- VI5_DATA14_MARK,
- DU_DB6_MARK,
- A7_IMARK,
- LCDOUT23_MARK,
- MSIOF2_SS2_A_MARK,
- TX4_B_MARK,
- VI4_DATA15_MARK,
- V15_DATA15_MARK,
- DU_DB7_MARK,
- A8_IMARK,
- RX3_B_MARK,
- MSIOF2_SYNC_A_MARK,
- HRX4_B_MARK,
- SDA6_A_MARK,
- AVB_AVTP_MATCH_B_MARK,
- PWM1_B_MARK,
-
- /* IPSR3 */
- A9_IMARK,
- MSIOF2_SCK_A_MARK,
- CTS4x_B_MARK,
- VI5_VSYNCx_MARK,
- A10_IMARK,
- MSIOF2_RXD_A_MARK,
- RTS4n_TANS_B_MARK,
- VI5_HSYNCx_MARK,
- A11_IMARK,
- TX3_B_MARK,
- MSIOF2_TXD_A_MARK,
- HTX4_B_MARK,
- HSCK4_MARK,
- VI5_FIELD_MARK,
- SCL6_A_MARK,
- AVB_AVTP_CAPTURE_B_MARK,
- PWM2_B_MARK,
- A12_IMARK,
- LCDOUT12_MARK,
- MSIOF3_SCK_C_MARK,
- HRX4_A_MARK,
- VI5_DATA8_MARK,
- DU_DG4_MARK,
- A13_IMARK,
- LCDOUT13_MARK,
- MSIOF3_SYNC_C_MARK,
- HTX4_A_MARK,
- VI5_DATA9_MARK,
- DU_DG5_MARK,
- A14_IMARK,
- LCDOUT14_MARK,
- MSIOF3_RXD_C_MARK,
- HCTS4x_MARK,
- VI5_DATA10_MARK,
- DU_DG6_MARK,
- A15_IMARK,
- LCDOUT15_MARK,
- MSIOF3_TXD_C_MARK,
- HRTS4x_MARK,
- VI5_DATA11_MARK,
- DU_DG7_MARK,
- A16_IMARK,
- LCDOUT8_MARK,
- VI4_FIELD_MARK,
- DU_DG0_MARK,
-
- /* IPSR4 */
- A17_IMARK,
- LCDOUT9_MARK,
- VI4_VSYNCx_MARK,
- DU_DG1_MARK,
- A18_IMARK,
- LCDOUT10_MARK,
- VI4_HSYNCx_MARK,
- DU_DG2_MARK,
- A19_IMARK,
- LCDOUT11_MARK,
- VI4_CLKENB_MARK,
- DU_DG3_MARK,
- CS0x_IMARK,
- VI5_CLKENB_MARK,
- CS1x_A26_IMARK,
- VI5_CLK_MARK,
- EX_WAIT0_B_MARK,
- BSx_IMARK,
- QSTVA_QVS_MARK,
- MSIOF3_SCK_D_MARK,
- SCK3_MARK,
- HSCK3_MARK,
- CAN1_TX_MARK,
- CANFD1_TX_MARK,
- IETX_A_MARK,
- RDx_IMARK,
- MSIOF3_SYNC_D_MARK,
- RX3_A_MARK,
- HRX3_A_MARK,
- CAN0_TX_A_MARK,
- CANFD0_TX_A_MARK,
- RD_WRx_IMARK,
- MSIOF3_RXD_D_MARK,
- TX3_A_MARK,
- HTX3_A_MARK,
- CAN0_RX_A_MARK,
- CANFD0_RX_A_MARK,
-
- /* IPSR5 */
- WE0x_IMARK,
- MSIIOF3_TXD_D_MARK,
- CTS3x_MARK,
- HCTS3x_MARK,
- SCL6_B_MARK,
- CAN_CLK_MARK,
- IECLK_A_MARK,
- WE1x_IMARK,
- MSIOF3_SS1_D_MARK,
- RTS3x_TANS_MARK,
- HRTS3x_MARK,
- SDA6_B_MARK,
- CAN1_RX_MARK,
- CANFD1_RX_MARK,
- IERX_A_MARK,
- EX_WAIT0_A_IMARK,
- QCLK_MARK,
- VI4_CLK_MARK,
- DU_DOTCLKOUT0_MARK,
- D0_IMARK,
- MSIOF2_SS1_B_MARK,
- MSIOF3_SCK_A_MARK,
- VI4_DATA16_MARK,
- VI5_DATA0_MARK,
- D1_IMARK,
- MSIOF2_SS2_B_MARK,
- MSIOF3_SYNC_A_MARK,
- VI4_DATA17_MARK,
- VI5_DATA1_MARK,
- D2_IMARK,
- MSIOF3_RXD_A_MARK,
- VI4_DATA18_MARK,
- VI5_DATA2_MARK,
- D3_IMARK,
- MSIOF3_TXD_A_MARK,
- VI4_DATA19_MARK,
- VI5_DATA3_MARK,
- D4_IMARK,
- MSIOF2_SCK_B_MARK,
- VI4_DATA20_MARK,
- VI5_DATA4_MARK,
-
- /* IPSR6 */
- D5_IMARK,
- MSIOF2_SYNC_B_MARK,
- VI4_DATA21_MARK,
- VI5_DATA5_MARK,
- D6_IMARK,
- MSIOF2_RXD_B_MARK,
- VI4_DATA22_MARK,
- VI5_DATA6_MARK,
- D7_IMARK,
- MSIOF2_TXD_B_MARK,
- VI4_DATA23_MARK,
- VI5_DATA7_MARK,
- D8_IMARK,
- LCDOUT0_MARK,
- MSIOF2_SCK_D_MARK,
- SCK4_C_MARK,
- VI4_DATA0_A_MARK,
- DU_DR0_MARK,
- D9_IMARK,
- LCDOUT1_MARK,
- MSIOF2_SYNC_D_MARK,
- VI4_DATA1_A_MARK,
- DU_DR1_MARK,
- D10_IMARK,
- LCDOUT2_MARK,
- MSIOF2_RXD_D_MARK,
- HRX3_B_MARK,
- VI4_DATA2_A_MARK,
- CTS4x_C_MARK,
- DU_DR2_MARK,
- D11_IMARK,
- LCDOUT3_MARK,
- MSIOF2_TXD_D_MARK,
- HTX3_B_MARK,
- VI4_DATA3_A_MARK,
- RTS4x_TANS_C_MARK,
- DU_DR3_MARK,
- D12_IMARK,
- LCDOUT4_MARK,
- MSIOF2_SS1_D_MARK,
- RX4_C_MARK,
- VI4_DATA4_A_MARK,
- DU_DR4_MARK,
-
- /* IPSR7 */
- D13_IMARK,
- LCDOUT5_MARK,
- MSIOF2_SS2_D_MARK,
- TX4_C_MARK,
- VI4_DATA5_A_MARK,
- DU_DR5_MARK,
- D14_IMARK,
- LCDOUT6_MARK,
- MSIOF3_SS1_A_MARK,
- HRX3_C_MARK,
- VI4_DATA6_A_MARK,
- DU_DR6_MARK,
- SCL6_C_MARK,
- D15_IMARK,
- LCDOUT7_MARK,
- MSIOF3_SS2_A_MARK,
- HTX3_C_MARK,
- VI4_DATA7_A_MARK,
- DU_DR7_MARK,
- SDA6_C_MARK,
- FSCLKST_MARK,
- SD0_CLK_IMARK,
- MSIOF1_SCK_E_MARK,
- STP_OPWM_0_B_MARK,
- SD0_CMD_IMARK,
- MSIOF1_SYNC_E_MARK,
- STP_IVCXO27_0_B_MARK,
- SD0_DAT0_IMARK,
- MSIOF1_RXD_E_MARK,
- TS_SCK0_B_MARK,
- STP_ISCLK_0_B_MARK,
- SD0_DAT1_IMARK,
- MSIOF1_TXD_E_MARK,
- TS_SPSYNC0_B_MARK,
- STP_ISSYNC_0_B_MARK,
-
- /* IPSR8 */
- SD0_DAT2_IMARK,
- MSIOF1_SS1_E_MARK,
- TS_SDAT0_B_MARK,
- STP_ISD_0_B_MARK,
- SD0_DAT3_IMARK,
- MSIOF1_SS2_E_MARK,
- TS_SDEN0_B_MARK,
- STP_ISEN_0_B_MARK,
- SD1_CLK_IMARK,
- MSIOF1_SCK_G_MARK,
- SIM0_CLK_A_MARK,
- SD1_CMD_IMARK,
- MSIOF1_SYNC_G_MARK,
- NFCEx_B_MARK,
- SIM0_D_A_MARK,
- STP_IVCXO27_1_B_MARK,
- SD1_DAT0_IMARK,
- SD2_DAT4_MARK,
- MSIOF1_RXD_G_MARK,
- NFWPx_B_MARK,
- TS_SCK1_B_MARK,
- STP_ISCLK_1_B_MARK,
- SD1_DAT1_IMARK,
- SD2_DAT5_MARK,
- MSIOF1_TXD_G_MARK,
- NFDATA14_B_MARK,
- TS_SPSYNC1_B_MARK,
- STP_ISSYNC_1_B_MARK,
- SD1_DAT2_IMARK,
- SD2_DAT6_MARK,
- MSIOF1_SS1_G_MARK,
- NFDATA15_B_MARK,
- TS_SDAT1_B_MARK,
- STP_IOD_1_B_MARK,
- SD1_DAT3_IMARK,
- SD2_DAT7_MARK,
- MSIOF1_SS2_G_MARK,
- NFRBx_B_MARK,
- TS_SDEN1_B_MARK,
- STP_ISEN_1_B_MARK,
-
- /* IPSR9 */
- SD2_CLK_IMARK,
- NFDATA8_MARK,
- SD2_CMD_IMARK,
- NFDATA9_MARK,
- SD2_DAT0_IMARK,
- NFDATA10_MARK,
- SD2_DAT1_IMARK,
- NFDATA11_MARK,
- SD2_DAT2_IMARK,
- NFDATA12_MARK,
- SD2_DAT3_IMARK,
- NFDATA13_MARK,
- SD2_DS_IMARK,
- NFALE_MARK,
- SATA_DEVSLP_B_MARK,
- SD3_CLK_IMARK,
- NFWEx_MARK,
-
- /* IPSR10 */
- SD3_CMD_IMARK,
- NFREx_MARK,
- SD3_DAT0_IMARK,
- NFDATA0_MARK,
- SD3_DAT1_IMARK,
- NFDATA1_MARK,
- SD3_DAT2_IMARK,
- NFDATA2_MARK,
- SD3_DAT3_IMARK,
- NFDATA3_MARK,
- SD3_DAT4_IMARK,
- SD2_CD_A_MARK,
- NFDATA4_MARK,
- SD3_DAT5_IMARK,
- SD2_WP_A_MARK,
- NFDATA5_MARK,
- SD3_DAT6_IMARK,
- SD3_CD_MARK,
- NFDATA6_MARK,
-
- /* IPSR11 */
- SD3_DAT7_IMARK,
- SD3_WP_MARK,
- NFDATA7_MARK,
- SD3_DS_IMARK,
- NFCLE_MARK,
- SD0_CD_IMARK,
- NFDATA14_A_MARK,
- SCL2_B_MARK,
- SIM0_RST_A_MARK,
- SD0_WP_IMARK,
- NFDATA15_A_MARK,
- SDA2_B_MARK,
- SD1_CD_IMARK,
- NFRBx_A_MARK,
- SIM0_CLK_B_MARK,
- SD1_WP_IMARK,
- NFCEx_A_MARK,
- SIM0_D_B_MARK,
- SCK0_IMARK,
- HSCK1_B_MARK,
- MSIOF1_SS2_B_MARK,
- AUDIO_CLKC_B_MARK,
- SDA2_A_MARK,
- SIM0_RST_B_MARK,
- STP_OPWM_0_C_MARK,
- RIF0_CLK_B_MARK,
- ADICHS2_MARK,
- SCK5_B_MARK,
- RX0_IMARK,
- HRX1_B_MARK,
- TS_SCK0_C_MARK,
- STP_ISCLK_0_C_MARK,
- RIF0_D0_B_MARK,
-
- /* IPSR12 */
- TX0_IMARK,
- HTX1_B_MARK,
- TS_SPSYNC0_C_MARK,
- STP_ISSYNC_0_C_MARK,
- RIF0_D1_B_MARK,
- CTS0x_IMARK,
- HCTS1x_B_MARK,
- MSIOF1_SYNC_B_MARK,
- TS_SPSYNC1_C_MARK,
- STP_ISSYNC_1_C_MARK,
- RIF1_SYNC_B_MARK,
- AUDIO_CLKOUT_C_MARK,
- ADICS_SAMP_MARK,
- RTS0x_TANS_IMARK,
- HRTS1x_B_MARK,
- MSIOF1_SS1_B_MARK,
- AUDIO_CLKA_B_MARK,
- SCL2_A_MARK,
- STP_IVCXO27_1_C_MARK,
- RIF0_SYNC_B_MARK,
- ADICHS1_MARK,
- RX1_A_IMARK,
- HRX1_A_MARK,
- TS_SDAT0_C_MARK,
- STP_ISD_0_C_MARK,
- RIF1_CLK_C_MARK,
- TX1_A_IMARK,
- HTX1_A_MARK,
- TS_SDEN0_C_MARK,
- STP_ISEN_0_C_MARK,
- RIF1_D0_C_MARK,
- CTS1x_IMARK,
- HCTS1x_A_MARK,
- MSIOF1_RXD_B_MARK,
- TS_SDEN1_C_MARK,
- STP_ISEN_1_C_MARK,
- RIF1_D0_B_MARK,
- ADIDATA_MARK,
- RTS1x_TANS_IMARK,
- HRTS1x_A_MARK,
- MSIOF1_TXD_B_MARK,
- TS_SDAT1_C_MARK,
- STP_ISD_1_C_MARK,
- RIF1_D1_B_MARK,
- ADICHS0_MARK,
- SCK2_IMARK,
- SCIF_CLK_B_MARK,
- MSIOF1_SCK_B_MARK,
- TS_SCK1_C_MARK,
- STP_ISCLK_1_C_MARK,
- RIF1_CLK_B_MARK,
- ADICLK_MARK,
-
- /* IPSR13 */
- TX2_A_IMARK,
- SD2_CD_B_MARK,
- SCL1_A_MARK,
- FMCLK_A_MARK,
- RIF1_D1_C_MARK,
- FSO_CFE_0x_MARK,
- RX2_A_IMARK,
- SD2_WP_B_MARK,
- SDA1_A_MARK,
- FMIN_A_MARK,
- RIF1_SYNC_C_MARK,
- FSO_CFE_1x_MARK,
- HSCK0_IMARK,
- MSIOF1_SCK_D_MARK,
- AUDIO_CLKB_A_MARK,
- SSI_SDATA1_B_MARK,
- TS_SCK0_D_MARK,
- STP_ISCLK_0_D_MARK,
- RIF0_CLK_C_MARK,
- RX5_B_MARK,
- HRX0_IMARK,
- MSIOF1_RXD_D_MARK,
- SSI_SDATA2_B_MARK,
- TS_SDEN0_D_MARK,
- STP_ISEN_0_D_MARK,
- RIF0_D0_C_MARK,
- HTX0_IMARK,
- MSIOF1_TXD_D_MARK,
- SSI_SDATA9_B_MARK,
- TS_SDAT0_D_MARK,
- STP_ISD_0_D_MARK,
- RIF0_D1_C_MARK,
- HCTS0x_IMARK,
- RX2_B_MARK,
- MSIOF1_SYNC_D_MARK,
- SSI_SCK9_A_MARK,
- TS_SPSYNC0_D_MARK,
- STP_ISSYNC_0_D_MARK,
- RIF0_SYNC_C_MARK,
- AUDIO_CLKOUT1_A_MARK,
- HRTS0x_IMARK,
- TX2_B_MARK,
- MSIOF1_SS1_D_MARK,
- SSI_WS9_A_MARK,
- STP_IVCXO27_0_D_MARK,
- BPFCLK_A_MARK,
- AUDIO_CLKOUT2_A_MARK,
- MSIOF0_SYNC_IMARK,
- AUDIO_CLKOUT_A_MARK,
- TX5_B_MARK,
- BPFCLK_D_MARK,
-
- /* IPSR14 */
- MSIOF0_SS1_IMARK,
- RX5_A_MARK,
- NFWPx_A_MARK,
- AUDIO_CLKA_C_MARK,
- SSI_SCK2_A_MARK,
- STP_IVCXO27_0_C_MARK,
- AUDIO_CLKOUT3_A_MARK,
- TCLK1_B_MARK,
- MSIOF0_SS2_IMARK,
- TX5_A_MARK,
- MSIOF1_SS2_D_MARK,
- AUDIO_CLKC_A_MARK,
- SSI_WS2_A_MARK,
- STP_OPWM_0_D_MARK,
- AUDIO_CLKOUT_D_MARK,
- SPEEDIN_B_MARK,
- MLB_CLK_IMARK,
- MSIOF1_SCK_F_MARK,
- SCL1_B_MARK,
- MLB_SIG_IMARK,
- RX1_B_MARK,
- MSIOF1_SYNC_F_MARK,
- SDA1_B_MARK,
- MLB_DAT_IMARK,
- TX1_B_MARK,
- MSIOF1_RXD_F_MARK,
- SSI_SCK01239_IMARK,
- MSIOF1_TXD_F_MARK,
- MOUT0_MARK,
- SSI_WS01239_IMARK,
- MSIOF1_SS1_F_MARK,
- MOUT1_MARK,
- SSI_SDATA0_IMARK,
- MSIOF1_SS2_F_MARK,
- MOUT2_MARK,
-
- /* IPSR15 */
- SSI_SDATA1_A_IMARK,
- MOUT5_MARK,
- SSI_SDATA2_A_IMARK,
- SSI_SCK1_B_MARK,
- MOUT6_MARK,
- SSI_SCK34_IMARK,
- MSIOF1_SS1_A_MARK,
- STP_OPWM_0_A_MARK,
- SSI_WS34_IMARK,
- HCTS2x_A_MARK,
- MSIOF1_SS2_A_MARK,
- STP_IVCXO27_0_A_MARK,
- SSI_SDATA3_IMARK,
- HRTS2x_A_MARK,
- MSIOF1_TXD_A_MARK,
- TS_SCK0_A_MARK,
- STP_ISCLK_0_A_MARK,
- RIF0_D1_A_MARK,
- RIF2_D0_A_MARK,
- SSI_SCK4_IMARK,
- HRX2_A_MARK,
- MSIOF1_SCK_A_MARK,
- TS_SDAT0_A_MARK,
- STP_ISD_0_A_MARK,
- RIF0_CLK_A_MARK,
- RIF2_CLK_A_MARK,
- SSI_WS4_IMARK,
- HTX2_A_MARK,
- MSIOF1_SYNC_A_MARK,
- TS_SDEN0_A_MARK,
- STP_ISEN_0_A_MARK,
- RIF0_SYNC_A_MARK,
- RIF2_SYNC_A_MARK,
- SSI_SDATA4_IMARK,
- HSCK2_A_MARK,
- MSIOF1_RXD_A_MARK,
- TS_SPSYNC0_A_MARK,
- STP_ISSYNC_0_A_MARK,
- RIF0_D0_A_MARK,
- RIF2_D1_A_MARK,
-
- /* IPSR16 */
- SSI_SCK6_IMARK,
- SIM0_RST_D_MARK,
- SSI_WS6_IMARK,
- SIM0_D_D_MARK,
- SSI_SDATA6_IMARK,
- SIM0_CLK_D_MARK,
- SATA_DEVSLP_A_MARK,
- SSI_SCK78_IMARK,
- HRX2_B_MARK,
- MSIOF1_SCK_C_MARK,
- TS_SCK1_A_MARK,
- STP_ISCLK_1_A_MARK,
- RIF1_CLK_A_MARK,
- RIF3_CLK_A_MARK,
- SSI_WS78_IMARK,
- HTX2_B_MARK,
- MSIOF1_SYNC_C_MARK,
- TS_SDAT1_A_MARK,
- STP_ISD_1_A_MARK,
- RIF1_SYNC_A_MARK,
- RIF3_SYNC_A_MARK,
- SSI_SDATA7_IMARK,
- HCTS2x_B_MARK,
- MSIOF1_RXD_C_MARK,
- TS_SDEN1_A_MARK,
- STP_ISEN_1_A_MARK,
- RIF1_D0_A_MARK,
- RIF3_D0_A_MARK,
- TCLK2_A_MARK,
- SSI_SDATA8_IMARK,
- HRTS2x_B_MARK,
- MSIOF1_TXD_C_MARK,
- TS_SPSYNC1_A_MARK,
- STP_ISSYNC_1_A_MARK,
- RIF1_D1_A_MARK,
- RIF3_D1_A_MARK,
- SSI_SDATA9_A_IMARK,
- HSCK2_B_MARK,
- MSIOF1_SS1_C_MARK,
- HSCK1_A_MARK,
- SSI_WS1_B_MARK,
- SCK1_MARK,
- STP_IVCXO27_1_A_MARK,
- SCK5_A_MARK,
-
- /* IPSR17 */
- AUDIO_CLKA_A_IMARK,
- CC5_OSCOUT_MARK,
- AUDIO_CLKB_B_IMARK,
- SCIF_CLK_A_MARK,
- STP_IVCXO27_1_D_MARK,
- REMOCON_A_MARK,
- TCLK1_A_MARK,
- USB0_PWEN_IMARK,
- SIM0_RST_C_MARK,
- TS_SCK1_D_MARK,
- STP_ISCLK_1_D_MARK,
- BPFCLK_B_MARK,
- RIF3_CLK_B_MARK,
- HSCK2_C_MARK,
- USB0_OVC_IMARK,
- SIM0_D_C_MARK,
- TS_SDAT1_D_MARK,
- STP_ISD_1_D_MARK,
- RIF3_SYNC_B_MARK,
- HRX2_C_MARK,
- USB1_PWEN_IMARK,
- SIM0_CLK_C_MARK,
- SSI_SCK1_A_MARK,
- TS_SCK0_E_MARK,
- STP_ISCLK_0_E_MARK,
- FMCLK_B_MARK,
- RIF2_CLK_B_MARK,
- SPEEDIN_A_MARK,
- HTX2_C_MARK,
- USB1_OVC_IMARK,
- MSIOF1_SS2_C_MARK,
- SSI_WS1_A_MARK,
- TS_SDAT0_E_MARK,
- STP_ISD_0_E_MARK,
- FMIN_B_MARK,
- RIF2_SYNC_B_MARK,
- REMOCON_B_MARK,
- HCTS2x_C_MARK,
- USB30_PWEN_IMARK,
- AUDIO_CLKOUT_B_MARK,
- SSI_SCK2_B_MARK,
- TS_SDEN1_D_MARK,
- STP_ISEN_1_D_MARK,
- STP_OPWM_0_E_MARK,
- RIF3_D0_B_MARK,
- TCLK2_B_MARK,
- TPU0TO0_MARK,
- BPFCLK_C_MARK,
- HRTS2x_C_MARK,
- USB30_OVC_IMARK,
- AUDIO_CLKOUT1_B_MARK,
- SSI_WS2_B_MARK,
- TS_SPSYNC1_D_MARK,
- STP_ISSYNC_1_D_MARK,
- STP_IVCXO27_0_E_MARK,
- RIF3_D1_B_MARK,
- FSO_TOEx_MARK,
- TPU0TO1_MARK,
-
- /* IPSR18 */
- USB3_PWEN_IMARK,
- AUDIO_CLKOUT2_B_MARK,
- SSI_SCK9_B_MARK,
- TS_SDEN0_E_MARK,
- STP_ISEN_0_E_MARK,
- RIF2_D0_B_MARK,
- TPU0TO2_MARK,
- FMCLK_C_MARK,
- FMCLK_D_MARK,
-
- USB3_OVC_IMARK,
- AUDIO_CLKOUT3_B_MARK,
- SSI_WS9_B_MARK,
- TS_SPSYNC0_E_MARK,
- STP_ISSYNC_0_E_MARK,
- RIF2_D1_B_MARK,
- TPU0TO3_MARK,
- FMIN_C_MARK,
- FMIN_D_MARK,
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- /* GPSR0 */
- PINMUX_DATA(D15_GMARK, GFN_D15),
- PINMUX_DATA(D14_GMARK, GFN_D14),
- PINMUX_DATA(D13_GMARK, GFN_D13),
- PINMUX_DATA(D12_GMARK, GFN_D12),
- PINMUX_DATA(D11_GMARK, GFN_D11),
- PINMUX_DATA(D10_GMARK, GFN_D10),
- PINMUX_DATA(D9_GMARK, GFN_D9),
- PINMUX_DATA(D8_GMARK, GFN_D8),
- PINMUX_DATA(D7_GMARK, GFN_D7),
- PINMUX_DATA(D6_GMARK, GFN_D6),
- PINMUX_DATA(D5_GMARK, GFN_D5),
- PINMUX_DATA(D4_GMARK, GFN_D4),
- PINMUX_DATA(D3_GMARK, GFN_D3),
- PINMUX_DATA(D2_GMARK, GFN_D2),
- PINMUX_DATA(D1_GMARK, GFN_D1),
- PINMUX_DATA(D0_GMARK, GFN_D0),
-
- /* GPSR1 */
- PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT),
- PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),
- PINMUX_DATA(WE1x_GMARK, GFN_WE1x),
- PINMUX_DATA(WE0x_GMARK, GFN_WE0x),
- PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx),
- PINMUX_DATA(RDx_GMARK, GFN_RDx),
- PINMUX_DATA(BSx_GMARK, GFN_BSx),
- PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26),
- PINMUX_DATA(CS0x_GMARK, GFN_CS0x),
- PINMUX_DATA(A19_GMARK, GFN_A19),
- PINMUX_DATA(A18_GMARK, GFN_A18),
- PINMUX_DATA(A17_GMARK, GFN_A17),
- PINMUX_DATA(A16_GMARK, GFN_A16),
- PINMUX_DATA(A15_GMARK, GFN_A15),
- PINMUX_DATA(A14_GMARK, GFN_A14),
- PINMUX_DATA(A13_GMARK, GFN_A13),
- PINMUX_DATA(A12_GMARK, GFN_A12),
- PINMUX_DATA(A11_GMARK, GFN_A11),
- PINMUX_DATA(A10_GMARK, GFN_A10),
- PINMUX_DATA(A9_GMARK, GFN_A9),
- PINMUX_DATA(A8_GMARK, GFN_A8),
- PINMUX_DATA(A7_GMARK, GFN_A7),
- PINMUX_DATA(A6_GMARK, GFN_A6),
- PINMUX_DATA(A5_GMARK, GFN_A5),
- PINMUX_DATA(A4_GMARK, GFN_A4),
- PINMUX_DATA(A3_GMARK, GFN_A3),
- PINMUX_DATA(A2_GMARK, GFN_A2),
- PINMUX_DATA(A1_GMARK, GFN_A1),
- PINMUX_DATA(A0_GMARK, GFN_A0),
-
- /* GPSR2 */
- PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A),
- PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A),
- PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK),
- PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT),
- PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC),
- PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC),
- PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A),
- PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A),
- PINMUX_DATA(PWM0_GMARK, GFN_PWM0),
- PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),
- PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),
- PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3),
- PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2),
- PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1),
- PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),
-
- /* GPSR3 */
- PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP),
- PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD),
- PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP),
- PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD),
- PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3),
- PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2),
- PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1),
- PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0),
- PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD),
- PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK),
- PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3),
- PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2),
- PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1),
- PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0),
- PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD),
- PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),
-
- /* GPSR4 */
- PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS),
- PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),
- PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),
- PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),
- PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),
- PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3),
- PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2),
- PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1),
- PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0),
- PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD),
- PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK),
- PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),
- PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),
- PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),
- PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),
- PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),
- PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD),
- PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),
-
- /* GPSR5 */
- PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT),
- PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG),
- PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK),
- PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD),
- PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),
- PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD),
- PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),
- PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),
- PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK),
- PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x),
- PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x),
- PINMUX_DATA(HTX0_GMARK, GFN_HTX0),
- PINMUX_DATA(HRX0_GMARK, GFN_HRX0),
- PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0),
- PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A),
- PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A),
- PINMUX_DATA(SCK2_GMARK, GFN_SCK2),
- PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS),
- PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x),
- PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A),
- PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A),
- PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS),
- PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x),
- PINMUX_DATA(TX0_GMARK, GFN_TX0),
- PINMUX_DATA(RX0_GMARK, GFN_RX0),
- PINMUX_DATA(SCK0_GMARK, GFN_SCK0),
-
- /* GPSR6 */
- PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC),
- PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN),
- PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),
- PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),
- PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),
- PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN),
- PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC),
- PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN),
- PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B),
- PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A),
- PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A),
- PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8),
- PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7),
- PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78),
- PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78),
- PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6),
- PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6),
- PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6),
- PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5),
- PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5),
- PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5),
- PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4),
- PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4),
- PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4),
- PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3),
- PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34),
- PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34),
- PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),
- PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),
- PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),
- PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239),
- PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239),
-
- /* GPSR7 */
- PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),
- PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),
- PINMUX_DATA(AVS2_MARK, FN_AVS2),
- PINMUX_DATA(AVS1_MARK, FN_AVS1),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
- /* GPSR0 */
- GPIO_GFN(D15),
- GPIO_GFN(D14),
- GPIO_GFN(D13),
- GPIO_GFN(D12),
- GPIO_GFN(D11),
- GPIO_GFN(D10),
- GPIO_GFN(D9),
- GPIO_GFN(D8),
- GPIO_GFN(D7),
- GPIO_GFN(D6),
- GPIO_GFN(D5),
- GPIO_GFN(D4),
- GPIO_GFN(D3),
- GPIO_GFN(D2),
- GPIO_GFN(D1),
- GPIO_GFN(D0),
- /* GPSR1 */
- GPIO_GFN(CLKOUT),
- GPIO_GFN(EX_WAIT0_A),
- GPIO_GFN(WE1x),
- GPIO_GFN(WE0x),
- GPIO_GFN(RD_WRx),
- GPIO_GFN(RDx),
- GPIO_GFN(BSx),
- GPIO_GFN(CS1x_A26),
- GPIO_GFN(CS0x),
- GPIO_GFN(A19),
- GPIO_GFN(A18),
- GPIO_GFN(A17),
- GPIO_GFN(A16),
- GPIO_GFN(A15),
- GPIO_GFN(A14),
- GPIO_GFN(A13),
- GPIO_GFN(A12),
- GPIO_GFN(A11),
- GPIO_GFN(A10),
- GPIO_GFN(A9),
- GPIO_GFN(A8),
- GPIO_GFN(A7),
- GPIO_GFN(A6),
- GPIO_GFN(A5),
- GPIO_GFN(A4),
- GPIO_GFN(A3),
- GPIO_GFN(A2),
- GPIO_GFN(A1),
- GPIO_GFN(A0),
-
- /* GPSR2 */
- GPIO_GFN(AVB_AVTP_CAPTURE_A),
- GPIO_GFN(AVB_AVTP_MATCH_A),
- GPIO_GFN(AVB_LINK),
- GPIO_GFN(AVB_PHY_INT),
- GPIO_GFN(AVB_MAGIC),
- GPIO_GFN(AVB_MDC),
- GPIO_GFN(PWM2_A),
- GPIO_GFN(PWM1_A),
- GPIO_GFN(PWM0),
- GPIO_GFN(IRQ5),
- GPIO_GFN(IRQ4),
- GPIO_GFN(IRQ3),
- GPIO_GFN(IRQ2),
- GPIO_GFN(IRQ1),
- GPIO_GFN(IRQ0),
-
- /* GPSR3 */
- GPIO_GFN(SD1_WP),
- GPIO_GFN(SD1_CD),
- GPIO_GFN(SD0_WP),
- GPIO_GFN(SD0_CD),
- GPIO_GFN(SD1_DAT3),
- GPIO_GFN(SD1_DAT2),
- GPIO_GFN(SD1_DAT1),
- GPIO_GFN(SD1_DAT0),
- GPIO_GFN(SD1_CMD),
- GPIO_GFN(SD1_CLK),
- GPIO_GFN(SD0_DAT3),
- GPIO_GFN(SD0_DAT2),
- GPIO_GFN(SD0_DAT1),
- GPIO_GFN(SD0_DAT0),
- GPIO_GFN(SD0_CMD),
- GPIO_GFN(SD0_CLK),
-
- /* GPSR4 */
- GPIO_GFN(SD3_DS),
- GPIO_GFN(SD3_DAT7),
- GPIO_GFN(SD3_DAT6),
- GPIO_GFN(SD3_DAT5),
- GPIO_GFN(SD3_DAT4),
- GPIO_GFN(SD3_DAT3),
- GPIO_GFN(SD3_DAT2),
- GPIO_GFN(SD3_DAT1),
- GPIO_GFN(SD3_DAT0),
- GPIO_GFN(SD3_CMD),
- GPIO_GFN(SD3_CLK),
- GPIO_GFN(SD2_DS),
- GPIO_GFN(SD2_DAT3),
- GPIO_GFN(SD2_DAT2),
- GPIO_GFN(SD2_DAT1),
- GPIO_GFN(SD2_DAT0),
- GPIO_GFN(SD2_CMD),
- GPIO_GFN(SD2_CLK),
-
- /* GPSR5 */
- GPIO_GFN(MLB_DAT),
- GPIO_GFN(MLB_SIG),
- GPIO_GFN(MLB_CLK),
- GPIO_FN(MSIOF0_RXD),
- GPIO_GFN(MSIOF0_SS2),
- GPIO_FN(MSIOF0_TXD),
- GPIO_GFN(MSIOF0_SS1),
- GPIO_GFN(MSIOF0_SYNC),
- GPIO_FN(MSIOF0_SCK),
- GPIO_GFN(HRTS0x),
- GPIO_GFN(HCTS0x),
- GPIO_GFN(HTX0),
- GPIO_GFN(HRX0),
- GPIO_GFN(HSCK0),
- GPIO_GFN(RX2_A),
- GPIO_GFN(TX2_A),
- GPIO_GFN(SCK2),
- GPIO_GFN(RTS1x_TANS),
- GPIO_GFN(CTS1x),
- GPIO_GFN(TX1_A),
- GPIO_GFN(RX1_A),
- GPIO_GFN(RTS0x_TANS),
- GPIO_GFN(CTS0x),
- GPIO_GFN(TX0),
- GPIO_GFN(RX0),
- GPIO_GFN(SCK0),
-
- /* GPSR6 */
- GPIO_GFN(USB3_OVC),
- GPIO_GFN(USB3_PWEN),
- GPIO_GFN(USB30_OVC),
- GPIO_GFN(USB30_PWEN),
- GPIO_GFN(USB1_OVC),
- GPIO_GFN(USB1_PWEN),
- GPIO_GFN(USB0_OVC),
- GPIO_GFN(USB0_PWEN),
- GPIO_GFN(AUDIO_CLKB_B),
- GPIO_GFN(AUDIO_CLKA_A),
- GPIO_GFN(SSI_SDATA9_A),
- GPIO_GFN(SSI_SDATA8),
- GPIO_GFN(SSI_SDATA7),
- GPIO_GFN(SSI_WS78),
- GPIO_GFN(SSI_SCK78),
- GPIO_GFN(SSI_SDATA6),
- GPIO_GFN(SSI_WS6),
- GPIO_GFN(SSI_SCK6),
- GPIO_FN(SSI_SDATA5),
- GPIO_FN(SSI_WS5),
- GPIO_FN(SSI_SCK5),
- GPIO_GFN(SSI_SDATA4),
- GPIO_GFN(SSI_WS4),
- GPIO_GFN(SSI_SCK4),
- GPIO_GFN(SSI_SDATA3),
- GPIO_GFN(SSI_WS34),
- GPIO_GFN(SSI_SCK34),
- GPIO_GFN(SSI_SDATA2_A),
- GPIO_GFN(SSI_SDATA1_A),
- GPIO_GFN(SSI_SDATA0),
- GPIO_GFN(SSI_WS01239),
- GPIO_GFN(SSI_SCK01239),
-
- /* GPSR7 */
- GPIO_FN(HDMI1_CEC),
- GPIO_FN(HDMI0_CEC),
- GPIO_FN(AVS2),
- GPIO_FN(AVS1),
-
- /* IPSR0 */
- GPIO_IFN(AVB_MDC),
- GPIO_FN(MSIOF2_SS2_C),
- GPIO_IFN(AVB_MAGIC),
- GPIO_FN(MSIOF2_SS1_C),
- GPIO_FN(SCK4_A),
- GPIO_IFN(AVB_PHY_INT),
- GPIO_FN(MSIOF2_SYNC_C),
- GPIO_FN(RX4_A),
- GPIO_IFN(AVB_LINK),
- GPIO_FN(MSIOF2_SCK_C),
- GPIO_FN(TX4_A),
- GPIO_IFN(AVB_AVTP_MATCH_A),
- GPIO_FN(MSIOF2_RXD_C),
- GPIO_FN(CTS4x_A),
- GPIO_FN(FSCLKST2x_A),
- GPIO_IFN(AVB_AVTP_CAPTURE_A),
- GPIO_FN(MSIOF2_TXD_C),
- GPIO_FN(RTS4x_TANS_A),
- GPIO_IFN(IRQ0),
- GPIO_FN(QPOLB),
- GPIO_FN(DU_CDE),
- GPIO_FN(VI4_DATA0_B),
- GPIO_FN(CAN0_TX_B),
- GPIO_FN(CANFD0_TX_B),
- GPIO_FN(MSIOF3_SS2_E),
- GPIO_IFN(IRQ1),
- GPIO_FN(QPOLA),
- GPIO_FN(DU_DISP),
- GPIO_FN(VI4_DATA1_B),
- GPIO_FN(CAN0_RX_B),
- GPIO_FN(CANFD0_RX_B),
- GPIO_FN(MSIOF3_SS1_E),
-
- /* IPSR1 */
- GPIO_IFN(IRQ2),
- GPIO_FN(QCPV_QDE),
- GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),
- GPIO_FN(VI4_DATA2_B),
- GPIO_FN(MSIOF3_SYNC_E),
- GPIO_FN(PWM3_B),
- GPIO_IFN(IRQ3),
- GPIO_FN(QSTVB_QVE),
- GPIO_FN(DU_DOTCLKOUT1),
- GPIO_FN(VI4_DATA3_B),
- GPIO_FN(MSIOF3_SCK_E),
- GPIO_FN(PWM4_B),
- GPIO_IFN(IRQ4),
- GPIO_FN(QSTH_QHS),
- GPIO_FN(DU_EXHSYNC_DU_HSYNC),
- GPIO_FN(VI4_DATA4_B),
- GPIO_FN(MSIOF3_RXD_E),
- GPIO_FN(PWM5_B),
- GPIO_IFN(IRQ5),
- GPIO_FN(QSTB_QHE),
- GPIO_FN(DU_EXVSYNC_DU_VSYNC),
- GPIO_FN(VI4_DATA5_B),
- GPIO_FN(FSCLKST2x_B),
- GPIO_FN(MSIOF3_TXD_E),
- GPIO_FN(PWM6_B),
- GPIO_IFN(PWM0),
- GPIO_FN(AVB_AVTP_PPS),
- GPIO_FN(VI4_DATA6_B),
- GPIO_FN(IECLK_B),
- GPIO_IFN(PWM1_A),
- GPIO_FN(HRX3_D),
- GPIO_FN(VI4_DATA7_B),
- GPIO_FN(IERX_B),
- GPIO_IFN(PWM2_A),
- GPIO_FN(HTX3_D),
- GPIO_FN(IETX_B),
- GPIO_IFN(A0),
- GPIO_FN(LCDOUT16),
- GPIO_FN(MSIOF3_SYNC_B),
- GPIO_FN(VI4_DATA8),
- GPIO_FN(DU_DB0),
- GPIO_FN(PWM3_A),
-
- /* IPSR2 */
- GPIO_IFN(A1),
- GPIO_FN(LCDOUT17),
- GPIO_FN(MSIOF3_TXD_B),
- GPIO_FN(VI4_DATA9),
- GPIO_FN(DU_DB1),
- GPIO_FN(PWM4_A),
- GPIO_IFN(A2),
- GPIO_FN(LCDOUT18),
- GPIO_FN(MSIOF3_SCK_B),
- GPIO_FN(VI4_DATA10),
- GPIO_FN(DU_DB2),
- GPIO_FN(PWM5_A),
- GPIO_IFN(A3),
- GPIO_FN(LCDOUT19),
- GPIO_FN(MSIOF3_RXD_B),
- GPIO_FN(VI4_DATA11),
- GPIO_FN(DU_DB3),
- GPIO_FN(PWM6_A),
- GPIO_IFN(A4),
- GPIO_FN(LCDOUT20),
- GPIO_FN(MSIOF3_SS1_B),
- GPIO_FN(VI4_DATA12),
- GPIO_FN(VI5_DATA12),
- GPIO_FN(DU_DB4),
- GPIO_IFN(A5),
- GPIO_FN(LCDOUT21),
- GPIO_FN(MSIOF3_SS2_B),
- GPIO_FN(SCK4_B),
- GPIO_FN(VI4_DATA13),
- GPIO_FN(VI5_DATA13),
- GPIO_FN(DU_DB5),
- GPIO_IFN(A6),
- GPIO_FN(LCDOUT22),
- GPIO_FN(MSIOF2_SS1_A),
- GPIO_FN(RX4_B),
- GPIO_FN(VI4_DATA14),
- GPIO_FN(VI5_DATA14),
- GPIO_FN(DU_DB6),
- GPIO_IFN(A7),
- GPIO_FN(LCDOUT23),
- GPIO_FN(MSIOF2_SS2_A),
- GPIO_FN(TX4_B),
- GPIO_FN(VI4_DATA15),
- GPIO_FN(V15_DATA15),
- GPIO_FN(DU_DB7),
- GPIO_IFN(A8),
- GPIO_FN(RX3_B),
- GPIO_FN(MSIOF2_SYNC_A),
- GPIO_FN(HRX4_B),
- GPIO_FN(SDA6_A),
- GPIO_FN(AVB_AVTP_MATCH_B),
- GPIO_FN(PWM1_B),
-
- /* IPSR3 */
- GPIO_IFN(A9),
- GPIO_FN(MSIOF2_SCK_A),
- GPIO_FN(CTS4x_B),
- GPIO_FN(VI5_VSYNCx),
- GPIO_IFN(A10),
- GPIO_FN(MSIOF2_RXD_A),
- GPIO_FN(RTS4n_TANS_B),
- GPIO_FN(VI5_HSYNCx),
- GPIO_IFN(A11),
- GPIO_FN(TX3_B),
- GPIO_FN(MSIOF2_TXD_A),
- GPIO_FN(HTX4_B),
- GPIO_FN(HSCK4),
- GPIO_FN(VI5_FIELD),
- GPIO_FN(SCL6_A),
- GPIO_FN(AVB_AVTP_CAPTURE_B),
- GPIO_FN(PWM2_B),
- GPIO_IFN(A12),
- GPIO_FN(LCDOUT12),
- GPIO_FN(MSIOF3_SCK_C),
- GPIO_FN(HRX4_A),
- GPIO_FN(VI5_DATA8),
- GPIO_FN(DU_DG4),
- GPIO_IFN(A13),
- GPIO_FN(LCDOUT13),
- GPIO_FN(MSIOF3_SYNC_C),
- GPIO_FN(HTX4_A),
- GPIO_FN(VI5_DATA9),
- GPIO_FN(DU_DG5),
- GPIO_IFN(A14),
- GPIO_FN(LCDOUT14),
- GPIO_FN(MSIOF3_RXD_C),
- GPIO_FN(HCTS4x),
- GPIO_FN(VI5_DATA10),
- GPIO_FN(DU_DG6),
- GPIO_IFN(A15),
- GPIO_FN(LCDOUT15),
- GPIO_FN(MSIOF3_TXD_C),
- GPIO_FN(HRTS4x),
- GPIO_FN(VI5_DATA11),
- GPIO_FN(DU_DG7),
- GPIO_IFN(A16),
- GPIO_FN(LCDOUT8),
- GPIO_FN(VI4_FIELD),
- GPIO_FN(DU_DG0),
-
- /* IPSR4 */
- GPIO_IFN(A17),
- GPIO_FN(LCDOUT9),
- GPIO_FN(VI4_VSYNCx),
- GPIO_FN(DU_DG1),
- GPIO_IFN(A18),
- GPIO_FN(LCDOUT10),
- GPIO_FN(VI4_HSYNCx),
- GPIO_FN(DU_DG2),
- GPIO_IFN(A19),
- GPIO_FN(LCDOUT11),
- GPIO_FN(VI4_CLKENB),
- GPIO_FN(DU_DG3),
- GPIO_IFN(CS0x),
- GPIO_FN(VI5_CLKENB),
- GPIO_IFN(CS1x_A26),
- GPIO_FN(VI5_CLK),
- GPIO_FN(EX_WAIT0_B),
- GPIO_IFN(BSx),
- GPIO_FN(QSTVA_QVS),
- GPIO_FN(MSIOF3_SCK_D),
- GPIO_FN(SCK3),
- GPIO_FN(HSCK3),
- GPIO_FN(CAN1_TX),
- GPIO_FN(CANFD1_TX),
- GPIO_FN(IETX_A),
- GPIO_IFN(RDx),
- GPIO_FN(MSIOF3_SYNC_D),
- GPIO_FN(RX3_A),
- GPIO_FN(HRX3_A),
- GPIO_FN(CAN0_TX_A),
- GPIO_FN(CANFD0_TX_A),
- GPIO_IFN(RD_WRx),
- GPIO_FN(MSIOF3_RXD_D),
- GPIO_FN(TX3_A),
- GPIO_FN(HTX3_A),
- GPIO_FN(CAN0_RX_A),
- GPIO_FN(CANFD0_RX_A),
-
- /* IPSR5 */
- GPIO_IFN(WE0x),
- GPIO_FN(MSIIOF3_TXD_D),
- GPIO_FN(CTS3x),
- GPIO_FN(HCTS3x),
- GPIO_FN(SCL6_B),
- GPIO_FN(CAN_CLK),
- GPIO_FN(IECLK_A),
- GPIO_IFN(WE1x),
- GPIO_FN(MSIOF3_SS1_D),
- GPIO_FN(RTS3x_TANS),
- GPIO_FN(HRTS3x),
- GPIO_FN(SDA6_B),
- GPIO_FN(CAN1_RX),
- GPIO_FN(CANFD1_RX),
- GPIO_FN(IERX_A),
- GPIO_IFN(EX_WAIT0_A),
- GPIO_FN(QCLK),
- GPIO_FN(VI4_CLK),
- GPIO_FN(DU_DOTCLKOUT0),
- GPIO_IFN(D0),
- GPIO_FN(MSIOF2_SS1_B),
- GPIO_FN(MSIOF3_SCK_A),
- GPIO_FN(VI4_DATA16),
- GPIO_FN(VI5_DATA0),
- GPIO_IFN(D1),
- GPIO_FN(MSIOF2_SS2_B),
- GPIO_FN(MSIOF3_SYNC_A),
- GPIO_FN(VI4_DATA17),
- GPIO_FN(VI5_DATA1),
- GPIO_IFN(D2),
- GPIO_FN(MSIOF3_RXD_A),
- GPIO_FN(VI4_DATA18),
- GPIO_FN(VI5_DATA2),
- GPIO_IFN(D3),
- GPIO_FN(MSIOF3_TXD_A),
- GPIO_FN(VI4_DATA19),
- GPIO_FN(VI5_DATA3),
- GPIO_IFN(D4),
- GPIO_FN(MSIOF2_SCK_B),
- GPIO_FN(VI4_DATA20),
- GPIO_FN(VI5_DATA4),
-
- /* IPSR6 */
- GPIO_IFN(D5),
- GPIO_FN(MSIOF2_SYNC_B),
- GPIO_FN(VI4_DATA21),
- GPIO_FN(VI5_DATA5),
- GPIO_IFN(D6),
- GPIO_FN(MSIOF2_RXD_B),
- GPIO_FN(VI4_DATA22),
- GPIO_FN(VI5_DATA6),
- GPIO_IFN(D7),
- GPIO_FN(MSIOF2_TXD_B),
- GPIO_FN(VI4_DATA23),
- GPIO_FN(VI5_DATA7),
- GPIO_IFN(D8),
- GPIO_FN(LCDOUT0),
- GPIO_FN(MSIOF2_SCK_D),
- GPIO_FN(SCK4_C),
- GPIO_FN(VI4_DATA0_A),
- GPIO_FN(DU_DR0),
- GPIO_IFN(D9),
- GPIO_FN(LCDOUT1),
- GPIO_FN(MSIOF2_SYNC_D),
- GPIO_FN(VI4_DATA1_A),
- GPIO_FN(DU_DR1),
- GPIO_IFN(D10),
- GPIO_FN(LCDOUT2),
- GPIO_FN(MSIOF2_RXD_D),
- GPIO_FN(HRX3_B),
- GPIO_FN(VI4_DATA2_A),
- GPIO_FN(CTS4x_C),
- GPIO_FN(DU_DR2),
- GPIO_IFN(D11),
- GPIO_FN(LCDOUT3),
- GPIO_FN(MSIOF2_TXD_D),
- GPIO_FN(HTX3_B),
- GPIO_FN(VI4_DATA3_A),
- GPIO_FN(RTS4x_TANS_C),
- GPIO_FN(DU_DR3),
- GPIO_IFN(D12),
- GPIO_FN(LCDOUT4),
- GPIO_FN(MSIOF2_SS1_D),
- GPIO_FN(RX4_C),
- GPIO_FN(VI4_DATA4_A),
- GPIO_FN(DU_DR4),
-
- /* IPSR7 */
- GPIO_IFN(D13),
- GPIO_FN(LCDOUT5),
- GPIO_FN(MSIOF2_SS2_D),
- GPIO_FN(TX4_C),
- GPIO_FN(VI4_DATA5_A),
- GPIO_FN(DU_DR5),
- GPIO_IFN(D14),
- GPIO_FN(LCDOUT6),
- GPIO_FN(MSIOF3_SS1_A),
- GPIO_FN(HRX3_C),
- GPIO_FN(VI4_DATA6_A),
- GPIO_FN(DU_DR6),
- GPIO_FN(SCL6_C),
- GPIO_IFN(D15),
- GPIO_FN(LCDOUT7),
- GPIO_FN(MSIOF3_SS2_A),
- GPIO_FN(HTX3_C),
- GPIO_FN(VI4_DATA7_A),
- GPIO_FN(DU_DR7),
- GPIO_FN(SDA6_C),
- GPIO_FN(FSCLKST),
- GPIO_IFN(SD0_CLK),
- GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(STP_OPWM_0_B),
- GPIO_IFN(SD0_CMD),
- GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(STP_IVCXO27_0_B),
- GPIO_IFN(SD0_DAT0),
- GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(TS_SCK0_B),
- GPIO_FN(STP_ISCLK_0_B),
- GPIO_IFN(SD0_DAT1),
- GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(STP_ISSYNC_0_B),
-
- /* IPSR8 */
- GPIO_IFN(SD0_DAT2),
- GPIO_FN(MSIOF1_SS1_E),
- GPIO_FN(TS_SDAT0_B),
- GPIO_FN(STP_ISD_0_B),
- GPIO_IFN(SD0_DAT3),
- GPIO_FN(MSIOF1_SS2_E),
- GPIO_FN(TS_SDEN0_B),
- GPIO_FN(STP_ISEN_0_B),
- GPIO_IFN(SD1_CLK),
- GPIO_FN(MSIOF1_SCK_G),
- GPIO_FN(SIM0_CLK_A),
- GPIO_IFN(SD1_CMD),
- GPIO_FN(MSIOF1_SYNC_G),
- GPIO_FN(NFCEx_B),
- GPIO_FN(SIM0_D_A),
- GPIO_FN(STP_IVCXO27_1_B),
- GPIO_IFN(SD1_DAT0),
- GPIO_FN(SD2_DAT4),
- GPIO_FN(MSIOF1_RXD_G),
- GPIO_FN(NFWPx_B),
- GPIO_FN(TS_SCK1_B),
- GPIO_FN(STP_ISCLK_1_B),
- GPIO_IFN(SD1_DAT1),
- GPIO_FN(SD2_DAT5),
- GPIO_FN(MSIOF1_TXD_G),
- GPIO_FN(NFDATA14_B),
- GPIO_FN(TS_SPSYNC1_B),
- GPIO_FN(STP_ISSYNC_1_B),
- GPIO_IFN(SD1_DAT2),
- GPIO_FN(SD2_DAT6),
- GPIO_FN(MSIOF1_SS1_G),
- GPIO_FN(NFDATA15_B),
- GPIO_FN(TS_SDAT1_B),
- GPIO_FN(STP_IOD_1_B),
- GPIO_IFN(SD1_DAT3),
- GPIO_FN(SD2_DAT7),
- GPIO_FN(MSIOF1_SS2_G),
- GPIO_FN(NFRBx_B),
- GPIO_FN(TS_SDEN1_B),
- GPIO_FN(STP_ISEN_1_B),
-
- /* IPSR9 */
- GPIO_IFN(SD2_CLK),
- GPIO_FN(NFDATA8),
- GPIO_IFN(SD2_CMD),
- GPIO_FN(NFDATA9),
- GPIO_IFN(SD2_DAT0),
- GPIO_FN(NFDATA10),
- GPIO_IFN(SD2_DAT1),
- GPIO_FN(NFDATA11),
- GPIO_IFN(SD2_DAT2),
- GPIO_FN(NFDATA12),
- GPIO_IFN(SD2_DAT3),
- GPIO_FN(NFDATA13),
- GPIO_IFN(SD2_DS),
- GPIO_FN(NFALE),
- GPIO_FN(SATA_DEVSLP_B),
- GPIO_IFN(SD3_CLK),
- GPIO_FN(NFWEx),
-
- /* IPSR10 */
- GPIO_IFN(SD3_CMD),
- GPIO_FN(NFREx),
- GPIO_IFN(SD3_DAT0),
- GPIO_FN(NFDATA0),
- GPIO_IFN(SD3_DAT1),
- GPIO_FN(NFDATA1),
- GPIO_IFN(SD3_DAT2),
- GPIO_FN(NFDATA2),
- GPIO_IFN(SD3_DAT3),
- GPIO_FN(NFDATA3),
- GPIO_IFN(SD3_DAT4),
- GPIO_FN(SD2_CD_A),
- GPIO_FN(NFDATA4),
- GPIO_IFN(SD3_DAT5),
- GPIO_FN(SD2_WP_A),
- GPIO_FN(NFDATA5),
- GPIO_IFN(SD3_DAT6),
- GPIO_FN(SD3_CD),
- GPIO_FN(NFDATA6),
-
- /* IPSR11 */
- GPIO_IFN(SD3_DAT7),
- GPIO_FN(SD3_WP),
- GPIO_FN(NFDATA7),
- GPIO_IFN(SD3_DS),
- GPIO_FN(NFCLE),
- GPIO_IFN(SD0_CD),
- GPIO_FN(NFDATA14_A),
- GPIO_FN(SCL2_B),
- GPIO_FN(SIM0_RST_A),
- GPIO_IFN(SD0_WP),
- GPIO_FN(NFDATA15_A),
- GPIO_FN(SDA2_B),
- GPIO_IFN(SD1_CD),
- GPIO_FN(NFRBx_A),
- GPIO_FN(SIM0_CLK_B),
- GPIO_IFN(SD1_WP),
- GPIO_FN(NFCEx_A),
- GPIO_FN(SIM0_D_B),
- GPIO_IFN(SCK0),
- GPIO_FN(HSCK1_B),
- GPIO_FN(MSIOF1_SS2_B),
- GPIO_FN(AUDIO_CLKC_B),
- GPIO_FN(SDA2_A),
- GPIO_FN(SIM0_RST_B),
- GPIO_FN(STP_OPWM_0_C),
- GPIO_FN(RIF0_CLK_B),
- GPIO_FN(ADICHS2),
- GPIO_FN(SCK5_B),
- GPIO_IFN(RX0),
- GPIO_FN(HRX1_B),
- GPIO_FN(TS_SCK0_C),
- GPIO_FN(STP_ISCLK_0_C),
- GPIO_FN(RIF0_D0_B),
-
- /* IPSR12 */
- GPIO_IFN(TX0),
- GPIO_FN(HTX1_B),
- GPIO_FN(TS_SPSYNC0_C),
- GPIO_FN(STP_ISSYNC_0_C),
- GPIO_FN(RIF0_D1_B),
- GPIO_IFN(CTS0x),
- GPIO_FN(HCTS1x_B),
- GPIO_FN(MSIOF1_SYNC_B),
- GPIO_FN(TS_SPSYNC1_C),
- GPIO_FN(STP_ISSYNC_1_C),
- GPIO_FN(RIF1_SYNC_B),
- GPIO_FN(AUDIO_CLKOUT_C),
- GPIO_FN(ADICS_SAMP),
- GPIO_IFN(RTS0x_TANS),
- GPIO_FN(HRTS1x_B),
- GPIO_FN(MSIOF1_SS1_B),
- GPIO_FN(AUDIO_CLKA_B),
- GPIO_FN(SCL2_A),
- GPIO_FN(STP_IVCXO27_1_C),
- GPIO_FN(RIF0_SYNC_B),
- GPIO_FN(ADICHS1),
- GPIO_IFN(RX1_A),
- GPIO_FN(HRX1_A),
- GPIO_FN(TS_SDAT0_C),
- GPIO_FN(STP_ISD_0_C),
- GPIO_FN(RIF1_CLK_C),
- GPIO_IFN(TX1_A),
- GPIO_FN(HTX1_A),
- GPIO_FN(TS_SDEN0_C),
- GPIO_FN(STP_ISEN_0_C),
- GPIO_FN(RIF1_D0_C),
- GPIO_IFN(CTS1x),
- GPIO_FN(HCTS1x_A),
- GPIO_FN(MSIOF1_RXD_B),
- GPIO_FN(TS_SDEN1_C),
- GPIO_FN(STP_ISEN_1_C),
- GPIO_FN(RIF1_D0_B),
- GPIO_FN(ADIDATA),
- GPIO_IFN(RTS1x_TANS),
- GPIO_FN(HRTS1x_A),
- GPIO_FN(MSIOF1_TXD_B),
- GPIO_FN(TS_SDAT1_C),
- GPIO_FN(STP_ISD_1_C),
- GPIO_FN(RIF1_D1_B),
- GPIO_FN(ADICHS0),
- GPIO_IFN(SCK2),
- GPIO_FN(SCIF_CLK_B),
- GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(TS_SCK1_C),
- GPIO_FN(STP_ISCLK_1_C),
- GPIO_FN(RIF1_CLK_B),
- GPIO_FN(ADICLK),
-
- /* IPSR13 */
- GPIO_IFN(TX2_A),
- GPIO_FN(SD2_CD_B),
- GPIO_FN(SCL1_A),
- GPIO_FN(FMCLK_A),
- GPIO_FN(RIF1_D1_C),
- GPIO_FN(FSO_CFE_0x),
- GPIO_IFN(RX2_A),
- GPIO_FN(SD2_WP_B),
- GPIO_FN(SDA1_A),
- GPIO_FN(FMIN_A),
- GPIO_FN(RIF1_SYNC_C),
- GPIO_FN(FSO_CFE_1x),
- GPIO_IFN(HSCK0),
- GPIO_FN(MSIOF1_SCK_D),
- GPIO_FN(AUDIO_CLKB_A),
- GPIO_FN(SSI_SDATA1_B),
- GPIO_FN(TS_SCK0_D),
- GPIO_FN(STP_ISCLK_0_D),
- GPIO_FN(RIF0_CLK_C),
- GPIO_FN(RX5_B),
- GPIO_IFN(HRX0),
- GPIO_FN(MSIOF1_RXD_D),
- GPIO_FN(SSI_SDATA2_B),
- GPIO_FN(TS_SDEN0_D),
- GPIO_FN(STP_ISEN_0_D),
- GPIO_FN(RIF0_D0_C),
- GPIO_IFN(HTX0),
- GPIO_FN(MSIOF1_TXD_D),
- GPIO_FN(SSI_SDATA9_B),
- GPIO_FN(TS_SDAT0_D),
- GPIO_FN(STP_ISD_0_D),
- GPIO_FN(RIF0_D1_C),
- GPIO_IFN(HCTS0x),
- GPIO_FN(RX2_B),
- GPIO_FN(MSIOF1_SYNC_D),
- GPIO_FN(SSI_SCK9_A),
- GPIO_FN(TS_SPSYNC0_D),
- GPIO_FN(STP_ISSYNC_0_D),
- GPIO_FN(RIF0_SYNC_C),
- GPIO_FN(AUDIO_CLKOUT1_A),
- GPIO_IFN(HRTS0x),
- GPIO_FN(TX2_B),
- GPIO_FN(MSIOF1_SS1_D),
- GPIO_FN(SSI_WS9_A),
- GPIO_FN(STP_IVCXO27_0_D),
- GPIO_FN(BPFCLK_A),
- GPIO_FN(AUDIO_CLKOUT2_A),
- GPIO_IFN(MSIOF0_SYNC),
- GPIO_FN(AUDIO_CLKOUT_A),
- GPIO_FN(TX5_B),
- GPIO_FN(BPFCLK_D),
-
- /* IPSR14 */
- GPIO_IFN(MSIOF0_SS1),
- GPIO_FN(RX5_A),
- GPIO_FN(NFWPx_A),
- GPIO_FN(AUDIO_CLKA_C),
- GPIO_FN(SSI_SCK2_A),
- GPIO_FN(STP_IVCXO27_0_C),
- GPIO_FN(AUDIO_CLKOUT3_A),
- GPIO_FN(TCLK1_B),
- GPIO_IFN(MSIOF0_SS2),
- GPIO_FN(TX5_A),
- GPIO_FN(MSIOF1_SS2_D),
- GPIO_FN(AUDIO_CLKC_A),
- GPIO_FN(SSI_WS2_A),
- GPIO_FN(STP_OPWM_0_D),
- GPIO_FN(AUDIO_CLKOUT_D),
- GPIO_FN(SPEEDIN_B),
- GPIO_IFN(MLB_CLK),
- GPIO_FN(MSIOF1_SCK_F),
- GPIO_FN(SCL1_B),
- GPIO_IFN(MLB_SIG),
- GPIO_FN(RX1_B),
- GPIO_FN(MSIOF1_SYNC_F),
- GPIO_FN(SDA1_B),
- GPIO_IFN(MLB_DAT),
- GPIO_FN(TX1_B),
- GPIO_FN(MSIOF1_RXD_F),
- GPIO_IFN(SSI_SCK01239),
- GPIO_FN(MSIOF1_TXD_F),
- GPIO_FN(MOUT0),
- GPIO_IFN(SSI_WS01239),
- GPIO_FN(MSIOF1_SS1_F),
- GPIO_FN(MOUT1),
- GPIO_IFN(SSI_SDATA0),
- GPIO_FN(MSIOF1_SS2_F),
- GPIO_FN(MOUT2),
-
- /* IPSR15 */
- GPIO_IFN(SSI_SDATA1_A),
- GPIO_FN(MOUT5),
- GPIO_IFN(SSI_SDATA2_A),
- GPIO_FN(SSI_SCK1_B),
- GPIO_FN(MOUT6),
- GPIO_IFN(SSI_SCK34),
- GPIO_FN(MSIOF1_SS1_A),
- GPIO_FN(STP_OPWM_0_A),
- GPIO_IFN(SSI_WS34),
- GPIO_FN(HCTS2x_A),
- GPIO_FN(MSIOF1_SS2_A),
- GPIO_FN(STP_IVCXO27_0_A),
- GPIO_IFN(SSI_SDATA3),
- GPIO_FN(HRTS2x_A),
- GPIO_FN(MSIOF1_TXD_A),
- GPIO_FN(TS_SCK0_A),
- GPIO_FN(STP_ISCLK_0_A),
- GPIO_FN(RIF0_D1_A),
- GPIO_FN(RIF2_D0_A),
- GPIO_IFN(SSI_SCK4),
- GPIO_FN(HRX2_A),
- GPIO_FN(MSIOF1_SCK_A),
- GPIO_FN(TS_SDAT0_A),
- GPIO_FN(STP_ISD_0_A),
- GPIO_FN(RIF0_CLK_A),
- GPIO_FN(RIF2_CLK_A),
- GPIO_IFN(SSI_WS4),
- GPIO_FN(HTX2_A),
- GPIO_FN(MSIOF1_SYNC_A),
- GPIO_FN(TS_SDEN0_A),
- GPIO_FN(STP_ISEN_0_A),
- GPIO_FN(RIF0_SYNC_A),
- GPIO_FN(RIF2_SYNC_A),
- GPIO_IFN(SSI_SDATA4),
- GPIO_FN(HSCK2_A),
- GPIO_FN(MSIOF1_RXD_A),
- GPIO_FN(TS_SPSYNC0_A),
- GPIO_FN(STP_ISSYNC_0_A),
- GPIO_FN(RIF0_D0_A),
- GPIO_FN(RIF2_D1_A),
-
- /* IPSR16 */
- GPIO_IFN(SSI_SCK6),
- GPIO_FN(SIM0_RST_D),
- GPIO_IFN(SSI_WS6),
- GPIO_FN(SIM0_D_D),
- GPIO_IFN(SSI_SDATA6),
- GPIO_FN(SIM0_CLK_D),
- GPIO_FN(SATA_DEVSLP_A),
- GPIO_IFN(SSI_SCK78),
- GPIO_FN(HRX2_B),
- GPIO_FN(MSIOF1_SCK_C),
- GPIO_FN(TS_SCK1_A),
- GPIO_FN(STP_ISCLK_1_A),
- GPIO_FN(RIF1_CLK_A),
- GPIO_FN(RIF3_CLK_A),
- GPIO_IFN(SSI_WS78),
- GPIO_FN(HTX2_B),
- GPIO_FN(MSIOF1_SYNC_C),
- GPIO_FN(TS_SDAT1_A),
- GPIO_FN(STP_ISD_1_A),
- GPIO_FN(RIF1_SYNC_A),
- GPIO_FN(RIF3_SYNC_A),
- GPIO_IFN(SSI_SDATA7),
- GPIO_FN(HCTS2x_B),
- GPIO_FN(MSIOF1_RXD_C),
- GPIO_FN(TS_SDEN1_A),
- GPIO_FN(STP_ISEN_1_A),
- GPIO_FN(RIF1_D0_A),
- GPIO_FN(RIF3_D0_A),
- GPIO_FN(TCLK2_A),
- GPIO_IFN(SSI_SDATA8),
- GPIO_FN(HRTS2x_B),
- GPIO_FN(MSIOF1_TXD_C),
- GPIO_FN(TS_SPSYNC1_A),
- GPIO_FN(STP_ISSYNC_1_A),
- GPIO_FN(RIF1_D1_A),
- GPIO_FN(RIF3_D1_A),
- GPIO_IFN(SSI_SDATA9_A),
- GPIO_FN(HSCK2_B),
- GPIO_FN(MSIOF1_SS1_C),
- GPIO_FN(HSCK1_A),
- GPIO_FN(SSI_WS1_B),
- GPIO_FN(SCK1),
- GPIO_FN(STP_IVCXO27_1_A),
- GPIO_FN(SCK5_A),
-
- /* IPSR17 */
- GPIO_IFN(AUDIO_CLKA_A),
- GPIO_FN(CC5_OSCOUT),
- GPIO_IFN(AUDIO_CLKB_B),
- GPIO_FN(SCIF_CLK_A),
- GPIO_FN(STP_IVCXO27_1_D),
- GPIO_FN(REMOCON_A),
- GPIO_FN(TCLK1_A),
- GPIO_IFN(USB0_PWEN),
- GPIO_FN(SIM0_RST_C),
- GPIO_FN(TS_SCK1_D),
- GPIO_FN(STP_ISCLK_1_D),
- GPIO_FN(BPFCLK_B),
- GPIO_FN(RIF3_CLK_B),
- GPIO_FN(HSCK2_C),
- GPIO_IFN(USB0_OVC),
- GPIO_FN(SIM0_D_C),
- GPIO_FN(TS_SDAT1_D),
- GPIO_FN(STP_ISD_1_D),
- GPIO_FN(RIF3_SYNC_B),
- GPIO_FN(HRX2_C),
- GPIO_IFN(USB1_PWEN),
- GPIO_FN(SIM0_CLK_C),
- GPIO_FN(SSI_SCK1_A),
- GPIO_FN(TS_SCK0_E),
- GPIO_FN(STP_ISCLK_0_E),
- GPIO_FN(FMCLK_B),
- GPIO_FN(RIF2_CLK_B),
- GPIO_FN(SPEEDIN_A),
- GPIO_FN(HTX2_C),
- GPIO_IFN(USB1_OVC),
- GPIO_FN(MSIOF1_SS2_C),
- GPIO_FN(SSI_WS1_A),
- GPIO_FN(TS_SDAT0_E),
- GPIO_FN(STP_ISD_0_E),
- GPIO_FN(FMIN_B),
- GPIO_FN(RIF2_SYNC_B),
- GPIO_FN(REMOCON_B),
- GPIO_FN(HCTS2x_C),
- GPIO_IFN(USB30_PWEN),
- GPIO_FN(AUDIO_CLKOUT_B),
- GPIO_FN(SSI_SCK2_B),
- GPIO_FN(TS_SDEN1_D),
- GPIO_FN(STP_ISEN_1_D),
- GPIO_FN(STP_OPWM_0_E),
- GPIO_FN(RIF3_D0_B),
- GPIO_FN(TCLK2_B),
- GPIO_FN(TPU0TO0),
- GPIO_FN(BPFCLK_C),
- GPIO_FN(HRTS2x_C),
- GPIO_IFN(USB30_OVC),
- GPIO_FN(AUDIO_CLKOUT1_B),
- GPIO_FN(SSI_WS2_B),
- GPIO_FN(TS_SPSYNC1_D),
- GPIO_FN(STP_ISSYNC_1_D),
- GPIO_FN(STP_IVCXO27_0_E),
- GPIO_FN(RIF3_D1_B),
- GPIO_FN(FSO_TOEx),
- GPIO_FN(TPU0TO1),
-
- /* IPSR18 */
- GPIO_IFN(USB3_PWEN),
- GPIO_FN(AUDIO_CLKOUT2_B),
- GPIO_FN(SSI_SCK9_B),
- GPIO_FN(TS_SDEN0_E),
- GPIO_FN(STP_ISEN_0_E),
- GPIO_FN(RIF2_D0_B),
- GPIO_FN(TPU0TO2),
- GPIO_FN(FMCLK_C),
- GPIO_FN(FMCLK_D),
-
- GPIO_IFN(USB3_OVC),
- GPIO_FN(AUDIO_CLKOUT3_B),
- GPIO_FN(SSI_WS9_B),
- GPIO_FN(TS_SPSYNC0_E),
- GPIO_FN(STP_ISSYNC_0_E),
- GPIO_FN(RIF2_D1_B),
- GPIO_FN(TPU0TO3),
- GPIO_FN(FMIN_C),
- GPIO_FN(FMIN_D),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- /* GPSR0(0xE6060100) md[3:1] controls initial value */
- /* md[3:1] .. 0 : 0x0000FFFF */
- /* .. other : 0x00000000 */
- { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_0_15_FN, GFN_D15,
- GP_0_14_FN, GFN_D14,
- GP_0_13_FN, GFN_D13,
- GP_0_12_FN, GFN_D12,
- GP_0_11_FN, GFN_D11,
- GP_0_10_FN, GFN_D10,
- GP_0_9_FN, GFN_D9,
- GP_0_8_FN, GFN_D8,
- GP_0_7_FN, GFN_D7,
- GP_0_6_FN, GFN_D6,
- GP_0_5_FN, GFN_D5,
- GP_0_4_FN, GFN_D4,
- GP_0_3_FN, GFN_D3,
- GP_0_2_FN, GFN_D2,
- GP_0_1_FN, GFN_D1,
- GP_0_0_FN, GFN_D0 }
- },
- /* GPSR1(0xE6060104) is md[3:1] controls initial value */
- /* md[3:1] .. 0 : 0x0EFFFFFF */
- /* .. other : 0x00000000 */
- { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_28_FN, GFN_CLKOUT,
- GP_1_27_FN, GFN_EX_WAIT0_A,
- GP_1_26_FN, GFN_WE1x,
- GP_1_25_FN, GFN_WE0x,
- GP_1_24_FN, GFN_RD_WRx,
- GP_1_23_FN, GFN_RDx,
- GP_1_22_FN, GFN_BSx,
- GP_1_21_FN, GFN_CS1x_A26,
- GP_1_20_FN, GFN_CS0x,
- GP_1_19_FN, GFN_A19,
- GP_1_18_FN, GFN_A18,
- GP_1_17_FN, GFN_A17,
- GP_1_16_FN, GFN_A16,
- GP_1_15_FN, GFN_A15,
- GP_1_14_FN, GFN_A14,
- GP_1_13_FN, GFN_A13,
- GP_1_12_FN, GFN_A12,
- GP_1_11_FN, GFN_A11,
- GP_1_10_FN, GFN_A10,
- GP_1_9_FN, GFN_A9,
- GP_1_8_FN, GFN_A8,
- GP_1_7_FN, GFN_A7,
- GP_1_6_FN, GFN_A6,
- GP_1_5_FN, GFN_A5,
- GP_1_4_FN, GFN_A4,
- GP_1_3_FN, GFN_A3,
- GP_1_2_FN, GFN_A2,
- GP_1_1_FN, GFN_A1,
- GP_1_0_FN, GFN_A0 }
- },
- /* GPSR2(0xE6060108) is md[3:1] controls */
- /* md[3:1] .. 0 : 0x000003C0 */
- /* .. other : 0x00000200 */
- { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A,
- GP_2_13_FN, GFN_AVB_AVTP_MATCH_A,
- GP_2_12_FN, GFN_AVB_LINK,
- GP_2_11_FN, GFN_AVB_PHY_INT,
- GP_2_10_FN, GFN_AVB_MAGIC,
- GP_2_9_FN, GFN_AVB_MDC,
- GP_2_8_FN, GFN_PWM2_A,
- GP_2_7_FN, GFN_PWM1_A,
- GP_2_6_FN, GFN_PWM0,
- GP_2_5_FN, GFN_IRQ5,
- GP_2_4_FN, GFN_IRQ4,
- GP_2_3_FN, GFN_IRQ3,
- GP_2_2_FN, GFN_IRQ2,
- GP_2_1_FN, GFN_IRQ1,
- GP_2_0_FN, GFN_IRQ0 }
- },
-
- /* GPSR3 */
- { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_3_15_FN, GFN_SD1_WP,
- GP_3_14_FN, GFN_SD1_CD,
- GP_3_13_FN, GFN_SD0_WP,
- GP_3_12_FN, GFN_SD0_CD,
- GP_3_11_FN, GFN_SD1_DAT3,
- GP_3_10_FN, GFN_SD1_DAT2,
- GP_3_9_FN, GFN_SD1_DAT1,
- GP_3_8_FN, GFN_SD1_DAT0,
- GP_3_7_FN, GFN_SD1_CMD,
- GP_3_6_FN, GFN_SD1_CLK,
- GP_3_5_FN, GFN_SD0_DAT3,
- GP_3_4_FN, GFN_SD0_DAT2,
- GP_3_3_FN, GFN_SD0_DAT1,
- GP_3_2_FN, GFN_SD0_DAT0,
- GP_3_1_FN, GFN_SD0_CMD,
- GP_3_0_FN, GFN_SD0_CLK }
- },
- /* GPSR4 */
- { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_17_FN, GFN_SD3_DS,
- GP_4_16_FN, GFN_SD3_DAT7,
-
- GP_4_15_FN, GFN_SD3_DAT6,
- GP_4_14_FN, GFN_SD3_DAT5,
- GP_4_13_FN, GFN_SD3_DAT4,
- GP_4_12_FN, GFN_SD3_DAT3,
- GP_4_11_FN, GFN_SD3_DAT2,
- GP_4_10_FN, GFN_SD3_DAT1,
- GP_4_9_FN, GFN_SD3_DAT0,
- GP_4_8_FN, GFN_SD3_CMD,
- GP_4_7_FN, GFN_SD3_CLK,
- GP_4_6_FN, GFN_SD2_DS,
- GP_4_5_FN, GFN_SD2_DAT3,
- GP_4_4_FN, GFN_SD2_DAT2,
- GP_4_3_FN, GFN_SD2_DAT1,
- GP_4_2_FN, GFN_SD2_DAT0,
- GP_4_1_FN, GFN_SD2_CMD,
- GP_4_0_FN, GFN_SD2_CLK }
- },
- /* GPSR5 */
- { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_25_FN, GFN_MLB_DAT,
- GP_5_24_FN, GFN_MLB_SIG,
- GP_5_23_FN, GFN_MLB_CLK,
- GP_5_22_FN, FN_MSIOF0_RXD,
- GP_5_21_FN, GFN_MSIOF0_SS2,
- GP_5_20_FN, FN_MSIOF0_TXD,
- GP_5_19_FN, GFN_MSIOF0_SS1,
- GP_5_18_FN, GFN_MSIOF0_SYNC,
- GP_5_17_FN, FN_MSIOF0_SCK,
- GP_5_16_FN, GFN_HRTS0x,
- GP_5_15_FN, GFN_HCTS0x,
- GP_5_14_FN, GFN_HTX0,
- GP_5_13_FN, GFN_HRX0,
- GP_5_12_FN, GFN_HSCK0,
- GP_5_11_FN, GFN_RX2_A,
- GP_5_10_FN, GFN_TX2_A,
- GP_5_9_FN, GFN_SCK2,
- GP_5_8_FN, GFN_RTS1x_TANS,
- GP_5_7_FN, GFN_CTS1x,
- GP_5_6_FN, GFN_TX1_A,
- GP_5_5_FN, GFN_RX1_A,
- GP_5_4_FN, GFN_RTS0x_TANS,
- GP_5_3_FN, GFN_CTS0x,
- GP_5_2_FN, GFN_TX0,
- GP_5_1_FN, GFN_RX0,
- GP_5_0_FN, GFN_SCK0 }
- },
- /* GPSR6 */
- { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
- GP_6_31_FN, GFN_USB3_OVC,
- GP_6_30_FN, GFN_USB3_PWEN,
- GP_6_29_FN, GFN_USB30_OVC,
- GP_6_28_FN, GFN_USB30_PWEN,
- GP_6_27_FN, GFN_USB1_OVC,
- GP_6_26_FN, GFN_USB1_PWEN,
- GP_6_25_FN, GFN_USB0_OVC,
- GP_6_24_FN, GFN_USB0_PWEN,
- GP_6_23_FN, GFN_AUDIO_CLKB_B,
- GP_6_22_FN, GFN_AUDIO_CLKA_A,
- GP_6_21_FN, GFN_SSI_SDATA9_A,
- GP_6_20_FN, GFN_SSI_SDATA8,
- GP_6_19_FN, GFN_SSI_SDATA7,
- GP_6_18_FN, GFN_SSI_WS78,
- GP_6_17_FN, GFN_SSI_SCK78,
- GP_6_16_FN, GFN_SSI_SDATA6,
- GP_6_15_FN, GFN_SSI_WS6,
- GP_6_14_FN, GFN_SSI_SCK6,
- GP_6_13_FN, FN_SSI_SDATA5,
- GP_6_12_FN, FN_SSI_WS5,
- GP_6_11_FN, FN_SSI_SCK5,
- GP_6_10_FN, GFN_SSI_SDATA4,
- GP_6_9_FN, GFN_SSI_WS4,
- GP_6_8_FN, GFN_SSI_SCK4,
- GP_6_7_FN, GFN_SSI_SDATA3,
- GP_6_6_FN, GFN_SSI_WS34,
- GP_6_5_FN, GFN_SSI_SCK34,
- GP_6_4_FN, GFN_SSI_SDATA2_A,
- GP_6_3_FN, GFN_SSI_SDATA1_A,
- GP_6_2_FN, GFN_SSI_SDATA0,
- GP_6_1_FN, GFN_SSI_WS01239,
- GP_6_0_FN, GFN_SSI_SCK01239 }
- },
- /* GPSR7 */
- { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_3_FN, FN_HDMI1_CEC,
- GP_7_2_FN, FN_HDMI0_CEC,
- GP_7_1_FN, FN_AVS2,
- GP_7_0_FN, FN_AVS1 }
- },
- { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR0_31_28 [4] */
- IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,
- FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_27_24 [4] */
- IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,
- FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_23_20 [4] */
- IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_19_16 [4] */
- IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,
- 0, FN_FSCLKST2x_A, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_15_12 [4] */
- IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_11_8 [4] */
- IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_7_4 [4] */
- IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_3_0 [4] */
- IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR1_31_28 [4] */
- IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,
- FN_VI4_DATA8, 0, FN_DU_DB0, 0,
- 0, FN_PWM3_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_27_24 [4] */
- IFN_PWM2_A, 0, 0, FN_HTX3_D,
- 0, 0, 0, 0,
- 0, FN_IETX_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_23_20 [4] */
- IFN_PWM1_A, 0, 0, FN_HRX3_D,
- FN_VI4_DATA7_B, 0, 0, 0,
- 0, FN_IERX_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_19_16 [4] */
- IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0,
- FN_VI4_DATA6_B, 0, 0, 0,
- 0, FN_IECLK_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_15_12 [4] */
- IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,
- FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E,
- 0, FN_PWM6_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_11_8 [4] */
- IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,
- FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E,
- 0, FN_PWM5_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_7_4 [4] */
- IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,
- FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E,
- 0, FN_PWM4_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_3_0 [4] */
- IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E,
- 0, FN_PWM3_B, 0, 0,
- 0, 0, 0, 0
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR2_31_28 [4] */
- IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,
- 0, 0, 0, FN_SDA6_A,
- FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_27_24 [4] */
- IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,
- FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_23_20 [4] */
- IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,
- FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_19_16 [4] */
- IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,
- FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_15_12 [4] */
- IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,
- FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_11_8 [4] */
- IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,
- FN_VI4_DATA11, 0, FN_DU_DB3, 0,
- 0, FN_PWM6_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_7_4 [4] */
- IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,
- FN_VI4_DATA10, 0, FN_DU_DB2, 0,
- 0, FN_PWM5_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_3_0 [4] */
- IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,
- FN_VI4_DATA9, 0, FN_DU_DB1, 0,
- 0, FN_PWM4_A, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR3_31_28 [4] */
- IFN_A16, FN_LCDOUT8, 0, 0,
- FN_VI4_FIELD, 0, FN_DU_DG0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_27_24 [4] */
- IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,
- FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_23_20 [4] */
- IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,
- FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_19_16 [4] */
- IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,
- FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_15_12 [4] */
- IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,
- FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_11_8 [4] */
- IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,
- FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,
- FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_7_4 [4] */
- IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,
- 0, FN_VI5_HSYNCx, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_3_0 [4] */
- IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B,
- 0, FN_VI5_VSYNCx, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR4_31_28 [4] */
- IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A,
- FN_HTX3_A, 0, 0, 0,
- FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_27_24 [4] */
- IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,
- FN_HRX3_A, 0, 0, 0,
- FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_23_20 [4] */
- IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,
- FN_HSCK3, 0, 0, 0,
- FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,
- 0, 0, 0, 0,
- /* IPSR4_19_16 [4] */
- IFN_CS1x_A26, 0, 0, 0,
- 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_15_12 [4] */
- IFN_CS0x, 0, 0, 0,
- 0, FN_VI5_CLKENB, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_11_8 [4] */
- IFN_A19, FN_LCDOUT11, 0, 0,
- FN_VI4_CLKENB, 0, FN_DU_DG3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_7_4 [4] */
- IFN_A18, FN_LCDOUT10, 0, 0,
- FN_VI4_HSYNCx, 0, FN_DU_DG2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_3_0 [4] */
- IFN_A17, FN_LCDOUT9, 0, 0,
- FN_VI4_VSYNCx, 0, FN_DU_DG1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR5_31_28 [4] */
- IFN_D4, FN_MSIOF2_SCK_B, 0, 0,
- FN_VI4_DATA20, FN_VI5_DATA4, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_27_24 [4] */
- IFN_D3, 0, FN_MSIOF3_TXD_A, 0,
- FN_VI4_DATA19, FN_VI5_DATA3, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_23_20 [4] */
- IFN_D2, 0, FN_MSIOF3_RXD_A, 0,
- FN_VI4_DATA18, FN_VI5_DATA2, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_19_16 [4] */
- IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,
- FN_VI4_DATA17, FN_VI5_DATA1, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_15_12 [4] */
- IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,
- FN_VI4_DATA16, FN_VI5_DATA0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_11_8 [4] */
- IFN_EX_WAIT0_A, FN_QCLK, 0, 0,
- FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_7_4 [4] */
- IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS,
- FN_HRTS3x, 0, 0, FN_SDA6_B,
- FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,
- 0, 0, 0, 0,
- /* IPSR5_3_0 [4] */
- IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x,
- FN_HCTS3x, 0, 0, FN_SCL6_B,
- FN_CAN_CLK, 0, FN_IECLK_A, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR6_31_28 [4] */
- IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,
- FN_VI4_DATA4_A, 0, FN_DU_DR4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_27_24 [4] */
- IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,
- FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_23_20 [4] */
- IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,
- FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_19_16 [4] */
- IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,
- FN_VI4_DATA1_A, 0, FN_DU_DR1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_15_12 [4] */
- IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,
- FN_VI4_DATA0_A, 0, FN_DU_DR0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_11_8 [4] */
- IFN_D7, FN_MSIOF2_TXD_B, 0, 0,
- FN_VI4_DATA23, FN_VI5_DATA7, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_7_4 [4] */
- IFN_D6, FN_MSIOF2_RXD_B, 0, 0,
- FN_VI4_DATA22, FN_VI5_DATA6, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_3_0 [4] */
- IFN_D5, FN_MSIOF2_SYNC_B, 0, 0,
- FN_VI4_DATA21, FN_VI5_DATA5, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR7_31_28 [4] */
- IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,
- 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_27_24 [4] */
- IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,
- 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_23_20 [4] */
- IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,
- 0, 0, FN_STP_IVCXO27_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_19_16 [4] */
- IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,
- 0, 0, FN_STP_OPWM_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_15_12 [4] */
- FN_FSCLKST, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_11_8 [4] */
- IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,
- FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_7_4 [4] */
- IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,
- FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_3_0 [4] */
- IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,
- FN_VI4_DATA5_A, 0, FN_DU_DR5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR8_31_28 [4] */
- IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B,
- 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_27_24 [4] */
- IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B,
- 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_23_20 [4] */
- IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B,
- 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_19_16 [4] */
- IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B,
- 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_15_12 [4] */
- IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B,
- 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_11_8 [4] */
- IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,
- 0, FN_SIM0_CLK_A, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_7_4 [4] */
- IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,
- 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_3_0 [4] */
- IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,
- 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR9_31_28 [4] */
- IFN_SD3_CLK, 0, FN_NFWEx, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_27_24 [4] */
- IFN_SD2_DS, 0, FN_NFALE, 0,
- 0, 0, 0, 0,
- FN_SATA_DEVSLP_B, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_23_20 [4] */
- IFN_SD2_DAT3, 0, FN_NFDATA13, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_19_16 [4] */
- IFN_SD2_DAT2, 0, FN_NFDATA12, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_15_12 [4] */
- IFN_SD2_DAT1, 0, FN_NFDATA11, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_11_8 [4] */
- IFN_SD2_DAT0, 0, FN_NFDATA10, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_7_4 [4] */
- IFN_SD2_CMD, 0, FN_NFDATA9, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_3_0 [4] */
- IFN_SD2_CLK, 0, FN_NFDATA8, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR10_31_28 [4] */
- IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_27_24 [4] */
- IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_23_20 [4] */
- IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_19_16 [4] */
- IFN_SD3_DAT3, 0, FN_NFDATA3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_15_12 [4] */
- IFN_SD3_DAT2, 0, FN_NFDATA2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_11_8 [4] */
- IFN_SD3_DAT1, 0, FN_NFDATA1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_7_4 [4] */
- IFN_SD3_DAT0, 0, FN_NFDATA0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_3_0 [4] */
- IFN_SD3_CMD, 0, FN_NFREx, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR11_31_28 [4] */
- IFN_RX0, FN_HRX1_B, 0, 0,
- 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_27_24 [4] */
- IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
- FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B,
- FN_ADICHS2, FN_SCK5_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_23_20 [4] */
- IFN_SD1_WP, 0, FN_NFCEx_A, 0,
- 0, FN_SIM0_D_B, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_19_16 [4] */
- IFN_SD1_CD, 0, FN_NFRBx_A, 0,
- 0, FN_SIM0_CLK_B, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_15_12 [4] */
- IFN_SD0_WP, 0, FN_NFDATA15_A, 0,
- FN_SDA2_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_11_8 [4] */
- IFN_SD0_CD, 0, FN_NFDATA14_A, 0,
- FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_7_4 [4] */
- IFN_SD3_DS, 0, FN_NFCLE, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_3_0 [4] */
- IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR12_31_28 [4] */
- IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,
- 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
- 0, FN_ADICLK, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_27_24 [4] */
- IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,
- 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,
- 0, FN_ADICHS0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_23_20 [4] */
- IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,
- 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,
- 0, FN_ADIDATA, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_19_16 [4] */
- IFN_TX1_A, FN_HTX1_A, 0, 0,
- 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_15_12 [4] */
- IFN_RX1_A, FN_HRX1_A, 0, 0,
- 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_11_8 [4] */
- IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,
- FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,
- 0, FN_ADICHS1, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_7_4 [4] */
- IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,
- 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
- FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_3_0 [4] */
- IFN_TX0, FN_HTX1_B, 0, 0,
- 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR13_31_28 [4] */
- IFN_MSIOF0_SYNC, 0, 0, 0,
- 0, 0, 0, 0,
- FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0,
- 0, FN_BPFCLK_D, 0, 0,
- /* IPSR13_27_24 [4] */
- IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,
- FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,
- FN_AUDIO_CLKOUT2_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_23_20 [4] */
- IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,
- FN_SSI_SCK9_A, FN_TS_SPSYNC0_D,
- FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C,
- FN_AUDIO_CLKOUT1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_19_16 [4] */
- IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,
- FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_15_12 [4] */
- IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,
- FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_11_8 [4] */
- IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,
- FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,
- 0, 0, FN_RX5_B, 0,
- 0, 0, 0, 0,
- /* IPSR13_7_4 [4] */
- IFN_RX2_A, 0, 0, FN_SD2_WP_B,
- FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,
- 0, FN_FSO_CFE_1x, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_3_0 [4] */
- IFN_TX2_A, 0, 0, FN_SD2_CD_B,
- FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,
- 0, FN_FSO_CFE_0x, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR14_31_28 [4] */
- IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,
- 0, 0, 0, FN_MOUT2,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_27_24 [4] */
- IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0,
- 0, 0, 0, 0, FN_MOUT1,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_23_20 [4] */
- IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0,
- 0, 0, 0, FN_MOUT0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_19_16 [4] */
- IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_15_12 [4] */
- IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,
- FN_SDA1_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_11_8 [4] */
- IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,
- FN_SCL1_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_7_4 [4] */
- IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
- FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,
- FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,
- 0, 0, 0, 0,
- /* IPSR14_3_0 [4] */
- IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C,
- FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,
- FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR15_31_28 [4] */
- IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,
- 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,
- FN_RIF2_D1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_27_24 [4] */
- IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,
- 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,
- FN_RIF2_SYNC_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_23_20 [4] */
- IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,
- 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
- FN_RIF2_CLK_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_19_16 [4] */
- IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,
- 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,
- FN_RIF2_D0_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_15_12 [4] */
- IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,
- 0, 0, FN_STP_IVCXO27_0_A, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_11_8 [4] */
- IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,
- 0, 0, FN_STP_OPWM_0_A, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_7_4 [4] */
- IFN_SSI_SDATA2_A, 0, 0, 0,
- FN_SSI_SCK1_B, 0, 0, FN_MOUT6,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_3_0 [4] */
- IFN_SSI_SDATA1_A, 0, 0, 0,
- 0, 0, 0, FN_MOUT5,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR16_31_28 [4] */
- IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,
- FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_27_24 [4] */
- IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,
- 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,
- FN_RIF3_D1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_23_20 [4] */
- IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,
- 0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A,
- FN_RIF3_D0_A, 0, FN_TCLK2_A, 0,
- 0, 0, 0, 0,
- /* IPSR16_19_16 [4] */
- IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,
- 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
- FN_RIF3_SYNC_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_15_12 [4] */
- IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,
- 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,
- FN_RIF3_CLK_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_11_8 [4] */
- IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,
- 0, 0, 0, 0,
- FN_SATA_DEVSLP_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_7_4 [4] */
- IFN_SSI_WS6, 0, 0, FN_SIM0_D_D,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_3_0 [4] */
- IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR17_31_28 [4] */
- IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B,
- FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E,
- FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1,
- 0, 0, 0, 0,
- /* IPSR17_27_24 [4] */
- IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,
- FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
- FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,
- FN_BPFCLK_C, FN_HRTS2x_C, 0, 0,
- /* IPSR17_23_20 [4] */
- IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,
- FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
- FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,
- 0, FN_HCTS2x_C, 0, 0,
- /* IPSR17_19_16 [4] */
- IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,
- FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
- FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,
- 0, FN_HTX2_C, 0, 0,
- /* IPSR17_15_12 [4] */
- IFN_USB0_OVC, 0, 0, FN_SIM0_D_C,
- 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,
- FN_RIF3_SYNC_B, 0, 0, 0,
- 0, FN_HRX2_C, 0, 0,
- /* IPSR17_11_8 [4] */
- IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,
- 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
- FN_RIF3_CLK_B, 0, 0, 0,
- 0, FN_HSCK2_C, 0, 0,
- /* IPSR17_7_4 [4] */
- IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,
- 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
- 0, 0, FN_TCLK1_A, 0,
- 0, 0, 0, 0,
- /* IPSR17_3_0 [4] */
- IFN_AUDIO_CLKA_A, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, FN_CC5_OSCOUT,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 4, 4) {
- /* reserved [31..24] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* reserved [23..16] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* reserved [15..8] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* IPSR18_7_4 [4] */
- IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,
- FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,
- FN_RIF2_D1_B, 0, 0, FN_TPU0TO3,
- FN_FMIN_C, FN_FMIN_D, 0, 0,
- /* IPSR18_3_0 [4] */
- IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,
- FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
- FN_RIF2_D0_B, 0, 0, FN_TPU0TO2,
- FN_FMCLK_C, FN_FMCLK_D, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) {
- /* MOD_SEL0 */
- /* sel_msiof3[3](0,1,2,3,4) */
- FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
- FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
- FN_SEL_MSIOF3_4, 0,
- 0, 0,
- /* sel_msiof2[2](0,1,2,3) */
- FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
- FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
- /* sel_msiof1[3](0,1,2,3,4,5,6) */
- FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
- FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
- FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
- FN_SEL_MSIOF1_6, 0,
- /* sel_lbsc[1](0,1) */
- FN_SEL_LBSC_0, FN_SEL_LBSC_1,
- /* sel_iebus[1](0,1) */
- FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
- /* sel_i2c2[1](0,1) */
- FN_SEL_I2C2_0, FN_SEL_I2C2_1,
- /* sel_i2c1[1](0,1) */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1,
- /* sel_hscif4[1](0,1) */
- FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
- /* sel_hscif3[2](0,1,2,3) */
- FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
- FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
- /* sel_hscif1[1](0,1) */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* reserved[1] */
- 0, 0,
- /* sel_hscif2[2](0,1,2) */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, 0,
- /* sel_etheravb[1](0,1) */
- FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
- /* sel_drif3[1](0,1) */
- FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
- /* sel_drif2[1](0,1) */
- FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
- /* sel_drif1[2](0,1,2) */
- FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
- FN_SEL_DRIF1_2, 0,
- /* sel_drif0[2](0,1,2) */
- FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
- FN_SEL_DRIF0_2, 0,
- /* sel_canfd0[1](0,1) */
- FN_SEL_CANFD_0, FN_SEL_CANFD_1,
- /* sel_adg_a[2](0,1,2) */
- FN_SEL_ADG_A_0, FN_SEL_ADG_A_1,
- FN_SEL_ADG_A_2, 0,
- /* reserved[3]*/
- 0, 0,
- 0, 0,
- 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32,
- 2, 3, 1, 2,
- 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
- /* sel_tsif1[2](0,1,2,3) */
- FN_SEL_TSIF1_0, FN_SEL_TSIF1_1,
- FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
- /* sel_tsif0[3](0,1,2,3,4) */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_TSIF0_4, 0,
- 0, 0,
- /* sel_timer_tmu1[1](0,1) */
- FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,
- /* sel_ssp1_1[2](0,1,2,3) */
- FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,
- FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,
- /* sel_ssp1_0[3](0,1,2,3,4) */
- FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
- FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,
- FN_SEL_SSP1_0_4, 0,
- 0, 0,
- /* sel_ssi1[1](0,1) */
- FN_SEL_SSI_0, FN_SEL_SSI_1,
- /* sel_speed_pulse_if[1](0,1) */
- FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
- /* sel_simcard[2](0,1,2,3) */
- FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,
- FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
- /* sel_sdhi2[1](0,1) */
- FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
- /* sel_scif4[2](0,1,2) */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
- FN_SEL_SCIF4_2, 0,
- /* sel_scif3[1](0,1) */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- /* sel_scif2[1](0,1) */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
- /* sel_scif1[1](0,1) */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
- /* sel_scif[1](0,1) */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* sel_remocon[1](0,1) */
- FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
- /* reserved[8..7] */
- 0, 0,
- 0, 0,
- /* sel_rcan0[1](0,1) */
- FN_SEL_RCAN_0, FN_SEL_RCAN_1,
- /* sel_pwm6[1](0,1) */
- FN_SEL_PWM6_0, FN_SEL_PWM6_1,
- /* sel_pwm5[1](0,1) */
- FN_SEL_PWM5_0, FN_SEL_PWM5_1,
- /* sel_pwm4[1](0,1) */
- FN_SEL_PWM4_0, FN_SEL_PWM4_1,
- /* sel_pwm3[1](0,1) */
- FN_SEL_PWM3_0, FN_SEL_PWM3_1,
- /* sel_pwm2[1](0,1) */
- FN_SEL_PWM2_0, FN_SEL_PWM2_1,
- /* sel_pwm1[1](0,1) */
- FN_SEL_PWM1_0, FN_SEL_PWM1_1,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
- /* i2c_sel_5[1](0,1) */
- FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
- /* i2c_sel_3[1](0,1) */
- FN_I2C_SEL_3_0, FN_I2C_SEL_3_1,
- /* i2c_sel_0[1](0,1) */
- FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
- /* sel_fm[2](0,1,2,3) */
- FN_SEL_FM_0, FN_SEL_FM_1,
- FN_SEL_FM_2, FN_SEL_FM_3,
- /* sel_scif5[1](0,1) */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* sel_i2c6[3](0,1,2) */
- FN_SEL_I2C6_0, FN_SEL_I2C6_1,
- FN_SEL_I2C6_2, 0,
- /* sel_ndfc[1](0,1) */
- FN_SEL_NDFC_0, FN_SEL_NDFC_1,
- /* sel_ssi2[1](0,1) */
- FN_SEL_SSI2_0, FN_SEL_SSI2_1,
- /* sel_ssi9[1](0,1) */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* sel_timer_tmu2[1](0,1) */
- FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,
- /* sel_adg_b[1](0,1) */
- FN_SEL_ADG_B_0, FN_SEL_ADG_B_1,
- /* sel_adg_c[1](0,1) */
- FN_SEL_ADG_C_0, FN_SEL_ADG_C_1,
- /* reserved[16..16] */
- 0, 0,
- /* reserved[15..8] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* reserved[7..1] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* sel_vin4[1](0,1) */
- FN_SEL_VIN4_0, FN_SEL_VIN4_1,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_0_15_IN, GP_0_15_OUT,
- GP_0_14_IN, GP_0_14_OUT,
- GP_0_13_IN, GP_0_13_OUT,
- GP_0_12_IN, GP_0_12_OUT,
- GP_0_11_IN, GP_0_11_OUT,
- GP_0_10_IN, GP_0_10_OUT,
- GP_0_9_IN, GP_0_9_OUT,
- GP_0_8_IN, GP_0_8_OUT,
- GP_0_7_IN, GP_0_7_OUT,
- GP_0_6_IN, GP_0_6_OUT,
- GP_0_5_IN, GP_0_5_OUT,
- GP_0_4_IN, GP_0_4_OUT,
- GP_0_3_IN, GP_0_3_OUT,
- GP_0_2_IN, GP_0_2_OUT,
- GP_0_1_IN, GP_0_1_OUT,
- GP_0_0_IN, GP_0_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_28_IN, GP_1_28_OUT,
- GP_1_27_IN, GP_1_27_OUT,
- GP_1_26_IN, GP_1_26_OUT,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- GP_2_14_IN, GP_2_14_OUT,
- GP_2_13_IN, GP_2_13_OUT,
- GP_2_12_IN, GP_2_12_OUT,
- GP_2_11_IN, GP_2_11_OUT,
- GP_2_10_IN, GP_2_10_OUT,
- GP_2_9_IN, GP_2_9_OUT,
- GP_2_8_IN, GP_2_8_OUT,
- GP_2_7_IN, GP_2_7_OUT,
- GP_2_6_IN, GP_2_6_OUT,
- GP_2_5_IN, GP_2_5_OUT,
- GP_2_4_IN, GP_2_4_OUT,
- GP_2_3_IN, GP_2_3_OUT,
- GP_2_2_IN, GP_2_2_OUT,
- GP_2_1_IN, GP_2_1_OUT,
- GP_2_0_IN, GP_2_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_3_15_IN, GP_3_15_OUT,
- GP_3_14_IN, GP_3_14_OUT,
- GP_3_13_IN, GP_3_13_OUT,
- GP_3_12_IN, GP_3_12_OUT,
- GP_3_11_IN, GP_3_11_OUT,
- GP_3_10_IN, GP_3_10_OUT,
- GP_3_9_IN, GP_3_9_OUT,
- GP_3_8_IN, GP_3_8_OUT,
- GP_3_7_IN, GP_3_7_OUT,
- GP_3_6_IN, GP_3_6_OUT,
- GP_3_5_IN, GP_3_5_OUT,
- GP_3_4_IN, GP_3_4_OUT,
- GP_3_3_IN, GP_3_3_OUT,
- GP_3_2_IN, GP_3_2_OUT,
- GP_3_1_IN, GP_3_1_OUT,
- GP_3_0_IN, GP_3_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_17_IN, GP_4_17_OUT,
- GP_4_16_IN, GP_4_16_OUT,
-
- GP_4_15_IN, GP_4_15_OUT,
- GP_4_14_IN, GP_4_14_OUT,
- GP_4_13_IN, GP_4_13_OUT,
- GP_4_12_IN, GP_4_12_OUT,
- GP_4_11_IN, GP_4_11_OUT,
- GP_4_10_IN, GP_4_10_OUT,
- GP_4_9_IN, GP_4_9_OUT,
- GP_4_8_IN, GP_4_8_OUT,
- GP_4_7_IN, GP_4_7_OUT,
- GP_4_6_IN, GP_4_6_OUT,
- GP_4_5_IN, GP_4_5_OUT,
- GP_4_4_IN, GP_4_4_OUT,
- GP_4_3_IN, GP_4_3_OUT,
- GP_4_2_IN, GP_4_2_OUT,
- GP_4_1_IN, GP_4_1_OUT,
- GP_4_0_IN, GP_4_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_25_IN, GP_5_25_OUT,
- GP_5_24_IN, GP_5_24_OUT,
-
- GP_5_23_IN, GP_5_23_OUT,
- GP_5_22_IN, GP_5_22_OUT,
- GP_5_21_IN, GP_5_21_OUT,
- GP_5_20_IN, GP_5_20_OUT,
- GP_5_19_IN, GP_5_19_OUT,
- GP_5_18_IN, GP_5_18_OUT,
- GP_5_17_IN, GP_5_17_OUT,
- GP_5_16_IN, GP_5_16_OUT,
-
- GP_5_15_IN, GP_5_15_OUT,
- GP_5_14_IN, GP_5_14_OUT,
- GP_5_13_IN, GP_5_13_OUT,
- GP_5_12_IN, GP_5_12_OUT,
- GP_5_11_IN, GP_5_11_OUT,
- GP_5_10_IN, GP_5_10_OUT,
- GP_5_9_IN, GP_5_9_OUT,
- GP_5_8_IN, GP_5_8_OUT,
- GP_5_7_IN, GP_5_7_OUT,
- GP_5_6_IN, GP_5_6_OUT,
- GP_5_5_IN, GP_5_5_OUT,
- GP_5_4_IN, GP_5_4_OUT,
- GP_5_3_IN, GP_5_3_OUT,
- GP_5_2_IN, GP_5_2_OUT,
- GP_5_1_IN, GP_5_1_OUT,
- GP_5_0_IN, GP_5_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
- GP_INOUTSEL(6)
- }
- },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT,
- }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- /* use OUTDT registers? */
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
- GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
- GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
- GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
- },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, GP_1_28_DATA,
- GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
- GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
- GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
- GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
- },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
- GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
- GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
- GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
- },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA,
- GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
- GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
- GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
- GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
- },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_5_25_DATA, GP_5_24_DATA,
- GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
- GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
- GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
- GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
- GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
- GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
- },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
- GP_INDT(6) }
- },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-
-static struct pinmux_info r8a7795_pinmux_info = {
- .name = "r8a7795_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_FMIN_D,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7795_pinmux_init(void)
-{
- register_pinmux(&r8a7795_pinmux_info);
-}
+++ /dev/null
-/*
- * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c
- * This file is r8a7796 processor support - PFC hardware block.
- *
- * Copyright (C) 2016 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx)
-
-#define CPU_32_PORT2(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx)
-
-#define CPU_32_PORT_29(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), \
- PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), \
- PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), \
- PORT_1(fn, pfx##25, sfx), \
- PORT_1(fn, pfx##26, sfx), \
- PORT_1(fn, pfx##27, sfx), \
- PORT_1(fn, pfx##28, sfx)
-
-#define CPU_32_PORT_26(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), \
- PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), \
- PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), \
- PORT_1(fn, pfx##25, sfx)
-
-#define CPU_32_PORT_18(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx), \
- PORT_1(fn, pfx##15, sfx), \
- PORT_1(fn, pfx##16, sfx), \
- PORT_1(fn, pfx##17, sfx)
-
-#define CPU_32_PORT_16(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx), \
- PORT_1(fn, pfx##15, sfx)
-
-#define CPU_32_PORT_15(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
- PORT_1(fn, pfx##10, sfx), \
- PORT_1(fn, pfx##11, sfx), \
- PORT_1(fn, pfx##12, sfx), \
- PORT_1(fn, pfx##13, sfx), \
- PORT_1(fn, pfx##14, sfx)
-
-#define CPU_32_PORT_4(fn, pfx, sfx) \
- PORT_1(fn, pfx##0, sfx), \
- PORT_1(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##3, sfx)
-
-
-/* --gen3-- */
-/* GP_0_0_DATA -> GP_7_4_DATA */
-/* except for GP0[16] - [31],
- GP1[28] - [31],
- GP2[15] - [31],
- GP3[16] - [31],
- GP4[18] - [31],
- GP5[26] - [31],
- GP7[4] - [31] */
-
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT_16(fn, pfx##_0_, sfx), \
- CPU_32_PORT_29(fn, pfx##_1_, sfx), \
- CPU_32_PORT_15(fn, pfx##_2_, sfx), \
- CPU_32_PORT_16(fn, pfx##_3_, sfx), \
- CPU_32_PORT_18(fn, pfx##_4_, sfx), \
- CPU_32_PORT_26(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT_4(fn, pfx##_7_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- GFN_D15,
- GFN_D14,
- GFN_D13,
- GFN_D12,
- GFN_D11,
- GFN_D10,
- GFN_D9,
- GFN_D8,
- GFN_D7,
- GFN_D6,
- GFN_D5,
- GFN_D4,
- GFN_D3,
- GFN_D2,
- GFN_D1,
- GFN_D0,
-
- /* GPSR1 */
- GFN_CLKOUT,
- GFN_EX_WAIT0_A,
- GFN_WE1x,
- GFN_WE0x,
- GFN_RD_WRx,
- GFN_RDx,
- GFN_BSx,
- GFN_CS1x_A26,
- GFN_CS0x,
- GFN_A19,
- GFN_A18,
- GFN_A17,
- GFN_A16,
- GFN_A15,
- GFN_A14,
- GFN_A13,
- GFN_A12,
- GFN_A11,
- GFN_A10,
- GFN_A9,
- GFN_A8,
- GFN_A7,
- GFN_A6,
- GFN_A5,
- GFN_A4,
- GFN_A3,
- GFN_A2,
- GFN_A1,
- GFN_A0,
-
- /* GPSR2 */
- GFN_AVB_AVTP_CAPTURE_A,
- GFN_AVB_AVTP_MATCH_A,
- GFN_AVB_LINK,
- GFN_AVB_PHY_INT,
- GFN_AVB_MAGIC,
- GFN_AVB_MDC,
- GFN_PWM2_A,
- GFN_PWM1_A,
- GFN_PWM0,
- GFN_IRQ5,
- GFN_IRQ4,
- GFN_IRQ3,
- GFN_IRQ2,
- GFN_IRQ1,
- GFN_IRQ0,
-
- /* GPSR3 */
- GFN_SD1_WP,
- GFN_SD1_CD,
- GFN_SD0_WP,
- GFN_SD0_CD,
- GFN_SD1_DAT3,
- GFN_SD1_DAT2,
- GFN_SD1_DAT1,
- GFN_SD1_DAT0,
- GFN_SD1_CMD,
- GFN_SD1_CLK,
- GFN_SD0_DAT3,
- GFN_SD0_DAT2,
- GFN_SD0_DAT1,
- GFN_SD0_DAT0,
- GFN_SD0_CMD,
- GFN_SD0_CLK,
-
- /* GPSR4 */
- GFN_SD3_DS,
- GFN_SD3_DAT7,
- GFN_SD3_DAT6,
- GFN_SD3_DAT5,
- GFN_SD3_DAT4,
- FN_SD3_DAT3,
- FN_SD3_DAT2,
- FN_SD3_DAT1,
- FN_SD3_DAT0,
- FN_SD3_CMD,
- FN_SD3_CLK,
- GFN_SD2_DS,
- GFN_SD2_DAT3,
- GFN_SD2_DAT2,
- GFN_SD2_DAT1,
- GFN_SD2_DAT0,
- FN_SD2_CMD,
- GFN_SD2_CLK,
-
- /* GPSR5 */
- GFN_MLB_DAT,
- GFN_MLB_SIG,
- GFN_MLB_CLK,
- FN_MSIOF0_RXD,
- GFN_MSIOF0_SS2,
- FN_MSIOF0_TXD,
- GFN_MSIOF0_SS1,
- GFN_MSIOF0_SYNC,
- FN_MSIOF0_SCK,
- GFN_HRTS0x,
- GFN_HCTS0x,
- GFN_HTX0,
- GFN_HRX0,
- GFN_HSCK0,
- GFN_RX2_A,
- GFN_TX2_A,
- GFN_SCK2,
- GFN_RTS1x_TANS,
- GFN_CTS1x,
- GFN_TX1_A,
- GFN_RX1_A,
- GFN_RTS0x_TANS,
- GFN_CTS0x,
- GFN_TX0,
- GFN_RX0,
- GFN_SCK0,
-
- /* GPSR6 */
- GFN_GP6_30,
- GFN_GP6_31,
- GFN_USB30_OVC,
- GFN_USB30_PWEN,
- GFN_USB1_OVC,
- GFN_USB1_PWEN,
- GFN_USB0_OVC,
- GFN_USB0_PWEN,
- GFN_AUDIO_CLKB_B,
- GFN_AUDIO_CLKA_A,
- GFN_SSI_SDATA9_A,
- GFN_SSI_SDATA8,
- GFN_SSI_SDATA7,
- GFN_SSI_WS78,
- GFN_SSI_SCK78,
- GFN_SSI_SDATA6,
- GFN_SSI_WS6,
- GFN_SSI_SCK6,
- FN_SSI_SDATA5,
- FN_SSI_WS5,
- FN_SSI_SCK5,
- GFN_SSI_SDATA4,
- GFN_SSI_WS4,
- GFN_SSI_SCK4,
- GFN_SSI_SDATA3,
- GFN_SSI_WS34,
- GFN_SSI_SCK34,
- GFN_SSI_SDATA2_A,
- GFN_SSI_SDATA1_A,
- GFN_SSI_SDATA0,
- GFN_SSI_WS01239,
- GFN_SSI_SCK01239,
-
- /* GPSR7 */
- FN_HDMI1_CEC,
- FN_HDMI0_CEC,
- FN_AVS2,
- FN_AVS1,
-
- /* IPSR0 */
- IFN_AVB_MDC,
- FN_MSIOF2_SS2_C,
- IFN_AVB_MAGIC,
- FN_MSIOF2_SS1_C,
- FN_SCK4_A,
- IFN_AVB_PHY_INT,
- FN_MSIOF2_SYNC_C,
- FN_RX4_A,
- IFN_AVB_LINK,
- FN_MSIOF2_SCK_C,
- FN_TX4_A,
- IFN_AVB_AVTP_MATCH_A,
- FN_MSIOF2_RXD_C,
- FN_CTS4x_A,
- IFN_AVB_AVTP_CAPTURE_A,
- FN_MSIOF2_TXD_C,
- FN_RTS4x_TANS_A,
- IFN_IRQ0,
- FN_QPOLB,
- FN_DU_CDE,
- FN_VI4_DATA0_B,
- FN_CAN0_TX_B,
- FN_CANFD0_TX_B,
- FN_MSIOF3_SS2_E,
- IFN_IRQ1,
- FN_QPOLA,
- FN_DU_DISP,
- FN_VI4_DATA1_B,
- FN_CAN0_RX_B,
- FN_CANFD0_RX_B,
- FN_MSIOF3_SS1_E,
-
- /* IPSR1 */
- IFN_IRQ2,
- FN_QCPV_QDE,
- FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- FN_VI4_DATA2_B,
- FN_MSIOF3_SYNC_E,
- FN_PWM3_B,
- IFN_IRQ3,
- FN_QSTVB_QVE,
- FN_DU_DOTCLKOUT1,
- FN_VI4_DATA3_B,
- FN_MSIOF3_SCK_E,
- FN_PWM4_B,
- IFN_IRQ4,
- FN_QSTH_QHS,
- FN_DU_EXHSYNC_DU_HSYNC,
- FN_VI4_DATA4_B,
- FN_MSIOF3_RXD_E,
- FN_PWM5_B,
- IFN_IRQ5,
- FN_QSTB_QHE,
- FN_DU_EXVSYNC_DU_VSYNC,
- FN_VI4_DATA5_B,
- FN_MSIOF3_TXD_E,
- FN_PWM6_B,
- IFN_PWM0,
- FN_AVB_AVTP_PPS,
- FN_VI4_DATA6_B,
- FN_IECLK_B,
- IFN_PWM1_A,
- FN_HRX3_D,
- FN_VI4_DATA7_B,
- FN_IERX_B,
- IFN_PWM2_A,
- FN_PWMFSW0,
- FN_HTX3_D,
- FN_IETX_B,
- IFN_A0,
- FN_LCDOUT16,
- FN_MSIOF3_SYNC_B,
- FN_VI4_DATA8,
- FN_DU_DB0,
- FN_PWM3_A,
-
- /* IPSR2 */
- IFN_A1,
- FN_LCDOUT17,
- FN_MSIOF3_TXD_B,
- FN_VI4_DATA9,
- FN_DU_DB1,
- FN_PWM4_A,
- IFN_A2,
- FN_LCDOUT18,
- FN_MSIOF3_SCK_B,
- FN_VI4_DATA10,
- FN_DU_DB2,
- FN_PWM5_A,
- IFN_A3,
- FN_LCDOUT19,
- FN_MSIOF3_RXD_B,
- FN_VI4_DATA11,
- FN_DU_DB3,
- FN_PWM6_A,
- IFN_A4,
- FN_LCDOUT20,
- FN_MSIOF3_SS1_B,
- FN_VI4_DATA12,
- FN_VI5_DATA12,
- FN_DU_DB4,
- IFN_A5,
- FN_LCDOUT21,
- FN_MSIOF3_SS2_B,
- FN_SCK4_B,
- FN_VI4_DATA13,
- FN_VI5_DATA13,
- FN_DU_DB5,
- IFN_A6,
- FN_LCDOUT22,
- FN_MSIOF2_SS1_A,
- FN_RX4_B,
- FN_VI4_DATA14,
- FN_VI5_DATA14,
- FN_DU_DB6,
- IFN_A7,
- FN_LCDOUT23,
- FN_MSIOF2_SS2_A,
- FN_TX4_B,
- FN_VI4_DATA15,
- FN_V15_DATA15,
- FN_DU_DB7,
- IFN_A8,
- FN_RX3_B,
- FN_MSIOF2_SYNC_A,
- FN_HRX4_B,
- FN_SDA6_A,
- FN_AVB_AVTP_MATCH_B,
- FN_PWM1_B,
-
- /* IPSR3 */
- IFN_A9,
- FN_MSIOF2_SCK_A,
- FN_CTS4x_B,
- FN_VI5_VSYNCx,
- IFN_A10,
- FN_MSIOF2_RXD_A,
- FN_RTS4n_TANS_B,
- FN_VI5_HSYNCx,
- IFN_A11,
- FN_TX3_B,
- FN_MSIOF2_TXD_A,
- FN_HTX4_B,
- FN_HSCK4,
- FN_VI5_FIELD,
- FN_SCL6_A,
- FN_AVB_AVTP_CAPTURE_B,
- FN_PWM2_B,
- FN_SPV_EVEN,
- IFN_A12,
- FN_LCDOUT12,
- FN_MSIOF3_SCK_C,
- FN_HRX4_A,
- FN_VI5_DATA8,
- FN_DU_DG4,
- IFN_A13,
- FN_LCDOUT13,
- FN_MSIOF3_SYNC_C,
- FN_HTX4_A,
- FN_VI5_DATA9,
- FN_DU_DG5,
- IFN_A14,
- FN_LCDOUT14,
- FN_MSIOF3_RXD_C,
- FN_HCTS4x,
- FN_VI5_DATA10,
- FN_DU_DG6,
- IFN_A15,
- FN_LCDOUT15,
- FN_MSIOF3_TXD_C,
- FN_HRTS4x,
- FN_VI5_DATA11,
- FN_DU_DG7,
- IFN_A16,
- FN_LCDOUT8,
- FN_VI4_FIELD,
- FN_DU_DG0,
-
- /* IPSR4 */
- IFN_A17,
- FN_LCDOUT9,
- FN_VI4_VSYNCx,
- FN_DU_DG1,
- IFN_A18,
- FN_LCDOUT10,
- FN_VI4_HSYNCx,
- FN_DU_DG2,
- IFN_A19,
- FN_LCDOUT11,
- FN_VI4_CLKENB,
- FN_DU_DG3,
- IFN_CS0x,
- FN_VI5_CLKENB,
- IFN_CS1x_A26,
- FN_VI5_CLK,
- FN_EX_WAIT0_B,
- IFN_BSx,
- FN_QSTVA_QVS,
- FN_MSIOF3_SCK_D,
- FN_SCK3,
- FN_HSCK3,
- FN_CAN1_TX,
- FN_CANFD1_TX,
- FN_IETX_A,
- IFN_RDx,
- FN_MSIOF3_SYNC_D,
- FN_RX3_A,
- FN_HRX3_A,
- FN_CAN0_TX_A,
- FN_CANFD0_TX_A,
- IFN_RD_WRx,
- FN_MSIOF3_RXD_D,
- FN_TX3_A,
- FN_HTX3_A,
- FN_CAN0_RX_A,
- FN_CANFD0_RX_A,
-
- /* IPSR5 */
- IFN_WE0x,
- FN_MSIIOF3_TXD_D,
- FN_CTS3x,
- FN_HCTS3x,
- FN_SCL6_B,
- FN_CAN_CLK,
- FN_IECLK_A,
- IFN_WE1x,
- FN_MSIOF3_SS1_D,
- FN_RTS3x_TANS,
- FN_HRTS3x,
- FN_SDA6_B,
- FN_CAN1_RX,
- FN_CANFD1_RX,
- FN_IERX_A,
- IFN_EX_WAIT0_A,
- FN_QCLK,
- FN_VI4_CLK,
- FN_DU_DOTCLKOUT0,
- IFN_D0,
- FN_MSIOF2_SS1_B,
- FN_MSIOF3_SCK_A,
- FN_VI4_DATA16,
- FN_VI5_DATA0,
- IFN_D1,
- FN_MSIOF2_SS2_B,
- FN_MSIOF3_SYNC_A,
- FN_VI4_DATA17,
- FN_VI5_DATA1,
- IFN_D2,
- FN_MSIOF3_RXD_A,
- FN_VI4_DATA18,
- FN_VI5_DATA2,
- IFN_D3,
- FN_MSIOF3_TXD_A,
- FN_VI4_DATA19,
- FN_VI5_DATA3,
- IFN_D4,
- FN_MSIOF2_SCK_B,
- FN_VI4_DATA20,
- FN_VI5_DATA4,
-
- /* IPSR6 */
- IFN_D5,
- FN_MSIOF2_SYNC_B,
- FN_VI4_DATA21,
- FN_VI5_DATA5,
- IFN_D6,
- FN_MSIOF2_RXD_B,
- FN_VI4_DATA22,
- FN_VI5_DATA6,
- IFN_D7,
- FN_MSIOF2_TXD_B,
- FN_VI4_DATA23,
- FN_VI5_DATA7,
- IFN_D8,
- FN_LCDOUT0,
- FN_MSIOF2_SCK_D,
- FN_SCK4_C,
- FN_VI4_DATA0_A,
- FN_DU_DR0,
- IFN_D9,
- FN_LCDOUT1,
- FN_MSIOF2_SYNC_D,
- FN_VI4_DATA1_A,
- FN_DU_DR1,
- IFN_D10,
- FN_LCDOUT2,
- FN_MSIOF2_RXD_D,
- FN_HRX3_B,
- FN_VI4_DATA2_A,
- FN_CTS4x_C,
- FN_DU_DR2,
- IFN_D11,
- FN_LCDOUT3,
- FN_MSIOF2_TXD_D,
- FN_HTX3_B,
- FN_VI4_DATA3_A,
- FN_RTS4x_TANS_C,
- FN_DU_DR3,
- IFN_D12,
- FN_LCDOUT4,
- FN_MSIOF2_SS1_D,
- FN_RX4_C,
- FN_VI4_DATA4_A,
- FN_DU_DR4,
-
- /* IPSR7 */
- IFN_D13,
- FN_LCDOUT5,
- FN_MSIOF2_SS2_D,
- FN_TX4_C,
- FN_VI4_DATA5_A,
- FN_DU_DR5,
- IFN_D14,
- FN_LCDOUT6,
- FN_MSIOF3_SS1_A,
- FN_HRX3_C,
- FN_VI4_DATA6_A,
- FN_DU_DR6,
- FN_SCL6_C,
- IFN_D15,
- FN_LCDOUT7,
- FN_MSIOF3_SS2_A,
- FN_HTX3_C,
- FN_VI4_DATA7_A,
- FN_DU_DR7,
- FN_SDA6_C,
- FN_FSCLKST,
- IFN_SD0_CLK,
- FN_MSIOF1_SCK_E,
- FN_STP_OPWM_0_B,
- IFN_SD0_CMD,
- FN_MSIOF1_SYNC_E,
- FN_STP_IVCXO27_0_B,
- IFN_SD0_DAT0,
- FN_MSIOF1_RXD_E,
- FN_TS_SCK0_B,
- FN_STP_ISCLK_0_B,
- IFN_SD0_DAT1,
- FN_MSIOF1_TXD_E,
- FN_TS_SPSYNC0_B,
- FN_STP_ISSYNC_0_B,
-
- /* IPSR8 */
- IFN_SD0_DAT2,
- FN_MSIOF1_SS1_E,
- FN_TS_SDAT0_B,
- FN_STP_ISD_0_B,
-
- IFN_SD0_DAT3,
- FN_MSIOF1_SS2_E,
- FN_TS_SDEN0_B,
- FN_STP_ISEN_0_B,
-
- IFN_SD1_CLK,
- FN_MSIOF1_SCK_G,
- FN_SIM0_CLK_A,
-
- IFN_SD1_CMD,
- FN_MSIOF1_SYNC_G,
- FN_NFCEx_B,
- FN_SIM0_D_A,
- FN_STP_IVCXO27_1_B,
-
- IFN_SD1_DAT0,
- FN_SD2_DAT4,
- FN_MSIOF1_RXD_G,
- FN_NFWPx_B,
- FN_TS_SCK1_B,
- FN_STP_ISCLK_1_B,
-
- IFN_SD1_DAT1,
- FN_SD2_DAT5,
- FN_MSIOF1_TXD_G,
- FN_NFDATA14_B,
- FN_TS_SPSYNC1_B,
- FN_STP_ISSYNC_1_B,
-
- IFN_SD1_DAT2,
- FN_SD2_DAT6,
- FN_MSIOF1_SS1_G,
- FN_NFDATA15_B,
- FN_TS_SDAT1_B,
- FN_STP_IOD_1_B,
-
- IFN_SD1_DAT3,
- FN_SD2_DAT7,
- FN_MSIOF1_SS2_G,
- FN_NFRBx_B,
- FN_TS_SDEN1_B,
- FN_STP_ISEN_1_B,
-
- /* IPSR9 */
- IFN_SD2_CLK,
- FN_NFDATA8,
-
- IFN_SD2_CMD,
- FN_NFDATA9,
-
- IFN_SD2_DAT0,
- FN_NFDATA10,
-
- IFN_SD2_DAT1,
- FN_NFDATA11,
-
- IFN_SD2_DAT2,
- FN_NFDATA12,
-
- IFN_SD2_DAT3,
- FN_NFDATA13,
-
- IFN_SD2_DS,
- FN_NFALE,
-
- IFN_SD3_CLK,
- FN_NFWEx,
-
- /* IPSR10 */
- IFN_SD3_CMD,
- FN_NFREx,
-
- IFN_SD3_DAT0,
- FN_NFDATA0,
-
- IFN_SD3_DAT1,
- FN_NFDATA1,
-
- IFN_SD3_DAT2,
- FN_NFDATA2,
-
- IFN_SD3_DAT3,
- FN_NFDATA3,
-
- IFN_SD3_DAT4,
- FN_SD2_CD_A,
- FN_NFDATA4,
-
- IFN_SD3_DAT5,
- FN_SD2_WP_A,
- FN_NFDATA5,
-
- IFN_SD3_DAT6,
- FN_SD3_CD,
- FN_NFDATA6,
-
- /* IPSR11 */
- IFN_SD3_DAT7,
- FN_SD3_WP,
- FN_NFDATA7,
-
- IFN_SD3_DS,
- FN_NFCLE,
-
- IFN_SD0_CD,
- FN_NFDATA14_A,
- FN_SCL2_B,
- FN_SIM0_RST_A,
-
- IFN_SD0_WP,
- FN_NFDATA15_A,
- FN_SDA2_B,
-
- IFN_SD1_CD,
- FN_NFRBx_A,
- FN_SIM0_CLK_B,
-
- IFN_SD1_WP,
- FN_NFCEx_A,
- FN_SIM0_D_B,
-
- IFN_SCK0,
- FN_HSCK1_B,
- FN_MSIOF1_SS2_B,
- FN_AUDIO_CLKC_B,
- FN_SDA2_A,
- FN_SIM0_RST_B,
- FN_STP_OPWM_0_C,
- FN_RIF0_CLK_B,
- FN_ADICHS2,
- FN_SCK5_B,
-
- IFN_RX0,
- FN_HRX1_B,
- FN_TS_SCK0_C,
- FN_STP_ISCLK_0_C,
- FN_RIF0_D0_B,
-
- /* IPSR12 */
- IFN_TX0,
- FN_HTX1_B,
- FN_TS_SPSYNC0_C,
- FN_STP_ISSYNC_0_C,
- FN_RIF0_D1_B,
-
- IFN_CTS0x,
- FN_HCTS1x_B,
- FN_MSIOF1_SYNC_B,
- FN_TS_SPSYNC1_C,
- FN_STP_ISSYNC_1_C,
- FN_RIF1_SYNC_B,
- FN_AUDIO_CLKOUT_C,
- FN_ADICS_SAMP,
-
- IFN_RTS0x_TANS,
- FN_HRTS1x_B,
- FN_MSIOF1_SS1_B,
- FN_AUDIO_CLKA_B,
- FN_SCL2_A,
- FN_STP_IVCXO27_1_C,
- FN_RIF0_SYNC_B,
- FN_ADICHS1,
-
- IFN_RX1_A,
- FN_HRX1_A,
- FN_TS_SDAT0_C,
- FN_STP_ISD_0_C,
- FN_RIF1_CLK_C,
-
- IFN_TX1_A,
- FN_HTX1_A,
- FN_TS_SDEN0_C,
- FN_STP_ISEN_0_C,
- FN_RIF1_D0_C,
-
- IFN_CTS1x,
- FN_HCTS1x_A,
- FN_MSIOF1_RXD_B,
- FN_TS_SDEN1_C,
- FN_STP_ISEN_1_C,
- FN_RIF1_D0_B,
- FN_ADIDATA,
-
- IFN_RTS1x_TANS,
- FN_HRTS1x_A,
- FN_MSIOF1_TXD_B,
- FN_TS_SDAT1_C,
- FN_STP_ISD_1_C,
- FN_RIF1_D1_B,
- FN_ADICHS0,
-
- IFN_SCK2,
- FN_SCIF_CLK_B,
- FN_MSIOF1_SCK_B,
- FN_TS_SCK1_C,
- FN_STP_ISCLK_1_C,
- FN_RIF1_CLK_B,
- FN_ADICLK,
-
- /* IPSR13 */
- IFN_TX2_A,
- FN_SD2_CD_B,
- FN_SCL1_A,
- FN_FMCLK_A,
- FN_RIF1_D1_C,
- FN_FSO_CFE_0_B,
-
- IFN_RX2_A,
- FN_SD2_WP_B,
- FN_SDA1_A,
- FN_FMIN_A,
- FN_RIF1_SYNC_C,
- FN_FSO_CEF_1_B,
-
- IFN_HSCK0,
- FN_MSIOF1_SCK_D,
- FN_AUDIO_CLKB_A,
- FN_SSI_SDATA1_B,
- FN_TS_SCK0_D,
- FN_STP_ISCLK_0_D,
- FN_RIF0_CLK_C,
- FN_RX5_B,
-
- IFN_HRX0,
- FN_MSIOF1_RXD_D,
- FN_SS1_SDATA2_B,
- FN_TS_SDEN0_D,
- FN_STP_ISEN_0_D,
- FN_RIF0_D0_C,
-
- IFN_HTX0,
- FN_MSIOF1_TXD_D,
- FN_SSI_SDATA9_B,
- FN_TS_SDAT0_D,
- FN_STP_ISD_0_D,
- FN_RIF0_D1_C,
-
- IFN_HCTS0x,
- FN_RX2_B,
- FN_MSIOF1_SYNC_D,
- FN_SSI_SCK9_A,
- FN_TS_SPSYNC0_D,
- FN_STP_ISSYNC_0_D,
- FN_RIF0_SYNC_C,
- FN_AUDIO_CLKOUT1_A,
-
- IFN_HRTS0x,
- FN_TX2_B,
- FN_MSIOF1_SS1_D,
- FN_SSI_WS9_A,
- FN_STP_IVCXO27_0_D,
- FN_BPFCLK_A,
- FN_AUDIO_CLKOUT2_A,
-
- IFN_MSIOF0_SYNC,
- FN_AUDIO_CLKOUT_A,
- FN_TX5_B,
- FN_BPFCLK_D,
-
- /* IPSR14 */
- IFN_MSIOF0_SS1,
- FN_RX5_A,
- FN_NFWPx_A,
- FN_AUDIO_CLKA_C,
- FN_SSI_SCK2_A,
- FN_STP_IVCXO27_0_C,
- FN_AUDIO_CLKOUT3_A,
- FN_TCLK1_B,
-
- IFN_MSIOF0_SS2,
- FN_TX5_A,
- FN_MSIOF1_SS2_D,
- FN_AUDIO_CLKC_A,
- FN_SSI_WS2_A,
- FN_STP_OPWM_0_D,
- FN_AUDIO_CLKOUT_D,
- FN_SPEEDIN_B,
-
- IFN_MLB_CLK,
- FN_MSIOF1_SCK_F,
- FN_SCL1_B,
-
- IFN_MLB_SIG,
- FN_RX1_B,
- FN_MSIOF1_SYNC_F,
- FN_SDA1_B,
-
- IFN_MLB_DAT,
- FN_TX1_B,
- FN_MSIOF1_RXD_F,
-
- IFN_SSI_SCK0129,
- FN_MSIOF1_TXD_F,
- FN_MOUT0,
-
- IFN_SSI_WS0129,
- FN_MSIOF1_SS1_F,
- FN_MOUT1,
-
- IFN_SSI_SDATA0,
- FN_MSIOF1_SS2_F,
- FN_MOUT2,
-
- /* IPSR15 */
- IFN_SSI_SDATA1_A,
- FN_MOUT5,
-
- IFN_SSI_SDATA2_A,
- FN_SSI_SCK1_B,
- FN_MOUT6,
-
- IFN_SSI_SCK34,
- FN_MSIOF1_SS1_A,
- FN_STP_OPWM_0_A,
-
- IFN_SSI_WS34,
- FN_HCTS2x_A,
- FN_MSIOF1_SS2_A,
- FN_STP_IVCXO27_0_A,
-
- IFN_SSI_SDATA3,
- FN_HRTS2x_A,
- FN_MSIOF1_TXD_A,
- FN_TS_SCK0_A,
- FN_STP_ISCLK_0_A,
- FN_RIF0_D1_A,
- FN_RIF2_D0_A,
-
- IFN_SSI_SCK4,
- FN_HRX2_A,
- FN_MSIOF1_SCK_A,
- FN_TS_SDAT0_A,
- FN_STP_ISD_0_A,
- FN_RIF0_CLK_A,
- FN_RIF2_CLK_A,
-
- IFN_SSI_WS4,
- FN_HTX2_A,
- FN_MSIOF1_SYNC_A,
- FN_TS_SDEN0_A,
- FN_STP_ISEN_0_A,
- FN_RIF0_SYNC_A,
- FN_RIF2_SYNC_A,
-
- IFN_SSI_SDATA4,
- FN_HSCK2_A,
- FN_MSIOF1_RXD_A,
- FN_TS_SPSYNC0_A,
- FN_STP_ISSYNC_0_A,
- FN_RIF0_D0_A,
- FN_RIF2_D1_A,
-
- /* IPSR16 */
- IFN_SSI_SCK6,
- FN_SIM0_RST_D,
- FN_FSO_TOE_A,
-
- IFN_SSI_WS6,
- FN_SIM0_D_D,
-
- IFN_SSI_SDATA6,
- FN_SIM0_CLK_D,
-
- IFN_SSI_SCK78,
- FN_HRX2_B,
- FN_MSIOF1_SCK_C,
- FN_TS_SCK1_A,
- FN_STP_ISCLK_1_A,
- FN_RIF1_CLK_A,
- FN_RIF3_CLK_A,
-
- IFN_SSI_WS78,
- FN_HTX2_B,
- FN_MSIOF1_SYNC_C,
- FN_TS_SDAT1_A,
- FN_STP_ISD_1_A,
- FN_RIF1_SYNC_A,
- FN_RIF3_SYNC_A,
-
- IFN_SSI_SDATA7,
- FN_HCTS2x_B,
- FN_MSIOF1_RXD_C,
- FN_TS_SDEN1_A,
- FN_STP_IEN_1_A,
- FN_RIF1_D0_A,
- FN_RIF3_D0_A,
- FN_TCLK2_A,
-
- IFN_SSI_SDATA8,
- FN_HRTS2x_B,
- FN_MSIOF1_TXD_C,
- FN_TS_SPSYNC1_A,
- FN_STP_ISSYNC_1_A,
- FN_RIF1_D1_A,
- FN_EIF3_D1_A,
-
- IFN_SSI_SDATA9_A,
- FN_HSCK2_B,
- FN_MSIOF1_SS1_C,
- FN_HSCK1_A,
- FN_SSI_WS1_B,
- FN_SCK1,
- FN_STP_IVCXO27_1_A,
- FN_SCK5,
-
- /* IPSR17 */
- IFN_AUDIO_CLKA_A,
- FN_CC5_OSCOUT,
-
- IFN_AUDIO_CLKB_B,
- FN_SCIF_CLK_A,
- FN_STP_IVCXO27_1_D,
- FN_REMOCON_A,
- FN_TCLK1_A,
-
- IFN_USB0_PWEN,
- FN_SIM0_RST_C,
- FN_TS_SCK1_D,
- FN_STP_ISCLK_1_D,
- FN_BPFCLK_B,
- FN_RIF3_CLK_B,
- FN_FSO_CFE_1_A,
- FN_HSCK2_C,
-
- IFN_USB0_OVC,
- FN_SIM0_D_C,
- FN_TS_SDAT1_D,
- FN_STP_ISD_1_D,
- FN_RIF3_SYNC_B,
- FN_HRX2_C,
-
- IFN_USB1_PWEN,
- FN_SIM0_CLK_C,
- FN_SSI_SCK1_A,
- FN_TS_SCK0_E,
- FN_STP_ISCLK_0_E,
- FN_FMCLK_B,
- FN_RIF2_CLK_B,
- FN_SPEEDIN_A,
- FN_HTX2_C,
-
- IFN_USB1_OVC,
- FN_MSIOF1_SS2_C,
- FN_SSI_WS1_A,
- FN_TS_SDAT0_E,
- FN_STP_ISD_0_E,
- FN_FMIN_B,
- FN_RIF2_SYNC_B,
- FN_REMOCON_B,
- FN_HCTS2x_C,
-
- IFN_USB30_PWEN,
- FN_AUDIO_CLKOUT_B,
- FN_SSI_SCK2_B,
- FN_TS_SDEN1_D,
- FN_STP_ISEN_1_D,
- FN_STP_OPWM_0_E,
- FN_RIF3_D0_B,
- FN_TCLK2_B,
- FN_TPU0TO0,
- FN_BPFCLK_C,
- FN_HRTS2x_C,
-
- IFN_USB30_OVC,
- FN_AUDIO_CLKOUT1_B,
- FN_SSI_WS2_B,
- FN_TS_SPSYNC1_D,
- FN_STP_ISSYNC_1_D,
- FN_STP_IVCXO27_0_E,
- FN_RIF3_D1_B,
- FN_FSO_TOE_B,
- FN_TPU0TO1,
-
- /* IPSR18 */
- IFN_GP6_30,
- FN_AUDIO_CLKOUT2_B,
- FN_SSI_SCK9_B,
- FN_TS_SDEN0_E,
- FN_STP_ISEN_0_E,
- FN_RIF2_D0_B,
- FN_FSO_CFE_0_A,
- FN_TPU0TO2,
- FN_FMCLK_C,
- FN_FMCLK_D,
-
- IFN_GP6_31,
- FN_AUDIO_CLKOUT3_B,
- FN_SSI_WS9_B,
- FN_TS_SPSYNC0_E,
- FN_STP_ISSYNC_0_E,
- FN_RIF2_D1_B,
- FN_TPU0TO3,
- FN_FMIN_C,
- FN_FMIN_D,
-
- /* MOD_SEL0 */
- FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
- FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
- FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5,
- FN_SEL_MSIOF3_6,
- FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
- FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
- FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
- FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
- FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
- FN_SEL_MSIOF1_6,
- FN_SEL_LBSC_0, FN_SEL_LBSC_1,
- FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
- FN_SEL_I2C2_0, FN_SEL_I2C2_1,
- FN_SEL_I2C1_0, FN_SEL_I2C1_1,
- FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
- FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
- FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
- FN_SEL_FSO_0, FN_SEL_FSO_1,
- FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
- FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
- FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
- FN_SEL_DRIF1_2,
- FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
- FN_SEL_DRIF0_2,
- FN_SEL_CANFD_0, FN_SEL_CANFD_1,
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_ADG_2, FN_SEL_ADG_3,
-
- /* MOD_SEL1 */
- FN_SEL_TSIF1_0,
- FN_SEL_TSIF1_1,
- FN_SEL_TSIF1_2,
- FN_SEL_TSIF1_3,
- FN_SEL_TSIF0_0,
- FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2,
- FN_SEL_TSIF0_3,
- FN_SEL_TSIF0_4,
- FN_SEL_TIMER_TMU_0,
- FN_SEL_TIMER_TMU_1,
- FN_SEL_SSP1_1_0,
- FN_SEL_SSP1_1_1,
- FN_SEL_SSP1_1_2,
- FN_SEL_SSP1_1_3,
- FN_SEL_SSP1_0_0,
- FN_SEL_SSP1_0_1,
- FN_SEL_SSP1_0_2,
- FN_SEL_SSP1_0_3,
- FN_SEL_SSP1_0_4,
- FN_SEL_SSI_0,
- FN_SEL_SSI_1,
- FN_SEL_SPEED_PULSE_IF_0,
- FN_SEL_SPEED_PULSE_IF_1,
- FN_SEL_SIMCARD_0,
- FN_SEL_SIMCARD_1,
- FN_SEL_SIMCARD_2,
- FN_SEL_SIMCARD_3,
- FN_SEL_SDHI2_0,
- FN_SEL_SDHI2_1,
- FN_SEL_SCIF4_0,
- FN_SEL_SCIF4_1,
- FN_SEL_SCIF4_2,
- FN_SEL_SCIF3_0,
- FN_SEL_SCIF3_1,
- FN_SEL_SCIF2_0,
- FN_SEL_SCIF2_1,
- FN_SEL_SCIF1_0,
- FN_SEL_SCIF1_1,
- FN_SEL_SCIF_0,
- FN_SEL_SCIF_1,
- FN_SEL_REMOCON_0,
- FN_SEL_REMOCON_1,
- FN_SEL_RCAN_0,
- FN_SEL_RCAN_1,
- FN_SEL_PWM6_0,
- FN_SEL_PWM6_1,
- FN_SEL_PWM5_0,
- FN_SEL_PWM5_1,
- FN_SEL_PWM4_0,
- FN_SEL_PWM4_1,
- FN_SEL_PWM3_0,
- FN_SEL_PWM3_1,
- FN_SEL_PWM2_0,
- FN_SEL_PWM2_1,
- FN_SEL_PWM1_0,
- FN_SEL_PWM1_1,
-
- /* MOD_SEL2 */
- FN_I2C_SEL_5_0,
- FN_I2C_SEL_5_1,
- FN_I2C_SEL_3_0,
- FN_I2C_SEL_3_1,
- FN_I2C_SEL_0_0,
- FN_I2C_SEL_0_1,
- FN_SEL_FM_0,
- FN_SEL_FM_1,
- FN_SEL_FM_2,
- FN_SEL_FM_3,
- FN_SEL_SCIF5_0,
- FN_SEL_SCIF5_1,
- FN_SEL_I2C6_0,
- FN_SEL_I2C6_1,
- FN_SEL_I2C6_2,
- FN_SEL_NDF_0,
- FN_SEL_NDF_1,
- FN_SEL_SSI2_0,
- FN_SEL_SSI2_1,
- FN_SEL_SSI9_0,
- FN_SEL_SSI9_1,
- FN_SEL_TIMER_TMU2_0,
- FN_SEL_TIMER_TMU2_1,
- FN_SEL_ADG_B_0,
- FN_SEL_ADG_B_1,
- FN_SEL_ADG_C_0,
- FN_SEL_ADG_C_1,
- FN_SEL_VIN4_0,
- FN_SEL_VIN4_1,
-
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- /* GPSR0 */
- D15_GMARK,
- D14_GMARK,
- D13_GMARK,
- D12_GMARK,
- D11_GMARK,
- D10_GMARK,
- D9_GMARK,
- D8_GMARK,
- D7_GMARK,
- D6_GMARK,
- D5_GMARK,
- D4_GMARK,
- D3_GMARK,
- D2_GMARK,
- D1_GMARK,
- D0_GMARK,
-
- /* GPSR1 */
- CLKOUT_GMARK,
- EX_WAIT0_A_GMARK,
- WE1x_GMARK,
- WE0x_GMARK,
- RD_WRx_GMARK,
- RDx_GMARK,
- BSx_GMARK,
- CS1x_A26_GMARK,
- CS0x_GMARK,
- A19_GMARK,
- A18_GMARK,
- A17_GMARK,
- A16_GMARK,
- A15_GMARK,
- A14_GMARK,
- A13_GMARK,
- A12_GMARK,
- A11_GMARK,
- A10_GMARK,
- A9_GMARK,
- A8_GMARK,
- A7_GMARK,
- A6_GMARK,
- A5_GMARK,
- A4_GMARK,
- A3_GMARK,
- A2_GMARK,
- A1_GMARK,
- A0_GMARK,
-
- /* GPSR2 */
- AVB_AVTP_CAPTURE_A_GMARK,
- AVB_AVTP_MATCH_A_GMARK,
- AVB_LINK_GMARK,
- AVB_PHY_INT_GMARK,
- AVB_MAGIC_GMARK,
- AVB_MDC_GMARK,
- PWM2_A_GMARK,
- PWM1_A_GMARK,
- PWM0_GMARK,
- IRQ5_GMARK,
- IRQ4_GMARK,
- IRQ3_GMARK,
- IRQ2_GMARK,
- IRQ1_GMARK,
- IRQ0_GMARK,
-
- /* GPSR3 */
- SD1_WP_GMARK,
- SD1_CD_GMARK,
- SD0_WP_GMARK,
- SD0_CD_GMARK,
- SD1_DAT3_GMARK,
- SD1_DAT2_GMARK,
- SD1_DAT1_GMARK,
- SD1_DAT0_GMARK,
- SD1_CMD_GMARK,
- SD1_CLK_GMARK,
- SD0_DAT3_GMARK,
- SD0_DAT2_GMARK,
- SD0_DAT1_GMARK,
- SD0_DAT0_GMARK,
- SD0_CMD_GMARK,
- SD0_CLK_GMARK,
-
- /* GPSR4 */
- SD3_DS_GMARK,
- SD3_DAT7_GMARK,
- SD3_DAT6_GMARK,
- SD3_DAT5_GMARK,
- SD3_DAT4_GMARK,
- SD3_DAT3_MARK,
- SD3_DAT2_MARK,
- SD3_DAT1_MARK,
- SD3_DAT0_MARK,
- SD3_CMD_MARK,
- SD3_CLK_MARK,
- SD2_DS_GMARK,
- SD2_DAT3_GMARK,
- SD2_DAT2_GMARK,
- SD2_DAT1_GMARK,
- SD2_DAT0_GMARK,
- SD2_CMD_MARK,
- SD2_CLK_GMARK,
-
- /* GPSR5 */
- MLB_DAT_GMARK,
- MLB_SIG_GMARK,
- MLB_CLK_GMARK,
- MSIOF0_RXD_MARK,
- MSIOF0_SS2_GMARK,
- MSIOF0_TXD_MARK,
- MSIOF0_SS1_GMARK,
- MSIOF0_SYNC_GMARK,
- MSIOF0_SCK_MARK,
- HRTS0x_GMARK,
- HCTS0x_GMARK,
- HTX0_GMARK,
- HRX0_GMARK,
- HSCK0_GMARK,
- RX2_A_GMARK,
- TX2_A_GMARK,
- SCK2_GMARK,
- RTS1x_TANS_GMARK,
- CTS1x_GMARK,
- TX1_A_GMARK,
- RX1_A_GMARK,
- RTS0x_TANS_GMARK,
- CTS0x_GMARK,
- TX0_GMARK,
- RX0_GMARK,
- SCK0_GMARK,
-
- /* GPSR6 */
- GP6_30_GMARK,
- GP6_31_GMARK,
- USB30_OVC_GMARK,
- USB30_PWEN_GMARK,
- USB1_OVC_GMARK,
- USB1_PWEN_GMARK,
- USB0_OVC_GMARK,
- USB0_PWEN_GMARK,
- AUDIO_CLKB_B_GMARK,
- AUDIO_CLKA_A_GMARK,
- SSI_SDATA9_A_GMARK,
- SSI_SDATA8_GMARK,
- SSI_SDATA7_GMARK,
- SSI_WS78_GMARK,
- SSI_SCK78_GMARK,
- SSI_SDATA6_GMARK,
- SSI_WS6_GMARK,
- SSI_SCK6_GMARK,
- SSI_SDATA5_MARK,
- SSI_WS5_MARK,
- SSI_SCK5_MARK,
- SSI_SDATA4_GMARK,
- SSI_WS4_GMARK,
- SSI_SCK4_GMARK,
- SSI_SDATA3_GMARK,
- SSI_WS34_GMARK,
- SSI_SCK34_GMARK,
- SSI_SDATA2_A_GMARK,
- SSI_SDATA1_A_GMARK,
- SSI_SDATA0_GMARK,
- SSI_WS01239_GMARK,
- SSI_SCK01239_GMARK,
-
- /* GPSR7 */
- HDMI1_CEC_MARK,
- HDMI0_CEC_MARK,
- AVS2_MARK,
- AVS1_MARK,
-
- /* IPSR0 */
- AVB_MDC_IMARK,
- MSIOF2_SS2_C_MARK,
- AVB_MAGIC_IMARK,
- MSIOF2_SS1_C_MARK,
- SCK4_A_MARK,
- AVB_PHY_INT_IMARK,
- MSIOF2_SYNC_C_MARK,
- RX4_A_MARK,
- AVB_LINK_IMARK,
- MSIOF2_SCK_C_MARK,
- TX4_A_MARK,
- AVB_AVTP_MATCH_A_IMARK,
- MSIOF2_RXD_C_MARK,
- CTS4x_A_MARK,
- AVB_AVTP_CAPTURE_A_IMARK,
- MSIOF2_TXD_C_MARK,
- RTS4x_TANS_A_MARK,
- IRQ0_IMARK,
- QPOLB_MARK,
- DU_CDE_MARK,
- VI4_DATA0_B_MARK,
- CAN0_TX_B_MARK,
- CANFD0_TX_B_MARK,
- MSIOF3_SS2_E_MARK,
- IRQ1_IMARK,
- QPOLA_MARK,
- DU_DISP_MARK,
- VI4_DATA1_B_MARK,
- CAN0_RX_B_MARK,
- CANFD0_RX_B_MARK,
- MSIOF3_SS1_E_MARK,
-
- /* IPSR1 */
- IRQ2_IMARK,
- QCPV_QDE_MARK,
- DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
- VI4_DATA2_B_MARK,
- MSIOF3_SYNC_E_MARK,
- PWM3_B_MARK,
- IRQ3_IMARK,
- QSTVB_QVE_MARK,
- DU_DOTCLKOUT1_MARK,
- VI4_DATA3_B_MARK,
- MSIOF3_SCK_E_MARK,
- PWM4_B_MARK,
- IRQ4_IMARK,
- QSTH_QHS_MARK,
- DU_EXHSYNC_DU_HSYNC_MARK,
- VI4_DATA4_B_MARK,
- MSIOF3_RXD_E_MARK,
- PWM5_B_MARK,
- IRQ5_IMARK,
- QSTB_QHE_MARK,
- DU_EXVSYNC_DU_VSYNC_MARK,
- VI4_DATA5_B_MARK,
- MSIOF3_TXD_E_MARK,
- PWM6_B_MARK,
- PWM0_IMARK,
- AVB_AVTP_PPS_MARK,
- VI4_DATA6_B_MARK,
- IECLK_B_MARK,
- PWM1_A_IMARK,
- HRX3_D_MARK,
- VI4_DATA7_B_MARK,
- IERX_B_MARK,
- PWM2_A_IMARK,
- PWMFSW0_MARK,
- HTX3_D_MARK,
- IETX_B_MARK,
- A0_IMARK,
- LCDOUT16_MARK,
- MSIOF3_SYNC_B_MARK,
- VI4_DATA8_MARK,
- DU_DB0_MARK,
- PWM3_A_MARK,
-
- /* IPSR2 */
- A1_IMARK,
- LCDOUT17_MARK,
- MSIOF3_TXD_B_MARK,
- VI4_DATA9_MARK,
- DU_DB1_MARK,
- PWM4_A_MARK,
- A2_IMARK,
- LCDOUT18_MARK,
- MSIOF3_SCK_B_MARK,
- VI4_DATA10_MARK,
- DU_DB2_MARK,
- PWM5_A_MARK,
- A3_IMARK,
- LCDOUT19_MARK,
- MSIOF3_RXD_B_MARK,
- VI4_DATA11_MARK,
- DU_DB3_MARK,
- PWM6_A_MARK,
- A4_IMARK,
- LCDOUT20_MARK,
- MSIOF3_SS1_B_MARK,
- VI4_DATA12_MARK,
- VI5_DATA12_MARK,
- DU_DB4_MARK,
- A5_IMARK,
- LCDOUT21_MARK,
- MSIOF3_SS2_B_MARK,
- SCK4_B_MARK,
- VI4_DATA13_MARK,
- VI5_DATA13_MARK,
- DU_DB5_MARK,
- A6_IMARK,
- LCDOUT22_MARK,
- MSIOF2_SS1_A_MARK,
- RX4_B_MARK,
- VI4_DATA14_MARK,
- VI5_DATA14_MARK,
- DU_DB6_MARK,
- A7_IMARK,
- LCDOUT23_MARK,
- MSIOF2_SS2_A_MARK,
- TX4_B_MARK,
- VI4_DATA15_MARK,
- V15_DATA15_MARK,
- DU_DB7_MARK,
- A8_IMARK,
- RX3_B_MARK,
- MSIOF2_SYNC_A_MARK,
- HRX4_B_MARK,
- SDA6_A_MARK,
- AVB_AVTP_MATCH_B_MARK,
- PWM1_B_MARK,
-
- /* IPSR3 */
- A9_IMARK,
- MSIOF2_SCK_A_MARK,
- CTS4x_B_MARK,
- VI5_VSYNCx_MARK,
- A10_IMARK,
- MSIOF2_RXD_A_MARK,
- RTS4n_TANS_B_MARK,
- VI5_HSYNCx_MARK,
- A11_IMARK,
- TX3_B_MARK,
- MSIOF2_TXD_A_MARK,
- HTX4_B_MARK,
- HSCK4_MARK,
- VI5_FIELD_MARK,
- SCL6_A_MARK,
- AVB_AVTP_CAPTURE_B_MARK,
- PWM2_B_MARK,
- SPV_EVEN_MARK,
- A12_IMARK,
- LCDOUT12_MARK,
- MSIOF3_SCK_C_MARK,
- HRX4_A_MARK,
- VI5_DATA8_MARK,
- DU_DG4_MARK,
- A13_IMARK,
- LCDOUT13_MARK,
- MSIOF3_SYNC_C_MARK,
- HTX4_A_MARK,
- VI5_DATA9_MARK,
- DU_DG5_MARK,
- A14_IMARK,
- LCDOUT14_MARK,
- MSIOF3_RXD_C_MARK,
- HCTS4x_MARK,
- VI5_DATA10_MARK,
- DU_DG6_MARK,
- A15_IMARK,
- LCDOUT15_MARK,
- MSIOF3_TXD_C_MARK,
- HRTS4x_MARK,
- VI5_DATA11_MARK,
- DU_DG7_MARK,
- A16_IMARK,
- LCDOUT8_MARK,
- VI4_FIELD_MARK,
- DU_DG0_MARK,
-
- /* IPSR4 */
- A17_IMARK,
- LCDOUT9_MARK,
- VI4_VSYNCx_MARK,
- DU_DG1_MARK,
- A18_IMARK,
- LCDOUT10_MARK,
- VI4_HSYNCx_MARK,
- DU_DG2_MARK,
- A19_IMARK,
- LCDOUT11_MARK,
- VI4_CLKENB_MARK,
- DU_DG3_MARK,
- CS0x_IMARK,
- VI5_CLKENB_MARK,
- CS1x_A26_IMARK,
- VI5_CLK_MARK,
- EX_WAIT0_B_MARK,
- BSx_IMARK,
- QSTVA_QVS_MARK,
- MSIOF3_SCK_D_MARK,
- SCK3_MARK,
- HSCK3_MARK,
- CAN1_TX_MARK,
- CANFD1_TX_MARK,
- IETX_A_MARK,
- RDx_IMARK,
- MSIOF3_SYNC_D_MARK,
- RX3_A_MARK,
- HRX3_A_MARK,
- CAN0_TX_A_MARK,
- CANFD0_TX_A_MARK,
- RD_WRx_IMARK,
- MSIOF3_RXD_D_MARK,
- TX3_A_MARK,
- HTX3_A_MARK,
- CAN0_RX_A_MARK,
- CANFD0_RX_A_MARK,
-
- /* IPSR5 */
- WE0x_IMARK,
- MSIIOF3_TXD_D_MARK,
- CTS3x_MARK,
- HCTS3x_MARK,
- SCL6_B_MARK,
- CAN_CLK_MARK,
- IECLK_A_MARK,
- WE1x_IMARK,
- MSIOF3_SS1_D_MARK,
- RTS3x_TANS_MARK,
- HRTS3x_MARK,
- SDA6_B_MARK,
- CAN1_RX_MARK,
- CANFD1_RX_MARK,
- IERX_A_MARK,
- EX_WAIT0_A_IMARK,
- QCLK_MARK,
- VI4_CLK_MARK,
- DU_DOTCLKOUT0_MARK,
- D0_IMARK,
- MSIOF2_SS1_B_MARK,
- MSIOF3_SCK_A_MARK,
- VI4_DATA16_MARK,
- VI5_DATA0_MARK,
- D1_IMARK,
- MSIOF2_SS2_B_MARK,
- MSIOF3_SYNC_A_MARK,
- VI4_DATA17_MARK,
- VI5_DATA1_MARK,
- D2_IMARK,
- MSIOF3_RXD_A_MARK,
- VI4_DATA18_MARK,
- VI5_DATA2_MARK,
- D3_IMARK,
- MSIOF3_TXD_A_MARK,
- VI4_DATA19_MARK,
- VI5_DATA3_MARK,
- D4_IMARK,
- MSIOF2_SCK_B_MARK,
- VI4_DATA20_MARK,
- VI5_DATA4_MARK,
-
- /* IPSR6 */
- D5_IMARK,
- MSIOF2_SYNC_B_MARK,
- VI4_DATA21_MARK,
- VI5_DATA5_MARK,
- D6_IMARK,
- MSIOF2_RXD_B_MARK,
- VI4_DATA22_MARK,
- VI5_DATA6_MARK,
- D7_IMARK,
- MSIOF2_TXD_B_MARK,
- VI4_DATA23_MARK,
- VI5_DATA7_MARK,
- D8_IMARK,
- LCDOUT0_MARK,
- MSIOF2_SCK_D_MARK,
- SCK4_C_MARK,
- VI4_DATA0_A_MARK,
- DU_DR0_MARK,
- D9_IMARK,
- LCDOUT1_MARK,
- MSIOF2_SYNC_D_MARK,
- VI4_DATA1_A_MARK,
- DU_DR1_MARK,
- D10_IMARK,
- LCDOUT2_MARK,
- MSIOF2_RXD_D_MARK,
- HRX3_B_MARK,
- VI4_DATA2_A_MARK,
- CTS4x_C_MARK,
- DU_DR2_MARK,
- D11_IMARK,
- LCDOUT3_MARK,
- MSIOF2_TXD_D_MARK,
- HTX3_B_MARK,
- VI4_DATA3_A_MARK,
- RTS4x_TANS_C_MARK,
- DU_DR3_MARK,
- D12_IMARK,
- LCDOUT4_MARK,
- MSIOF2_SS1_D_MARK,
- RX4_C_MARK,
- VI4_DATA4_A_MARK,
- DU_DR4_MARK,
-
- /* IPSR7 */
- D13_IMARK,
- LCDOUT5_MARK,
- MSIOF2_SS2_D_MARK,
- TX4_C_MARK,
- VI4_DATA5_A_MARK,
- DU_DR5_MARK,
- D14_IMARK,
- LCDOUT6_MARK,
- MSIOF3_SS1_A_MARK,
- HRX3_C_MARK,
- VI4_DATA6_A_MARK,
- DU_DR6_MARK,
- SCL6_C_MARK,
- D15_IMARK,
- LCDOUT7_MARK,
- MSIOF3_SS2_A_MARK,
- HTX3_C_MARK,
- VI4_DATA7_A_MARK,
- DU_DR7_MARK,
- SDA6_C_MARK,
- FSCLKST_MARK,
- SD0_CLK_IMARK,
- MSIOF1_SCK_E_MARK,
- STP_OPWM_0_B_MARK,
- SD0_CMD_IMARK,
- MSIOF1_SYNC_E_MARK,
- STP_IVCXO27_0_B_MARK,
- SD0_DAT0_IMARK,
- MSIOF1_RXD_E_MARK,
- TS_SCK0_B_MARK,
- STP_ISCLK_0_B_MARK,
- SD0_DAT1_IMARK,
- MSIOF1_TXD_E_MARK,
- TS_SPSYNC0_B_MARK,
- STP_ISSYNC_0_B_MARK,
-
- /* IPSR8 */
- SD0_DAT2_IMARK,
- MSIOF1_SS1_E_MARK,
- TS_SDAT0_B_MARK,
- STP_ISD_0_B_MARK,
-
- SD0_DAT3_IMARK,
- MSIOF1_SS2_E_MARK,
- TS_SDEN0_B_MARK,
- STP_ISEN_0_B_MARK,
-
- SD1_CLK_IMARK,
- MSIOF1_SCK_G_MARK,
- SIM0_CLK_A_MARK,
-
- SD1_CMD_IMARK,
- MSIOF1_SYNC_G_MARK,
- NFCEx_B_MARK,
- SIM0_D_A_MARK,
- STP_IVCXO27_1_B_MARK,
-
- SD1_DAT0_IMARK,
- SD2_DAT4_MARK,
- MSIOF1_RXD_G_MARK,
- NFWPx_B_MARK,
- TS_SCK1_B_MARK,
- STP_ISCLK_1_B_MARK,
-
- SD1_DAT1_IMARK,
- SD2_DAT5_MARK,
- MSIOF1_TXD_G_MARK,
- NFDATA14_B_MARK,
- TS_SPSYNC1_B_MARK,
- STP_ISSYNC_1_B_MARK,
-
- SD1_DAT2_IMARK,
- SD2_DAT6_MARK,
- MSIOF1_SS1_G_MARK,
- NFDATA15_B_MARK,
- TS_SDAT1_B_MARK,
- STP_IOD_1_B_MARK,
-
- SD1_DAT3_IMARK,
- SD2_DAT7_MARK,
- MSIOF1_SS2_G_MARK,
- NFRBx_B_MARK,
- TS_SDEN1_B_MARK,
- STP_ISEN_1_B_MARK,
-
- /* IPSR9 */
- SD2_CLK_IMARK,
- NFDATA8_MARK,
-
- SD2_CMD_IMARK,
- NFDATA9_MARK,
-
- SD2_DAT0_IMARK,
- NFDATA10_MARK,
-
- SD2_DAT1_IMARK,
- NFDATA11_MARK,
-
- SD2_DAT2_IMARK,
- NFDATA12_MARK,
-
- SD2_DAT3_IMARK,
- NFDATA13_MARK,
-
- SD2_DS_IMARK,
- NFALE_MARK,
-
- SD3_CLK_IMARK,
- NFWEx_MARK,
-
- /* IPSR10 */
- SD3_CMD_IMARK,
- NFREx_MARK,
-
- SD3_DAT0_IMARK,
- NFDATA0_MARK,
-
- SD3_DAT1_IMARK,
- NFDATA1_MARK,
-
- SD3_DAT2_IMARK,
- NFDATA2_MARK,
-
- SD3_DAT3_IMARK,
- NFDATA3_MARK,
-
- SD3_DAT4_IMARK,
- SD2_CD_A_MARK,
- NFDATA4_MARK,
-
- SD3_DAT5_IMARK,
- SD2_WP_A_MARK,
- NFDATA5_MARK,
-
- SD3_DAT6_IMARK,
- SD3_CD_MARK,
- NFDATA6_MARK,
-
- /* IPSR11 */
- SD3_DAT7_IMARK,
- SD3_WP_MARK,
- NFDATA7_MARK,
-
- SD3_DS_IMARK,
- NFCLE_MARK,
-
- SD0_CD_IMARK,
- NFDATA14_A_MARK,
- SCL2_B_MARK,
- SIM0_RST_A_MARK,
-
- SD0_WP_IMARK,
- NFDATA15_A_MARK,
- SDA2_B_MARK,
-
- SD1_CD_IMARK,
- NFRBx_A_MARK,
- SIM0_CLK_B_MARK,
-
- SD1_WP_IMARK,
- NFCEx_A_MARK,
- SIM0_D_B_MARK,
-
- SCK0_IMARK,
- HSCK1_B_MARK,
- MSIOF1_SS2_B_MARK,
- AUDIO_CLKC_B_MARK,
- SDA2_A_MARK,
- SIM0_RST_B_MARK,
- STP_OPWM_0_C_MARK,
- RIF0_CLK_B_MARK,
- ADICHS2_MARK,
- SCK5_B_MARK,
-
- RX0_IMARK,
- HRX1_B_MARK,
- TS_SCK0_C_MARK,
- STP_ISCLK_0_C_MARK,
- RIF0_D0_B_MARK,
-
- /* IPSR12 */
- TX0_IMARK,
- HTX1_B_MARK,
- TS_SPSYNC0_C_MARK,
- STP_ISSYNC_0_C_MARK,
- RIF0_D1_B_MARK,
-
- CTS0x_IMARK,
- HCTS1x_B_MARK,
- MSIOF1_SYNC_B_MARK,
- TS_SPSYNC1_C_MARK,
- STP_ISSYNC_1_C_MARK,
- RIF1_SYNC_B_MARK,
- AUDIO_CLKOUT_C_MARK,
- ADICS_SAMP_MARK,
-
- RTS0x_TANS_IMARK,
- HRTS1x_B_MARK,
- MSIOF1_SS1_B_MARK,
- AUDIO_CLKA_B_MARK,
- SCL2_A_MARK,
- STP_IVCXO27_1_C_MARK,
- RIF0_SYNC_B_MARK,
- ADICHS1_MARK,
-
- RX1_A_IMARK,
- HRX1_A_MARK,
- TS_SDAT0_C_MARK,
- STP_ISD_0_C_MARK,
- RIF1_CLK_C_MARK,
-
- TX1_A_IMARK,
- HTX1_A_MARK,
- TS_SDEN0_C_MARK,
- STP_ISEN_0_C_MARK,
- RIF1_D0_C_MARK,
-
- CTS1x_IMARK,
- HCTS1x_A_MARK,
- MSIOF1_RXD_B_MARK,
- TS_SDEN1_C_MARK,
- STP_ISEN_1_C_MARK,
- RIF1_D0_B_MARK,
- ADIDATA_MARK,
-
- RTS1x_TANS_IMARK,
- HRTS1x_A_MARK,
- MSIOF1_TXD_B_MARK,
- TS_SDAT1_C_MARK,
- STP_ISD_1_C_MARK,
- RIF1_D1_B_MARK,
- ADICHS0_MARK,
-
- SCK2_IMARK,
- SCIF_CLK_B_MARK,
- MSIOF1_SCK_B_MARK,
- TS_SCK1_C_MARK,
- STP_ISCLK_1_C_MARK,
- RIF1_CLK_B_MARK,
- ADICLK_MARK,
-
- /* IPSR13 */
- TX2_A_IMARK,
- SD2_CD_B_MARK,
- SCL1_A_MARK,
- FMCLK_A_MARK,
- RIF1_D1_C_MARK,
- FSO_CFE_0_B_MARK,
-
- RX2_A_IMARK,
- SD2_WP_B_MARK,
- SDA1_A_MARK,
- FMIN_A_MARK,
- RIF1_SYNC_C_MARK,
- FSO_CEF_1_B_MARK,
-
- HSCK0_IMARK,
- MSIOF1_SCK_D_MARK,
- AUDIO_CLKB_A_MARK,
- SSI_SDATA1_B_MARK,
- TS_SCK0_D_MARK,
- STP_ISCLK_0_D_MARK,
- RIF0_CLK_C_MARK,
- RX5_B_MARK,
-
- HRX0_IMARK,
- MSIOF1_RXD_D_MARK,
- SS1_SDATA2_B_MARK,
- TS_SDEN0_D_MARK,
- STP_ISEN_0_D_MARK,
- RIF0_D0_C_MARK,
-
- HTX0_IMARK,
- MSIOF1_TXD_D_MARK,
- SSI_SDATA9_B_MARK,
- TS_SDAT0_D_MARK,
- STP_ISD_0_D_MARK,
- RIF0_D1_C_MARK,
-
- HCTS0x_IMARK,
- RX2_B_MARK,
- MSIOF1_SYNC_D_MARK,
- SSI_SCK9_A_MARK,
- TS_SPSYNC0_D_MARK,
- STP_ISSYNC_0_D_MARK,
- RIF0_SYNC_C_MARK,
- AUDIO_CLKOUT1_A_MARK,
-
- HRTS0x_IMARK,
- TX2_B_MARK,
- MSIOF1_SS1_D_MARK,
- SSI_WS9_A_MARK,
- STP_IVCXO27_0_D_MARK,
- BPFCLK_A_MARK,
- AUDIO_CLKOUT2_A_MARK,
-
- MSIOF0_SYNC_IMARK,
- AUDIO_CLKOUT_A_MARK,
- TX5_B_MARK,
- BPFCLK_D_MARK,
-
- /* IPSR14 */
- MSIOF0_SS1_IMARK,
- RX5_A_MARK,
- NFWPx_A_MARK,
- AUDIO_CLKA_C_MARK,
- SSI_SCK2_A_MARK,
- STP_IVCXO27_0_C_MARK,
- AUDIO_CLKOUT3_A_MARK,
- TCLK1_B_MARK,
-
- MSIOF0_SS2_IMARK,
- TX5_A_MARK,
- MSIOF1_SS2_D_MARK,
- AUDIO_CLKC_A_MARK,
- SSI_WS2_A_MARK,
- STP_OPWM_0_D_MARK,
- AUDIO_CLKOUT_D_MARK,
- SPEEDIN_B_MARK,
-
- MLB_CLK_IMARK,
- MSIOF1_SCK_F_MARK,
- SCL1_B_MARK,
-
- MLB_SIG_IMARK,
- RX1_B_MARK,
- MSIOF1_SYNC_F_MARK,
- SDA1_B_MARK,
-
- MLB_DAT_IMARK,
- TX1_B_MARK,
- MSIOF1_RXD_F_MARK,
-
- SSI_SCK0129_IMARK,
- MSIOF1_TXD_F_MARK,
- MOUT0_MARK,
-
- SSI_WS0129_IMARK,
- MSIOF1_SS1_F_MARK,
- MOUT1_MARK,
-
- SSI_SDATA0_IMARK,
- MSIOF1_SS2_F_MARK,
- MOUT2_MARK,
-
- /* IPSR15 */
- SSI_SDATA1_A_IMARK,
- MOUT5_MARK,
-
- SSI_SDATA2_A_IMARK,
- SSI_SCK1_B_MARK,
- MOUT6_MARK,
-
- SSI_SCK34_IMARK,
- MSIOF1_SS1_A_MARK,
- STP_OPWM_0_A_MARK,
-
- SSI_WS34_IMARK,
- HCTS2x_A_MARK,
- MSIOF1_SS2_A_MARK,
- STP_IVCXO27_0_A_MARK,
-
- SSI_SDATA3_IMARK,
- HRTS2x_A_MARK,
- MSIOF1_TXD_A_MARK,
- TS_SCK0_A_MARK,
- STP_ISCLK_0_A_MARK,
- RIF0_D1_A_MARK,
- RIF2_D0_A_MARK,
-
- SSI_SCK4_IMARK,
- HRX2_A_MARK,
- MSIOF1_SCK_A_MARK,
- TS_SDAT0_A_MARK,
- STP_ISD_0_A_MARK,
- RIF0_CLK_A_MARK,
- RIF2_CLK_A_MARK,
-
- SSI_WS4_IMARK,
- HTX2_A_MARK,
- MSIOF1_SYNC_A_MARK,
- TS_SDEN0_A_MARK,
- STP_ISEN_0_A_MARK,
- RIF0_SYNC_A_MARK,
- RIF2_SYNC_A_MARK,
-
- SSI_SDATA4_IMARK,
- HSCK2_A_MARK,
- MSIOF1_RXD_A_MARK,
- TS_SPSYNC0_A_MARK,
- STP_ISSYNC_0_A_MARK,
- RIF0_D0_A_MARK,
- RIF2_D1_A_MARK,
-
- /* IPSR16 */
- SSI_SCK6_IMARK,
- SIM0_RST_D_MARK,
- FSO_TOE_A_MARK,
-
- SSI_WS6_IMARK,
- SIM0_D_D_MARK,
-
- SSI_SDATA6_IMARK,
- SIM0_CLK_D_MARK,
-
- SSI_SCK78_IMARK,
- HRX2_B_MARK,
- MSIOF1_SCK_C_MARK,
- TS_SCK1_A_MARK,
- STP_ISCLK_1_A_MARK,
- RIF1_CLK_A_MARK,
- RIF3_CLK_A_MARK,
-
- SSI_WS78_IMARK,
- HTX2_B_MARK,
- MSIOF1_SYNC_C_MARK,
- TS_SDAT1_A_MARK,
- STP_ISD_1_A_MARK,
- RIF1_SYNC_A_MARK,
- RIF3_SYNC_A_MARK,
-
- SSI_SDATA7_IMARK,
- HCTS2x_B_MARK,
- MSIOF1_RXD_C_MARK,
- TS_SDEN1_A_MARK,
- STP_IEN_1_A_MARK,
- RIF1_D0_A_MARK,
- RIF3_D0_A_MARK,
- TCLK2_A_MARK,
-
- SSI_SDATA8_IMARK,
- HRTS2x_B_MARK,
- MSIOF1_TXD_C_MARK,
- TS_SPSYNC1_A_MARK,
- STP_ISSYNC_1_A_MARK,
- RIF1_D1_A_MARK,
- EIF3_D1_A_MARK,
-
- SSI_SDATA9_A_IMARK,
- HSCK2_B_MARK,
- MSIOF1_SS1_C_MARK,
- HSCK1_A_MARK,
- SSI_WS1_B_MARK,
- SCK1_MARK,
- STP_IVCXO27_1_A_MARK,
- SCK5_MARK,
-
- /* IPSR17 */
- AUDIO_CLKA_A_IMARK,
- CC5_OSCOUT_MARK,
-
- AUDIO_CLKB_B_IMARK,
- SCIF_CLK_A_MARK,
- STP_IVCXO27_1_D_MARK,
- REMOCON_A_MARK,
- TCLK1_A_MARK,
-
- USB0_PWEN_IMARK,
- SIM0_RST_C_MARK,
- TS_SCK1_D_MARK,
- STP_ISCLK_1_D_MARK,
- BPFCLK_B_MARK,
- RIF3_CLK_B_MARK,
- FSO_CFE_1_A_MARK,
- HSCK2_C_MARK,
-
- USB0_OVC_IMARK,
- SIM0_D_C_MARK,
- TS_SDAT1_D_MARK,
- STP_ISD_1_D_MARK,
- RIF3_SYNC_B_MARK,
- HRX2_C_MARK,
-
- USB1_PWEN_IMARK,
- SIM0_CLK_C_MARK,
- SSI_SCK1_A_MARK,
- TS_SCK0_E_MARK,
- STP_ISCLK_0_E_MARK,
- FMCLK_B_MARK,
- RIF2_CLK_B_MARK,
- SPEEDIN_A_MARK,
- HTX2_C_MARK,
-
- USB1_OVC_IMARK,
- MSIOF1_SS2_C_MARK,
- SSI_WS1_A_MARK,
- TS_SDAT0_E_MARK,
- STP_ISD_0_E_MARK,
- FMIN_B_MARK,
- RIF2_SYNC_B_MARK,
- REMOCON_B_MARK,
- HCTS2x_C_MARK,
-
- USB30_PWEN_IMARK,
- AUDIO_CLKOUT_B_MARK,
- SSI_SCK2_B_MARK,
- TS_SDEN1_D_MARK,
- STP_ISEN_1_D_MARK,
- STP_OPWM_0_E_MARK,
- RIF3_D0_B_MARK,
- TCLK2_B_MARK,
- TPU0TO0_MARK,
- BPFCLK_C_MARK,
- HRTS2x_C_MARK,
-
- USB30_OVC_IMARK,
- AUDIO_CLKOUT1_B_MARK,
- SSI_WS2_B_MARK,
- TS_SPSYNC1_D_MARK,
- STP_ISSYNC_1_D_MARK,
- STP_IVCXO27_0_E_MARK,
- RIF3_D1_B_MARK,
- FSO_TOE_B_MARK,
- TPU0TO1_MARK,
-
- /* IPSR18 */
- GP6_30_IMARK,
- AUDIO_CLKOUT2_B_MARK,
- SSI_SCK9_B_MARK,
- TS_SDEN0_E_MARK,
- STP_ISEN_0_E_MARK,
- RIF2_D0_B_MARK,
- FSO_CFE_0_A_MARK,
- TPU0TO2_MARK,
- FMCLK_C_MARK,
- FMCLK_D_MARK,
-
- GP6_31_IMARK,
- AUDIO_CLKOUT3_B_MARK,
- SSI_WS9_B_MARK,
- TS_SPSYNC0_E_MARK,
- STP_ISSYNC_0_E_MARK,
- RIF2_D1_B_MARK,
- TPU0TO3_MARK,
- FMIN_C_MARK,
- FMIN_D_MARK,
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- /* GPSR0 */
- PINMUX_DATA(D15_GMARK, GFN_D15),
- PINMUX_DATA(D14_GMARK, GFN_D14),
- PINMUX_DATA(D13_GMARK, GFN_D13),
- PINMUX_DATA(D12_GMARK, GFN_D12),
- PINMUX_DATA(D11_GMARK, GFN_D11),
- PINMUX_DATA(D10_GMARK, GFN_D10),
- PINMUX_DATA(D9_GMARK, GFN_D9),
- PINMUX_DATA(D8_GMARK, GFN_D8),
- PINMUX_DATA(D7_GMARK, GFN_D7),
- PINMUX_DATA(D6_GMARK, GFN_D6),
- PINMUX_DATA(D5_GMARK, GFN_D5),
- PINMUX_DATA(D4_GMARK, GFN_D4),
- PINMUX_DATA(D3_GMARK, GFN_D3),
- PINMUX_DATA(D2_GMARK, GFN_D2),
- PINMUX_DATA(D1_GMARK, GFN_D1),
- PINMUX_DATA(D0_GMARK, GFN_D0),
-
- /* GPSR1 */
- PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT),
- PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),
- PINMUX_DATA(WE1x_GMARK, GFN_WE1x),
- PINMUX_DATA(WE0x_GMARK, GFN_WE0x),
- PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx),
- PINMUX_DATA(RDx_GMARK, GFN_RDx),
- PINMUX_DATA(BSx_GMARK, GFN_BSx),
- PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26),
- PINMUX_DATA(CS0x_GMARK, GFN_CS0x),
- PINMUX_DATA(A19_GMARK, GFN_A19),
- PINMUX_DATA(A18_GMARK, GFN_A18),
- PINMUX_DATA(A17_GMARK, GFN_A17),
- PINMUX_DATA(A16_GMARK, GFN_A16),
- PINMUX_DATA(A15_GMARK, GFN_A15),
- PINMUX_DATA(A14_GMARK, GFN_A14),
- PINMUX_DATA(A13_GMARK, GFN_A13),
- PINMUX_DATA(A12_GMARK, GFN_A12),
- PINMUX_DATA(A11_GMARK, GFN_A11),
- PINMUX_DATA(A10_GMARK, GFN_A10),
- PINMUX_DATA(A9_GMARK, GFN_A9),
- PINMUX_DATA(A8_GMARK, GFN_A8),
- PINMUX_DATA(A7_GMARK, GFN_A7),
- PINMUX_DATA(A6_GMARK, GFN_A6),
- PINMUX_DATA(A5_GMARK, GFN_A5),
- PINMUX_DATA(A4_GMARK, GFN_A4),
- PINMUX_DATA(A3_GMARK, GFN_A3),
- PINMUX_DATA(A2_GMARK, GFN_A2),
- PINMUX_DATA(A1_GMARK, GFN_A1),
- PINMUX_DATA(A0_GMARK, GFN_A0),
-
- /* GPSR2 */
- PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A),
- PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A),
- PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK),
- PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT),
- PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC),
- PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC),
- PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A),
- PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A),
- PINMUX_DATA(PWM0_GMARK, GFN_PWM0),
- PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),
- PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),
- PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3),
- PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2),
- PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1),
- PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),
-
- /* GPSR3 */
- PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP),
- PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD),
- PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP),
- PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD),
- PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3),
- PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2),
- PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1),
- PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0),
- PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD),
- PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK),
- PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3),
- PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2),
- PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1),
- PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0),
- PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD),
- PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),
-
- /* GPSR4 */
- PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS),
- PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),
- PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),
- PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),
- PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),
- PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3),
- PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2),
- PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1),
- PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0),
- PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD),
- PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK),
- PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),
- PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),
- PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),
- PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),
- PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),
- PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD),
- PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),
-
- /* GPSR5 */
- PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT),
- PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG),
- PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK),
- PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD),
- PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),
- PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD),
- PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),
- PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),
- PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK),
- PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x),
- PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x),
- PINMUX_DATA(HTX0_GMARK, GFN_HTX0),
- PINMUX_DATA(HRX0_GMARK, GFN_HRX0),
- PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0),
- PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A),
- PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A),
- PINMUX_DATA(SCK2_GMARK, GFN_SCK2),
- PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS),
- PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x),
- PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A),
- PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A),
- PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS),
- PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x),
- PINMUX_DATA(TX0_GMARK, GFN_TX0),
- PINMUX_DATA(RX0_GMARK, GFN_RX0),
- PINMUX_DATA(SCK0_GMARK, GFN_SCK0),
-
- /* GPSR6 */
- PINMUX_DATA(GP6_30_GMARK, GFN_GP6_30),
- PINMUX_DATA(GP6_31_GMARK, GFN_GP6_31),
- PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),
- PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),
- PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),
- PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN),
- PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC),
- PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN),
- PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B),
- PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A),
- PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A),
- PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8),
- PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7),
- PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78),
- PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78),
- PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6),
- PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6),
- PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6),
- PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5),
- PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5),
- PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5),
- PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4),
- PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4),
- PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4),
- PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3),
- PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34),
- PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34),
- PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),
- PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),
- PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),
- PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239),
- PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239),
-
- /* GPSR7 */
- PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),
- PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),
- PINMUX_DATA(AVS2_MARK, FN_AVS2),
- PINMUX_DATA(AVS1_MARK, FN_AVS1),
-
- /* ipsr setting .. underconstruction */
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
- /* GPSR0 */
- GPIO_GFN(D15),
- GPIO_GFN(D14),
- GPIO_GFN(D13),
- GPIO_GFN(D12),
- GPIO_GFN(D11),
- GPIO_GFN(D10),
- GPIO_GFN(D9),
- GPIO_GFN(D8),
- GPIO_GFN(D7),
- GPIO_GFN(D6),
- GPIO_GFN(D5),
- GPIO_GFN(D4),
- GPIO_GFN(D3),
- GPIO_GFN(D2),
- GPIO_GFN(D1),
- GPIO_GFN(D0),
- /* GPSR1 */
- GPIO_GFN(CLKOUT),
- GPIO_GFN(EX_WAIT0_A),
- GPIO_GFN(WE1x),
- GPIO_GFN(WE0x),
- GPIO_GFN(RD_WRx),
- GPIO_GFN(RDx),
- GPIO_GFN(BSx),
- GPIO_GFN(CS1x_A26),
- GPIO_GFN(CS0x),
- GPIO_GFN(A19),
- GPIO_GFN(A18),
- GPIO_GFN(A17),
- GPIO_GFN(A16),
- GPIO_GFN(A15),
- GPIO_GFN(A14),
- GPIO_GFN(A13),
- GPIO_GFN(A12),
- GPIO_GFN(A11),
- GPIO_GFN(A10),
- GPIO_GFN(A9),
- GPIO_GFN(A8),
- GPIO_GFN(A7),
- GPIO_GFN(A6),
- GPIO_GFN(A5),
- GPIO_GFN(A4),
- GPIO_GFN(A3),
- GPIO_GFN(A2),
- GPIO_GFN(A1),
- GPIO_GFN(A0),
-
- /* GPSR2 */
- GPIO_GFN(AVB_AVTP_CAPTURE_A),
- GPIO_GFN(AVB_AVTP_MATCH_A),
- GPIO_GFN(AVB_LINK),
- GPIO_GFN(AVB_PHY_INT),
- GPIO_GFN(AVB_MAGIC),
- GPIO_GFN(AVB_MDC),
- GPIO_GFN(PWM2_A),
- GPIO_GFN(PWM1_A),
- GPIO_GFN(PWM0),
- GPIO_GFN(IRQ5),
- GPIO_GFN(IRQ4),
- GPIO_GFN(IRQ3),
- GPIO_GFN(IRQ2),
- GPIO_GFN(IRQ1),
- GPIO_GFN(IRQ0),
-
- /* GPSR3 */
- GPIO_GFN(SD1_WP),
- GPIO_GFN(SD1_CD),
- GPIO_GFN(SD0_WP),
- GPIO_GFN(SD0_CD),
- GPIO_GFN(SD1_DAT3),
- GPIO_GFN(SD1_DAT2),
- GPIO_GFN(SD1_DAT1),
- GPIO_GFN(SD1_DAT0),
- GPIO_GFN(SD1_CMD),
- GPIO_GFN(SD1_CLK),
- GPIO_GFN(SD0_DAT3),
- GPIO_GFN(SD0_DAT2),
- GPIO_GFN(SD0_DAT1),
- GPIO_GFN(SD0_DAT0),
- GPIO_GFN(SD0_CMD),
- GPIO_GFN(SD0_CLK),
-
- /* GPSR4 */
- GPIO_GFN(SD3_DS),
- GPIO_GFN(SD3_DAT7),
- GPIO_GFN(SD3_DAT6),
- GPIO_GFN(SD3_DAT5),
- GPIO_GFN(SD3_DAT4),
- GPIO_FN(SD3_DAT3),
- GPIO_FN(SD3_DAT2),
- GPIO_FN(SD3_DAT1),
- GPIO_FN(SD3_DAT0),
- GPIO_FN(SD3_CMD),
- GPIO_FN(SD3_CLK),
- GPIO_GFN(SD2_DS),
- GPIO_GFN(SD2_DAT3),
- GPIO_GFN(SD2_DAT2),
- GPIO_GFN(SD2_DAT1),
- GPIO_GFN(SD2_DAT0),
- GPIO_FN(SD2_CMD),
- GPIO_GFN(SD2_CLK),
-
- /* GPSR5 */
- GPIO_GFN(MLB_DAT),
- GPIO_GFN(MLB_SIG),
- GPIO_GFN(MLB_CLK),
- GPIO_FN(MSIOF0_RXD),
- GPIO_GFN(MSIOF0_SS2),
- GPIO_FN(MSIOF0_TXD),
- GPIO_GFN(MSIOF0_SS1),
- GPIO_GFN(MSIOF0_SYNC),
- GPIO_FN(MSIOF0_SCK),
- GPIO_GFN(HRTS0x),
- GPIO_GFN(HCTS0x),
- GPIO_GFN(HTX0),
- GPIO_GFN(HRX0),
- GPIO_GFN(HSCK0),
- GPIO_GFN(RX2_A),
- GPIO_GFN(TX2_A),
- GPIO_GFN(SCK2),
- GPIO_GFN(RTS1x_TANS),
- GPIO_GFN(CTS1x),
- GPIO_GFN(TX1_A),
- GPIO_GFN(RX1_A),
- GPIO_GFN(RTS0x_TANS),
- GPIO_GFN(CTS0x),
- GPIO_GFN(TX0),
- GPIO_GFN(RX0),
- GPIO_GFN(SCK0),
-
- /* GPSR6 */
- GPIO_GFN(GP6_30),
- GPIO_GFN(GP6_31),
- GPIO_GFN(USB30_OVC),
- GPIO_GFN(USB30_PWEN),
- GPIO_GFN(USB1_OVC),
- GPIO_GFN(USB1_PWEN),
- GPIO_GFN(USB0_OVC),
- GPIO_GFN(USB0_PWEN),
- GPIO_GFN(AUDIO_CLKB_B),
- GPIO_GFN(AUDIO_CLKA_A),
- GPIO_GFN(SSI_SDATA9_A),
- GPIO_GFN(SSI_SDATA8),
- GPIO_GFN(SSI_SDATA7),
- GPIO_GFN(SSI_WS78),
- GPIO_GFN(SSI_SCK78),
- GPIO_GFN(SSI_SDATA6),
- GPIO_GFN(SSI_WS6),
- GPIO_GFN(SSI_SCK6),
- GPIO_FN(SSI_SDATA5),
- GPIO_FN(SSI_WS5),
- GPIO_FN(SSI_SCK5),
- GPIO_GFN(SSI_SDATA4),
- GPIO_GFN(SSI_WS4),
- GPIO_GFN(SSI_SCK4),
- GPIO_GFN(SSI_SDATA3),
- GPIO_GFN(SSI_WS34),
- GPIO_GFN(SSI_SCK34),
- GPIO_GFN(SSI_SDATA2_A),
- GPIO_GFN(SSI_SDATA1_A),
- GPIO_GFN(SSI_SDATA0),
- GPIO_GFN(SSI_WS01239),
- GPIO_GFN(SSI_SCK01239),
-
- /* GPSR7 */
- GPIO_FN(HDMI1_CEC),
- GPIO_FN(HDMI0_CEC),
- GPIO_FN(AVS2),
- GPIO_FN(AVS1),
-
- /* IPSR0 */
- GPIO_IFN(AVB_MDC),
- GPIO_FN(MSIOF2_SS2_C),
- GPIO_IFN(AVB_MAGIC),
- GPIO_FN(MSIOF2_SS1_C),
- GPIO_FN(SCK4_A),
- GPIO_IFN(AVB_PHY_INT),
- GPIO_FN(MSIOF2_SYNC_C),
- GPIO_FN(RX4_A),
- GPIO_IFN(AVB_LINK),
- GPIO_FN(MSIOF2_SCK_C),
- GPIO_FN(TX4_A),
- GPIO_IFN(AVB_AVTP_MATCH_A),
- GPIO_FN(MSIOF2_RXD_C),
- GPIO_FN(CTS4x_A),
- GPIO_IFN(AVB_AVTP_CAPTURE_A),
- GPIO_FN(MSIOF2_TXD_C),
- GPIO_FN(RTS4x_TANS_A),
- GPIO_IFN(IRQ0),
- GPIO_FN(QPOLB),
- GPIO_FN(DU_CDE),
- GPIO_FN(VI4_DATA0_B),
- GPIO_FN(CAN0_TX_B),
- GPIO_FN(CANFD0_TX_B),
- GPIO_FN(MSIOF3_SS2_E),
- GPIO_IFN(IRQ1),
- GPIO_FN(QPOLA),
- GPIO_FN(DU_DISP),
- GPIO_FN(VI4_DATA1_B),
- GPIO_FN(CAN0_RX_B),
- GPIO_FN(CANFD0_RX_B),
- GPIO_FN(MSIOF3_SS1_E),
-
- /* IPSR1 */
- GPIO_IFN(IRQ2),
- GPIO_FN(QCPV_QDE),
- GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),
- GPIO_FN(VI4_DATA2_B),
- GPIO_FN(MSIOF3_SYNC_E),
- GPIO_FN(PWM3_B),
- GPIO_IFN(IRQ3),
- GPIO_FN(QSTVB_QVE),
- GPIO_FN(DU_DOTCLKOUT1),
- GPIO_FN(VI4_DATA3_B),
- GPIO_FN(MSIOF3_SCK_E),
- GPIO_FN(PWM4_B),
- GPIO_IFN(IRQ4),
- GPIO_FN(QSTH_QHS),
- GPIO_FN(DU_EXHSYNC_DU_HSYNC),
- GPIO_FN(VI4_DATA4_B),
- GPIO_FN(MSIOF3_RXD_E),
- GPIO_FN(PWM5_B),
- GPIO_IFN(IRQ5),
- GPIO_FN(QSTB_QHE),
- GPIO_FN(DU_EXVSYNC_DU_VSYNC),
- GPIO_FN(VI4_DATA5_B),
- GPIO_FN(MSIOF3_TXD_E),
- GPIO_FN(PWM6_B),
- GPIO_IFN(PWM0),
- GPIO_FN(AVB_AVTP_PPS),
- GPIO_FN(VI4_DATA6_B),
- GPIO_FN(IECLK_B),
- GPIO_IFN(PWM1_A),
- GPIO_FN(HRX3_D),
- GPIO_FN(VI4_DATA7_B),
- GPIO_FN(IERX_B),
- GPIO_IFN(PWM2_A),
- GPIO_FN(PWMFSW0),
- GPIO_FN(HTX3_D),
- GPIO_FN(IETX_B),
- GPIO_IFN(A0),
- GPIO_FN(LCDOUT16),
- GPIO_FN(MSIOF3_SYNC_B),
- GPIO_FN(VI4_DATA8),
- GPIO_FN(DU_DB0),
- GPIO_FN(PWM3_A),
-
- /* IPSR2 */
- GPIO_IFN(A1),
- GPIO_FN(LCDOUT17),
- GPIO_FN(MSIOF3_TXD_B),
- GPIO_FN(VI4_DATA9),
- GPIO_FN(DU_DB1),
- GPIO_FN(PWM4_A),
- GPIO_IFN(A2),
- GPIO_FN(LCDOUT18),
- GPIO_FN(MSIOF3_SCK_B),
- GPIO_FN(VI4_DATA10),
- GPIO_FN(DU_DB2),
- GPIO_FN(PWM5_A),
- GPIO_IFN(A3),
- GPIO_FN(LCDOUT19),
- GPIO_FN(MSIOF3_RXD_B),
- GPIO_FN(VI4_DATA11),
- GPIO_FN(DU_DB3),
- GPIO_FN(PWM6_A),
- GPIO_IFN(A4),
- GPIO_FN(LCDOUT20),
- GPIO_FN(MSIOF3_SS1_B),
- GPIO_FN(VI4_DATA12),
- GPIO_FN(VI5_DATA12),
- GPIO_FN(DU_DB4),
- GPIO_IFN(A5),
- GPIO_FN(LCDOUT21),
- GPIO_FN(MSIOF3_SS2_B),
- GPIO_FN(SCK4_B),
- GPIO_FN(VI4_DATA13),
- GPIO_FN(VI5_DATA13),
- GPIO_FN(DU_DB5),
- GPIO_IFN(A6),
- GPIO_FN(LCDOUT22),
- GPIO_FN(MSIOF2_SS1_A),
- GPIO_FN(RX4_B),
- GPIO_FN(VI4_DATA14),
- GPIO_FN(VI5_DATA14),
- GPIO_FN(DU_DB6),
- GPIO_IFN(A7),
- GPIO_FN(LCDOUT23),
- GPIO_FN(MSIOF2_SS2_A),
- GPIO_FN(TX4_B),
- GPIO_FN(VI4_DATA15),
- GPIO_FN(V15_DATA15),
- GPIO_FN(DU_DB7),
- GPIO_IFN(A8),
- GPIO_FN(RX3_B),
- GPIO_FN(MSIOF2_SYNC_A),
- GPIO_FN(HRX4_B),
- GPIO_FN(SDA6_A),
- GPIO_FN(AVB_AVTP_MATCH_B),
- GPIO_FN(PWM1_B),
-
- /* IPSR3 */
- GPIO_IFN(A9),
- GPIO_FN(MSIOF2_SCK_A),
- GPIO_FN(CTS4x_B),
- GPIO_FN(VI5_VSYNCx),
- GPIO_IFN(A10),
- GPIO_FN(MSIOF2_RXD_A),
- GPIO_FN(RTS4n_TANS_B),
- GPIO_FN(VI5_HSYNCx),
- GPIO_IFN(A11),
- GPIO_FN(TX3_B),
- GPIO_FN(MSIOF2_TXD_A),
- GPIO_FN(HTX4_B),
- GPIO_FN(HSCK4),
- GPIO_FN(VI5_FIELD),
- GPIO_FN(SCL6_A),
- GPIO_FN(AVB_AVTP_CAPTURE_B),
- GPIO_FN(PWM2_B),
- GPIO_FN(SPV_EVEN),
- GPIO_IFN(A12),
- GPIO_FN(LCDOUT12),
- GPIO_FN(MSIOF3_SCK_C),
- GPIO_FN(HRX4_A),
- GPIO_FN(VI5_DATA8),
- GPIO_FN(DU_DG4),
- GPIO_IFN(A13),
- GPIO_FN(LCDOUT13),
- GPIO_FN(MSIOF3_SYNC_C),
- GPIO_FN(HTX4_A),
- GPIO_FN(VI5_DATA9),
- GPIO_FN(DU_DG5),
- GPIO_IFN(A14),
- GPIO_FN(LCDOUT14),
- GPIO_FN(MSIOF3_RXD_C),
- GPIO_FN(HCTS4x),
- GPIO_FN(VI5_DATA10),
- GPIO_FN(DU_DG6),
- GPIO_IFN(A15),
- GPIO_FN(LCDOUT15),
- GPIO_FN(MSIOF3_TXD_C),
- GPIO_FN(HRTS4x),
- GPIO_FN(VI5_DATA11),
- GPIO_FN(DU_DG7),
- GPIO_IFN(A16),
- GPIO_FN(LCDOUT8),
- GPIO_FN(VI4_FIELD),
- GPIO_FN(DU_DG0),
-
- /* IPSR4 */
- GPIO_IFN(A17),
- GPIO_FN(LCDOUT9),
- GPIO_FN(VI4_VSYNCx),
- GPIO_FN(DU_DG1),
- GPIO_IFN(A18),
- GPIO_FN(LCDOUT10),
- GPIO_FN(VI4_HSYNCx),
- GPIO_FN(DU_DG2),
- GPIO_IFN(A19),
- GPIO_FN(LCDOUT11),
- GPIO_FN(VI4_CLKENB),
- GPIO_FN(DU_DG3),
- GPIO_IFN(CS0x),
- GPIO_FN(VI5_CLKENB),
- GPIO_IFN(CS1x_A26),
- GPIO_FN(VI5_CLK),
- GPIO_FN(EX_WAIT0_B),
- GPIO_IFN(BSx),
- GPIO_FN(QSTVA_QVS),
- GPIO_FN(MSIOF3_SCK_D),
- GPIO_FN(SCK3),
- GPIO_FN(HSCK3),
- GPIO_FN(CAN1_TX),
- GPIO_FN(CANFD1_TX),
- GPIO_FN(IETX_A),
- GPIO_IFN(RDx),
- GPIO_FN(MSIOF3_SYNC_D),
- GPIO_FN(RX3_A),
- GPIO_FN(HRX3_A),
- GPIO_FN(CAN0_TX_A),
- GPIO_FN(CANFD0_TX_A),
- GPIO_IFN(RD_WRx),
- GPIO_FN(MSIOF3_RXD_D),
- GPIO_FN(TX3_A),
- GPIO_FN(HTX3_A),
- GPIO_FN(CAN0_RX_A),
- GPIO_FN(CANFD0_RX_A),
-
- /* IPSR5 */
- GPIO_IFN(WE0x),
- GPIO_FN(MSIIOF3_TXD_D),
- GPIO_FN(CTS3x),
- GPIO_FN(HCTS3x),
- GPIO_FN(SCL6_B),
- GPIO_FN(CAN_CLK),
- GPIO_FN(IECLK_A),
- GPIO_IFN(WE1x),
- GPIO_FN(MSIOF3_SS1_D),
- GPIO_FN(RTS3x_TANS),
- GPIO_FN(HRTS3x),
- GPIO_FN(SDA6_B),
- GPIO_FN(CAN1_RX),
- GPIO_FN(CANFD1_RX),
- GPIO_FN(IERX_A),
- GPIO_IFN(EX_WAIT0_A),
- GPIO_FN(QCLK),
- GPIO_FN(VI4_CLK),
- GPIO_FN(DU_DOTCLKOUT0),
- GPIO_IFN(D0),
- GPIO_FN(MSIOF2_SS1_B),
- GPIO_FN(MSIOF3_SCK_A),
- GPIO_FN(VI4_DATA16),
- GPIO_FN(VI5_DATA0),
- GPIO_IFN(D1),
- GPIO_FN(MSIOF2_SS2_B),
- GPIO_FN(MSIOF3_SYNC_A),
- GPIO_FN(VI4_DATA17),
- GPIO_FN(VI5_DATA1),
- GPIO_IFN(D2),
- GPIO_FN(MSIOF3_RXD_A),
- GPIO_FN(VI4_DATA18),
- GPIO_FN(VI5_DATA2),
- GPIO_IFN(D3),
- GPIO_FN(MSIOF3_TXD_A),
- GPIO_FN(VI4_DATA19),
- GPIO_FN(VI5_DATA3),
- GPIO_IFN(D4),
- GPIO_FN(MSIOF2_SCK_B),
- GPIO_FN(VI4_DATA20),
- GPIO_FN(VI5_DATA4),
-
- /* IPSR6 */
- GPIO_IFN(D5),
- GPIO_FN(MSIOF2_SYNC_B),
- GPIO_FN(VI4_DATA21),
- GPIO_FN(VI5_DATA5),
- GPIO_IFN(D6),
- GPIO_FN(MSIOF2_RXD_B),
- GPIO_FN(VI4_DATA22),
- GPIO_FN(VI5_DATA6),
- GPIO_IFN(D7),
- GPIO_FN(MSIOF2_TXD_B),
- GPIO_FN(VI4_DATA23),
- GPIO_FN(VI5_DATA7),
- GPIO_IFN(D8),
- GPIO_FN(LCDOUT0),
- GPIO_FN(MSIOF2_SCK_D),
- GPIO_FN(SCK4_C),
- GPIO_FN(VI4_DATA0_A),
- GPIO_FN(DU_DR0),
- GPIO_IFN(D9),
- GPIO_FN(LCDOUT1),
- GPIO_FN(MSIOF2_SYNC_D),
- GPIO_FN(VI4_DATA1_A),
- GPIO_FN(DU_DR1),
- GPIO_IFN(D10),
- GPIO_FN(LCDOUT2),
- GPIO_FN(MSIOF2_RXD_D),
- GPIO_FN(HRX3_B),
- GPIO_FN(VI4_DATA2_A),
- GPIO_FN(CTS4x_C),
- GPIO_FN(DU_DR2),
- GPIO_IFN(D11),
- GPIO_FN(LCDOUT3),
- GPIO_FN(MSIOF2_TXD_D),
- GPIO_FN(HTX3_B),
- GPIO_FN(VI4_DATA3_A),
- GPIO_FN(RTS4x_TANS_C),
- GPIO_FN(DU_DR3),
- GPIO_IFN(D12),
- GPIO_FN(LCDOUT4),
- GPIO_FN(MSIOF2_SS1_D),
- GPIO_FN(RX4_C),
- GPIO_FN(VI4_DATA4_A),
- GPIO_FN(DU_DR4),
-
- /* IPSR7 */
- GPIO_IFN(D13),
- GPIO_FN(LCDOUT5),
- GPIO_FN(MSIOF2_SS2_D),
- GPIO_FN(TX4_C),
- GPIO_FN(VI4_DATA5_A),
- GPIO_FN(DU_DR5),
- GPIO_IFN(D14),
- GPIO_FN(LCDOUT6),
- GPIO_FN(MSIOF3_SS1_A),
- GPIO_FN(HRX3_C),
- GPIO_FN(VI4_DATA6_A),
- GPIO_FN(DU_DR6),
- GPIO_FN(SCL6_C),
- GPIO_IFN(D15),
- GPIO_FN(LCDOUT7),
- GPIO_FN(MSIOF3_SS2_A),
- GPIO_FN(HTX3_C),
- GPIO_FN(VI4_DATA7_A),
- GPIO_FN(DU_DR7),
- GPIO_FN(SDA6_C),
- GPIO_FN(FSCLKST),
- GPIO_IFN(SD0_CLK),
- GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(STP_OPWM_0_B),
- GPIO_IFN(SD0_CMD),
- GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(STP_IVCXO27_0_B),
- GPIO_IFN(SD0_DAT0),
- GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(TS_SCK0_B),
- GPIO_FN(STP_ISCLK_0_B),
- GPIO_IFN(SD0_DAT1),
- GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(STP_ISSYNC_0_B),
-
- /* IPSR8 */
- GPIO_IFN(SD0_DAT2),
- GPIO_FN(MSIOF1_SS1_E),
- GPIO_FN(TS_SDAT0_B),
- GPIO_FN(STP_ISD_0_B),
-
- GPIO_IFN(SD0_DAT3),
- GPIO_FN(MSIOF1_SS2_E),
- GPIO_FN(TS_SDEN0_B),
- GPIO_FN(STP_ISEN_0_B),
-
- GPIO_IFN(SD1_CLK),
- GPIO_FN(MSIOF1_SCK_G),
- GPIO_FN(SIM0_CLK_A),
-
- GPIO_IFN(SD1_CMD),
- GPIO_FN(MSIOF1_SYNC_G),
- GPIO_FN(NFCEx_B),
- GPIO_FN(SIM0_D_A),
- GPIO_FN(STP_IVCXO27_1_B),
-
- GPIO_IFN(SD1_DAT0),
- GPIO_FN(SD2_DAT4),
- GPIO_FN(MSIOF1_RXD_G),
- GPIO_FN(NFWPx_B),
- GPIO_FN(TS_SCK1_B),
- GPIO_FN(STP_ISCLK_1_B),
-
- GPIO_IFN(SD1_DAT1),
- GPIO_FN(SD2_DAT5),
- GPIO_FN(MSIOF1_TXD_G),
- GPIO_FN(NFDATA14_B),
- GPIO_FN(TS_SPSYNC1_B),
- GPIO_FN(STP_ISSYNC_1_B),
-
- GPIO_IFN(SD1_DAT2),
- GPIO_FN(SD2_DAT6),
- GPIO_FN(MSIOF1_SS1_G),
- GPIO_FN(NFDATA15_B),
- GPIO_FN(TS_SDAT1_B),
- GPIO_FN(STP_IOD_1_B),
-
- GPIO_IFN(SD1_DAT3),
- GPIO_FN(SD2_DAT7),
- GPIO_FN(MSIOF1_SS2_G),
- GPIO_FN(NFRBx_B),
- GPIO_FN(TS_SDEN1_B),
- GPIO_FN(STP_ISEN_1_B),
-
- /* IPSR9 */
- GPIO_IFN(SD2_CLK),
- GPIO_FN(NFDATA8),
-
- GPIO_IFN(SD2_CMD),
- GPIO_FN(NFDATA9),
-
- GPIO_IFN(SD2_DAT0),
- GPIO_FN(NFDATA10),
-
- GPIO_IFN(SD2_DAT1),
- GPIO_FN(NFDATA11),
-
- GPIO_IFN(SD2_DAT2),
- GPIO_FN(NFDATA12),
-
- GPIO_IFN(SD2_DAT3),
- GPIO_FN(NFDATA13),
-
- GPIO_IFN(SD2_DS),
- GPIO_FN(NFALE),
-
- GPIO_IFN(SD3_CLK),
- GPIO_FN(NFWEx),
-
- /* IPSR10 */
- GPIO_IFN(SD3_CMD),
- GPIO_FN(NFREx),
-
- GPIO_IFN(SD3_DAT0),
- GPIO_FN(NFDATA0),
-
- GPIO_IFN(SD3_DAT1),
- GPIO_FN(NFDATA1),
-
- GPIO_IFN(SD3_DAT2),
- GPIO_FN(NFDATA2),
-
- GPIO_IFN(SD3_DAT3),
- GPIO_FN(NFDATA3),
-
- GPIO_IFN(SD3_DAT4),
- GPIO_FN(SD2_CD_A),
- GPIO_FN(NFDATA4),
-
- GPIO_IFN(SD3_DAT5),
- GPIO_FN(SD2_WP_A),
- GPIO_FN(NFDATA5),
-
- GPIO_IFN(SD3_DAT6),
- GPIO_FN(SD3_CD),
- GPIO_FN(NFDATA6),
-
- /* IPSR11 */
- GPIO_IFN(SD3_DAT7),
- GPIO_FN(SD3_WP),
- GPIO_FN(NFDATA7),
-
- GPIO_IFN(SD3_DS),
- GPIO_FN(NFCLE),
-
- GPIO_IFN(SD0_CD),
- GPIO_FN(NFDATA14_A),
- GPIO_FN(SCL2_B),
- GPIO_FN(SIM0_RST_A),
-
- GPIO_IFN(SD0_WP),
- GPIO_FN(NFDATA15_A),
- GPIO_FN(SDA2_B),
-
- GPIO_IFN(SD1_CD),
- GPIO_FN(NFRBx_A),
- GPIO_FN(SIM0_CLK_B),
-
- GPIO_IFN(SD1_WP),
- GPIO_FN(NFCEx_A),
- GPIO_FN(SIM0_D_B),
-
- GPIO_IFN(SCK0),
- GPIO_FN(HSCK1_B),
- GPIO_FN(MSIOF1_SS2_B),
- GPIO_FN(AUDIO_CLKC_B),
- GPIO_FN(SDA2_A),
- GPIO_FN(SIM0_RST_B),
- GPIO_FN(STP_OPWM_0_C),
- GPIO_FN(RIF0_CLK_B),
- GPIO_FN(ADICHS2),
- GPIO_FN(SCK5_B),
-
- GPIO_IFN(RX0),
- GPIO_FN(HRX1_B),
- GPIO_FN(TS_SCK0_C),
- GPIO_FN(STP_ISCLK_0_C),
- GPIO_FN(RIF0_D0_B),
-
- /* IPSR12 */
- GPIO_IFN(TX0),
- GPIO_FN(HTX1_B),
- GPIO_FN(TS_SPSYNC0_C),
- GPIO_FN(STP_ISSYNC_0_C),
- GPIO_FN(RIF0_D1_B),
-
- GPIO_IFN(CTS0x),
- GPIO_FN(HCTS1x_B),
- GPIO_FN(MSIOF1_SYNC_B),
- GPIO_FN(TS_SPSYNC1_C),
- GPIO_FN(STP_ISSYNC_1_C),
- GPIO_FN(RIF1_SYNC_B),
- GPIO_FN(AUDIO_CLKOUT_C),
- GPIO_FN(ADICS_SAMP),
-
- GPIO_IFN(RTS0x_TANS),
- GPIO_FN(HRTS1x_B),
- GPIO_FN(MSIOF1_SS1_B),
- GPIO_FN(AUDIO_CLKA_B),
- GPIO_FN(SCL2_A),
- GPIO_FN(STP_IVCXO27_1_C),
- GPIO_FN(RIF0_SYNC_B),
- GPIO_FN(ADICHS1),
-
- GPIO_IFN(RX1_A),
- GPIO_FN(HRX1_A),
- GPIO_FN(TS_SDAT0_C),
- GPIO_FN(STP_ISD_0_C),
- GPIO_FN(RIF1_CLK_C),
-
- GPIO_IFN(TX1_A),
- GPIO_FN(HTX1_A),
- GPIO_FN(TS_SDEN0_C),
- GPIO_FN(STP_ISEN_0_C),
- GPIO_FN(RIF1_D0_C),
-
- GPIO_IFN(CTS1x),
- GPIO_FN(HCTS1x_A),
- GPIO_FN(MSIOF1_RXD_B),
- GPIO_FN(TS_SDEN1_C),
- GPIO_FN(STP_ISEN_1_C),
- GPIO_FN(RIF1_D0_B),
- GPIO_FN(ADIDATA),
-
- GPIO_IFN(RTS1x_TANS),
- GPIO_FN(HRTS1x_A),
- GPIO_FN(MSIOF1_TXD_B),
- GPIO_FN(TS_SDAT1_C),
- GPIO_FN(STP_ISD_1_C),
- GPIO_FN(RIF1_D1_B),
- GPIO_FN(ADICHS0),
-
- GPIO_IFN(SCK2),
- GPIO_FN(SCIF_CLK_B),
- GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(TS_SCK1_C),
- GPIO_FN(STP_ISCLK_1_C),
- GPIO_FN(RIF1_CLK_B),
- GPIO_FN(ADICLK),
-
- /* IPSR13 */
- GPIO_IFN(TX2_A),
- GPIO_FN(SD2_CD_B),
- GPIO_FN(SCL1_A),
- GPIO_FN(FMCLK_A),
- GPIO_FN(RIF1_D1_C),
- GPIO_FN(FSO_CFE_0_B),
-
- GPIO_IFN(RX2_A),
- GPIO_FN(SD2_WP_B),
- GPIO_FN(SDA1_A),
- GPIO_FN(FMIN_A),
- GPIO_FN(RIF1_SYNC_C),
- GPIO_FN(FSO_CEF_1_B),
-
- GPIO_IFN(HSCK0),
- GPIO_FN(MSIOF1_SCK_D),
- GPIO_FN(AUDIO_CLKB_A),
- GPIO_FN(SSI_SDATA1_B),
- GPIO_FN(TS_SCK0_D),
- GPIO_FN(STP_ISCLK_0_D),
- GPIO_FN(RIF0_CLK_C),
- GPIO_FN(RX5_B),
-
- GPIO_IFN(HRX0),
- GPIO_FN(MSIOF1_RXD_D),
- GPIO_FN(SS1_SDATA2_B),
- GPIO_FN(TS_SDEN0_D),
- GPIO_FN(STP_ISEN_0_D),
- GPIO_FN(RIF0_D0_C),
-
- GPIO_IFN(HTX0),
- GPIO_FN(MSIOF1_TXD_D),
- GPIO_FN(SSI_SDATA9_B),
- GPIO_FN(TS_SDAT0_D),
- GPIO_FN(STP_ISD_0_D),
- GPIO_FN(RIF0_D1_C),
-
- GPIO_IFN(HCTS0x),
- GPIO_FN(RX2_B),
- GPIO_FN(MSIOF1_SYNC_D),
- GPIO_FN(SSI_SCK9_A),
- GPIO_FN(TS_SPSYNC0_D),
- GPIO_FN(STP_ISSYNC_0_D),
- GPIO_FN(RIF0_SYNC_C),
- GPIO_FN(AUDIO_CLKOUT1_A),
-
- GPIO_IFN(HRTS0x),
- GPIO_FN(TX2_B),
- GPIO_FN(MSIOF1_SS1_D),
- GPIO_FN(SSI_WS9_A),
- GPIO_FN(STP_IVCXO27_0_D),
- GPIO_FN(BPFCLK_A),
- GPIO_FN(AUDIO_CLKOUT2_A),
-
- GPIO_IFN(MSIOF0_SYNC),
- GPIO_FN(AUDIO_CLKOUT_A),
- GPIO_FN(TX5_B),
- GPIO_FN(BPFCLK_D),
-
- /* IPSR14 */
- GPIO_IFN(MSIOF0_SS1),
- GPIO_FN(RX5_A),
- GPIO_FN(NFWPx_A),
- GPIO_FN(AUDIO_CLKA_C),
- GPIO_FN(SSI_SCK2_A),
- GPIO_FN(STP_IVCXO27_0_C),
- GPIO_FN(AUDIO_CLKOUT3_A),
- GPIO_FN(TCLK1_B),
-
- GPIO_IFN(MSIOF0_SS2),
- GPIO_FN(TX5_A),
- GPIO_FN(MSIOF1_SS2_D),
- GPIO_FN(AUDIO_CLKC_A),
- GPIO_FN(SSI_WS2_A),
- GPIO_FN(STP_OPWM_0_D),
- GPIO_FN(AUDIO_CLKOUT_D),
- GPIO_FN(SPEEDIN_B),
-
- GPIO_IFN(MLB_CLK),
- GPIO_FN(MSIOF1_SCK_F),
- GPIO_FN(SCL1_B),
-
- GPIO_IFN(MLB_SIG),
- GPIO_FN(RX1_B),
- GPIO_FN(MSIOF1_SYNC_F),
- GPIO_FN(SDA1_B),
-
- GPIO_IFN(MLB_DAT),
- GPIO_FN(TX1_B),
- GPIO_FN(MSIOF1_RXD_F),
-
- GPIO_IFN(SSI_SCK0129),
- GPIO_FN(MSIOF1_TXD_F),
- GPIO_FN(MOUT0),
-
- GPIO_IFN(SSI_WS0129),
- GPIO_FN(MSIOF1_SS1_F),
- GPIO_FN(MOUT1),
-
- GPIO_IFN(SSI_SDATA0),
- GPIO_FN(MSIOF1_SS2_F),
- GPIO_FN(MOUT2),
-
- /* IPSR15 */
- GPIO_IFN(SSI_SDATA1_A),
- GPIO_FN(MOUT5),
-
- GPIO_IFN(SSI_SDATA2_A),
- GPIO_FN(SSI_SCK1_B),
- GPIO_FN(MOUT6),
-
- GPIO_IFN(SSI_SCK34),
- GPIO_FN(MSIOF1_SS1_A),
- GPIO_FN(STP_OPWM_0_A),
-
- GPIO_IFN(SSI_WS34),
- GPIO_FN(HCTS2x_A),
- GPIO_FN(MSIOF1_SS2_A),
- GPIO_FN(STP_IVCXO27_0_A),
-
- GPIO_IFN(SSI_SDATA3),
- GPIO_FN(HRTS2x_A),
- GPIO_FN(MSIOF1_TXD_A),
- GPIO_FN(TS_SCK0_A),
- GPIO_FN(STP_ISCLK_0_A),
- GPIO_FN(RIF0_D1_A),
- GPIO_FN(RIF2_D0_A),
-
- GPIO_IFN(SSI_SCK4),
- GPIO_FN(HRX2_A),
- GPIO_FN(MSIOF1_SCK_A),
- GPIO_FN(TS_SDAT0_A),
- GPIO_FN(STP_ISD_0_A),
- GPIO_FN(RIF0_CLK_A),
- GPIO_FN(RIF2_CLK_A),
-
- GPIO_IFN(SSI_WS4),
- GPIO_FN(HTX2_A),
- GPIO_FN(MSIOF1_SYNC_A),
- GPIO_FN(TS_SDEN0_A),
- GPIO_FN(STP_ISEN_0_A),
- GPIO_FN(RIF0_SYNC_A),
- GPIO_FN(RIF2_SYNC_A),
-
- GPIO_IFN(SSI_SDATA4),
- GPIO_FN(HSCK2_A),
- GPIO_FN(MSIOF1_RXD_A),
- GPIO_FN(TS_SPSYNC0_A),
- GPIO_FN(STP_ISSYNC_0_A),
- GPIO_FN(RIF0_D0_A),
- GPIO_FN(RIF2_D1_A),
-
- /* IPSR16 */
- GPIO_IFN(SSI_SCK6),
- GPIO_FN(SIM0_RST_D),
- GPIO_FN(FSO_TOE_A),
-
- GPIO_IFN(SSI_WS6),
- GPIO_FN(SIM0_D_D),
-
- GPIO_IFN(SSI_SDATA6),
- GPIO_FN(SIM0_CLK_D),
-
- GPIO_IFN(SSI_SCK78),
- GPIO_FN(HRX2_B),
- GPIO_FN(MSIOF1_SCK_C),
- GPIO_FN(TS_SCK1_A),
- GPIO_FN(STP_ISCLK_1_A),
- GPIO_FN(RIF1_CLK_A),
- GPIO_FN(RIF3_CLK_A),
-
- GPIO_IFN(SSI_WS78),
- GPIO_FN(HTX2_B),
- GPIO_FN(MSIOF1_SYNC_C),
- GPIO_FN(TS_SDAT1_A),
- GPIO_FN(STP_ISD_1_A),
- GPIO_FN(RIF1_SYNC_A),
- GPIO_FN(RIF3_SYNC_A),
-
- GPIO_IFN(SSI_SDATA7),
- GPIO_FN(HCTS2x_B),
- GPIO_FN(MSIOF1_RXD_C),
- GPIO_FN(TS_SDEN1_A),
- GPIO_FN(STP_IEN_1_A),
- GPIO_FN(RIF1_D0_A),
- GPIO_FN(RIF3_D0_A),
- GPIO_FN(TCLK2_A),
-
- GPIO_IFN(SSI_SDATA8),
- GPIO_FN(HRTS2x_B),
- GPIO_FN(MSIOF1_TXD_C),
- GPIO_FN(TS_SPSYNC1_A),
- GPIO_FN(STP_ISSYNC_1_A),
- GPIO_FN(RIF1_D1_A),
- GPIO_FN(EIF3_D1_A),
-
- GPIO_IFN(SSI_SDATA9_A),
- GPIO_FN(HSCK2_B),
- GPIO_FN(MSIOF1_SS1_C),
- GPIO_FN(HSCK1_A),
- GPIO_FN(SSI_WS1_B),
- GPIO_FN(SCK1),
- GPIO_FN(STP_IVCXO27_1_A),
- GPIO_FN(SCK5),
-
- /* IPSR17 */
- GPIO_IFN(AUDIO_CLKA_A),
- GPIO_FN(CC5_OSCOUT),
-
- GPIO_IFN(AUDIO_CLKB_B),
- GPIO_FN(SCIF_CLK_A),
- GPIO_FN(STP_IVCXO27_1_D),
- GPIO_FN(REMOCON_A),
- GPIO_FN(TCLK1_A),
-
- GPIO_IFN(USB0_PWEN),
- GPIO_FN(SIM0_RST_C),
- GPIO_FN(TS_SCK1_D),
- GPIO_FN(STP_ISCLK_1_D),
- GPIO_FN(BPFCLK_B),
- GPIO_FN(RIF3_CLK_B),
- GPIO_FN(FSO_CFE_1_A),
- GPIO_FN(HSCK2_C),
-
- GPIO_IFN(USB0_OVC),
- GPIO_FN(SIM0_D_C),
- GPIO_FN(TS_SDAT1_D),
- GPIO_FN(STP_ISD_1_D),
- GPIO_FN(RIF3_SYNC_B),
- GPIO_FN(HRX2_C),
-
- GPIO_IFN(USB1_PWEN),
- GPIO_FN(SIM0_CLK_C),
- GPIO_FN(SSI_SCK1_A),
- GPIO_FN(TS_SCK0_E),
- GPIO_FN(STP_ISCLK_0_E),
- GPIO_FN(FMCLK_B),
- GPIO_FN(RIF2_CLK_B),
- GPIO_FN(SPEEDIN_A),
- GPIO_FN(HTX2_C),
-
- GPIO_IFN(USB1_OVC),
- GPIO_FN(MSIOF1_SS2_C),
- GPIO_FN(SSI_WS1_A),
- GPIO_FN(TS_SDAT0_E),
- GPIO_FN(STP_ISD_0_E),
- GPIO_FN(FMIN_B),
- GPIO_FN(RIF2_SYNC_B),
- GPIO_FN(REMOCON_B),
- GPIO_FN(HCTS2x_C),
-
- GPIO_IFN(USB30_PWEN),
- GPIO_FN(AUDIO_CLKOUT_B),
- GPIO_FN(SSI_SCK2_B),
- GPIO_FN(TS_SDEN1_D),
- GPIO_FN(STP_ISEN_1_D),
- GPIO_FN(STP_OPWM_0_E),
- GPIO_FN(RIF3_D0_B),
- GPIO_FN(TCLK2_B),
- GPIO_FN(TPU0TO0),
- GPIO_FN(BPFCLK_C),
- GPIO_FN(HRTS2x_C),
-
- GPIO_IFN(USB30_OVC),
- GPIO_FN(AUDIO_CLKOUT1_B),
- GPIO_FN(SSI_WS2_B),
- GPIO_FN(TS_SPSYNC1_D),
- GPIO_FN(STP_ISSYNC_1_D),
- GPIO_FN(STP_IVCXO27_0_E),
- GPIO_FN(RIF3_D1_B),
- GPIO_FN(FSO_TOE_B),
- GPIO_FN(TPU0TO1),
-
- /* IPSR18 */
- GPIO_IFN(GP6_30),
- GPIO_FN(AUDIO_CLKOUT2_B),
- GPIO_FN(SSI_SCK9_B),
- GPIO_FN(TS_SDEN0_E),
- GPIO_FN(STP_ISEN_0_E),
- GPIO_FN(RIF2_D0_B),
- GPIO_FN(FSO_CFE_0_A),
- GPIO_FN(TPU0TO2),
- GPIO_FN(FMCLK_C),
- GPIO_FN(FMCLK_D),
-
- GPIO_IFN(GP6_31),
- GPIO_FN(AUDIO_CLKOUT3_B),
- GPIO_FN(SSI_WS9_B),
- GPIO_FN(TS_SPSYNC0_E),
- GPIO_FN(STP_ISSYNC_0_E),
- GPIO_FN(RIF2_D1_B),
- GPIO_FN(TPU0TO3),
- GPIO_FN(FMIN_C),
- GPIO_FN(FMIN_D),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- /* GPSR0(0xE6060100) md[3:1] controls initial value */
- /* md[3:1] .. 0 : 0x0000FFFF */
- /* .. other : 0x00000000 */
- { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_0_15_FN, GFN_D15,
- GP_0_14_FN, GFN_D14,
- GP_0_13_FN, GFN_D13,
- GP_0_12_FN, GFN_D12,
- GP_0_11_FN, GFN_D11,
- GP_0_10_FN, GFN_D10,
- GP_0_9_FN, GFN_D9,
- GP_0_8_FN, GFN_D8,
- GP_0_7_FN, GFN_D7,
- GP_0_6_FN, GFN_D6,
- GP_0_5_FN, GFN_D5,
- GP_0_4_FN, GFN_D4,
- GP_0_3_FN, GFN_D3,
- GP_0_2_FN, GFN_D2,
- GP_0_1_FN, GFN_D1,
- GP_0_0_FN, GFN_D0 }
- },
- /* GPSR1(0xE6060104) is md[3:1] controls initial value */
- /* md[3:1] .. 0 : 0x0EFFFFFF */
- /* .. other : 0x00000000 */
- { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_28_FN, GFN_CLKOUT,
- GP_1_27_FN, GFN_EX_WAIT0_A,
- GP_1_26_FN, GFN_WE1x,
- GP_1_25_FN, GFN_WE0x,
- GP_1_24_FN, GFN_RD_WRx,
- GP_1_23_FN, GFN_RDx,
- GP_1_22_FN, GFN_BSx,
- GP_1_21_FN, GFN_CS1x_A26,
- GP_1_20_FN, GFN_CS0x,
- GP_1_19_FN, GFN_A19,
- GP_1_18_FN, GFN_A18,
- GP_1_17_FN, GFN_A17,
- GP_1_16_FN, GFN_A16,
- GP_1_15_FN, GFN_A15,
- GP_1_14_FN, GFN_A14,
- GP_1_13_FN, GFN_A13,
- GP_1_12_FN, GFN_A12,
- GP_1_11_FN, GFN_A11,
- GP_1_10_FN, GFN_A10,
- GP_1_9_FN, GFN_A9,
- GP_1_8_FN, GFN_A8,
- GP_1_7_FN, GFN_A7,
- GP_1_6_FN, GFN_A6,
- GP_1_5_FN, GFN_A5,
- GP_1_4_FN, GFN_A4,
- GP_1_3_FN, GFN_A3,
- GP_1_2_FN, GFN_A2,
- GP_1_1_FN, GFN_A1,
- GP_1_0_FN, GFN_A0 }
- },
- /* GPSR2(0xE6060108) is md[3:1] controls */
- /* md[3:1] .. 0 : 0x000003C0 */
- /* .. other : 0x00000200 */
- { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A,
- GP_2_13_FN, GFN_AVB_AVTP_MATCH_A,
- GP_2_12_FN, GFN_AVB_LINK,
- GP_2_11_FN, GFN_AVB_PHY_INT,
- GP_2_10_FN, GFN_AVB_MAGIC,
- GP_2_9_FN, GFN_AVB_MDC,
- GP_2_8_FN, GFN_PWM2_A,
- GP_2_7_FN, GFN_PWM1_A,
- GP_2_6_FN, GFN_PWM0,
- GP_2_5_FN, GFN_IRQ5,
- GP_2_4_FN, GFN_IRQ4,
- GP_2_3_FN, GFN_IRQ3,
- GP_2_2_FN, GFN_IRQ2,
- GP_2_1_FN, GFN_IRQ1,
- GP_2_0_FN, GFN_IRQ0 }
- },
-
- /* GPSR3 */
- { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_3_15_FN, GFN_SD1_WP,
- GP_3_14_FN, GFN_SD1_CD,
- GP_3_13_FN, GFN_SD0_WP,
- GP_3_12_FN, GFN_SD0_CD,
- GP_3_11_FN, GFN_SD1_DAT3,
- GP_3_10_FN, GFN_SD1_DAT2,
- GP_3_9_FN, GFN_SD1_DAT1,
- GP_3_8_FN, GFN_SD1_DAT0,
- GP_3_7_FN, GFN_SD1_CMD,
- GP_3_6_FN, GFN_SD1_CLK,
- GP_3_5_FN, GFN_SD0_DAT3,
- GP_3_4_FN, GFN_SD0_DAT2,
- GP_3_3_FN, GFN_SD0_DAT1,
- GP_3_2_FN, GFN_SD0_DAT0,
- GP_3_1_FN, GFN_SD0_CMD,
- GP_3_0_FN, GFN_SD0_CLK }
- },
- /* GPSR4 */
- { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_17_FN, GFN_SD3_DS,
- GP_4_16_FN, GFN_SD3_DAT7,
-
- GP_4_15_FN, GFN_SD3_DAT6,
- GP_4_14_FN, GFN_SD3_DAT5,
- GP_4_13_FN, GFN_SD3_DAT4,
- GP_4_12_FN, FN_SD3_DAT3,
- GP_4_11_FN, FN_SD3_DAT2,
- GP_4_10_FN, FN_SD3_DAT1,
- GP_4_9_FN, FN_SD3_DAT0,
- GP_4_8_FN, FN_SD3_CMD,
- GP_4_7_FN, FN_SD3_CLK,
- GP_4_6_FN, GFN_SD2_DS,
- GP_4_5_FN, GFN_SD2_DAT3,
- GP_4_4_FN, GFN_SD2_DAT2,
- GP_4_3_FN, GFN_SD2_DAT1,
- GP_4_2_FN, GFN_SD2_DAT0,
- GP_4_1_FN, FN_SD2_CMD,
- GP_4_0_FN, GFN_SD2_CLK }
- },
- /* GPSR5 */
- { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_25_FN, GFN_MLB_DAT,
- GP_5_24_FN, GFN_MLB_SIG,
-
- GP_5_23_FN, GFN_MLB_CLK,
- GP_5_22_FN, FN_MSIOF0_RXD,
- GP_5_21_FN, GFN_MSIOF0_SS2,
- GP_5_20_FN, FN_MSIOF0_TXD,
- GP_5_19_FN, GFN_MSIOF0_SS1,
- GP_5_18_FN, GFN_MSIOF0_SYNC,
- GP_5_17_FN, FN_MSIOF0_SCK,
- GP_5_16_FN, GFN_HRTS0x,
- GP_5_15_FN, GFN_HCTS0x,
- GP_5_14_FN, GFN_HTX0,
- GP_5_13_FN, GFN_HRX0,
- GP_5_12_FN, GFN_HSCK0,
- GP_5_11_FN, GFN_RX2_A,
- GP_5_10_FN, GFN_TX2_A,
- GP_5_9_FN, GFN_SCK2,
- GP_5_8_FN, GFN_RTS1x_TANS,
- GP_5_7_FN, GFN_CTS1x,
- GP_5_6_FN, GFN_TX1_A,
- GP_5_5_FN, GFN_RX1_A,
- GP_5_4_FN, GFN_RTS0x_TANS,
- GP_5_3_FN, GFN_CTS0x,
- GP_5_2_FN, GFN_TX0,
- GP_5_1_FN, GFN_RX0,
- GP_5_0_FN, GFN_SCK0 }
- },
- /* GPSR6 */
- { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
- GP_6_31_FN, GFN_GP6_31,
- GP_6_30_FN, GFN_GP6_30,
- GP_6_29_FN, GFN_USB30_OVC,
- GP_6_28_FN, GFN_USB30_PWEN,
- GP_6_27_FN, GFN_USB1_OVC,
- GP_6_26_FN, GFN_USB1_PWEN,
- GP_6_25_FN, GFN_USB0_OVC,
- GP_6_24_FN, GFN_USB0_PWEN,
- GP_6_23_FN, GFN_AUDIO_CLKB_B,
- GP_6_22_FN, GFN_AUDIO_CLKA_A,
- GP_6_21_FN, GFN_SSI_SDATA9_A,
- GP_6_20_FN, GFN_SSI_SDATA8,
- GP_6_19_FN, GFN_SSI_SDATA7,
- GP_6_18_FN, GFN_SSI_WS78,
- GP_6_17_FN, GFN_SSI_SCK78,
- GP_6_16_FN, GFN_SSI_SDATA6,
- GP_6_15_FN, GFN_SSI_WS6,
- GP_6_14_FN, GFN_SSI_SCK6,
- GP_6_13_FN, FN_SSI_SDATA5,
- GP_6_12_FN, FN_SSI_WS5,
- GP_6_11_FN, FN_SSI_SCK5,
- GP_6_10_FN, GFN_SSI_SDATA4,
- GP_6_9_FN, GFN_SSI_WS4,
- GP_6_8_FN, GFN_SSI_SCK4,
- GP_6_7_FN, GFN_SSI_SDATA3,
- GP_6_6_FN, GFN_SSI_WS34,
- GP_6_5_FN, GFN_SSI_SCK34,
- GP_6_4_FN, GFN_SSI_SDATA2_A,
- GP_6_3_FN, GFN_SSI_SDATA1_A,
- GP_6_2_FN, GFN_SSI_SDATA0,
- GP_6_1_FN, GFN_SSI_WS01239,
- GP_6_0_FN, GFN_SSI_SCK01239 }
- },
- /* GPSR7 */
- { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_3_FN, FN_HDMI1_CEC,
- GP_7_2_FN, FN_HDMI0_CEC,
- GP_7_1_FN, FN_AVS2,
- GP_7_0_FN, FN_AVS1 }
- },
- { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR0_31_28 [4] */
- IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,
- FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B,
- FN_MSIOF3_SS1_E,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_27_24 [4] */
- IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,
- FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B,
- FN_MSIOF3_SS2_E,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_23_20 [4] */
- IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_19_16 [4] */
- IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_15_12 [4] */
- IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_11_8 [4] */
- IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_7_4 [4] */
- IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR0_3_0 [4] */
- IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR1_31_28 [4] */
- IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,
- FN_VI4_DATA8, 0, FN_DU_DB0, 0,
- 0, FN_PWM3_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_27_24 [4] */
- IFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D,
- 0, 0, 0, 0,
- 0, FN_IETX_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_23_20 [4] */
- IFN_PWM1_A, 0, 0, FN_HRX3_D,
- FN_VI4_DATA7_B, 0, 0, 0,
- 0, FN_IERX_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_19_16 [4] */
- IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0,
- FN_VI4_DATA6_B, 0, 0, 0,
- 0, FN_IECLK_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_15_12 [4] */
- IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,
- FN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E,
- 0, FN_PWM6_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_11_8 [4] */
- IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,
- FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E,
- 0, FN_PWM5_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_7_4 [4] */
- IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,
- FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E,
- 0, FN_PWM4_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR1_3_0 [4] */
- IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
- FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E,
- 0, FN_PWM3_B, 0, 0,
- 0, 0, 0, 0
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR2_31_28 [4] */
- IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,
- 0, 0, 0, FN_SDA6_A,
- FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_27_24 [4] */
- IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,
- FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_23_20 [4] */
- IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,
- FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_19_16 [4] */
- IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,
- FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_15_12 [4] */
- IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,
- FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_11_8 [4] */
- IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,
- FN_VI4_DATA11, 0, FN_DU_DB3, 0,
- 0, FN_PWM6_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_7_4 [4] */
- IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,
- FN_VI4_DATA10, 0, FN_DU_DB2, 0,
- 0, FN_PWM5_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR2_3_0 [4] */
- IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,
- FN_VI4_DATA9, 0, FN_DU_DB1, 0,
- 0, FN_PWM4_A, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR3_31_28 [4] */
- IFN_A16, FN_LCDOUT8, 0, 0,
- FN_VI4_FIELD, 0, FN_DU_DG0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_27_24 [4] */
- IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,
- FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_23_20 [4] */
- IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,
- FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_19_16 [4] */
- IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,
- FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_15_12 [4] */
- IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,
- FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_11_8 [4] */
- IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,
- FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,
- FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0,
- 0, 0, 0, 0,
- /* IPSR3_7_4 [4] */
- IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,
- 0, FN_VI5_HSYNCx, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR3_3_0 [4] */
- IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B,
- 0, FN_VI5_VSYNCx, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR4_31_28 [4] */
- IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A,
- FN_HTX3_A, 0, 0, 0,
- FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_27_24 [4] */
- IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,
- FN_HRX3_A, 0, 0, 0,
- FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_23_20 [4] */
- IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,
- FN_HSCK3, 0, 0, 0,
- FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,
- 0, 0, 0, 0,
- /* IPSR4_19_16 [4] */
- IFN_CS1x_A26, 0, 0, 0,
- 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_15_12 [4] */
- IFN_CS0x, 0, 0, 0,
- 0, FN_VI5_CLKENB, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_11_8 [4] */
- IFN_A19, FN_LCDOUT11, 0, 0,
- FN_VI4_CLKENB, 0, FN_DU_DG3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_7_4 [4] */
- IFN_A18, FN_LCDOUT10, 0, 0,
- FN_VI4_HSYNCx, 0, FN_DU_DG2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR4_3_0 [4] */
- IFN_A17, FN_LCDOUT9, 0, 0,
- FN_VI4_VSYNCx, 0, FN_DU_DG1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR5_31_28 [4] */
- IFN_D4, FN_MSIOF2_SCK_B, 0, 0,
- FN_VI4_DATA20, FN_VI5_DATA4, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_27_24 [4] */
- IFN_D3, 0, FN_MSIOF3_TXD_A, 0,
- FN_VI4_DATA19, FN_VI5_DATA3, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_23_20 [4] */
- IFN_D2, 0, FN_MSIOF3_RXD_A, 0,
- FN_VI4_DATA18, FN_VI5_DATA2, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_19_16 [4] */
- IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,
- FN_VI4_DATA17, FN_VI5_DATA1, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_15_12 [4] */
- IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,
- FN_VI4_DATA16, FN_VI5_DATA0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_11_8 [4] */
- IFN_EX_WAIT0_A, FN_QCLK, 0, 0,
- FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR5_7_4 [4] */
- IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS,
- FN_HRTS3x, 0, 0, FN_SDA6_B,
- FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,
- 0, 0, 0, 0,
- /* IPSR5_3_0 [4] */
- IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x,
- FN_HCTS3x, 0, 0, FN_SCL6_B,
- FN_CAN_CLK, 0, FN_IECLK_A, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR6_31_28 [4] */
- IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,
- FN_VI4_DATA4_A, 0, FN_DU_DR4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_27_24 [4] */
- IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,
- FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_23_20 [4] */
- IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,
- FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_19_16 [4] */
- IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,
- FN_VI4_DATA1_A, 0, FN_DU_DR1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_15_12 [4] */
- IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,
- FN_VI4_DATA0_A, 0, FN_DU_DR0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_11_8 [4] */
- IFN_D7, FN_MSIOF2_TXD_B, 0, 0,
- FN_VI4_DATA23, FN_VI5_DATA7, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_7_4 [4] */
- IFN_D6, FN_MSIOF2_RXD_B, 0, 0,
- FN_VI4_DATA22, FN_VI5_DATA6, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR6_3_0 [4] */
- IFN_D5, FN_MSIOF2_SYNC_B, 0, 0,
- FN_VI4_DATA21, FN_VI5_DATA5, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR7_31_28 [4] */
- IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,
- 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_27_24 [4] */
- IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,
- 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_23_20 [4] */
- IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,
- 0, 0, FN_STP_IVCXO27_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_19_16 [4] */
- IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,
- 0, 0, FN_STP_OPWM_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_15_12 [4] */
- FN_FSCLKST, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_11_8 [4] */
- IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,
- FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_7_4 [4] */
- IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,
- FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR7_3_0 [4] */
- IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,
- FN_VI4_DATA5_A, 0, FN_DU_DR5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR8_31_28 [4] */
- IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G,
- FN_NFRBx_B,
- 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_27_24 [4] */
- IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G,
- FN_NFDATA15_B,
- 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_23_20 [4] */
- IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G,
- FN_NFDATA14_B,
- 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_19_16 [4] */
- IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G,
- FN_NFWPx_B,
- 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_15_12 [4] */
- IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G,
- FN_NFCEx_B,
- 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_11_8 [4] */
- IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,
- 0, FN_SIM0_CLK_A, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_7_4 [4] */
- IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,
- 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR8_3_0 [4] */
- IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,
- 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR9_31_28 [4] */
- IFN_SD3_CLK, 0, FN_NFWEx, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_27_24 [4] */
- IFN_SD2_DS, 0, FN_NFALE, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_23_20 [4] */
- IFN_SD2_DAT3, 0, FN_NFDATA13, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_19_16 [4] */
- IFN_SD2_DAT2, 0, FN_NFDATA12, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_15_12 [4] */
- IFN_SD2_DAT1, 0, FN_NFDATA11, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_11_8 [4] */
- IFN_SD2_DAT0, 0, FN_NFDATA10, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_7_4 [4] */
- IFN_SD2_CMD, 0, FN_NFDATA9, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR9_3_0 [4] */
- IFN_SD3_CLK, 0, FN_NFDATA8, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR10_31_28 [4] */
- IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_27_24 [4] */
- IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_23_20 [4] */
- IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_19_16 [4] */
- IFN_SD3_DAT3, 0, FN_NFDATA3, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_15_12 [4] */
- IFN_SD3_DAT2, 0, FN_NFDATA2, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_11_8 [4] */
- IFN_SD3_DAT1, 0, FN_NFDATA1, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_7_4 [4] */
- IFN_SD3_DAT0, 0, FN_NFDATA0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR10_3_0 [4] */
- IFN_SD3_CMD, 0, FN_NFREx, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR11_31_28 [4] */
- IFN_RX0, FN_HRX1_B, 0, 0,
- 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_27_24 [4] */
- IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
- FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C,
- FN_RIF0_CLK_B,
- 0, FN_ADICHS2, 0, FN_RIF0_CLK_B,
- 0, 0, 0, 0,
- /* IPSR11_23_20 [4] */
- IFN_SD1_WP, 0, FN_NFCEx_A, 0,
- 0, FN_SIM0_D_B, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_19_16 [4] */
- IFN_SD1_CD, 0, FN_NFRBx_A, 0,
- 0, FN_SIM0_CLK_B, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_15_12 [4] */
- IFN_SD0_WP, 0, FN_NFDATA15_A, 0,
- FN_SDA2_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_11_8 [4] */
- IFN_SD0_CD, 0, FN_NFDATA14_A, 0,
- FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_7_4 [4] */
- IFN_SD3_DS, 0, FN_NFCLE, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR11_3_0 [4] */
- IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR12_31_28 [4] */
- IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,
- 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
- 0, FN_ADICLK, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_27_24 [4] */
- IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,
- 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,
- 0, FN_ADICHS0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_23_20 [4] */
- IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,
- 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,
- 0, FN_ADIDATA, 0, 0,
- /* IPSR12_19_16 [4] */
- IFN_TX1_A, FN_HTX1_A, 0, 0,
- 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_15_12 [4] */
- IFN_RX1_A, FN_HRX1_A, 0, 0,
- 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_11_8 [4] */
- IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,
- FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,
- 0, FN_ADICHS1, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_7_4 [4] */
- IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,
- 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
- FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,
- 0, 0, 0, 0,
- /* IPSR12_3_0 [4] */
- IFN_TX0, FN_HTX1_B, 0, 0,
- 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR13_31_28 [4] */
- IFN_MSIOF0_SYNC, 0, 0, 0,
- 0, 0, 0, 0,
- FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0,
- 0, FN_BPFCLK_D, 0, 0,
- /* IPSR13_27_24 [4] */
- IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,
- FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,
- FN_AUDIO_CLKOUT2_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_23_20 [4] */
- IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,
- FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D,
- FN_RIF0_SYNC_C,
- FN_AUDIO_CLKOUT1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_19_16 [4] */
- IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,
- FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_15_12 [4] */
- IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,
- FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_11_8 [4] */
- IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,
- FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,
- 0, 0, FN_RX5_B, 0,
- 0, 0, 0, 0,
- /* IPSR13_7_4 [4] */
- IFN_RX2_A, 0, 0, FN_SD2_WP_B,
- FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,
- 0, FN_FSO_CEF_1_B, 0, 0,
- 0, 0, 0, 0,
- /* IPSR13_3_0 [4] */
- IFN_TX2_A, 0, 0, FN_SD2_CD_B,
- FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,
- 0, FN_FSO_CFE_0_B, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR14_31_28 [4] */
- IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,
- 0, 0, 0, FN_MOUT2,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_27_24 [4] */
- IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0,
- 0, 0, 0, FN_MOUT1,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_23_20 [4] */
- IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0,
- 0, 0, 0, FN_MOUT0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_19_16 [4] */
- IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_15_12 [4] */
- IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,
- FN_SDA1_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_11_8 [4] */
- IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,
- FN_SCL1_B, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR14_7_4 [4] */
- IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
- FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,
- FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,
- /* IPSR14_3_0 [4] */
- IFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C,
- FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,
- FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR15_31_28 [4] */
- IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,
- 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,
- FN_RIF2_D1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_27_24 [4] */
- IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,
- 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,
- FN_RIF2_SYNC_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_23_20 [4] */
- IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,
- 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
- FN_RIF2_CLK_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_19_16 [4] */
- IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,
- 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,
- FN_RIF2_D0_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_15_12 [4] */
- IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,
- 0, 0, FN_STP_IVCXO27_0_A, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_11_8 [4] */
- IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,
- 0, 0, FN_STP_OPWM_0_A, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_7_4 [4] */
- IFN_SSI_SDATA2_A, 0, 0, 0,
- FN_SSI_SCK1_B, 0, 0, FN_MOUT6,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR15_3_0 [4] */
- IFN_SSI_SDATA1_A, 0, 0, 0,
- 0, 0, 0, FN_MOUT5,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR16_31_28 [4] */
- IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,
- FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_27_24 [4] */
- IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,
- 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,
- FN_EIF3_D1_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_23_20 [4] */
- IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,
- 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A,
- FN_RIF3_D0_A, 0, FN_TCLK2_A, 0,
- /* IPSR16_19_16 [4] */
- IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,
- 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
- FN_RIF3_SYNC_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_15_12 [4] */
- IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,
- 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,
- FN_RIF3_CLK_A, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_11_8 [4] */
- IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_7_4 [4] */
- IFN_SSI_WS6, 0, 0, FN_SIM0_D_D,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- /* IPSR16_3_0 [4] */
- IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D,
- 0, 0, 0, 0,
- 0, 0, FN_FSO_TOE_A, 0,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
- 4, 4, 4, 4, 4, 4, 4, 4) {
- /* IPSR17_31_28 [4] */
- IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0,
- FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D,
- FN_STP_IVCXO27_0_E,
- FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1,
- 0, 0, 0, 0,
- /* IPSR17_27_24 [4] */
- IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,
- FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
- FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,
- FN_BPFCLK_C, FN_HRTS2x_C, 0, 0,
- /* IPSR17_23_20 [4] */
- IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,
- FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
- FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,
- 0, FN_HCTS2x_C, 0, 0,
- /* IPSR17_19_16 [4] */
- IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,
- FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
- FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,
- 0, FN_HTX2_C, 0, 0,
- /* IPSR17_15_12 [4] */
- IFN_USB0_OVC, 0, 0, FN_SIM0_D_C,
- 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,
- FN_RIF3_SYNC_B, 0, 0, 0,
- 0, FN_HRX2_C, 0, 0,
- /* IPSR17_11_8 [4] */
- IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,
- 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
- FN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0,
- 0, FN_HSCK2_C, 0, 0,
- /* IPSR17_7_4 [4] */
- IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,
- 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
- 0, 0, FN_TCLK1_A, 0,
- 0, 0, 0, 0,
- /* IPSR17_3_0 [4] */
- IFN_AUDIO_CLKA_A, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, FN_CC5_OSCOUT,
- 0, 0, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 4, 4) {
- /* reserved [31..24] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* reserved [23..16] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* reserved [15..8] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* IPSR18_7_4 [4] */
- IFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B,
- FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,
- FN_RIF2_D1_B, 0, 0, FN_TPU0TO3,
- FN_FMIN_C, FN_FMIN_D, 0, 0,
- /* IPSR18_3_0 [4] */
- IFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B,
- FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
- FN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2,
- FN_FMCLK_C, FN_FMCLK_D, 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32,
- 3, 2, 3,
- 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2,
- 2, 1, 2, 1, 1, 1) {
- /* SEL_MSIOF3 [3] */
- FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
- FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
- FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5,
- FN_SEL_MSIOF3_6, 0,
- /* SEL_MSIOF2 [2] */
- FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
- FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
- /* SEL_MSIOF1 [3] */
- FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
- FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
- FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
- FN_SEL_MSIOF1_6, 0,
-
- /* SEL_LBSC [1] */
- FN_SEL_LBSC_0, FN_SEL_LBSC_1,
- /* SEL_IEBUS [1] */
- FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
- /* SEL_I2C2 [1] */
- FN_SEL_I2C2_0, FN_SEL_I2C2_1,
- /* SEL_I2C1 [1] */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1,
- /* SEL_HSCIF4 [1] */
- FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
- /* SEL_HSCIF3 [2] */
- FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
- FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
- /* SEL_HSCIF1 [1] */
- FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
-
- /* SEL_FSO [1] */
- FN_SEL_FSO_0, FN_SEL_FSO_1,
- /* SEL_HSCIF2 [2] */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, 0,
- /* SEL_ETHERAVB [1] */
- FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
- /* SEL_DRIF3 [1] */
- FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
- /* SEL_DRIF2 [1] */
- FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
- /* SEL_DRIF1 [2] */
- FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
- FN_SEL_DRIF1_2, 0,
-
- /* SEL_DRIF0 [2] */
- FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
- FN_SEL_DRIF0_2, 0,
- /* SEL_CANFD0 [1] */
- FN_SEL_CANFD_0, FN_SEL_CANFD_1,
- /* SEL_ADG [2] */
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_ADG_2, FN_SEL_ADG_3,
- /* reserved [3] */
- 0, 0,
- 0, 0,
- 0, 0,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32,
- 2, 3, 1, 2,
- 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
- /* SEL_TSIF1 [2] */
- FN_SEL_TSIF1_0,
- FN_SEL_TSIF1_1,
- FN_SEL_TSIF1_2,
- FN_SEL_TSIF1_3,
- /* SEL_TSIF0 [3] */
- FN_SEL_TSIF0_0,
- FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2,
- FN_SEL_TSIF0_3,
- FN_SEL_TSIF0_4,
- 0,
- 0,
- 0,
- /* SEL_TIMER_TMU [1] */
- FN_SEL_TIMER_TMU_0,
- FN_SEL_TIMER_TMU_1,
- /* SEL_SSP1_1 [2] */
- FN_SEL_SSP1_1_0,
- FN_SEL_SSP1_1_1,
- FN_SEL_SSP1_1_2,
- FN_SEL_SSP1_1_3,
-
- /* SEL_SSP1_0 [3] */
- FN_SEL_SSP1_0_0,
- FN_SEL_SSP1_0_1,
- FN_SEL_SSP1_0_2,
- FN_SEL_SSP1_0_3,
- FN_SEL_SSP1_0_4,
- 0,
- 0,
- 0,
- /* SEL_SSI [1] */
- FN_SEL_SSI_0,
- FN_SEL_SSI_1,
- /* SEL_SPEED_PULSE_IF [1] */
- FN_SEL_SPEED_PULSE_IF_0,
- FN_SEL_SPEED_PULSE_IF_1,
- /* SEL_SIMCARD [2] */
- FN_SEL_SIMCARD_0,
- FN_SEL_SIMCARD_1,
- FN_SEL_SIMCARD_2,
- FN_SEL_SIMCARD_3,
- /* SEL_SDHI2 [1] */
- FN_SEL_SDHI2_0,
- FN_SEL_SDHI2_1,
-
- /* SEL_SCIF4 [2] */
- FN_SEL_SCIF4_0,
- FN_SEL_SCIF4_1,
- FN_SEL_SCIF4_2,
- 0,
- /* SEL_SCIF3 [1] */
- FN_SEL_SCIF3_0,
- FN_SEL_SCIF3_1,
- /* SEL_SCIF2 [1] */
- FN_SEL_SCIF2_0,
- FN_SEL_SCIF2_1,
- /* SEL_SCIF1 [1] */
- FN_SEL_SCIF1_0,
- FN_SEL_SCIF1_1,
- /* SEL_SCIF [1] */
- FN_SEL_SCIF_0,
- FN_SEL_SCIF_1,
- /* SEL_REMOCON [1] */
- FN_SEL_REMOCON_0,
- FN_SEL_REMOCON_1,
- /* reserved [2] */
- 0, 0,
-
- 0, 0,
- /* SEL_RCAN [1] */
- FN_SEL_RCAN_0,
- FN_SEL_RCAN_1,
- /* SEL_PWM6 [1] */
- FN_SEL_PWM6_0,
- FN_SEL_PWM6_1,
- /* SEL_PWM5 [1] */
- FN_SEL_PWM5_0,
- FN_SEL_PWM5_1,
- /* SEL_PWM4 [1] */
- FN_SEL_PWM4_0,
- FN_SEL_PWM4_1,
- /* SEL_PWM3 [1] */
- FN_SEL_PWM3_0,
- FN_SEL_PWM3_1,
- /* SEL_PWM2 [1] */
- FN_SEL_PWM2_0,
- FN_SEL_PWM2_1,
- /* SEL_PWM1 [1] */
- FN_SEL_PWM1_0,
- FN_SEL_PWM1_1,
- }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32,
- 1, 1, 1, 2, 1,
- 3, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1) {
- /* I2C_SEL_5 [1] */
- FN_I2C_SEL_5_0,
- FN_I2C_SEL_5_1,
- /* I2C_SEL_3 [1] */
- FN_I2C_SEL_3_0,
- FN_I2C_SEL_3_1,
- /* I2C_SEL_0 [1] */
- FN_I2C_SEL_0_0,
- FN_I2C_SEL_0_1,
- /* SEL_FM [2] */
- FN_SEL_FM_0,
- FN_SEL_FM_1,
- FN_SEL_FM_2,
- FN_SEL_FM_3,
- /* SEL_SCIF5 [1] */
- FN_SEL_SCIF5_0,
- FN_SEL_SCIF5_1,
-
- /* SEL_I2C6 [3] */
- FN_SEL_I2C6_0,
- FN_SEL_I2C6_1,
- FN_SEL_I2C6_2,
- 0,
- 0,
- 0,
- 0,
- 0,
- /* SEL_NDF [1] */
- FN_SEL_NDF_0,
- FN_SEL_NDF_1,
- /* SEL_SSI2 [1] */
- FN_SEL_SSI2_0,
- FN_SEL_SSI2_1,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0,
- FN_SEL_SSI9_1,
- /* SEL_TIMER_TME2 [1] */
- FN_SEL_TIMER_TMU2_0,
- FN_SEL_TIMER_TMU2_1,
- /* SEL_ADG_B [1] */
- FN_SEL_ADG_B_0,
- FN_SEL_ADG_B_1,
-
- /* SEL_ADG_C [1] */
- FN_SEL_ADG_C_0,
- FN_SEL_ADG_C_1,
- /* reserved [16] */
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- /* SEL_VIN4 [1] */
- FN_SEL_VIN4_0,
- FN_SEL_VIN4_1,
- }
- },
-
- /* under construction */
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_0_15_IN, GP_0_15_OUT,
- GP_0_14_IN, GP_0_14_OUT,
- GP_0_13_IN, GP_0_13_OUT,
- GP_0_12_IN, GP_0_12_OUT,
- GP_0_11_IN, GP_0_11_OUT,
- GP_0_10_IN, GP_0_10_OUT,
- GP_0_9_IN, GP_0_9_OUT,
- GP_0_8_IN, GP_0_8_OUT,
- GP_0_7_IN, GP_0_7_OUT,
- GP_0_6_IN, GP_0_6_OUT,
- GP_0_5_IN, GP_0_5_OUT,
- GP_0_4_IN, GP_0_4_OUT,
- GP_0_3_IN, GP_0_3_OUT,
- GP_0_2_IN, GP_0_2_OUT,
- GP_0_1_IN, GP_0_1_OUT,
- GP_0_0_IN, GP_0_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_28_IN, GP_1_28_OUT,
- GP_1_27_IN, GP_1_27_OUT,
- GP_1_26_IN, GP_1_26_OUT,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- GP_2_14_IN, GP_2_14_OUT,
- GP_2_13_IN, GP_2_13_OUT,
- GP_2_12_IN, GP_2_12_OUT,
- GP_2_11_IN, GP_2_11_OUT,
- GP_2_10_IN, GP_2_10_OUT,
- GP_2_9_IN, GP_2_9_OUT,
- GP_2_8_IN, GP_2_8_OUT,
- GP_2_7_IN, GP_2_7_OUT,
- GP_2_6_IN, GP_2_6_OUT,
- GP_2_5_IN, GP_2_5_OUT,
- GP_2_4_IN, GP_2_4_OUT,
- GP_2_3_IN, GP_2_3_OUT,
- GP_2_2_IN, GP_2_2_OUT,
- GP_2_1_IN, GP_2_1_OUT,
- GP_2_0_IN, GP_2_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- GP_3_15_IN, GP_3_15_OUT,
- GP_3_14_IN, GP_3_14_OUT,
- GP_3_13_IN, GP_3_13_OUT,
- GP_3_12_IN, GP_3_12_OUT,
- GP_3_11_IN, GP_3_11_OUT,
- GP_3_10_IN, GP_3_10_OUT,
- GP_3_9_IN, GP_3_9_OUT,
- GP_3_8_IN, GP_3_8_OUT,
- GP_3_7_IN, GP_3_7_OUT,
- GP_3_6_IN, GP_3_6_OUT,
- GP_3_5_IN, GP_3_5_OUT,
- GP_3_4_IN, GP_3_4_OUT,
- GP_3_3_IN, GP_3_3_OUT,
- GP_3_2_IN, GP_3_2_OUT,
- GP_3_1_IN, GP_3_1_OUT,
- GP_3_0_IN, GP_3_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_17_IN, GP_4_17_OUT,
- GP_4_16_IN, GP_4_16_OUT,
-
- GP_4_15_IN, GP_4_15_OUT,
- GP_4_14_IN, GP_4_14_OUT,
- GP_4_13_IN, GP_4_13_OUT,
- GP_4_12_IN, GP_4_12_OUT,
- GP_4_11_IN, GP_4_11_OUT,
- GP_4_10_IN, GP_4_10_OUT,
- GP_4_9_IN, GP_4_9_OUT,
- GP_4_8_IN, GP_4_8_OUT,
- GP_4_7_IN, GP_4_7_OUT,
- GP_4_6_IN, GP_4_6_OUT,
- GP_4_5_IN, GP_4_5_OUT,
- GP_4_4_IN, GP_4_4_OUT,
- GP_4_3_IN, GP_4_3_OUT,
- GP_4_2_IN, GP_4_2_OUT,
- GP_4_1_IN, GP_4_1_OUT,
- GP_4_0_IN, GP_4_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_25_IN, GP_5_25_OUT,
- GP_5_24_IN, GP_5_24_OUT,
-
- GP_5_23_IN, GP_5_23_OUT,
- GP_5_22_IN, GP_5_22_OUT,
- GP_5_21_IN, GP_5_21_OUT,
- GP_5_20_IN, GP_5_20_OUT,
- GP_5_19_IN, GP_5_19_OUT,
- GP_5_18_IN, GP_5_18_OUT,
- GP_5_17_IN, GP_5_17_OUT,
- GP_5_16_IN, GP_5_16_OUT,
-
- GP_5_15_IN, GP_5_15_OUT,
- GP_5_14_IN, GP_5_14_OUT,
- GP_5_13_IN, GP_5_13_OUT,
- GP_5_12_IN, GP_5_12_OUT,
- GP_5_11_IN, GP_5_11_OUT,
- GP_5_10_IN, GP_5_10_OUT,
- GP_5_9_IN, GP_5_9_OUT,
- GP_5_8_IN, GP_5_8_OUT,
- GP_5_7_IN, GP_5_7_OUT,
- GP_5_6_IN, GP_5_6_OUT,
- GP_5_5_IN, GP_5_5_OUT,
- GP_5_4_IN, GP_5_4_OUT,
- GP_5_3_IN, GP_5_3_OUT,
- GP_5_2_IN, GP_5_2_OUT,
- GP_5_1_IN, GP_5_1_OUT,
- GP_5_0_IN, GP_5_0_OUT,
- }
- },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
- GP_INOUTSEL(6)
- }
- },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
-
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT,
- }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- /* use OUTDT registers? */
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
- GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
- GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
- GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
- },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, GP_1_28_DATA,
- GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
- GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
- GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
- GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
- },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
- GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
- GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
- GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
- },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA,
- GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
- GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
- GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
- GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
- },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_5_25_DATA, GP_5_24_DATA,
- GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
- GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
- GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
- GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
- GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
- GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
- },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
- GP_INDT(6) }
- },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7796_pinmux_info = {
- .name = "r8a7796_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_FMIN_D,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7796_pinmux_init(void)
-{
- register_pinmux(&r8a7796_pinmux_info);
-}
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK3128
+ bool "Support Rockchip RK3128"
+ select CPU_V7
+ help
+ The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
- select SUPPORT_TPL
select SPL
- select TPL
+ select SPL_CLK
+ select SPL_PINCTRL
+ select SPL_REGMAP
+ select SPL_SYSCON
+ select SPL_RAM
+ select SPL_DRIVERS_MISC_SUPPORT
+ select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
help
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select SPL_DRIVERS_MISC_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
+ select BOARD_LATE_INIT
+ select ROCKCHIP_BROM_HELPER
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
+config ROCKCHIP_BOOT_MODE_REG
+ hex "Rockchip boot mode flag register address"
+ default 0x200081c8 if ROCKCHIP_RK3036
+ default 0x20004040 if ROCKCHIP_RK3188
+ default 0x110005c8 if ROCKCHIP_RK322X
+ default 0xff730094 if ROCKCHIP_RK3288
+ default 0xff738200 if ROCKCHIP_RK3368
+ default 0xff320300 if ROCKCHIP_RK3399
+ default 0x10300580 if ROCKCHIP_RV1108
+ default 0
+ help
+ The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
+ according to the value from this register.
+
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
- default 0x4000
+ default 0
help
SPL may need reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlay with SPL text area if not
config ROCKCHIP_BROM_HELPER
bool
+config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
+ bool "SPL requires early-return (for RK3188-style BROM) to BROM"
+ depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
+ help
+ Some Rockchip BROM variants (e.g. on the RK3188) load the
+ first stage in segments and enter multiple times. E.g. on
+ the RK3188, the first 1KB of the first stage are loaded
+ first and entered; after returning to the BROM, the
+ remainder of the first stage is loaded, but the BROM
+ re-enters at the same address/to the same code as previously.
+
+ This enables support code in the BOOT0 hook for the SPL stage
+ to allow multiple entries.
+
+config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
+ bool "TPL requires early-return (for RK3188-style BROM) to BROM"
+ depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
+ help
+ Some Rockchip BROM variants (e.g. on the RK3188) load the
+ first stage in segments and enter multiple times. E.g. on
+ the RK3188, the first 1KB of the first stage are loaded
+ first and entered; after returning to the BROM, the
+ remainder of the first stage is loaded, but the BROM
+ re-enters at the same address/to the same code as previously.
+
+ This enables support code in the BOOT0 hook for the TPL stage
+ to allow multiple entries.
+
config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
# this may have entered from ATF with the stack-pointer pointing to
# inaccessible/protected memory (and the bootrom-helper assumes that
# the stack-pointer is valid before switching to the U-Boot stack).
-obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
-obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+
+# Always include boot_mode.o, as we bypass it (i.e. turn it off)
+# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
+# we can have the preprocessor correctly recognise both 0x0 and 0
+# meaning "turn it off".
+obj-y += boot_mode.o
+
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
+obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
--- /dev/null
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/io.h>
+#include <asm/arch/boot_mode.h>
+
+#if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0)
+
+int setup_boot_mode(void)
+{
+ return 0;
+}
+
+#else
+
+void set_back_to_bootrom_dnl_flag(void)
+{
+ writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+}
+
+/*
+ * detect download key status by adc, most rockchip
+ * based boards use adc sample the download key status,
+ * but there are also some use gpio. So it's better to
+ * make this a weak function that can be override by
+ * some special boards.
+ */
+#define KEY_DOWN_MIN_VAL 0
+#define KEY_DOWN_MAX_VAL 30
+
+__weak int rockchip_dnl_key_pressed(void)
+{
+ unsigned int val;
+
+ if (adc_channel_single_shot("saradc", 1, &val)) {
+ pr_err("%s: adc_channel_single_shot fail!\n", __func__);
+ return false;
+ }
+
+ if ((val >= KEY_DOWN_MIN_VAL) && (val <= KEY_DOWN_MAX_VAL))
+ return true;
+ else
+ return false;
+}
+
+void rockchip_dnl_mode_check(void)
+{
+ if (rockchip_dnl_key_pressed()) {
+ printf("download key pressed, entering download mode...");
+ set_back_to_bootrom_dnl_flag();
+ do_reset(NULL, 0, 0, NULL);
+ }
+}
+
+int setup_boot_mode(void)
+{
+ void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG;
+ int boot_mode = readl(reg);
+
+ rockchip_dnl_mode_check();
+
+ boot_mode = readl(reg);
+ debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, reg);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ debug("%s: enter fastboot!\n", __func__);
+ env_set("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ debug("%s: enter UMS!\n", __func__);
+ env_set("preboot", "setenv preboot; ums mmc 0");
+ break;
+ }
+
+ return 0;
+}
+
+#endif
#include <common.h>
#include <asm/arch/bootrom.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/io.h>
+#include <asm/setjmp.h>
+#include <asm/system.h>
-void back_to_bootrom(void)
+/*
+ * Force the jmp_buf to the data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+static jmp_buf brom_ctx __section(".data");
+
+static void _back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd)
+{
+ longjmp(brom_ctx, brom_cmd);
+}
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd)
{
#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)
puts("Returning to boot ROM...\n");
#endif
- _back_to_bootrom_s();
+ _back_to_bootrom(brom_cmd);
+}
+
+/*
+ * we back to bootrom download mode if get a
+ * BOOT_BROM_DOWNLOAD flag in boot mode register
+ *
+ * note: the boot mode register is configured by
+ * application(next stage bootloader, kernel, etc),
+ * and the bootrom never check this register, so we need
+ * to check it and back to bootrom at very early bootstage(before
+ * some basic configurations(such as interrupts) been
+ * changed by TPL/SPL, as the bootrom download operation
+ * relys on many default settings(such as interrupts) by
+ * it's self.
+ */
+static bool check_back_to_brom_dnl_flag(void)
+{
+ u32 boot_mode;
+
+ if (CONFIG_ROCKCHIP_BOOT_MODE_REG) {
+ boot_mode = readl(CONFIG_ROCKCHIP_BOOT_MODE_REG);
+ if (boot_mode == BOOT_BROM_DOWNLOAD) {
+ writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*
+ * All Rockchip BROM implementations enter with a valid stack-pointer,
+ * so this can safely be implemented in C (providing a single
+ * implementation both for ARMv7 and AArch64).
+ */
+int save_boot_params(void)
+{
+ int ret = setjmp(brom_ctx);
+
+ switch (ret) {
+ case 0:
+ if (check_back_to_brom_dnl_flag())
+ _back_to_bootrom(BROM_BOOT_ENTER_DNL);
+ /*
+ * This is the initial pass through this function
+ * (i.e. saving the context), setjmp just setup up the
+ * brom_ctx: transfer back into the startup-code at
+ * 'save_boot_params_ret' and let the compiler know
+ * that this will not return.
+ */
+ save_boot_params_ret();
+ while (true)
+ /* does not return */;
+ break;
+
+ case BROM_BOOT_NEXTSTAGE:
+ /*
+ * To instruct the BROM to boot the next stage, we
+ * need to return 0 to it: i.e. we need to rewrite
+ * the return code once more.
+ */
+ ret = 0;
+ break;
+ case BROM_BOOT_ENTER_DNL:
+ /*
+ * A non-zero return value will instruct the BROM enter
+ * download mode.
+ */
+ ret = 1;
+ break;
+ default:
+#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)
+ puts("FATAL: unexpected command to back_to_bootrom()\n");
+#endif
+ hang();
+ };
+
+ return ret;
}
--- /dev/null
+#!/usr/bin/env python2
+"""
+A script to generate FIT image source for rockchip boards
+with ARM Trusted Firmware
+and multiple device trees (given on the command line)
+
+usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+"""
+
+import os
+import sys
+import getopt
+
+# pip install pyelftools
+from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import SymbolTableSection
+from elftools.elf.segments import Segment, InterpSegment, NoteSegment
+
+ELF_SEG_P_TYPE='p_type'
+ELF_SEG_P_PADDR='p_paddr'
+ELF_SEG_P_VADDR='p_vaddr'
+ELF_SEG_P_OFFSET='p_offset'
+ELF_SEG_P_FILESZ='p_filesz'
+ELF_SEG_P_MEMSZ='p_memsz'
+
+DT_HEADER="""/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Minimal dts for a SPL FIT image payload.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+/dts-v1/;
+
+/ {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+
+ images {
+ uboot@1 {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x%08x>;
+ };
+"""
+
+DT_IMAGES_NODE_END="""
+ };
+"""
+
+DT_END="""
+};
+"""
+
+def append_atf_node(file, atf_index, phy_addr):
+ """
+ Append ATF DT node to input FIT dts file.
+ """
+ data = 'bl31_0x%08x.bin' % phy_addr
+ print >> file, '\t\tatf@%d {' % atf_index
+ print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";'
+ print >> file, '\t\t\tdata = /incbin/("%s");' % data
+ print >> file, '\t\t\ttype = "firmware";'
+ print >> file, '\t\t\tarch = "arm64";'
+ print >> file, '\t\t\tos = "arm-trusted-firmware";'
+ print >> file, '\t\t\tcompression = "none";'
+ print >> file, '\t\t\tload = <0x%08x>;' % phy_addr
+ if atf_index == 1:
+ print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr
+ print >> file, '\t\t};'
+ print >> file, ''
+
+def append_fdt_node(file, dtbs):
+ """
+ Append FDT nodes.
+ """
+ cnt = 1
+ for dtb in dtbs:
+ dtname = os.path.basename(dtb)
+ print >> file, '\t\tfdt@%d {' % cnt
+ print >> file, '\t\t\tdescription = "%s";' % dtname
+ print >> file, '\t\t\tdata = /incbin/("%s");' % dtb
+ print >> file, '\t\t\ttype = "flat_dt";'
+ print >> file, '\t\t\tcompression = "none";'
+ print >> file, '\t\t};'
+ print >> file, ''
+ cnt = cnt + 1
+
+def append_conf_section(file, cnt, dtname, atf_cnt):
+ print >> file, '\t\tconfig@%d {' % cnt
+ print >> file, '\t\t\tdescription = "%s";' % dtname
+ print >> file, '\t\t\tfirmware = "atf@1";'
+ print >> file, '\t\t\tloadables = "uboot@1",',
+ for i in range(1, atf_cnt):
+ print >> file, '"atf@%d"' % (i+1),
+ if i != (atf_cnt - 1):
+ print >> file, ',',
+ else:
+ print >> file, ';'
+ print >> file, '\t\t\tfdt = "fdt@1";'
+ print >> file, '\t\t};'
+ print >> file, ''
+
+def append_conf_node(file, dtbs, atf_cnt):
+ """
+ Append configeration nodes.
+ """
+ cnt = 1
+ print >> file, '\tconfigurations {'
+ print >> file, '\t\tdefault = "config@1";'
+ for dtb in dtbs:
+ dtname = os.path.basename(dtb)
+ append_conf_section(file, cnt, dtname, atf_cnt)
+ cnt = cnt + 1
+ print >> file, '\t};'
+ print >> file, ''
+
+def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
+ """
+ Generate FIT script for ATF image.
+ """
+ if fit_file_name != sys.stdout:
+ fit_file = open(fit_file_name, "wb")
+ else:
+ fit_file = sys.stdout
+
+ num_load_seg = 0
+ p_paddr = 0xFFFFFFFF
+ with open(uboot_file_name) as uboot_file:
+ uboot = ELFFile(uboot_file)
+ for i in range(uboot.num_segments()):
+ seg = uboot.get_segment(i)
+ if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+ num_load_seg = num_load_seg + 1
+
+ assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
+
+ print >> fit_file, DT_HEADER % p_paddr
+
+ with open(bl31_file_name) as bl31_file:
+ bl31 = ELFFile(bl31_file)
+ for i in range(bl31.num_segments()):
+ seg = bl31.get_segment(i)
+ if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+ p= seg.__getitem__(ELF_SEG_P_PADDR)
+ append_atf_node(fit_file, i+1, paddr)
+ atf_cnt = i+1
+ append_fdt_node(fit_file, dtbs_file_name)
+ print >> fit_file, '%s' % DT_IMAGES_NODE_END
+ append_conf_node(fit_file, dtbs_file_name, atf_cnt)
+ print >> fit_file, '%s' % DT_END
+
+ if fit_file_name != sys.stdout:
+ fit_file.close()
+
+def generate_atf_binary(bl31_file_name):
+ with open(bl31_file_name) as bl31_file:
+ bl31 = ELFFile(bl31_file)
+
+ num = bl31.num_segments()
+ for i in range(num):
+ seg = bl31.get_segment(i)
+ if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+ file_name = 'bl31_0x%08x.bin' % paddr
+ with open(file_name, "wb") as atf:
+ atf.write(seg.data());
+
+def get_bl31_segments_info(bl31_file_name):
+ """
+ Get load offset, physical offset, file size
+ from bl31 elf file program headers.
+ """
+ with open(bl31_file_name) as bl31_file:
+ bl31 = ELFFile(bl31_file)
+
+ num = bl31.num_segments()
+ print 'Number of Segments : %d' % bl31.num_segments()
+ for i in range(num):
+ print 'Segment %d' % i
+ seg = bl31.get_segment(i)
+ ptype = seg[ELF_SEG_P_TYPE]
+ poffset = seg[ELF_SEG_P_OFFSET]
+ pmemsz = seg[ELF_SEG_P_MEMSZ]
+ pfilesz = seg[ELF_SEG_P_FILESZ]
+ print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset)
+ paddr = seg[ELF_SEG_P_PADDR]
+ print 'paddr: %08x' % paddr
+
+def main():
+ uboot_elf="./u-boot"
+ bl31_elf="./bl31.elf"
+ FIT_ITS=sys.stdout
+
+ opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
+ for opt, val in opts:
+ if opt == "-o":
+ FIT_ITS=val
+ elif opt == "-u":
+ uboot_elf=val
+ elif opt == "-b":
+ bl31_elf=val
+ elif opt == "-h":
+ print __doc__
+ sys.exit(2)
+
+ dtbs = args
+ #get_bl31_segments_info("u-boot")
+ #get_bl31_segments_info("bl31.elf")
+
+ generate_atf_fit_dts(FIT_ITS, bl31_elf, uboot_elf, dtbs)
+ generate_atf_binary(bl31_elf);
+
+if __name__ == "__main__":
+ main()
sdram_init();
/* return to maskrom */
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
/* Place Holders */
DECLARE_GLOBAL_DATA_PTR;
-#define GRF_BASE 0x20008000
-
-static void setup_boot_mode(void)
-{
- struct rk3036_grf *const grf = (void *)GRF_BASE;
- int boot_mode = readl(&grf->os_reg[4]);
-
- debug("boot mode %x.\n", boot_mode);
-
- /* Clear boot mode */
- writel(BOOT_NORMAL, &grf->os_reg[4]);
-
- switch (boot_mode) {
- case BOOT_FASTBOOT:
- printf("enter fastboot!\n");
- env_set("preboot", "setenv preboot; fastboot usb0");
- break;
- case BOOT_UMS:
- printf("enter UMS!\n");
- env_set("preboot", "setenv preboot; ums mmc 0");
- break;
- }
-}
-
__weak int rk_board_late_init(void)
{
return 0;
struct rk3036_ddr_config ddr_config;
};
-/* use integer mode, 396MHz dpll setting
+/*
+ * use integer mode, dpll output 792MHz and ddr get 396MHz
* refdiv, fbdiv, postdiv1, postdiv2
*/
-const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
+const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
/* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c,
struct rk3036_pll *pll = &priv->cru->pll[1];
/* pll enter slow-mode */
- rk_clrsetreg(&priv->cru->cru_mode_con,
- DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
/* use integer mode */
- rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
- PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+ PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
(dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
dpll_init_cfg.fbdiv);
- rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
- PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
- (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
- dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
+ dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
/* waiting for pll lock */
while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
rockchip_udelay(1);
/* PLL enter normal-mode */
- rk_clrsetreg(&priv->cru->cru_mode_con,
- DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_NORM << DPLL_MODE_SHIFT);
}
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/arch/timer.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+ int ret = 0;
+
+ rockchip_timer_init();
+
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x8400000;
+ /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ + gd->bd->bi_dram[0].size + 0xe00000;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + gd->ram_size - gd->bd->bi_dram[1].start;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3128_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3128-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3128-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3128_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+ struct rk3128_grf *grf;
+
+ printf("Setting reboot to fastboot flag ...\n");
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, &grf->os_reg[0]);
+
+ return 0;
+}
+#endif
--- /dev/null
+if ROCKCHIP_RK3128
+
+choice
+ prompt "RK3128 board select"
+
+config TARGET_EVB_RK3128
+ bool "RK3128 evaluation board"
+ select BOARD_LATE_INIT
+ help
+ RK3128evb is a evaluation board for Rockchip rk3128,
+ with full function and phisical connectors support like
+ usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+
+endchoice
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+source "board/rockchip/evb_rk3128/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3128.o
+obj-y += syscon_rk3128.o
+obj-y += clk_rk3128.o
--- /dev/null
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3128.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3128_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3128_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3128_syscon_ids[] = {
+ { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3128) = {
+ .name = "rk3128_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3128_syscon_ids,
+};
void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev;
- struct rk3188_pmu *pmu;
int ret;
/* Example code showing how to enable the debug UART on RK3188 */
return;
}
- /*
- * Recover the bootrom's stackpointer.
- * For whatever reason needs to run after rockchip_get_clk.
- */
- pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
- if (IS_ERR(pmu))
- pr_err("pmu syscon returned %ld\n", PTR_ERR(pmu));
- SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
-
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("Pinctrl init failed: %d\n", ret);
setup_arm_clock();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
+++ /dev/null
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/pmu_rk3188.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* track how often we were entered */
-static int rk3188_num_entries __attribute__ ((section(".data")));
-
-#define PMU_BASE 0x20004000
-#define SPL_ENTRY 0x10080C00
-
-static void jump_to_spl(void)
-{
- typedef void __noreturn (*image_entry_noargs_t)(void);
-
- struct rk3188_pmu * const pmu = (void *)PMU_BASE;
- image_entry_noargs_t tpl_entry =
- (image_entry_noargs_t)(unsigned long)SPL_ENTRY;
-
- /* Store the SAVE_SP_ADDR in a location shared with SPL. */
- writel(SAVE_SP_ADDR, &pmu->sys_reg[2]);
- tpl_entry();
-}
-
-void board_init_f(ulong dummy)
-{
- /* Example code showing how to enable the debug UART on RK3188 */
-#ifdef EARLY_UART
-#include <asm/arch/grf_rk3188.h>
- /* Enable early UART on the RK3188 */
-#define GRF_BASE 0x20008000
- struct rk3188_grf * const grf = (void *)GRF_BASE;
-
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK << GPIO1B1_SHIFT |
- GPIO1B0_MASK << GPIO1B0_SHIFT,
- GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
- GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
-
- printch('t');
- printch('p');
- printch('l');
- printch('-');
- printch(rk3188_num_entries + 1 + '0');
- printch('\n');
-#endif
-
- rk3188_num_entries++;
-
- if (rk3188_num_entries == 1) {
- /*
- * The original loader did some very basic integrity
- * checking at this point, but the remaining few bytes
- * could be used for any improvement making sense
- * really early on.
- */
-
- back_to_bootrom();
- } else {
- /*
- * TPL part of the loader should now wait for us
- * at offset 0xC00 in the sram. Should never return
- * from there.
- */
- jump_to_spl();
- }
-}
{
struct rk3188_grf *grf;
+ setup_boot_mode();
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(grf)) {
pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
DECLARE_GLOBAL_DATA_PTR;
-#define GRF_BASE 0x11000000
-
-static void setup_boot_mode(void)
-{
- struct rk322x_grf *const grf = (void *)GRF_BASE;
- int boot_mode = readl(&grf->os_reg[0]);
-
- debug("boot mode %x.\n", boot_mode);
-
- /* Clear boot mode */
- writel(BOOT_NORMAL, &grf->os_reg[0]);
-
- switch (boot_mode) {
- case BOOT_FASTBOOT:
- printf("enter fastboot!\n");
- env_set("preboot", "setenv preboot; fastboot usb0");
- break;
- case BOOT_UMS:
- printf("enter UMS!\n");
- env_set("preboot", "setenv preboot; ums mmc 0");
- break;
- }
-}
-
__weak int rk_board_late_init(void)
{
return 0;
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
err:
void board_return_to_bootrom(void)
{
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
DECLARE_GLOBAL_DATA_PTR;
-#define PMU_BASE 0xff730000
-
-static void setup_boot_mode(void)
-{
- struct rk3288_pmu *const pmu = (void *)PMU_BASE;
- int boot_mode = readl(&pmu->sys_reg[0]);
-
- debug("boot mode %x.\n", boot_mode);
-
- /* Clear boot mode */
- writel(BOOT_NORMAL, &pmu->sys_reg[0]);
-
- switch (boot_mode) {
- case BOOT_FASTBOOT:
- printf("enter fastboot!\n");
- env_set("preboot", "setenv preboot; fastboot usb0");
- break;
- case BOOT_UMS:
- printf("enter UMS!\n");
- env_set("preboot", "setenv preboot; if mmc dev 0;"
- "then ums mmc 0; else ums mmc 1;fi");
- break;
- }
-}
-
__weak int rk_board_late_init(void)
{
return 0;
void board_return_to_bootrom(void)
{
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
void board_return_to_bootrom(void)
{
- back_to_bootrom();
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
--- /dev/null
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/boot_mode.h>
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+ return 0;
+}
+++ /dev/null
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#if defined(CONFIG_ARM64)
-.globl SAVE_SP_ADDR
-SAVE_SP_ADDR:
- .quad 0
-
-ENTRY(save_boot_params)
- sub sp, sp, #0x60
- stp x29, x30, [sp, #0x50]
- stp x27, x28, [sp, #0x40]
- stp x25, x26, [sp, #0x30]
- stp x23, x24, [sp, #0x20]
- stp x21, x22, [sp, #0x10]
- stp x19, x20, [sp, #0]
- ldr x8, =SAVE_SP_ADDR
- mov x9, sp
- str x9, [x8]
- b save_boot_params_ret /* back to my caller */
-ENDPROC(save_boot_params)
-
-.globl _back_to_bootrom_s
-ENTRY(_back_to_bootrom_s)
- ldr x0, =SAVE_SP_ADDR
- ldr x0, [x0]
- mov sp, x0
- ldp x29, x30, [sp, #0x50]
- ldp x27, x28, [sp, #0x40]
- ldp x25, x26, [sp, #0x30]
- ldp x23, x24, [sp, #0x20]
- ldp x21, x22, [sp, #0x10]
- ldp x19, x20, [sp]
- add sp, sp, #0x60
- mov x0, xzr
- ret
-ENDPROC(_back_to_bootrom_s)
-#else
-.globl SAVE_SP_ADDR
-SAVE_SP_ADDR:
- .word 0
-
-/*
- * void save_boot_params
- *
- * Save sp, lr, r1~r12
- */
-ENTRY(save_boot_params)
- push {r1-r12, lr}
- ldr r0, =SAVE_SP_ADDR
- str sp, [r0]
- b save_boot_params_ret @ back to my caller
-ENDPROC(save_boot_params)
-
-
-.globl _back_to_bootrom_s
-ENTRY(_back_to_bootrom_s)
- ldr r0, =SAVE_SP_ADDR
- ldr sp, [r0]
- mov r0, #0
- pop {r1-r12, pc}
-ENDPROC(_back_to_bootrom_s)
-#endif
#ifndef __BOOT0_H
#define __BOOT0_H
+_start:
+ ARM_VECTORS
+
#ifdef CONFIG_SPL_BUILD
.balignl 64,0xf33db33f;
#
# SPDX-License-Identifier: GPL-2.0+
#
-
+obj-y += soc.o
obj-$(CONFIG_STM32F4) += stm32f4/
obj-$(CONFIG_STM32F7) += stm32f7/
-obj-$(CONFIG_STM32H7) += stm32h7/
#include <asm/io.h>
#include <asm/armv7m_mpu.h>
-u32 get_cpu_rev(void)
-{
- return 0;
-}
-
int arch_cpu_init(void)
{
int i;
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_4GB },
- /* Code area, executable & strongly ordered */
- { 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_8MB },
+ /* armv7m code area */
+ { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, REGION_512MB },
- /* Device area in all H7 : Not executable */
+ /* Device area : Not executable */
{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
DEVICE_NON_SHARED, REGION_512MB },
* Armv7m fixed configuration: strongly ordered & not
* executable, not cacheable
*/
- { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
+ { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_512MB },
+
+#if !defined(CONFIG_STM32H7)
+ /* Device area : Not executable */
+ { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
+ DEVICE_NON_SHARED, REGION_512MB },
+#endif
};
disable_mpu();
return 0;
}
-
-void s_init(void)
-{
-}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += soc.o clock.o timer.o
+obj-y += clock.o timer.o
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
#define RCC_ENR_GPIO_J_EN (1 << 9)
#define RCC_ENR_GPIO_K_EN (1 << 10)
-struct pll_psc {
- u8 pll_m;
- u16 pll_n;
- u8 pll_p;
- u8 pll_q;
- u8 ahb_psc;
- u8 apb1_psc;
- u8 apb2_psc;
-};
-
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
-
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
-
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m_mpu.h>
-#include <asm/arch/stm32.h>
-
-u32 get_cpu_rev(void)
-{
- return 0;
-}
-
-int arch_cpu_init(void)
-{
- struct mpu_region_config stm32_region_config[] = {
- { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_4GB },
- };
- int i;
-
- configure_clocks();
- /*
- * Configure the memory protection unit (MPU) to allow full access to
- * the whole 4GB address space.
- */
- disable_mpu();
- for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
- mpu_config(&stm32_region_config[i]);
- enable_mpu();
-
- return 0;
-}
-
-void s_init(void)
-{
-}
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += timer.o soc.o
+obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m_mpu.h>
-#include <asm/arch/stm32.h>
-
-u32 get_cpu_rev(void)
-{
- return 0;
-}
-
-int arch_cpu_init(void)
-{
- int i;
-
- struct mpu_region_config stm32_region_config[] = {
- { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
- O_I_WB_RD_WR_ALLOC, REGION_4GB },
-
- { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
-
- { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
-
- { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
-
- { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
- };
-
- disable_mpu();
- for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
- mpu_config(&stm32_region_config[i]);
- enable_mpu();
-
- return 0;
-}
-
-void s_init(void)
-{
-}
*/
#include <common.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_defs.h>
+++ /dev/null
-#
-# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += soc.o
default 1008000000 if MACH_SUN5I
default 1008000000 if MACH_SUN6I
default 912000000 if MACH_SUN7I
+ default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
default 1008000000 if MACH_SUN8I
default 1008000000 if MACH_SUN9I
- default 816000000 if MACH_SUN50I
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
select BOARD_EARLY_INIT_F
+ select BINMAN
imply CRC32_VERIFY
config TEGRA_NO_BPMP
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <libfdt.h>
+#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include "init.h"
#include "micro-support-card.h"
-#include "sg-regs.h"
#include "soc-info.h"
-DECLARE_GLOBAL_DATA_PTR;
-
-static void uniphier_setup_xirq(void)
-{
- const void *fdt = gd->fdt_blob;
- int soc_node, aidet_node;
- const fdt32_t *val;
- unsigned long aidet_base;
- u32 tmp;
-
- soc_node = fdt_path_offset(fdt, "/soc");
- if (soc_node < 0)
- return;
-
- aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
- if (aidet_node < 0)
- return;
-
- val = fdt_getprop(fdt, aidet_node, "reg", NULL);
- if (!val)
- return;
-
- aidet_base = fdt32_to_cpu(*val);
-
- tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
- tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
- writel(tmp, aidet_base + 8);
-
- tmp = readl(0x55000090); /* IRQCTL */
- tmp |= 0x000000ff;
- writel(tmp, 0x55000090);
-}
-
-#ifdef CONFIG_ARCH_UNIPHIER_LD11
-static void uniphier_ld11_misc_init(void)
-{
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
-}
-#endif
-
#ifdef CONFIG_ARCH_UNIPHIER_LD20
static void uniphier_ld20_misc_init(void)
{
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
-
/* ES1 errata: increase VDD09 supply to suppress VBO noise */
if (uniphier_get_soc_revision() == 1) {
writel(0x00000003, 0x6184e004);
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
- .misc_init = uniphier_ld11_misc_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
led_puts("U3");
- uniphier_setup_xirq();
-
- led_puts("U4");
-
support_card_late_init();
led_puts("Uboo");
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
-#define SC_PLLCTRL3_REGI_SHIFT 16
#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
/* PLL type: VPLL27 */
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
- tmp |= (487 * freq * ssc_rate / divn / 512) &
- SC_PLLCTRL_SSC_DK_MASK;
+ tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
+ DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
+ divn * 512));
writel(tmp, base);
tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
- tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+ tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
+ DIV_ROUND_CLOSEST(21431887UL * freq,
+ divn * 512));
+ writel(tmp, base + 4);
udelay(50);
}
tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
- tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+ tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
writel(tmp, base + 8);
iounmap(base);
/* pins for NAND and System Bus are multiplexed */
if (spl_boot_device() != BOOT_DEVICE_NAND)
- uniphier_pin_init("system_bus_grp");
+ uniphier_pin_init("system-bus");
}
/* system bus output enable */
writel(0x17, PC0CTRL);
- uniphier_pin_init("system_bus_grp"); /* PXs3 */
+ uniphier_pin_init("system-bus"); /* PXs3 */
}
obj-y += clk.o
obj-y += lowlevel_init.o
AFLAGS_lowlevel_init.o := -mfpu=neon
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o
--- /dev/null
+/*
+ * Copyright (C) 2017 National Instruments Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <nand.h>
+
+void zynq_nand_init(void);
--- /dev/null
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PS7_INIT_GPL_H
+#define _ASM_ARCH_PS7_INIT_GPL_H
+
+/* Opcode exit is 0 all the time */
+#define OPCODE_EXIT 0U
+#define OPCODE_MASKWRITE 0U
+#define OPCODE_MASKPOLL 1U
+#define OPCODE_MASKDELAY 2U
+#define OPCODE_WRITE 3U
+#define OPCODE_ADDRESS_MASK (~3U)
+
+/* Sentinel */
+#define EMIT_EXIT() OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+#define EMIT_WRITE(addr, val) OPCODE_WRITE | addr, val
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS (0)
+#define PS7_INIT_CORRUPT (1)
+#define PS7_INIT_TIMEOUT (2)
+#define PS7_POLL_FAILED_DDR_INIT (3)
+#define PS7_POLL_FAILED_DMA (4)
+#define PS7_POLL_FAILED_PLL (5)
+
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
+
+unsigned long ps7GetSiliconVersion(void);
+
+#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
-/* Driver extern functions */
-extern void ps7_init(void);
-
#endif /* _SYS_PROTO_H_ */
/*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
* (c) Copyright 2016 Topic Embedded Products.
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "ps7_init_gpl.h"
#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
+
+__weak int ps7_init(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+ */
+ return 0;
+}
+
+__weak int ps7_post_config(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+ */
+ return 0;
+}
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
perf_start_clock();
}
-int ps7_config(unsigned long *ps7_config_init)
+int __weak ps7_config(unsigned long *ps7_config_init)
{
unsigned long *ptr = ps7_config_init;
unsigned long opcode;
iowrite((ioread(addr) & ~mask) | (val & mask), addr);
break;
+ case OPCODE_WRITE:
+ numargs = 2;
+ val = ptr[1];
+ iowrite(val, addr);
+ break;
+
case OPCODE_MASKPOLL:
numargs = 2;
mask = ptr[1];
ptr += numargs;
}
}
+
+unsigned long __weak __maybe_unused ps7GetSiliconVersion(void)
+{
+ return zynq_get_silicon_version();
+}
int zynq_slcr_get_mio_pin_status(const char *periph)
{
const struct zynq_slcr_mio_get_status *mio_ptr;
- int val, i, j;
+ int val, j;
int mio = 0;
+ u32 i;
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
#include <asm/spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-__weak void ps7_init(void)
-{
- /*
- * This function is overridden by the one in
- * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
- */
-}
-
-__weak int ps7_post_config(void)
-{
- /*
- * This function is overridden by the one in
- * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
- */
- return 0;
-}
-
void spl_board_prepare_for_boot(void)
{
ps7_post_config();
* SPDX-License-Identifier: GPL-2.0+
*/
-#if defined(CONFIG_64BIT)
-#define PTR_COUNT_SHIFT 3
-#else
-#define PTR_COUNT_SHIFT 2
-#endif
-
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
+#include <asm/asm.h>
#include <asm/sgidefs.h>
#include <asm/ptrace.h>
+#include <linux/stringify.h>
#if 0
#include <linux/kernel.h>
#endif
".set reorder");
}
+static inline void instruction_hazard_barrier(void)
+{
+ unsigned long tmp;
+
+ asm volatile(
+ __stringify(PTR_LA) "\t%0, 1f\n"
+ " jr.hb %0\n"
+ "1: .insn"
+ : "=&r"(tmp));
+}
+
#endif /* _ASM_SYSTEM_H */
#ifdef CONFIG_MIPS_L2_CACHE
#include <asm/cm.h>
#endif
+#include <asm/io.h>
#include <asm/mipsregs.h>
+#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
const unsigned int cache_ops[] = { ops }; \
unsigned int i; \
\
+ if (!lsize) \
+ break; \
+ \
for (; addr <= aend; addr += lsize) { \
for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
mips_cache(cache_ops[i], addr); \
/* flush I-cache & D-cache simultaneously */
cache_loop(start_addr, start_addr + size, ilsize,
HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
- return;
+ goto ops_done;
}
/* flush D-cache */
cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
/* flush L2 cache */
- if (slsize)
- cache_loop(start_addr, start_addr + size, slsize,
- HIT_WRITEBACK_INV_SD);
+ cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
/* flush I-cache */
cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
+
+ops_done:
+ /* ensure cache ops complete before any further memory accesses */
+ sync();
+
+ /* ensure the pipeline doesn't contain now-invalid instructions */
+ instruction_hazard_barrier();
}
void flush_dcache_range(ulong start_addr, ulong stop)
cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
/* flush L2 cache */
- if (slsize)
- cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
+ cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
+
+ /* ensure cache ops complete before any further memory accesses */
+ sync();
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
return;
/* invalidate L2 cache */
- if (slsize)
- cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
+ cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
+
+ /* ensure cache ops complete before any further memory accesses */
+ sync();
}
interrupts = <25 4>;
};
+ mmc0: mmc@f0e00000 {
+ compatible = "andestech,atsdc010";
+ max-frequency = <100000000>;
+ fifo-depth = <0x10>;
+ reg = <0xf0e00000 0x1000>;
+ interrupts = <17 4>;
+ };
+
nor@0,0 {
compatible = "cfi-flash";
reg = <0x88000000 0x1000>;
reg = <0x90900000 0x1000>;
interrupts = <25 4>;
};
+
+ mmc0: mmc@98e00000 {
+ compatible = "andestech,atsdc010";
+ max-frequency = <30000000>;
+ fifo-depth = <0x10>;
+ reg = <0x98e00000 0x1000>;
+ interrupts = <5 4>;
+ };
};
bool "Support MPC837XEMDS"
select BOARD_EARLY_INIT_F
imply CMD_SATA
+ imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
# Use DDR3 controller with DDR2 DIMMs on this board
select SYS_FSL_DDRC_GEN3
imply CMD_SATA
+ imply FSL_SATA
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select SUPPORT_SPL
select SUPPORT_TPL
imply CMD_SATA
+ imply FSL_SATA
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1025
imply CMD_EEPROM
imply CMD_SATA
+ imply SATA_SIL
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select ARCH_P2020
imply CMD_EEPROM
imply CMD_SATA
+ imply SATA_SIL
config TARGET_P1_TWR
bool "Support p1_twr"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
imply CMD_SATA
+ imply FSL_SATA
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select PHYS_64BIT
imply CMD_EEPROM
imply CMD_SATA
+ imply FSL_SATA
config TARGET_T1023RDB
bool "Support T1023RDB"
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P1011
bool
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1021
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1022
bool
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1025
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P4080
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P5020
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P5040
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_QEMU_E500
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T1042
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T2080
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T2081
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T4240
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config BOOKE
bool
return 0;
}
+void os_putc(int ch)
+{
+ putchar(ch);
+}
+
+void os_puts(const char *str)
+{
+ while (*str)
+ os_putc(*str++);
+}
+
int os_write_ram_buf(const char *fname)
{
struct sandbox_state *state = state_get_current();
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ no_match_by_nodename {
+ regulator-name = "buck_SUPPLY_1.5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
};
PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions
PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)
-LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
-LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
-
# This is used in the top-level Makefile which does not include
# PLATFORM_LDFLAGS
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply ICH_SPI
imply INTEL_BROADWELL_GPIO
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
imply MMC_PCI
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
{
const char *name;
name = "<invalid cpu vendor>";
- if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
- (x86_vendor_name[vendor] != 0))
+ if (vendor < ARRAY_SIZE(x86_vendor_name) &&
+ x86_vendor_name[vendor])
name = x86_vendor_name[vendor];
return name;
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
select ARCH_EARLY_INIT_R
imply AHCI_PCI
imply E1000
+ imply SCSI_AHCI
imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
config SYS_CAR_ADDR
hex
- default 0xd0000
+ default 0x10000
config SYS_CAR_SIZE
hex
imply MMC_SDHCI_SDMA
imply PCH_GBE
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
obj-y += early_cmos.o
obj-$(CONFIG_EFI) += efi/
obj-y += e820.o
-obj-y += gcc.o
obj-y += init_helpers.o
obj-y += interrupts.o
obj-y += lpc-uclass.o
obj-$(CONFIG_HAVE_FSP) += fsp/
obj-$(CONFIG_SPL_BUILD) += spl.o
-extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a
-
-NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
-OBJCOPYFLAGS := --prefix-symbols=__normal_
-$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
- $(call if_changed,objcopy)
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o
ifeq ($(CONFIG_$(SPL_)X86_64),)
obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
}
is_zimage = 1;
#if defined(CONFIG_FIT)
- } else if (images->fit_uname_os) {
+ } else if (images->fit_uname_os && is_zimage) {
ret = fit_image_get_data(images->fit_hdr_os,
images->fit_noffset_os,
(const void **)&data, &len);
--- /dev/null
+/*
+ * This file is copied from the coreboot repository as part of
+ * the libpayload project:
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+
+union overlay64 {
+ u64 longw;
+ struct {
+ u32 lower;
+ u32 higher;
+ } words;
+};
+
+u64 __ashldi3(u64 num, unsigned int shift)
+{
+ union overlay64 output;
+
+ output.longw = num;
+ if (shift >= 32) {
+ output.words.higher = output.words.lower << (shift - 32);
+ output.words.lower = 0;
+ } else {
+ if (!shift)
+ return num;
+ output.words.higher = (output.words.higher << shift) |
+ (output.words.lower >> (32 - shift));
+ output.words.lower = output.words.lower << shift;
+ }
+ return output.longw;
+}
+
+u64 __lshrdi3(u64 num, unsigned int shift)
+{
+ union overlay64 output;
+
+ output.longw = num;
+ if (shift >= 32) {
+ output.words.lower = output.words.higher >> (shift - 32);
+ output.words.higher = 0;
+ } else {
+ if (!shift)
+ return num;
+ output.words.lower = output.words.lower >> shift |
+ (output.words.higher << (32 - shift));
+ output.words.higher = output.words.higher >> shift;
+ }
+ return output.longw;
+}
+
+#define MAX_32BIT_UINT ((((u64)1) << 32) - 1)
+
+static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p)
+{
+ u64 result = 0;
+
+ /*
+ * If divider is zero - let the rest of the system care about the
+ * exception.
+ */
+ if (!divider)
+ return 1 / (u32)divider;
+
+ /* As an optimization, let's not use 64 bit division unless we must. */
+ if (dividend <= MAX_32BIT_UINT) {
+ if (divider > MAX_32BIT_UINT) {
+ result = 0;
+ if (rem_p)
+ *rem_p = divider;
+ } else {
+ result = (u32)dividend / (u32)divider;
+ if (rem_p)
+ *rem_p = (u32)dividend % (u32)divider;
+ }
+ return result;
+ }
+
+ while (divider <= dividend) {
+ u64 locald = divider;
+ u64 limit = __lshrdi3(dividend, 1);
+ int shifts = 0;
+
+ while (locald <= limit) {
+ shifts++;
+ locald = locald + locald;
+ }
+ result |= __ashldi3(1, shifts);
+ dividend -= locald;
+ }
+
+ if (rem_p)
+ *rem_p = dividend;
+
+ return result;
+}
+
+u64 __udivdi3(u64 num, u64 den)
+{
+ return _64bit_divide(num, den, NULL);
+}
+
+u64 __umoddi3(u64 num, u64 den)
+{
+ u64 v = 0;
+
+ _64bit_divide(num, den, &v);
+ return v;
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifdef __GNUC__
-
-/*
- * GCC's libgcc handling is quite broken. While the libgcc functions
- * are always regparm(0) the code that calls them uses whatever the
- * compiler call specifies. Therefore we need a wrapper around those
- * functions. See gcc bug PR41055 for more information.
- */
-#define WRAP_LIBGCC_CALL(type, name) \
- type __normal_##name(type a, type b) __attribute__((regparm(0))); \
- type __wrap_##name(type a, type b); \
- type __attribute__((no_instrument_function)) \
- __wrap_##name(type a, type b) \
- { return __normal_##name(a, b); }
-
-WRAP_LIBGCC_CALL(long long, __divdi3)
-WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
-WRAP_LIBGCC_CALL(long long, __moddi3)
-WRAP_LIBGCC_CALL(unsigned long long, __umoddi3)
-
-#endif
int board_mmc_init(bd_t *bis)
{
+#ifndef CONFIG_DM_MMC
#ifdef CONFIG_FTSDC010
ftsdc010_mmc_init(0);
+#endif
#endif
return 0;
}
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif /* RAMBOOT/SPL */
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_16, /* memory_width */
MEM_8G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_8, /* memory_width */
MEM_2G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_WIDTH_8, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
--- /dev/null
+if TARGET_KHADAS_VIM
+
+config SYS_BOARD
+ default "khadas-vim"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "khadas-vim"
+
+endif
--- /dev/null
+KHADAS-VIM
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+F: board/amlogic/khadas-vim/
+F: include/configs/khadas-vim.h
+F: configs/khadas-vim_defconfig
--- /dev/null
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := khadas-vim.o
--- /dev/null
+U-Boot for Khadas VIM
+=======================
+
+Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Tomato
+Technology Co., Ltd with the following specifications:
+
+ - Amlogic S905x ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
+ - 8GB/16GBeMMC
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - Two channels IR receiver
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+
+U-Boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make khadas-vim_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
+ > cd vim-u-boot
+ > make kvim_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+
+#define EFUSE_SN_OFFSET 20
+#define EFUSE_SN_SIZE 16
+#define EFUSE_MAC_OFFSET 52
+#define EFUSE_MAC_SIZE 6
+
+int board_init(void)
+{
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
+ ssize_t len;
+
+ meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
+ MESON_GXL_USE_INTERNAL_RMII_PHY);
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ if (!env_get("serial#")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial#", serial);
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ meson_gx_init_reserved_memory(blob);
+
+ return 0;
+}
--- /dev/null
+if TARGET_LIBRETECH_CC
+
+config SYS_BOARD
+ default "libretech-cc"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "libretech-cc"
+
+endif
--- /dev/null
+LIBRETECH-CC
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+F: board/amlogic/libretech-cc/
+F: include/configs/libretech-cc.h
+F: configs/libretech-cc_defconfig
--- /dev/null
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := libretech-cc.o
--- /dev/null
+U-Boot for LibreTech CC
+=======================
+
+LibreTech CC is a single board computer manufactured by Libre Technology
+with the following specifications:
+
+ - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the U-Boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+
+U-Boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make libretech-cc_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
+ > cd amlogic-u-boot
+ > make libretech_cc_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET 20
+#define EFUSE_SN_SIZE 16
+#define EFUSE_MAC_OFFSET 52
+#define EFUSE_MAC_SIZE 6
+
+int board_init(void)
+{
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
+ ssize_t len;
+
+ meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
+ MESON_GXL_USE_INTERNAL_RMII_PHY);
+
+ /* Enable power and clock gate */
+ setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+ clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ if (!env_get("serial#")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial#", serial);
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ meson_gx_init_reserved_memory(blob);
+
+ return 0;
+}
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
-#include <phy.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
char serial[EFUSE_SN_SIZE];
ssize_t len;
- /* Set RGMII mode */
- setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
- GXBB_ETH_REG_0_TX_PHASE(1) |
- GXBB_ETH_REG_0_TX_RATIO(4) |
- GXBB_ETH_REG_0_PHY_CLK_EN |
- GXBB_ETH_REG_0_CLK_EN);
+ meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
/* Enable power and clock gate */
setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
- setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
- clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
/* Reset PHY on GPIOZ_14 */
clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
return 0;
}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ meson_gx_init_reserved_memory(blob);
+
+ return 0;
+}
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
-#include <phy.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
char serial[EFUSE_SN_SIZE];
ssize_t len;
- /* Set RMII mode */
- out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
- GXBB_ETH_REG_0_CLK_EN);
-
- /* Use Internal PHY */
- out_le32(GXBB_ETH_REG_2, 0x10110181);
- out_le32(GXBB_ETH_REG_3, 0xe40908ff);
-
- /* Enable power and clock gate */
- setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
- clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+ meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
return 0;
}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ meson_gx_init_reserved_memory(blob);
+
+ return 0;
+}
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <atmel_lcdc.h>
#include <asm/mach-types.h>
+++ /dev/null
-SAMA5D2 PTC Engineering BOARD
-M: Wenyou Yang <wenyou.yang@atmel.com>
-S: Maintained
-F: board/atmel/sama5d2_ptc/
-F: include/configs/sama5d2_ptc.h
-F: configs/sama5d2_ptc_spiflash_defconfig
-F: configs/sama5d2_ptc_nandflash_defconfig
+++ /dev/null
-#
-# Copyright (C) 2016 Atmel
-# Wenyou Yang <wenyou.yang@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sama5d2_ptc.o
+++ /dev/null
-/*
- * Copyright (C) 2016 Atmel
- * Wenyou.Yang <wenyou.yang@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <atmel_hlcdc.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/atmel_pio4.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
-#include <asm/arch/atmel_sdhci.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sama5_sfr.h>
-#include <asm/arch/sama5d2.h>
-#include <asm/arch/sama5d3_smc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-}
-
-static void board_spi0_hw_init(void)
-{
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
-
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-
-static void board_nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-
- at91_periph_clk_enable(ATMEL_ID_HSMC);
-
- writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
- AT91_SFR_EBICFG_PULL0_NONE |
- AT91_SFR_EBICFG_DRIVE1_HIGH |
- AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
-
- /* Configure SMC CS3 for NAND */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
- AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
- AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
- AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
-}
-
-static void board_usb_hw_init(void)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
-}
-
-static void board_gmac_hw_init(void)
-{
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
-
- at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-
-static void board_uart0_hw_init(void)
-{
- atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
- atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
-
- at91_periph_clk_enable(CONFIG_USART_ID);
-}
-
-int board_early_init_f(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
-
- board_uart0_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_ATMEL_SPI
- board_spi0_hw_init();
-#endif
-#ifdef CONFIG_NAND_ATMEL
- board_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- board_gmac_hw_init();
-#endif
-#ifdef CONFIG_CMD_USB
- board_usb_hw_init();
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- at91_udp_hw_init();
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
- if (rc)
- printf("GMAC register failed\n");
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
- usb_eth_initialize(bis);
-#endif
-#endif
-
- return rc;
-}
-
-/* SPL */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-#ifdef CONFIG_SPI_BOOT
- board_spi0_hw_init();
-#endif
-
-#ifdef CONFIG_NAND_BOOT
- board_nand_hw_init();
-#endif
-}
-
-static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
-{
- ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
-
- ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
- ATMEL_MPDDRC_CR_NR_ROW_14 |
- ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
- ATMEL_MPDDRC_CR_DIC_DS |
- ATMEL_MPDDRC_CR_DIS_DLL |
- ATMEL_MPDDRC_CR_NB_8BANKS |
- ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
- ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
-
- ddrc->rtr = 0x511;
-
- ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
- (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
-
- ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
- (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
-
- ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
- (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
-}
-
-void mem_init(void)
-{
- struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
- struct atmel_mpddrc_config ddrc_config;
- u32 reg;
-
- ddrc_conf(&ddrc_config);
-
- at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- at91_system_clk_enable(AT91_PMC_DDR);
-
- reg = readl(&mpddrc->io_calibr);
- reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
- reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
- reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
- reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
- writel(reg, &mpddrc->io_calibr);
-
- writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
- &mpddrc->rd_data_path);
-
- ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
-
- writel(0x3, &mpddrc->cal_mr4);
- writel(64, &mpddrc->tim_cal);
-}
-
-void at91_pmc_init(void)
-{
- at91_plla_init(AT91_PMC_PLLAR_29 |
- AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
- AT91_PMC_PLLXR_MUL(82) |
- AT91_PMC_PLLXR_DIV(1));
-
- at91_pllicpr_init(0);
-
- at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
- AT91_PMC_MCKR_PLLADIV_2 |
- AT91_PMC_MCKR_MDIV_3 |
- AT91_PMC_MCKR_CSS_PLLA);
-}
-#endif
-if TARGET_SAMA5D2_PTC
+if TARGET_SAMA5D2_PTC_EK
config SYS_BOARD
- default "sama5d2_ptc"
+ default "sama5d2_ptc_ek"
config SYS_VENDOR
default "atmel"
default "at91"
config SYS_CONFIG_NAME
- default "sama5d2_ptc"
+ default "sama5d2_ptc_ek"
endif
--- /dev/null
+SAMA5D2 PTC EK BOARD
+M: Wenyou Yang <wenyou.yang@microchip.com>
+M: Ludovic Desroches <ludovic.desroches@microchip.com>
+S: Maintained
+F: board/atmel/sama5d2_ptc_ek/
+F: include/configs/sama5d2_ptc_ek.h
+F: configs/sama5d2_ptc_ek_mmc_defconfig
+F: configs/sama5d2_ptc_ek_nandflash_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Microchip Corporation
+# Wenyou Yang <wenyou.yang@microchip.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d2_ptc_ek.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <i2c.h>
+#include <nand.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d2_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+static void board_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+ /* Configure SMC CS3 for NAND */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+ AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
+ AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */
+}
+#endif
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ board_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ board_usb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#define AT24MAC_MAC_OFFSET 0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+ return 0;
+}
+#endif
return ret;
}
-void usb_hub_reset_devices(int port)
+void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
/* The LAN9730 needs to be reset after the port power has been set. */
if (port == 3) {
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x00440044,
- .p1_mpwldectrl1 = 0x00440044,
- .p0_mpdgctrl0 = 0x434B0350,
- .p0_mpdgctrl1 = 0x034C0359,
- .p1_mpdgctrl0 = 0x434B0350,
- .p1_mpdgctrl1 = 0x03650348,
- .p0_mprddlctl = 0x4436383B,
- .p1_mprddlctl = 0x39393341,
- .p0_mpwrdlctl = 0x35373933,
- .p1_mpwrdlctl = 0x48254A36,
+ .p0_mpwldectrl0 = 0x0011000E,
+ .p0_mpwldectrl1 = 0x000E001B,
+ .p1_mpwldectrl0 = 0x00190015,
+ .p1_mpwldectrl1 = 0x00070018,
+ .p0_mpdgctrl0 = 0x42720306,
+ .p0_mpdgctrl1 = 0x026F0266,
+ .p1_mpdgctrl0 = 0x4273030A,
+ .p1_mpdgctrl1 = 0x02740240,
+ .p0_mprddlctl = 0x45393B3E,
+ .p1_mprddlctl = 0x403A3747,
+ .p0_mpwrdlctl = 0x40434541,
+ .p1_mpwrdlctl = 0x473E4A3B,
};
static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
.mem_speed = 1600,
- .density = 4,
+ .density = 2,
.width = 64,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
+ .trcd = 1312,
+ .trcmin = 5863,
+ .trasmin = 3750,
};
static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
+ .cs_density = 16,
.ncs = 1, /* single chip select */
- .cs1_mirror = 0,
+ .cs1_mirror = 1,
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
};
static void ccgr_init(void)
/* Perform DDR DRAM calibration */
udelay(100);
- mmdc_do_write_level_calibration(&dhcom_ddr_info);
mmdc_do_dqs_calibration(&dhcom_ddr_info);
/* Clear the BSS. */
}
#endif
+static void setenv_fdt_file(void)
+{
+ const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
+
+ if (!strcmp(cmp_dtb, "imx6q-icore")) {
+ if (is_mx6dq())
+ env_set("fdt_file", "imx6q-icore.dtb");
+ else if(is_mx6dl() || is_mx6solo())
+ env_set("fdt_file", "imx6dl-icore.dtb");
+ } else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
+ if (is_mx6dq())
+ env_set("fdt_file", "imx6q-icore-rqs.dtb");
+ else if(is_mx6dl() || is_mx6solo())
+ env_set("fdt_file", "imx6dl-icore-rqs.dtb");
+ } else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
+ env_set("fdt_file", "imx6ul-geam-kit.dtb");
+ else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
+ env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
+ else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
+ env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
+ else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
+ env_set("fdt_file", "imx6ul-isiot-nand.dtb");
+}
+
int board_late_init(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
#ifndef _BOARD_H_
#define _BOARD_H_
-void setenv_fdt_file(void);
void setup_gpmi_nand(void);
void setup_display(void);
#endif /* _BOARD_H_ */
#endif
};
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
+ return 0;
+ else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
+ return 0;
+ else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
+ return 0;
+ else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
+ return 0;
+ else
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bmode = imx6_src_get_boot_mode();
+ u8 boot_dev = BOOT_DEVICE_MMC1;
+
+ switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ /* SD/eSD - BOOT_DEVICE_MMC1 */
+ break;
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+ /* MMC/eMMC */
+ boot_dev = BOOT_DEVICE_MMC2;
+ break;
+ default:
+ /* Default - BOOT_DEVICE_MMC1 */
+ printf("Wrong board boot order\n");
+ break;
+ }
+
+ spl_boot_list[0] = boot_dev;
+}
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
+++ /dev/null
-GEAM6UL BOARD
-M: Jagan Teki <jagan@amarulasolutions.com>
-S: Maintained
-F: board/engicam/geam6ul
-F: include/configs/imx6-engicam.h
-F: configs/imx6ul_geam_mmc_defconfig
-F: configs/imx6ul_geam_nand_defconfig
-F: arch/arm/dts/imx6ul-geam-kit.dts
+++ /dev/null
-How to use U-Boot on Engicam GEAM6UL Starter Kit:
--------------------------------------------------
-
-- Configure U-Boot for Engicam GEAM6UL:
-
-$ make mrproper
-$ make imx6ul_geam_mmc_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot-dtb.img image into the micro SD card:
-
-sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Jumper settings:
-
-MMC Boot: JM3 Closed
-
-- Connect the Serial cable between the Starter Kit and the PC for the console.
-(J28 is the Linux Serial console connector)
-
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
+++ /dev/null
-if TARGET_MX6Q_ICORE_RQS
-
-config SYS_BOARD
- default "icorem6_rqs"
-
-config SYS_VENDOR
- default "engicam"
-
-config SYS_CONFIG_NAME
- default "imx6-engicam"
-
-endif
+++ /dev/null
-ICOREM6QDL_RQS BOARD
-M: Jagan Teki <jagan@amarulasolutions.com>
-S: Maintained
-F: board/engicam/icorem6_rqs
-F: include/configs/imx6-engicam.h
-F: configs/imx6qdl_icore_rqs_defconfig
-F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
-F: arch/arm/dts/imx6q-icore-rqs.dts
-F: arch/arm/dts/imx6dl-icore-rqs.dts
+++ /dev/null
-# Copyright (C) 2016 Amarula Solutions B.V.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := icorem6_rqs.o
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <mmc.h>
-
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <linux/sizes.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
- return devno;
+ return devno - 1;
}
#endif
-void setenv_fdt_file(void)
-{
- if (is_mx6dq())
- env_set("fdt_file", "imx6q-icore-rqs.dtb");
- else if(is_mx6dl() || is_mx6solo())
- env_set("fdt_file", "imx6dl-icore-rqs.dtb");
-}
-
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
-/* MMC board initialization is needed till adding DM support in SPL */
-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
-#include <mmc.h>
-#include <fsl_esdhc.h>
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR, 1, 4},
- {USDHC4_BASE_ADDR, 1, 8},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
- case USDHC4_BASE_ADDR:
- ret = 1;
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC3
- * mmc1 USDHC4
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning - USDHC%d controller not supporting\n",
- i + 1);
- return 0;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = boot_dev;
}
#endif
-#endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
- return 0;
- else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
- return 0;
- else
- return -1;
-}
-#endif
#endif /* CONFIG_SPL_BUILD */
-if TARGET_MX6Q_ICORE
+if TARGET_MX6Q_ENGICAM
config SYS_BOARD
- default "icorem6"
+ default "imx6q"
config SYS_VENDOR
default "engicam"
-ICOREM6QDL BOARD
+MX6Q_ENGICAM BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
-F: board/engicam/icorem6
+F: board/engicam/imx6q
F: include/configs/imx6-engicam.h
F: configs/imx6qdl_icore_mmc_defconfig
F: configs/imx6qdl_icore_nand_defconfig
+F: configs/imx6qdl_icore_rqs_defconfig
F: arch/arm/dts/imx6qdl-icore.dtsi
F: arch/arm/dts/imx6q-icore.dts
F: arch/arm/dts/imx6dl-icore.dts
+F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
+F: arch/arm/dts/imx6q-icore-rqs.dts
+F: arch/arm/dts/imx6dl-icore-rqs.dts
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := geam6ul.o
+obj-y := imx6q.o
-How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
-----------------------------------------------------------------------------------
+Hsow to use U-Boot on Engicam i.CoreM6 (RQS) Solo/DualLite/Quad/Dual Starter Kit:
+--------------------------------------------------------------------------------
$ make mrproper
-- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
+- Configure U-Boot for Engicam i.CoreM6 Quad/Duali/Solo/DualLite:
+$ make imx6qdl_icore_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Duali/Solo/DualLite:
$ make imx6qdl_icore_rqs_defconfig
- Build U-Boot
*/
#include <common.h>
-#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_MXS
-
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-iomux_v3_cfg_t gpmi_pads[] = {
+static iomux_v3_cfg_t gpmi_pads[] = {
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
}
#endif /* CONFIG_VIDEO_IPUV3 */
-void setenv_fdt_file(void)
-{
- if (is_mx6dq())
- env_set("fdt_file", "imx6q-icore.dtb");
- else if(is_mx6dl() || is_mx6solo())
- env_set("fdt_file", "imx6dl-icore.dtb");
-}
-
-#ifdef CONFIG_SPL_BUILD
-/* MMC board initialization is needed till adding DM support in SPL */
-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
-#include <mmc.h>
-#include <fsl_esdhc.h>
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC1
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc1_pads);
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
- default:
- printf("Warning - USDHC%d controller not supporting\n",
- i + 1);
- return 0;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
{
- if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
- return 0;
- else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
- return 0;
- else
- return -1;
+ /* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
+ return (devno == 0) ? 0: (devno - 1);
}
#endif
-#endif /* CONFIG_SPL_BUILD */
-if TARGET_MX6UL_GEAM
+if TARGET_MX6UL_ENGICAM
config SYS_BOARD
- default "geam6ul"
+ default "imx6ul"
config SYS_VENDOR
default "engicam"
-ISIOTMX6UL BOARD
+MX6UL_ENGICAM BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
-F: board/engicam/isiotmx6ul
+F: board/engicam/imx6ul
F: include/configs/imx6-engicam.h
-F: configs/imx6ul_isiot_mmc_defconfig
+F: configs/imx6ul_geam_mmc_defconfig
+F: configs/imx6ul_geam_nand_defconfig
F: configs/imx6ul_isiot_emmc_defconfig
+F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_isiot_nand_defconfig
+F: arch/arm/dts/imx6ul-geam-kit.dts
F: arch/arm/dts/imx6ul-isiot.dtsi
F: arch/arm/dts/imx6ul-isiot-mmc.dts
F: arch/arm/dts/imx6ul-isiot-emmc.dts
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := icorem6.o
+obj-y := imx6ul.o
-How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
------------------------------------------------------------------------------
+Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
+-------------------------------------------------------------------
$ make mrproper
-- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
-$ make imx6qdl_icore_mmc_defconfig
+- Configure U-Boot for Engicam GEAM6UL:
+$ make imx6ul_geam_mmc_defconfig
+
+- Configure U-Boot for Engicam Is.IoT MX6UL:
+$ make imx6ul_isiot_mmc_defconfig
- Build U-Boot
$ make
}
#endif /* CONFIG_NAND_MXS */
-void setenv_fdt_file(void)
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
{
- if (is_mx6ul())
- env_set("fdt_file", "imx6ul-geam-kit.dtb");
+ /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
+ return (devno == 0) ? 0 : 1;
}
-
-#ifdef CONFIG_SPL_BUILD
-/* MMC board initialization is needed till adding DM support in SPL */
-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
-#include <mmc.h>
-#include <fsl_esdhc.h>
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-
- /* VSELECT */
- IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* CD */
- IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* RST_B */
- IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC1
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc1_pads);
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
- default:
- printf("Warning - USDHC%d controller not supporting\n",
- i + 1);
- return 0;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_FSL_ESDHC */
-#endif /* CONFIG_SPL_BUILD */
+#endif
+++ /dev/null
-if TARGET_MX6UL_ISIOT
-
-config SYS_BOARD
- default "isiotmx6ul"
-
-config SYS_VENDOR
- default "engicam"
-
-config SYS_CONFIG_NAME
- default "imx6-engicam"
-
-endif
+++ /dev/null
-# Copyright (C) 2016 Amarula Solutions B.V.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := isiotmx6ul.o
+++ /dev/null
-How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit:
------------------------------------------------------
-
-- Configure U-Boot for Engicam Is.IoT MX6UL
-
-$ make mrproper
-$ make imx6ul_isiot_mmc_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot-dtb.img image into the micro SD card:
-
-sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Jumper settings:
-
-MMC Boot: JM3 Closed
-
-- Connect the Serial cable between the Starter Kit and the PC for the console.
-(J28 is the Linux Serial console connector)
-
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
+++ /dev/null
-/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <linux/sizes.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-#include "../common/board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_NAND_MXS
-
-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
- PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-static iomux_v3_cfg_t const nand_pads[] = {
- IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-};
-
-void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- SETUP_IOMUX_PADS(nand_pads);
-
- clrbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-
- /*
- * config gpmi and bch clock to 100 MHz
- * bch/gpmi select PLL2 PFD2 400M
- * 100M = 400M / 4
- */
- clrbits_le32(&mxc_ccm->cscmr1,
- MXC_CCM_CSCMR1_BCH_CLK_SEL |
- MXC_CCM_CSCMR1_GPMI_CLK_SEL);
- clrsetbits_le32(&mxc_ccm->cscdr1,
- MXC_CCM_CSCDR1_BCH_PODF_MASK |
- MXC_CCM_CSCDR1_GPMI_PODF_MASK,
- (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
- (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif /* CONFIG_NAND_MXS */
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-int board_mmc_get_env_dev(int devno)
-{
- /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
- return (devno == 0) ? 0 : 1;
-}
-#endif
-
-void setenv_fdt_file(void)
-{
- if (is_mx6ul()) {
-#ifdef CONFIG_ENV_IS_IN_MMC
- env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
-#else
- env_set("fdt_file", "imx6ul-isiot-nand.dtb");
-#endif
- }
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-
-/* MMC board initialization is needed till adding DM support in SPL */
-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
-#include <mmc.h>
-#include <fsl_esdhc.h>
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-
- /* VSELECT */
- IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* CD */
- IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* RST_B */
- IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
-#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
-
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC1_BASE_ADDR, 0, 4},
- {USDHC2_BASE_ADDR, 0, 8},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC1
- * mmc1 USDHC2
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc1_pads);
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- default:
- printf("Warning - USDHC%d controller not supporting\n",
- i + 1);
- return 0;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-void board_boot_order(u32 *spl_boot_list)
-{
- u32 bmode = imx6_src_get_boot_mode();
- u8 boot_dev = BOOT_DEVICE_MMC1;
-
- switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
- case IMX6_BMODE_SD:
- case IMX6_BMODE_ESD:
- /* SD/eSD - BOOT_DEVICE_MMC1 */
- break;
- case IMX6_BMODE_MMC:
- case IMX6_BMODE_EMMC:
- /* MMC/eMMC */
- boot_dev = BOOT_DEVICE_MMC2;
- break;
- default:
- /* Default - BOOT_DEVICE_MMC1 */
- printf("Wrong board boot order\n");
- break;
- }
-
- spl_boot_list[0] = boot_dev;
-}
-#endif
-#endif /* CONFIG_FSL_ESDHC */
-#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 17, BOOKE_PAGESZ_2G, 1)
#endif
};
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
/* Initialize i2c early for Serial flash bank information */
i2c_set_bus_num(0);
- if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+ if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
puts("Version");
- if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+ switch (in1 & SW_REV_MASK) {
+ case SW_REV_A:
puts(": RevA");
- else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+ break;
+ case SW_REV_B:
puts(": RevB");
- else
+ break;
+ case SW_REV_C:
+ puts(": RevC");
+ break;
+ case SW_REV_C1:
+ puts(": RevC1");
+ break;
+ case SW_REV_C2:
+ puts(": RevC2");
+ break;
+ case SW_REV_D:
+ puts(": RevD");
+ break;
+ case SW_REV_E:
+ puts(": RevE");
+ break;
+ default:
puts(": unknown");
+ break;
+ }
printf(", boot from QSPI");
- if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+ if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
puts(": emu\n");
- else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+ else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
puts(": bank1\n");
- else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+ else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
puts(": bank2\n");
else
puts("unknown\n");
int esdhc_status_fixup(void *blob, const char *compat)
{
- char esdhc0_path[] = "/soc/esdhc@1560000";
char esdhc1_path[] = "/soc/esdhc@1580000";
- u8 io = 0;
+ bool sdhc2_en = false;
u8 mux_sdhc2;
-
- do_fixup_by_path(blob, esdhc0_path, "status", "okay",
- sizeof("okay"), 1);
+ u8 io = 0;
i2c_set_bus_num(0);
- /*
- * The I2C IO-expander for mux select is used to control the muxing
- * of various onboard interfaces.
- *
- * IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
- * 00 - SDIO wifi
- * 01 - GPIO (to Arduino)
- * 10 - eMMC Memory
- * 11 - SPI
- */
- if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
+ /* IO1[7:3] is the field of board revision info. */
+ if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
printf("Error reading i2c boot information!\n");
- return 0; /* Don't want to hang() on this error */
+ return 0;
+ }
+
+ /* hwconfig method is used for RevD and later versions. */
+ if ((io & SW_REV_MASK) <= SW_REV_D) {
+#ifdef CONFIG_HWCONFIG
+ if (hwconfig("esdhc1"))
+ sdhc2_en = true;
+#endif
+ } else {
+ /*
+ * The I2C IO-expander for mux select is used to control
+ * the muxing of various onboard interfaces.
+ *
+ * IO0[3:2] indicates SDHC2 interface demultiplexer
+ * select lines.
+ * 00 - SDIO wifi
+ * 01 - GPIO (to Arduino)
+ * 10 - eMMC Memory
+ * 11 - SPI
+ */
+ if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0;
+ }
+
+ mux_sdhc2 = (io & 0x0c) >> 2;
+ /* Enable SDHC2 only when use SDIO wifi and eMMC */
+ if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+ sdhc2_en = true;
}
- mux_sdhc2 = (io & 0x0c) >> 2;
- /* Enable SDHC2 only when use SDIO wifi and eMMC */
- if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+ if (sdhc2_en)
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
sizeof("okay"), 1);
else
config SYS_CONFIG_NAME
default "ls1088aqds"
+source "board/freescale/common/Kconfig"
endif
if TARGET_LS1088ARDB
config SYS_CONFIG_NAME
default "ls1088ardb"
+source "board/freescale/common/Kconfig"
endif
F: include/configs/ls1088aqds.h
F: configs/ls1088aqds_qspi_defconfig
F: configs/ls1088aqds_sdcard_qspi_defconfig
+
+LS1088AQDS_QSPI_SECURE_BOOT BOARD
+M: Udit Agarwal <udit.agarwal@nxp.com>
+M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
+S: Maintained
+F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_QSPI_SECURE_BOOT BOARD
+M: Udit Agarwal <udit.agarwal@nxp.com>
+M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
+S: Maintained
+F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
#include <environment.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_TARGET_LS1088ARDB
+ u8 brdcfg5;
+
+ if (hwconfig("esdhc-force-sd")) {
+ brdcfg5 = QIXIS_READ(brdcfg[5]);
+ brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
+ brdcfg5 |= BRDCFG5_FORCE_SD;
+ QIXIS_WRITE(brdcfg[5], brdcfg5);
+ }
+#endif
+ return 0;
+}
+#endif
+
int board_init(void)
{
init_final_memctl_regs();
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
return 0;
}
#endif
return;
}
- if (get_mc_boot_status() == 0)
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
+void fsl_fdt_fixup_flash(void *fdt)
+{
+ int offset;
+
+/*
+ * IFC-NOR and QSPI are muxed on SoC.
+ * So disable IFC node in dts if QSPI is enabled or
+ * disable QSPI node in dts in case QSPI is not enabled.
+ */
+
+#ifdef CONFIG_FSL_QSPI
+ offset = fdt_path_offset(fdt, "/soc/ifc/nor");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/ifc/nor");
+#else
+ offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/quadspi");
+#endif
+ if (offset < 0)
+ return;
+
+ fdt_status_disabled(fdt, offset);
+}
+
int ft_board_setup(void *blob, bd_t *bd)
{
int err, i;
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ fsl_fdt_fixup_flash(blob);
+
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
err = fsl_mc_ldpaa_exit(bd);
#define BRDCFG9_SFPTX_MASK 0x10
#define BRDCFG9_SFPTX_SHIFT 4
+/* Definitions of QIXIS Registers for LS1088ARDB */
+
+/* BRDCFG5 */
+#define BRDCFG5_SPISDHC_MASK 0x0C
+#define BRDCFG5_FORCE_SD 0x08
+
#endif
return;
}
- if (get_mc_boot_status() == 0)
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
return;
}
- if (get_mc_boot_status() == 0)
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
return;
}
- if (get_mc_boot_status() == 0)
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
* 0xf000_0000 64M LBC SDRAM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 2, BOOKE_PAGESZ_64M, 1),
/*
* 0xf000_0000 64M LBC SDRAM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 4, BOOKE_PAGESZ_64M, 1),
/*
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_SYS_RAMBOOT
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_256M, 1),
#endif
};
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
};
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 18, BOOKE_PAGESZ_2G, 1)
#endif
};
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_533, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
#ifdef CONFIG_SYS_RAMBOOT
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 6, BOOKE_PAGESZ_1G, 1),
#endif
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := bx50v3.o vpd_reader.o
+obj-y := bx50v3.o
#include <input.h>
#include <pwm.h>
#include <stdlib.h>
-#include "vpd_reader.h"
+#include "../common/vpd_reader.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
+++ /dev/null
-/*
- * Copyright 2016 General Electric Company
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "vpd_reader.h"
-
-#include <linux/bch.h>
-#include <stdlib.h>
-
-
-/* BCH configuration */
-
-const struct {
- int header_ecc_capability_bits;
- int data_ecc_capability_bits;
- unsigned int prim_poly;
- struct {
- int min;
- int max;
- } galois_field_order;
-} bch_configuration = {
- .header_ecc_capability_bits = 4,
- .data_ecc_capability_bits = 16,
- .prim_poly = 0,
- .galois_field_order = {
- .min = 5,
- .max = 15,
- },
-};
-
-static int calculate_galois_field_order(size_t source_length)
-{
- int gfo = bch_configuration.galois_field_order.min;
-
- for (; gfo < bch_configuration.galois_field_order.max &&
- ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
- gfo++) {
- }
-
- if (gfo == bch_configuration.galois_field_order.max) {
- return -1;
- }
-
- return gfo + 1;
-}
-
-static int verify_bch(int ecc_bits, unsigned int prim_poly,
- uint8_t * data, size_t data_length,
- const uint8_t * ecc, size_t ecc_length)
-{
- int gfo = calculate_galois_field_order(data_length);
- if (gfo < 0) {
- return -1;
- }
-
- struct bch_control * bch = init_bch(gfo, ecc_bits, prim_poly);
- if (!bch) {
- return -1;
- }
-
- if (bch->ecc_bytes != ecc_length) {
- free_bch(bch);
- return -1;
- }
-
- unsigned * errloc = (unsigned *)calloc(data_length, sizeof(unsigned));
- int errors = decode_bch(
- bch, data, data_length, ecc, NULL, NULL, errloc);
- free_bch(bch);
- if (errors < 0) {
- free(errloc);
- return -1;
- }
-
- if (errors > 0) {
- for (int n = 0; n < errors; n++) {
- if (errloc[n] >= 8 * data_length) {
- /* n-th error located in ecc (no need for data correction) */
- } else {
- /* n-th error located in data */
- data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
- }
- }
- }
-
- free(errloc);
- return 0;
-}
-
-
-static const int ID = 0;
-static const int LEN = 1;
-static const int VER = 2;
-static const int TYP = 3;
-static const int BLOCK_SIZE = 4;
-
-static const uint8_t HEADER_BLOCK_ID = 0x00;
-static const uint8_t HEADER_BLOCK_LEN = 18;
-static const uint32_t HEADER_BLOCK_MAGIC = 0xca53ca53;
-static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
-static const size_t HEADER_BLOCK_ECC_OFF = 14;
-static const size_t HEADER_BLOCK_ECC_LEN = 4;
-
-static const uint8_t ECC_BLOCK_ID = 0xFF;
-
-int vpd_reader(
- size_t size,
- uint8_t * data,
- void * userdata,
- int (*fn)(
- void * userdata,
- uint8_t id,
- uint8_t version,
- uint8_t type,
- size_t size,
- uint8_t const * data))
-{
- if ( size < HEADER_BLOCK_LEN
- || data == NULL
- || fn == NULL) {
- return -EINVAL;
- }
-
- /*
- * +--------------------+--------------------+--//--+--------------------+
- * | header block | data block | ... | ecc block |
- * +--------------------+--------------------+--//--+--------------------+
- * : : :
- * +------+-------+-----+ +------+-------------+
- * | id | magic | ecc | | ... | ecc |
- * | len | off | | +------+-------------+
- * | ver | size | | :
- * | type | | | :
- * +------+-------+-----+ :
- * : : : :
- * <----- [1] ----> <----------- [2] ----------->
- *
- * Repair (if necessary) the contents of header block [1] by using a
- * 4 byte ECC located at the end of the header block. A successful
- * return value means that we can trust the header.
- */
- int ret = verify_bch(
- bch_configuration.header_ecc_capability_bits,
- bch_configuration.prim_poly,
- data,
- HEADER_BLOCK_VERIFY_LEN,
- &data[HEADER_BLOCK_ECC_OFF],
- HEADER_BLOCK_ECC_LEN);
- if (ret < 0) {
- return ret;
- }
-
- /* Validate header block { id, length, version, type }. */
- if ( data[ID] != HEADER_BLOCK_ID
- || data[LEN] != HEADER_BLOCK_LEN
- || data[VER] != 0
- || data[TYP] != 0
- || ntohl(*(uint32_t *)(&data[4])) != HEADER_BLOCK_MAGIC) {
- return -EINVAL;
- }
-
- uint32_t offset = ntohl(*(uint32_t *)(&data[8]));
- uint16_t size_bits = ntohs(*(uint16_t *)(&data[12]));
-
- /* Check that ECC header fits. */
- if (offset + 3 >= size) {
- return -EINVAL;
- }
-
- /* Validate ECC block. */
- uint8_t * ecc = &data[offset];
- if ( ecc[ID] != ECC_BLOCK_ID
- || ecc[LEN] < BLOCK_SIZE
- || ecc[LEN] + offset > size
- || ecc[LEN] - BLOCK_SIZE != size_bits / 8
- || ecc[VER] != 1
- || ecc[TYP] != 1) {
- return -EINVAL;
- }
-
- /*
- * Use the header block to locate the ECC block and verify the data
- * blocks [2] against the ecc block ECC.
- */
- ret = verify_bch(
- bch_configuration.data_ecc_capability_bits,
- bch_configuration.prim_poly,
- &data[data[LEN]],
- offset - data[LEN],
- &data[offset + BLOCK_SIZE],
- ecc[LEN] - BLOCK_SIZE);
- if (ret < 0) {
- return ret;
- }
-
- /* Stop after ECC. Ignore possible zero padding. */
- size = offset;
-
- for (;;) {
- /* Move to next block. */
- size -= data[LEN];
- data += data[LEN];
-
- if (size == 0) {
- /* Finished iterating through blocks. */
- return 0;
- }
-
- if ( size < BLOCK_SIZE
- || data[LEN] < BLOCK_SIZE) {
- /* Not enough data for a header, or short header. */
- return -EINVAL;
- }
-
- ret = fn(
- userdata,
- data[ID],
- data[VER],
- data[TYP],
- data[LEN] - BLOCK_SIZE,
- &data[BLOCK_SIZE]);
- if (ret) {
- return ret;
- }
- }
-}
--- /dev/null
+#
+# Copyright 2017 General Electric Company
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vpd_reader.o
--- /dev/null
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "vpd_reader.h"
+
+#include <linux/bch.h>
+#include <stdlib.h>
+
+/* BCH configuration */
+
+const struct {
+ int header_ecc_capability_bits;
+ int data_ecc_capability_bits;
+ unsigned int prim_poly;
+ struct {
+ int min;
+ int max;
+ } galois_field_order;
+} bch_configuration = {
+ .header_ecc_capability_bits = 4,
+ .data_ecc_capability_bits = 16,
+ .prim_poly = 0,
+ .galois_field_order = {
+ .min = 5,
+ .max = 15,
+ },
+};
+
+static int calculate_galois_field_order(size_t source_length)
+{
+ int gfo = bch_configuration.galois_field_order.min;
+
+ for (; gfo < bch_configuration.galois_field_order.max &&
+ ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
+ gfo++) {
+ }
+
+ if (gfo == bch_configuration.galois_field_order.max)
+ return -1;
+
+ return gfo + 1;
+}
+
+static int verify_bch(int ecc_bits, unsigned int prim_poly, u8 *data,
+ size_t data_length, const u8 *ecc, size_t ecc_length)
+{
+ int gfo = calculate_galois_field_order(data_length);
+
+ if (gfo < 0)
+ return -1;
+
+ struct bch_control *bch = init_bch(gfo, ecc_bits, prim_poly);
+
+ if (!bch)
+ return -1;
+
+ if (bch->ecc_bytes != ecc_length) {
+ free_bch(bch);
+ return -1;
+ }
+
+ unsigned int *errloc = (unsigned int *)calloc(data_length,
+ sizeof(unsigned int));
+ int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL,
+ errloc);
+
+ free_bch(bch);
+ if (errors < 0) {
+ free(errloc);
+ return -1;
+ }
+
+ if (errors > 0) {
+ for (int n = 0; n < errors; n++) {
+ if (errloc[n] >= 8 * data_length) {
+ /*
+ * n-th error located in ecc (no need for data
+ * correction)
+ */
+ } else {
+ /* n-th error located in data */
+ data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
+ }
+ }
+ }
+
+ free(errloc);
+ return 0;
+}
+
+static const int ID;
+static const int LEN = 1;
+static const int VER = 2;
+static const int TYP = 3;
+static const int BLOCK_SIZE = 4;
+
+static const u8 HEADER_BLOCK_ID;
+static const u8 HEADER_BLOCK_LEN = 18;
+static const u32 HEADER_BLOCK_MAGIC = 0xca53ca53;
+static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
+static const size_t HEADER_BLOCK_ECC_OFF = 14;
+static const size_t HEADER_BLOCK_ECC_LEN = 4;
+
+static const u8 ECC_BLOCK_ID = 0xFF;
+
+int vpd_reader(size_t size, u8 *data, void *userdata,
+ int (*fn)(void *userdata, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data))
+{
+ if (size < HEADER_BLOCK_LEN || !data || !fn)
+ return -EINVAL;
+
+ /*
+ * +--------------------+----------------+--//--+--------------------+
+ * | header block | data block | ... | ecc block |
+ * +--------------------+----------------+--//--+--------------------+
+ * : : :
+ * +------+-------+-----+ +------+-------------+
+ * | id | magic | ecc | | ... | ecc |
+ * | len | off | | +------+-------------+
+ * | ver | size | | :
+ * | type | | | :
+ * +------+-------+-----+ :
+ * : : : :
+ * <----- [1] ----> <--------- [2] --------->
+ *
+ * Repair (if necessary) the contents of header block [1] by using a
+ * 4 byte ECC located at the end of the header block. A successful
+ * return value means that we can trust the header.
+ */
+ int ret = verify_bch(bch_configuration.header_ecc_capability_bits,
+ bch_configuration.prim_poly, data,
+ HEADER_BLOCK_VERIFY_LEN,
+ &data[HEADER_BLOCK_ECC_OFF], HEADER_BLOCK_ECC_LEN);
+ if (ret < 0)
+ return ret;
+
+ /* Validate header block { id, length, version, type }. */
+ if (data[ID] != HEADER_BLOCK_ID || data[LEN] != HEADER_BLOCK_LEN ||
+ data[VER] != 0 || data[TYP] != 0 ||
+ ntohl(*(u32 *)(&data[4])) != HEADER_BLOCK_MAGIC)
+ return -EINVAL;
+
+ u32 offset = ntohl(*(u32 *)(&data[8]));
+ u16 size_bits = ntohs(*(u16 *)(&data[12]));
+
+ /* Check that ECC header fits. */
+ if (offset + 3 >= size)
+ return -EINVAL;
+
+ /* Validate ECC block. */
+ u8 *ecc = &data[offset];
+
+ if (ecc[ID] != ECC_BLOCK_ID || ecc[LEN] < BLOCK_SIZE ||
+ ecc[LEN] + offset > size ||
+ ecc[LEN] - BLOCK_SIZE != size_bits / 8 || ecc[VER] != 1 ||
+ ecc[TYP] != 1)
+ return -EINVAL;
+
+ /*
+ * Use the header block to locate the ECC block and verify the data
+ * blocks [2] against the ecc block ECC.
+ */
+ ret = verify_bch(bch_configuration.data_ecc_capability_bits,
+ bch_configuration.prim_poly, &data[data[LEN]],
+ offset - data[LEN], &data[offset + BLOCK_SIZE],
+ ecc[LEN] - BLOCK_SIZE);
+ if (ret < 0)
+ return ret;
+
+ /* Stop after ECC. Ignore possible zero padding. */
+ size = offset;
+
+ for (;;) {
+ /* Move to next block. */
+ size -= data[LEN];
+ data += data[LEN];
+
+ if (size == 0) {
+ /* Finished iterating through blocks. */
+ return 0;
+ }
+
+ if (size < BLOCK_SIZE || data[LEN] < BLOCK_SIZE) {
+ /* Not enough data for a header, or short header. */
+ return -EINVAL;
+ }
+
+ ret = fn(userdata, data[ID], data[VER], data[TYP],
+ data[LEN] - BLOCK_SIZE, &data[BLOCK_SIZE]);
+ if (ret)
+ return ret;
+ }
+}
*
* Returns Non-zero on error. Negative numbers encode errno.
*/
-int vpd_reader(
- size_t size,
- uint8_t * data,
- void * userdata,
- int (*fn)(
- void * userdata,
- uint8_t id,
- uint8_t version,
- uint8_t type,
- size_t size,
- uint8_t const * data));
+int vpd_reader(size_t size, u8 *data, void *userdata,
+ int (*fn)(void *userdata, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data));
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+if TARGET_MX53PPD
+
+config SYS_BOARD
+ default "mx53ppd"
+
+config SYS_VENDOR
+ default "ge"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53ppd"
+
+endif
--- /dev/null
+MX53PPD BOARD
+M: Antti Mäentausta <antti.maentausta@ge.com>
+M: Martyn Welch <martyn.welch@collabora.co.uk>
+S: Maintained
+F: board/freescale/mx53ppd/
+F: include/configs/mx53ppd.h
+F: configs/mx53ppd_defconfig
--- /dev/null
+# Copyright 2017 General Electric Company
+#
+# Based on board/freescale/mx53loco/Makefile:
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx53ppd.o
+obj-$(CONFIG_VIDEO) += mx53ppd_video.o
--- /dev/null
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/imximage.cfg:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8004 0x00194005
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x85190000
+DATA 4 0x63fd900c 0x8b8f52e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x008f0e21
+DATA 4 0x63fd9008 0x09333030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00468031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00011110
+DATA 4 0x63fd901c 0x00000000
--- /dev/null
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco.c:
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <watchdog.h>
+#include "ppd_gpio.h"
+#include <stdlib.h>
+#include "../../ge/common/vpd_reader.h"
+#include <rtc.h>
+
+#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
+#define VPD_EEPROM_BUS 2
+
+/* Address of 24C08 EEPROM. */
+#define VPD_EEPROM_ADDR 0x50
+#define VPD_EEPROM_ADDR_LEN 1
+
+static u32 mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev() & ~(0xF << 8);
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ /* request VBUS power enable pin, GPIO7_8 */
+ imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+ gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+ return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
+ PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC3_BASE_ADDR},
+ {MMC_SDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11,
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
+ .gp = IMX_GPIO_NR(3, 28)
+ },
+ .sda = {
+ .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
+ .gp = IMX_GPIO_NR(3, 21)
+ }
+};
+
+static int clock_1GHz(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+ */
+ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+ if (ret) {
+ printf("CPU: Switch CPU clock to 1GHZ failed\n");
+ return -1;
+ }
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret) {
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+void ppd_gpio_init(void)
+{
+ int i;
+
+ imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
+ for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
+ gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_fec();
+ setup_iomux_lcd();
+ ppd_gpio_init();
+
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_PRODUCT_PPD 4
+#define VPD_HAS_MAC1 0x1
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+struct vpd_cache {
+ u8 product_id;
+ u8 has;
+ unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
+ u8 const *data)
+{
+ struct vpd_cache *vpd = (struct vpd_cache *)userdata;
+
+ if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
+ size >= 1) {
+ vpd->product_id = data[0];
+
+ } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
+ type != VPD_TYPE_INVALID) {
+ if (size >= 6) {
+ vpd->has |= VPD_HAS_MAC1;
+ memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+ }
+ }
+
+ return 0;
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+ int fec_index = -1;
+
+ if (vpd->product_id == VPD_PRODUCT_PPD)
+ fec_index = 0;
+
+ if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
+ eth_env_set_enetaddr("ethaddr", vpd->mac1);
+}
+
+static int read_vpd(uint eeprom_bus)
+{
+ struct vpd_cache vpd;
+ int res;
+ int size = 1024;
+ u8 *data;
+ unsigned int current_i2c_bus = i2c_get_bus_num();
+
+ res = i2c_set_bus_num(eeprom_bus);
+ if (res < 0)
+ return res;
+
+ data = malloc(size);
+ if (!data)
+ return -ENOMEM;
+
+ res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
+ if (res == 0) {
+ memset(&vpd, 0, sizeof(vpd));
+ vpd_reader(size, data, &vpd, vpd_callback);
+ process_vpd(&vpd);
+ }
+
+ free(data);
+
+ i2c_set_bus_num(current_i2c_bus);
+ return res;
+}
+
+static void check_time(void)
+{
+ int ret, i;
+ struct rtc_time tm;
+ u8 retry = 3;
+
+ unsigned int current_i2c_bus = i2c_get_bus_num();
+
+ ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+ if (ret < 0)
+ return;
+
+ rtc_init();
+
+ for (i = 0; i < retry; i++) {
+ ret = rtc_get(&tm);
+ if (!ret || ret == -EINVAL)
+ break;
+ }
+
+ if (ret < 0)
+ env_set("rtc_status", "RTC_ERROR");
+
+ if (tm.tm_year > 2037) {
+ tm.tm_sec = 0;
+ tm.tm_min = 0;
+ tm.tm_hour = 0;
+ tm.tm_mday = 1;
+ tm.tm_wday = 2;
+ tm.tm_mon = 1;
+ tm.tm_year = 2036;
+
+ for (i = 0; i < retry; i++) {
+ ret = rtc_set(&tm);
+ if (!ret)
+ break;
+ }
+
+ if (ret < 0)
+ env_set("rtc_status", "RTC_ERROR");
+ }
+
+ i2c_set_bus_num(current_i2c_bus);
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ mxc_set_sata_internal_clock();
+ setup_iomux_i2c();
+
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ const char *cause;
+
+ /* We care about WDOG only, treating everything else as
+ * a power-on-reset.
+ */
+ if (get_imx_reset_cause() & 0x0010)
+ cause = "WDOG";
+ else
+ cause = "POR";
+
+ env_set("bootcause", cause);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ int res;
+
+ read_vpd(VPD_EEPROM_BUS);
+
+ res = clock_1GHz();
+ if (res != 0)
+ return res;
+
+ print_cpuinfo();
+ hw_watchdog_init();
+
+ check_time();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: GE PPD\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * Based on board/freescale/mx53loco/mx53loco_video.c:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <pwm.h>
+#include "ppd_gpio.h"
+
+#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
+
+static struct fb_videomode const nv_spwg = {
+ .name = "NV-SPWGRGB888",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 15384,
+ .left_margin = 16,
+ .right_margin = 210,
+ .upper_margin = 10,
+ .lower_margin = 22,
+ .hsync_len = 30,
+ .vsync_len = 13,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+static void lcd_enable(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
+ clrsetbits_le32(&mxc_ccm->cscmr2,
+ MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
+ MXC_CCM_CSCMR2_DI0_CLK_SEL(
+ MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
+
+ /* Turn on IPU DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
+
+ /* Configure LDB */
+ writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ /* Enable backlights */
+ pwm_init(1, 0, 0);
+
+ /* duty cycle 5000000ns, period: 5000000ns */
+ pwm_config(1, 5000000, 5000000);
+
+ /* Backlight Power */
+ gpio_direction_output(BACKLIGHT_ENABLE, 1);
+
+ pwm_enable(1);
+}
+
+static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ lcd_enable();
+ return 0;
+}
+
+U_BOOT_CMD(
+ ppd_lcd_enable, 1, 1, do_lcd_enable,
+ "enable PPD LCD",
+ "no parameters"
+);
+
+int board_video_skip(void)
+{
+ int ret;
+
+ ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("Display cannot be configured: %d\n", ret);
+
+ return ret;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 General Electric Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PPD_GPIO_H_
+#define __PPD_GPIO_H_
+
+#include <asm/arch/iomux-mx53.h>
+#include <asm/gpio.h>
+
+#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+
+static const iomux_v3_cfg_t ppd_pads[] = {
+ /* FEC */
+ MX53_PAD_EIM_A22__GPIO2_16,
+ /* UART */
+ NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
+ /* Video */
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
+ MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
+ MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */
+ MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */
+ MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */
+ MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
+ MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */
+ MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */
+ /* I2C */
+ MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */
+
+ /* SPI */
+ MX53_PAD_DISP0_DAT23__GPIO5_17,
+ MX53_PAD_KEY_COL2__GPIO4_10,
+ MX53_PAD_KEY_ROW2__GPIO4_11,
+ MX53_PAD_KEY_COL3__GPIO4_12,
+};
+
+struct gpio_cfg {
+ unsigned int gpio;
+ int value;
+};
+
+#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
+#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
+#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
+#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
+#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
+#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
+#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
+#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
+#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
+#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
+#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
+#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
+#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
+#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
+#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
+#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
+#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
+#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
+
+static const struct gpio_cfg ppd_gpios[] = {
+ /* FEC */
+ /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
+ /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
+ { RESET_IMX535_ETHERNET_PHY_N, 0 },
+ { RESET_IMX535_ETHERNET_PHY_N, 1 },
+ /* Video */
+ { UD_SCAN_CTRL, 0 },
+ { LR_SCAN_CTRL, 1 },
+#ifdef PROPRIETARY_CHANGES
+ { LVDS0_MUX_CTRL, 1 },
+#else
+ { LVDS0_MUX_CTRL, 0 },
+#endif
+ { LVDS1_MUX_CTRL, 1 },
+ { HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
+ { DATA_WIDTH_CTRL, 0 },
+ { RESET_DP0_TRANSMITTER_N, 1 },
+ { RESET_DP1_TRANSMITTER_N, 1 },
+ { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
+ { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
+ { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
+ { BACKLIGHT_ENABLE, 0 },
+ { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
+ { ECSPI1_CS0, 1 },
+ { ECSPI1_CS1, 1 },
+ { ECSPI1_CS2, 1 },
+ { ECSPI1_CS3, 1 },
+};
+
+#endif /* __PPD_GPIO_H_ */
BOSTON BOARD
-M: Paul Burton <paul.burton@imgtec.com>
+M: Paul Burton <paul.burton@mips.com>
S: Maintained
F: board/imgtec/boston/
F: include/configs/boston.h
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -$2 $< -binary -offset $3
+
+u-boot.mcs: u-boot.bin
+ $(call cmd,srec_cat,intel,0x7c00000)
+
+# if srec_cat is present build u-boot.mcs by default
+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
+ALL-$(has_srec_cat) += u-boot.mcs
+CLEAN_FILES += u-boot.mcs
PTR_LA a0, msg_ddr_ok
bal lowlevel_display
- move v0, zero
jr s0
END(lowlevel_init)
sw k1, 4(AT)
#endif
.set pop
-1: jr ra
+ jr ra
END(lowlevel_display)
MALTA BOARD
-M: Paul Burton <paul.burton@imgtec.com>
+M: Paul Burton <paul.burton@mips.com>
S: Maintained
F: board/imgtec/malta/
F: include/configs/malta.h
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* Setup code for the FDC37M817 super I/O controller
*
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* Setup code for the FDC37M817 super I/O controller
*
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <jffs2/load_kernel.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include "igep00x0.h"
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/onenand.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <jffs2/load_kernel.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include "igep00x0.h"
/*
--- /dev/null
+if TARGET_WB45N
+
+config SYS_BOARD
+ default "wb45n"
+
+config SYS_VENDOR
+ default "laird"
+
+config SYS_CONFIG_NAME
+ default "wb45n"
+
+endif
--- /dev/null
+WB45N CPU MODULE
+M: Ben Whitten <ben.whitten@lairdtech.com>
+S: Maintained
+F: board/laird/wb45n/
+F: include/configs/wb45n.h
+F: configs/wb45n_defconfig
--- /dev/null
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb45n.o
--- /dev/null
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+static void wb45n_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ csa = readl(&matrix->ebicsa);
+ /* Enable CS3 */
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* NAND flash on D0 */
+ csa &= ~AT91_MATRIX_NFD0_ON_D16;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Disable Flash Write Protect Line */
+ at91_set_gpio_output(AT91_PIN_PD10, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+}
+
+static void wb45n_gpio_hw_init(void)
+{
+
+ /* Configure wifi gpio CHIP_PWD_L */
+ at91_set_gpio_output(AT91_PIN_PA28, 0);
+
+ /* Setup USB pins */
+ at91_set_gpio_input(AT91_PIN_PB11, 0);
+ at91_set_gpio_output(AT91_PIN_PB12, 0);
+
+ /* IRQ pin, pullup, deglitch */
+ at91_set_gpio_input(AT91_PIN_PB18, 1);
+ at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ if (has_emac0())
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+
+ return rc;
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ wb45n_gpio_hw_init();
+
+ wb45n_nand_hw_init();
+
+ at91_macb_hw_init();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+ /* Setup GPIO first */
+ wb45n_gpio_hw_init();
+
+ /* Bring up NAND */
+ wb45n_nand_hw_init();
+}
+
+void matrix_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ csa = readl(&matrix->ebicsa);
+ /* Pull ups on D0 - D16 */
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ /* Normal drive strength */
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ /* Multi-port off */
+ csa &= ~AT91_MATRIX_MP_ON;
+ writel(csa, &matrix->ebicsa);
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_DQMS_SHARED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddrc_config ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ at91_system_clk_enable(AT91_PMC_DDR);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
--- /dev/null
+if TARGET_WB50N
+
+config SYS_BOARD
+ default "wb50n"
+
+config SYS_VENDOR
+ default "laird"
+
+config SYS_CONFIG_NAME
+ default "wb50n"
+
+endif
--- /dev/null
+WB50N CPU MODULE
+M: Ben Whitten <ben.whitten@lairdtech.com>
+S: Maintained
+F: board/laird/wb50n/
+F: include/configs/wb50n.h
+F: configs/wb50n_defconfig
--- /dev/null
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb50n.o
--- /dev/null
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <micrel.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void wb50n_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+ AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+ AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
+
+ /* Disable Flash Write Protect Line */
+ at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ wb50n_nand_hw_init();
+
+ at91_macb_hw_init();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
+ /* tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
+ /* rx/tx clock delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+
+ return rc;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+#include <linux/ctype.h>
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ const char *LAIRD_NAME = "lrd_name";
+ char name[32], *p;
+
+ strcpy(name, get_cpu_name());
+ for (p = name; *p != '\0'; *p = tolower(*p), p++)
+ ;
+ strcat(name, "-wb50n");
+ env_set(LAIRD_NAME, name);
+
+#endif
+
+ return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ wb50n_nand_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NDQS_DISABLED |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ struct atmel_mpddrc_config ddr2;
+
+ ddr2_conf(&ddr2);
+
+ writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
+ &sfr->ddrcfg);
+
+ /* enable MPDDR clock */
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ at91_system_clk_enable(AT91_PMC_DDR);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+ tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
make distclean
make omap3_logic_defconfig
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem. In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # fatload mmc 0 ${loadaddr} uImage
+U-Boot # run loadfdt
+U-Boot # setenv optargs quiet
+U-Boot # run mmcargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+ Loading Device Tree to 8dec9000, end 8dee0295 ... OK
+
+So then note the starting address and write the args to mmc/sd:
+
+U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000
+
+The size of 0x20000 matches the CMD_SPL_WRITE_SIZE.
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND. In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as filesystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/omap_musb.h>
#include <linux/errno.h>
#include <linux/usb/ch9.h>
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
+
+#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
+#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
+#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
+
+void spl_board_prepare_for_linux(void)
+{
+ /* The Micron NAND starts locked which
+ * prohibits mounting the NAND as RW
+ * The following commands are what unlocks
+ * the NAND to become RW Falcon Mode does not
+ * have as many smarts as U-Boot, but Logic PD
+ * only makes NAND with 512MB so these hard coded
+ * values should work for all current models
+ */
+
+ writeb(0x70, GPMC_NAND_COMMAND_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(0x7a, GPMC_NAND_COMMAND_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_COMMAND_0);
+
+ /* Begin address 0 */
+ writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+
+ /* Ending address at the end of Flash */
+ writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
+ writeb(0xc0, GPMC_NAND_ADDRESS_0);
+ writeb(0xff, GPMC_NAND_ADDRESS_0);
+ writeb(0x03, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(0x79, GPMC_NAND_COMMAND_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+}
#endif
#ifdef CONFIG_USB_MUSB_OMAP2PLUS
}
#ifdef CONFIG_BOARD_LATE_INIT
+
+static void unlock_nand(void)
+{
+ int dev = nand_curr_device;
+ struct mtd_info *mtd;
+
+ mtd = get_nand_dev_by_index(dev);
+ nand_unlock(mtd, 0, mtd->size, 0);
+}
+
int board_late_init(void)
{
struct board_id *board;
/* restore hsusb0_data5 pin as hsusb0_data5 */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+ unlock_nand();
+#endif
return 0;
}
#endif
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
--- /dev/null
+ZYNQ BOARD
+M: Tom McLeod <tom.mcleod@opalkelly.com>
+S: Maintained
+F: board/opalkelly/zynq/
+F: include/configs/syzygy_hub.h
+F: configs/syzygy_hub_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
--- /dev/null
+#include "../../xilinx/zynq/board.c"
--- /dev/null
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+* (c) Copyright 2017 Opal Kelly Inc.
+*
+* SPDX-License-Identifier: GPL-2.0+
+ *****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC044DU),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00029000U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00029000U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029000U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00029000U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F9U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F9U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000F9U),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F9U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U, 0x00001201U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002E0037U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF0000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+ EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+ EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0XF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+unsigned long ps7_reset_apu_3_0[] = {
+ EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
+ EMIT_EXIT(),
+};
+
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_reset_apu_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
+
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
DTB_DIR "bcm2835-rpi-zero.dtb",
false,
},
+ [0xC] = {
+ "Zero W",
+ DTB_DIR "bcm2835-rpi-zero-w.dtb",
+ false,
+ },
};
static const struct rpi_model rpi_models_old_scheme[] = {
--- /dev/null
+if TARGET_DRAAK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "draak"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "draak"
+
+endif
--- /dev/null
+DRAAK BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/draak/
+F: include/configs/draak.h
+F: configs/r8a77995_draak_defconfig
--- /dev/null
+#
+# board/renesas/draak/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := draak.o
--- /dev/null
+/*
+ * board/renesas/draak/draak.c
+ * This file is Draak board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR 0xE6150904
+#define CPGWPR 0xE615090C
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ writel(0xA5A50000, CPGWPCR);
+ writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112 BIT(12) /* 3DG */
+#define TMU0_MSTP125 BIT(25) /* secure */
+#define TMU1_MSTP124 BIT(24) /* non-secure */
+#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
+#define DVFS_MSTP926 BIT(26)
+#define HSUSB_MSTP704 BIT(4) /* HSUSB */
+
+int board_early_init_f(void)
+{
+ /* TMU0,1 */ /* which use ? */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+ /* DVFS for reset */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+ return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define SYSC_PWRSR2 0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define SYSC_PWRONCR2 0xE618010C
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS 0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
+#define HSUSB_REG_UGCTRL2 0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ /* USB1 pull-up */
+ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+ /* Configure the HSUSB block */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ /* Choice USB0SEL */
+ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+ HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+ /* low power status */
+ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
--- /dev/null
+if TARGET_EAGLE
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "eagle"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "eagle"
+
+endif
--- /dev/null
+EAGLE BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/eagle/
+F: include/configs/eagle.h
+F: configs/r8a77970_eagle_defconfig
--- /dev/null
+#
+# board/renesas/eagle/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := eagle.o
--- /dev/null
+/*
+ * board/renesas/eagle/eagle.c
+ * This file is Eagle board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR 0xE6150904
+#define CPGWPR 0xE615090C
+
+/* PLL */
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_OFFSET 24
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 0.8GHz */
+ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+#define TMU0_MSTP125 BIT(25) /* secure */
+
+int board_early_init_f(void)
+{
+ writel(0xA5A5FFFF, CPGWPCR);
+ writel(0x5A5A0000, CPGWPR);
+
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := salvator-x.o ../rcar-common/common.o
+obj-y := salvator-x.o
int board_init(void)
{
+ u32 cpu_type = rmobile_get_cpu_type();
+
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
-#if defined(CONFIG_R8A7795)
- /* GSX: force power and clock supply */
- writel(0x0000001F, SYSC_PWRONCR2);
- while (readl(SYSC_PWRSR2) != 0x000003E0)
- mdelay(20);
+ if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
+ /* GSX: force power and clock supply */
+ writel(0x0000001F, SYSC_PWRONCR2);
+ while (readl(SYSC_PWRSR2) != 0x000003E0)
+ mdelay(20);
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
-#endif
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+ }
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
-#if (CONFIG_NR_DRAM_BANKS >= 2)
- gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 3)
- gd->ram_size += PHYS_SDRAM_3_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 4)
- gd->ram_size += PHYS_SDRAM_4_SIZE;
-#endif
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-#if (CONFIG_NR_DRAM_BANKS >= 2)
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 3)
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 4)
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-#endif
+ fdtdec_setup_memory_banksize();
+
return 0;
}
-const struct rmobile_sysinfo sysinfo = {
- CONFIG_RCAR_BOARD_STRING
-};
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := ulcb.o cpld.o ../rcar-common/common.o
+obj-y := ulcb.o cpld.o
*/
#include <common.h>
-#include <spi.h>
-#include <asm/io.h>
#include <asm/gpio.h>
-
-#define SCLK (192 + 8) /* GPIO6 8 */
-#define SSTBZ (64 + 3) /* GPIO2 3 */
-#define MOSI (192 + 7) /* GPIO6 8 */
-#define MISO (192 + 10) /* GPIO6 10 */
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x02 /* RW */
#define CPLD_ADDR_RESET 0x80 /* RW */
#define CPLD_ADDR_VERSION 0xFF /* R */
-static int cpld_initialized;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* Always valid */
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* Always active */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* Always active */
-}
-
-void ulcb_softspi_sda(int set)
-{
- gpio_set_value(MOSI, set);
-}
+struct renesas_ulcb_sysreset_priv {
+ struct gpio_desc miso;
+ struct gpio_desc mosi;
+ struct gpio_desc sck;
+ struct gpio_desc sstbz;
+};
-void ulcb_softspi_scl(int set)
-{
- gpio_set_value(SCLK, set);
-}
-
-unsigned char ulcb_softspi_read(void)
-{
- return !!gpio_get_value(MISO);
-}
-
-static void cpld_rw(u8 write)
-{
- gpio_set_value(MOSI, write);
- gpio_set_value(SSTBZ, 0);
- gpio_set_value(SCLK, 1);
- gpio_set_value(SCLK, 0);
- gpio_set_value(SSTBZ, 1);
-}
-
-static u32 cpld_read(u8 addr)
+static u32 cpld_read(struct udevice *dev, u8 addr)
{
+ struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
u32 data = 0;
+ int i;
- spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
-
- cpld_rw(0);
-
- spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END);
-
- return swab32(data);
-}
-
-static void cpld_write(u8 addr, u32 data)
-{
- data = swab32(data);
-
- spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ for (i = 0; i < 8; i++) {
+ dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
+ dm_gpio_set_value(&priv->sck, 1);
+ addr <<= 1;
+ dm_gpio_set_value(&priv->sck, 0);
+ }
- spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END);
+ dm_gpio_set_value(&priv->mosi, 0); /* READ */
+ dm_gpio_set_value(&priv->sstbz, 0);
+ dm_gpio_set_value(&priv->sck, 1);
+ dm_gpio_set_value(&priv->sck, 0);
+ dm_gpio_set_value(&priv->sstbz, 1);
+
+ for (i = 0; i < 32; i++) {
+ dm_gpio_set_value(&priv->sck, 1);
+ data <<= 1;
+ data |= dm_gpio_get_value(&priv->miso); /* MSB first */
+ dm_gpio_set_value(&priv->sck, 0);
+ }
- cpld_rw(1);
+ return data;
}
-static void cpld_init(void)
+static void cpld_write(struct udevice *dev, u8 addr, u32 data)
{
- if (cpld_initialized)
- return;
-
- /* PULL-UP on MISO line */
- setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
-
- gpio_request(SCLK, NULL);
- gpio_request(SSTBZ, NULL);
- gpio_request(MOSI, NULL);
- gpio_request(MISO, NULL);
-
- gpio_direction_output(SCLK, 0);
- gpio_direction_output(SSTBZ, 1);
- gpio_direction_output(MOSI, 0);
- gpio_direction_input(MISO);
+ struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
+ dm_gpio_set_value(&priv->sck, 1);
+ data <<= 1;
+ dm_gpio_set_value(&priv->sck, 0);
+ }
- /* Dummy read */
- cpld_read(CPLD_ADDR_VERSION);
+ for (i = 0; i < 8; i++) {
+ dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
+ dm_gpio_set_value(&priv->sck, 1);
+ addr <<= 1;
+ dm_gpio_set_value(&priv->sck, 0);
+ }
- cpld_initialized = 1;
+ dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
+ dm_gpio_set_value(&priv->sstbz, 0);
+ dm_gpio_set_value(&priv->sck, 1);
+ dm_gpio_set_value(&priv->sck, 0);
+ dm_gpio_set_value(&priv->sstbz, 1);
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ struct udevice *dev;
u32 addr, val;
+ int ret;
- cpld_init();
+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+ DM_GET_DRIVER(sysreset_renesas_ulcb),
+ &dev);
+ if (ret)
+ return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("CPLD version:\t\t\t0x%08x\n",
- cpld_read(CPLD_ADDR_VERSION));
+ cpld_read(dev, CPLD_ADDR_VERSION));
printf("H3 Mode setting (MD0..28):\t0x%08x\n",
- cpld_read(CPLD_ADDR_MODE));
+ cpld_read(dev, CPLD_ADDR_MODE));
printf("Multiplexer settings:\t\t0x%08x\n",
- cpld_read(CPLD_ADDR_MUX));
+ cpld_read(dev, CPLD_ADDR_MUX));
printf("DIPSW (SW6):\t\t\t0x%08x\n",
- cpld_read(CPLD_ADDR_DIPSW6));
+ cpld_read(dev, CPLD_ADDR_DIPSW6));
return 0;
}
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
- printf("0x%x\n", cpld_read(addr));
+ printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
- cpld_write(addr, val);
+ cpld_write(dev, addr, val);
}
return 0;
"cpld write addr val\n"
);
-void reset_cpu(ulong addr)
+static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+ return -EINPROGRESS;
+}
+
+static int renesas_ulcb_sysreset_probe(struct udevice *dev)
{
- cpld_init();
- cpld_write(CPLD_ADDR_RESET, 1);
+ struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
+
+ if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
+ GPIOD_IS_IN))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
+ return -EINVAL;
+
+ if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
+ GPIOD_IS_OUT))
+ return -EINVAL;
+
+ /* PULL-UP on MISO line */
+ setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
+
+ /* Dummy read */
+ cpld_read(dev, CPLD_ADDR_VERSION);
+
+ return 0;
}
+
+static struct sysreset_ops renesas_ulcb_sysreset = {
+ .request = renesas_ulcb_sysreset_request,
+};
+
+static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
+ { .compatible = "renesas,ulcb-cpld" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
+ .name = "renesas_ulcb_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &renesas_ulcb_sysreset,
+ .probe = renesas_ulcb_sysreset_probe,
+ .of_match = renesas_ulcb_sysreset_ids,
+ .priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
+};
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
-#if (CONFIG_NR_DRAM_BANKS >= 2)
- gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 3)
- gd->ram_size += PHYS_SDRAM_3_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 4)
- gd->ram_size += PHYS_SDRAM_4_SIZE;
-#endif
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-#if (CONFIG_NR_DRAM_BANKS >= 2)
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 3)
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-#endif
-#if (CONFIG_NR_DRAM_BANKS >= 4)
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-#endif
+ fdtdec_setup_memory_banksize();
+
return 0;
}
-
-const struct rmobile_sysinfo sysinfo = {
- CONFIG_RCAR_BOARD_STRING
-};
--- /dev/null
+if TARGET_EVB_RK3128
+
+config SYS_BOARD
+ default "evb_rk3128"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3128"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+EVB-RK3128
+M: Kever Yang <kever.yang@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3128
+F: include/configs/evb_rk3128.h
+F: configs/evb-rk3128_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evk-rk3128.o
* PMIC: rk808
* debug console: UART2
-In order to support Arm Trust Firmware(ATF), we need to use the
-miniloader from rockchip which:
+In order to support Arm Trust Firmware(ATF), we can use either SPL or
+miniloader from rockchip to do:
* do DRAM init
* load and verify ATF image
* load and verify U-Boot image
> mkdir ~/evb_rk3399
> cd ~/evb_rk3399
> git clone https://github.com/ARM-software/arm-trusted-firmware.git
- > git clone https://github.com/rockchip-linux/rkbin
- > git clone https://github.com/rockchip-linux/rkflashtool
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git
Compile the ATF
===============
> make realclean
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+ Or you can get the bl31.elf directly from Rockchip:
+ cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
+
+ Get bl31.elf in this step, copy it to U-Boot root dir:
+ > cp bl31.elf ../u-boot/
+
Compile the U-Boot
==================
> cd ../u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3399_defconfig all
+ > export ARCH=arm64
+ > export CROSS_COMPILE=aarch64-linux-gnu-
+ > make evb-rk3399_defconfig
+ for firefly-rk3399, use below instead:
+ > make firefly-rk3399_defconfig
+ > make
+ > make u-boot.itb
-Compile the rkflashtool
-=======================
+ Get spl/u-boot-spl.bin and u-boot.itb in this step.
+Compile the rkdeveloptool
+=======================
+ Follow instructions in latest README
> cd ../rkflashtool
+ > autoreconf -i
+ > ./configure
> make
+ > sudo make install
-Package the image for miniloader
-================================
+ Get rkdeveloptool in you Host in this step.
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+Package the image for U-Boot SPL(option 1)
+--------------------------------
> cd ..
- > cp arm-trusted-firmware/build/rk3399/release/bl31.bin rkbin/rk33
+ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img
+
+ Get idbspl.img in this step.
+
+Package the image for Rockchip miniloader(option 2)
+------------------------------------------
+ > cd ..
+ > cp arm-trusted-firmware/build/rk3399/release/bl31.elf rkbin/rk33
> ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini
> ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
- > mkdir image
- > mv trust.img ./image/
- > mv uboot.img ./image/rk3399evb-uboot.bin
-Flash the image
-===============
-Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ Get trust.img and uboot.img in this step.
- > ./rkflashtool/rkflashloader rk3399evb
+Flash the image to eMMC
+=======================
+
+Flash the image with U-Boot SPL(option 1)
+-------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 64 u-boot/idbspl.img
+ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+ > rkdeveloptool rd
-You should be able to get U-Boot log message in console/UART2 now.
+Flash the image with Rockchip miniloader(option 2)
+----------------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool ul rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 0x4000 u-boot/uboot.img
+ > rkdeveloptool wl 0x6000 u-boot/trust.img
+ > rkdeveloptool rd
+
+You should be able to get U-Boot log in console/UART2(baurdrate 1500000)
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
Get ddr init binary
==============================================================================
> git clone https://github.com/rockchip-linux/rkbin.git
- > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1
Compile U-Boot
===========================
> make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all
- > ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin
+ > ./tools/mkimage -n rv1108 -T rksd -d ../rkbin/rv1x/rv1108ddr_v1.00.bin spl.bin
> cat spl.bin u-boot.bin > u-boot.img
Flash the image by rkdeveloptool
rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
- > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin
+ > rkdeveloptool db ./rkbin/rv1x/rv1108usbboot_v1.00.bin
> rkdeveloptool wl 0x40 u-boot.img
> rkdeveloptool RD
};
/**
- * Odroix XU3/4 board revisions:
+ * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf):
* Rev ADCmax Board
* 0.1 0 XU3 0.1
- * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
- * 0.3 1408 XU4 0.1
- * Use +10 % for ADC value tolerance.
+ * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3 1280 XU4 0.1
+ * 0.4 739 XU4 0.2
+ * 0.5 1016 XU4+Air0.1 (Passive cooling)
+ * 0.6 1308 XU4S 0.1 (HC1)
+ * Use +1% for ADC value tolerance in the array below, the code loops until
+ * the measured ADC value is lower than then ADCmax from the array.
*/
struct odroid_rev_info odroid_info[] = {
{ EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" },
+ { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
+ { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
+ { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" },
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
goto rev_default;
for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
- /* ADC tolerance: +20 % */
+ /* ADC tolerance: +1% */
if (adcval < odroid_info[i].adc_val)
return odroid_info[i].board_type;
}
return false;
}
+bool board_is_odroidhc1(void)
+{
+ if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01)
+ return true;
+
+ return false;
+}
+
bool board_is_generic(void)
{
if (gd->board_type == EXYNOS5_BOARD_GENERIC)
{
char *info = "Not supported!";
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
return env_get("dfu_alt_system");
char *alt_boot;
int dev_num;
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
dev_num = simple_strtoul(devstr, NULL, 10);
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 3, BOOKE_PAGESZ_64M, 1),
/*
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 4, BOOKE_PAGESZ_64M, 1),
#endif
#include <asm/arch/atmel_serial.h>
#include <asm/arch/clk.h>
#include <asm/gpio.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <atmel_mci.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_l cas_wl */
+ 0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
#include <common.h>
#include <dm.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
{
int res;
+ configure_clocks();
+
res = uart_setup_gpio();
if (res)
return res;
S: Maintained
F: configs/nanopi_neo2_defconfig
+NANOPI-NEO-PLUS2 BOARD
+M: Antony Antony <antony@phenome.org>
+S: Maintained
+F: configs/nanopi_neo_plus2_defconfig
+
NANOPI-NEO-AIR BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
+#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
+#else
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#endif
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
return 0;
}
+#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;
return 1;
}
+ /*
+ * Switch SDIO external ciu clock divider from default div-by-8 to
+ * minimum possible div-by-2.
+ */
+ writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
+
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
host->ioaddr = (void *)ARC_DWMMC_BASE;
host->buswidth = 4;
host->dev_index = 0;
- host->bus_hz = 100000000;
+ host->bus_hz = 50000000;
add_dwmci(host, host->bus_hz / 2, 400000);
description = "U-Boot (64-bit)";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
+ os = "U-Boot";
arch = "arm64";
compression = "none";
load = <0x00200000>;
description = "ARM Trusted Firmware";
data = /incbin/("../../../bl31-rk3368.bin");
type = "firmware";
+ os = "arm-trusted-firmware";
arch = "arm64";
compression = "none";
load = <0x00100000>;
default = "conf";
conf {
description = "Theobroma Systems RK3368-uQ7 (Puma) SoM";
- firmware = "uboot";
- loadables = "atf";
+ firmware = "atf";
+ loadables = "uboot";
fdt = "fdt";
};
};
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+config ENV_SIZE
+ default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x3c000 if ENV_IS_IN_SPI_FLASH
+
endif
description = "U-Boot (64-bit)";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
+ os = "U-Boot";
arch = "arm64";
compression = "none";
load = <0x00200000>;
data = /incbin/("../../../bl31-rk3399.bin");
type = "firmware";
arch = "arm64";
+ os = "arm-trusted-firmware";
compression = "none";
- load = <0x00001000>;
- entry = <0x00001000>;
+ load = <0x1000>;
+ entry = <0x1000>;
};
pmu {
description = "Cortex-M0 firmware";
data = /incbin/("../../../rk3399m0.bin");
type = "pmu-firmware";
compression = "none";
- load = <0xff8c0000>;
+ load = <0x180000>;
};
fdt {
description = "RK3399-Q7 (Puma) flat device-tree";
default = "conf";
conf {
description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
- firmware = "uboot";
- loadables = "atf";
+ firmware = "atf";
+ loadables = "uboot", "pmu";
fdt = "fdt";
};
};
#include <common.h>
#include <dm.h>
#include <misc.h>
+#include <spl.h>
+#include <syscon.h>
+#include <usb.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/setup.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3399.h>
#include <asm/arch/periph.h>
#include <power/regulator.h>
-#include <spl.h>
#include <u-boot/sha256.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+static void rk3399_force_power_on_reset(void)
+{
+ ofnode node;
+ struct gpio_desc sysreset_gpio;
+
+ debug("%s: trying to force a power-on reset\n", __func__);
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ debug("%s: no /config node?\n", __func__);
+ return;
+ }
+
+ if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
+ &sysreset_gpio, GPIOD_IS_OUT)) {
+ debug("%s: could not find a /config/sysreset-gpio\n", __func__);
+ return;
+ }
+
+ dm_gpio_set_value(&sysreset_gpio, 1);
+}
+
void spl_board_init(void)
{
int ret;
+ struct rk3399_cru *cru = rockchip_get_cru();
+
+ /*
+ * The RK3399 resets only 'almost all logic' (see also in the TRM
+ * "3.9.4 Global software reset"), when issuing a software reset.
+ * This may cause issues during boot-up for some configurations of
+ * the application software stack.
+ *
+ * To work around this, we test whether the last reset reason was
+ * a power-on reset and (if not) issue an overtemp-reset to reset
+ * the entire module.
+ *
+ * While this was previously fixed by modifying the various places
+ * that could generate a software reset (e.g. U-Boot's sysreset
+ * driver, the ATF or Linux), we now have it here to ensure that
+ * we no longer have to track this through the various components.
+ */
+ if (cru->glb_rst_st != 0)
+ rk3399_force_power_on_reset();
/*
* Turning the eMMC and SPI back on (if disabled via the Qseven
serialno = crc32_no_comp(0, low, 8);
serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
- snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
+ snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
env_set("cpuid#", cpuid_str);
env_set("serial#", serialno_str);
#endif
}
+static void setup_iodomain(void)
+{
+ const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6).
+ * Linux assumes that PCIE_RST# works out of the box as it probes
+ * PCIe before loading the iodomain driver.
+ */
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
+}
+
int misc_init_r(void)
{
setup_serial();
setup_macaddr();
+ setup_iodomain();
return 0;
}
serialnr->low = (u32)(serial & 0xffffffff);
}
#endif
+
+/**
+ * Switch power at an external regulator (for our root hub).
+ *
+ * @param ctrl pointer to the xHCI controller
+ * @param port port number as in the control message (one-based)
+ * @param enable boolean indicating whether to enable or disable power
+ * @return returns 0 on success, an error-code on failure
+ */
+static int board_usb_port_power_set(struct udevice *dev, int port,
+ bool enable)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ /* We start counting ports at 0, while USB counts from 1. */
+ int index = port - 1;
+ const char *regname = NULL;
+ struct udevice *regulator;
+ const char *prop = "tsd,usb-port-power";
+ int ret;
+
+ debug("%s: ctrl '%s' port %d enable %s\n", __func__,
+ dev_read_name(dev), port, enable ? "true" : "false");
+
+ ret = dev_read_string_index(dev, prop, index, ®name);
+ if (ret < 0) {
+ debug("%s: ctrl '%s' port %d: no entry in '%s'\n",
+ __func__, dev_read_name(dev), port, prop);
+ return ret;
+ }
+
+ ret = regulator_get_by_platname(regname, ®ulator);
+ if (ret) {
+ debug("%s: ctrl '%s' port %d: could not get regulator '%s'\n",
+ __func__, dev_read_name(dev), port, regname);
+ return ret;
+ }
+
+ regulator_set_enable(regulator, enable);
+ return 0;
+#else
+ return -ENOTSUPP;
+#endif
+}
+
+void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
+{
+ struct udevice *dev = hub->pusb_dev->dev;
+ struct udevice *ctrl;
+
+ /* We are only interested in our root-hubs */
+ if (usb_hub_is_root_hub(dev) == false)
+ return;
+
+ ctrl = usb_get_bus(dev);
+ if (!ctrl) {
+ debug("%s: could not retrieve ctrl for hub\n", __func__);
+ return;
+ }
+
+ /*
+ * To work around an incompatibility between the single-threaded
+ * USB stack in U-Boot and (a strange low-power mode of) the USB
+ * hub we have on-module, we need to delay powering on the hub
+ * until the first time the port is probed.
+ */
+ board_usb_port_power_set(ctrl, port, true);
+}
#include <status_led.h>
#endif
#include <twl4030.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <twl4030.h>
#include <asm/mach-types.h>
#include <asm/omap_musb.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
return omap_ehci_hcd_stop();
}
-void usb_hub_reset_devices(int port)
+void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
/* The LAN9730 needs to be reset after the port power has been set. */
if (port == 3) {
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+++ /dev/null
-/*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
- * (c) Copyright 2016 Topic Embedded Products.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define OPCODE_EXIT 0U
-#define OPCODE_MASKWRITE 0U
-#define OPCODE_MASKPOLL 1U
-#define OPCODE_MASKDELAY 2U
-#define OPCODE_ADDRESS_MASK (~3U)
-
-/* Sentinel */
-#define EMIT_EXIT() OPCODE_EXIT
-/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
-#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
-#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
-
-/* Returns codes of ps7_init* */
-#define PS7_INIT_SUCCESS (0)
-#define PS7_INIT_CORRUPT (1)
-#define PS7_INIT_TIMEOUT (2)
-#define PS7_POLL_FAILED_DDR_INIT (3)
-#define PS7_POLL_FAILED_DMA (4)
-#define PS7_POLL_FAILED_PLL (5)
-
-/* Called by spl.c */
-int ps7_init(void);
-int ps7_post_config(void);
-
-/* Defined in ps7_init_common.c */
-int ps7_config(unsigned long *ps7_config_init);
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
}
+
+ udelay(100);
}
void board_init_f(ulong dummy)
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
+ u32 version = zynq_get_silicon_version();
+
+ version <<= 1;
+ if (version > (PCW_SILICON_VERSION_3 << 1))
+ version += 1;
+
puts("Board: Xilinx Zynq\n");
+ printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+
return 0;
}
#endif
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
int dram_init(void)
--- /dev/null
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ unsigned long *ps7_mio_init_data;
+ unsigned long *ps7_pll_init_data;
+ unsigned long *ps7_clock_init_data;
+ unsigned long *ps7_ddr_init_data;
+ unsigned long *ps7_peripherals_init_data;
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
--- /dev/null
+zynq-zc706
\ No newline at end of file
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
return PS7_INIT_SUCCESS;
}
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int
ps7_init()
{
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 100000000
-#define FPGA2_FREQ 33333336
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
return PS7_INIT_SUCCESS;
}
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int
ps7_init()
{
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 23809523
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
return PS7_INIT_SUCCESS;
}
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int
ps7_init()
{
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
return PS7_INIT_SUCCESS;
}
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int
ps7_init()
{
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
/* START: top */
/* */
};
-unsigned long ps7_debug_3_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_2_0[] = {
/* START: top */
/* */
};
-unsigned long ps7_debug_2_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_1_0[] = {
/* START: top */
/* */
};
-unsigned long ps7_debug_1_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
- char *err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS:
- err_msg = "PS7 initialization successful";
- break;
- case PS7_INIT_CORRUPT:
- err_msg = "PS7 init Data Corrupted";
- break;
- case PS7_INIT_TIMEOUT:
- err_msg = "PS7 init mask poll timeout";
- break;
- case PS7_POLL_FAILED_DDR_INIT:
- err_msg = "Mask Poll failed for DDR Init";
- break;
- case PS7_POLL_FAILED_DMA:
- err_msg = "Mask Poll failed for PLL Init";
- break;
- case PS7_POLL_FAILED_PLL:
- err_msg = "Mask Poll failed for DMA done bit";
- break;
- default:
- err_msg = "Undefined error status";
- break;
- }
-
- return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
- /* Read PS version from MCTRL register [31:28] */
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long *)0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
- unsigned long *addr = (unsigned long *)add;
- *addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
- volatile unsigned long *addr = (volatile unsigned long *)add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME)
- return -1;
- i++;
- }
- return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
- unsigned long *addr = (unsigned long *)add;
- unsigned long val = (*addr & mask);
- return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; /* current instruction .. */
- unsigned long args[16]; /* no opcode has so many args ... */
- int numargs; /* number of arguments of this instruction */
- int j; /* general purpose index */
-
- volatile unsigned long *addr; /* some variable to make code readable */
- unsigned long val, mask; /* some variable to make code readable */
-
- int finish = -1; /* loop while this is negative ! */
- int i = 0; /* Timeout variable */
-
- while (finish < 0) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for (j = 0; j < numargs; j++)
- args[j] = ptr[j + 1];
- ptr += numargs + 1;
-
- switch (opcode) {
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long *)args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long *)args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long *)args[0];
- mask = args[1];
- val = args[2];
- *addr = (val & mask) | (*addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long *)args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long *)args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay))
- ;
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
return PS7_INIT_SUCCESS;
}
-int ps7_debug(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config(ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config(ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else {
- ret = ps7_config(ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int ps7_init(void)
{
/* Get the PS_VERSION on run time */
return PS7_INIT_SUCCESS;
}
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8) /* Pre-scale */
- );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
- return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
-#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
-#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
-#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 200000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-int ps7_debug(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
static const struct {
- uint32_t id;
+ u32 id;
+ u32 ver;
char *name;
} zynqmp_devices[] = {
{
.id = 0x10,
.name = "3eg",
},
+ {
+ .id = 0x10,
+ .ver = 0x2c,
+ .name = "3cg",
+ },
{
.id = 0x11,
.name = "2eg",
},
+ {
+ .id = 0x11,
+ .ver = 0x2c,
+ .name = "2cg",
+ },
{
.id = 0x20,
.name = "5ev",
},
+ {
+ .id = 0x20,
+ .ver = 0x100,
+ .name = "5eg",
+ },
+ {
+ .id = 0x20,
+ .ver = 0x12c,
+ .name = "5cg",
+ },
{
.id = 0x21,
.name = "4ev",
},
+ {
+ .id = 0x21,
+ .ver = 0x100,
+ .name = "4eg",
+ },
+ {
+ .id = 0x21,
+ .ver = 0x12c,
+ .name = "4cg",
+ },
{
.id = 0x30,
.name = "7ev",
},
+ {
+ .id = 0x30,
+ .ver = 0x100,
+ .name = "7eg",
+ },
+ {
+ .id = 0x30,
+ .ver = 0x12c,
+ .name = "7cg",
+ },
{
.id = 0x38,
.name = "9eg",
},
+ {
+ .id = 0x38,
+ .ver = 0x2c,
+ .name = "9cg",
+ },
{
.id = 0x39,
.name = "6eg",
},
+ {
+ .id = 0x39,
+ .ver = 0x2c,
+ .name = "6cg",
+ },
{
.id = 0x40,
.name = "11eg",
},
+ { /* For testing purpose only */
+ .id = 0x50,
+ .ver = 0x2c,
+ .name = "15cg",
+ },
{
.id = 0x50,
.name = "15eg",
.id = 0x59,
.name = "17eg",
},
+ {
+ .id = 0x61,
+ .name = "21dr",
+ },
+ {
+ .id = 0x63,
+ .name = "23dr",
+ },
+ {
+ .id = 0x65,
+ .name = "25dr",
+ },
+ {
+ .id = 0x64,
+ .name = "27dr",
+ },
+ {
+ .id = 0x60,
+ .name = "28dr",
+ },
+ {
+ .id = 0x62,
+ .name = "29dr",
+ },
};
#endif
* regs[0][31:0] = status of the operation
* regs[0][63:32] = CSU.IDCODE register
* regs[1][31:0] = CSU.version register
+ * regs[1][63:32] = CSU.IDCODE2 register
*/
switch (id) {
case IDCODE:
regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
val = regs.regs[1];
break;
+ case IDCODE2:
+ regs.regs[1] = lower_32_bits(regs.regs[1]);
+ regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+ val = regs.regs[1];
+ break;
default:
printf("%s, Invalid Req:0x%x\n", __func__, id);
}
!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
- uint32_t i, id;
+ u32 i, id, ver;
id = chip_id(IDCODE);
+ ver = chip_id(IDCODE2);
+
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
- if (zynqmp_devices[i].id == id)
+ if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
return zynqmp_devices[i].name;
}
return "unknown";
if (current_el() != 3) {
static char version[ZYNQMP_VERSION_SIZE];
- strncat(version, "xczu", 4);
+ strncat(version, "zu", 2);
zynqmppl.name = strncat(version,
zynqmp_get_silicon_idcode_name(),
- ZYNQMP_VERSION_SIZE - 5);
+ ZYNQMP_VERSION_SIZE - 3);
printf("Chip ID:\t%s\n", zynqmppl.name);
fpga_init();
fpga_add(fpga_xilinx, &zynqmppl);
{
u32 val;
+ if (current_el() != 3)
+ return 0;
+
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
- if (current_el() == 3 && !val) {
+ if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
int dram_init(void)
u8 bootmode;
const char *mode;
char *new_targets;
+ int ret;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
- reg = readl(&crlapb_base->boot_mode);
+ ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
+ if (ret)
+ return -EINVAL;
+
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
case USB_MODE:
puts("USB_MODE\n");
mode = "usb";
+ env_set("modeboot", "usb_dfu_spl");
break;
case JTAG_MODE:
puts("JTAG_MODE\n");
mode = "pxe dhcp";
+ env_set("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
mode = "qspi0";
puts("QSPI_MODE\n");
+ env_set("modeboot", "qspiboot");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
mode = "mmc0";
+ env_set("modeboot", "emmcboot");
break;
case SD_MODE:
puts("SD_MODE\n");
mode = "mmc0";
+ env_set("modeboot", "sdboot");
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
mode = "mmc1";
+ env_set("sdbootdev", "1");
#else
mode = "mmc0";
#endif
+ env_set("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
mode = "nand0";
+ env_set("modeboot", "nandboot");
break;
default:
mode = "";
single-stepping, inspecting variables, etc. This is supported only
on PowerPC at present.
+config CMD_LOG
+ bool "log - Generation, control and access to logging"
+ help
+ This provides access to logging features. It allows the output of
+ log data to be controlled to a limited extent (setting up the default
+ maximum log level for emitting of records). It also provides access
+ to a command used for testing the log system.
+
config CMD_TRACE
bool "trace - Support tracing of function calls and timing"
help
obj-$(CONFIG_CMD_LED) += led.o
obj-$(CONFIG_CMD_LICENSE) += license.o
obj-y += load.o
-obj-$(CONFIG_LOGBUFFER) += log.o
+obj-$(CONFIG_CMD_LOG) += log.o
obj-$(CONFIG_ID_EEPROM) += mac.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
} else {
return CMD_RET_USAGE;
}
-
- return 0;
}
}
#endif
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <charset.h>
#include <common.h>
#include <command.h>
#include <dm.h>
#include <efi_loader.h>
+#include <efi_selftest.h>
#include <errno.h>
#include <libfdt.h>
#include <libfdt_env.h>
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
efi_smbios_register();
#endif
+ efi_watchdog_register();
/* Initialize EFI runtime services */
efi_reset_system_init();
efi_get_time_init();
}
+/*
+ * Set the load options of an image from an environment variable.
+ *
+ * @loaded_image_info: the image
+ * @env_var: name of the environment variable
+ */
+static void set_load_options(struct efi_loaded_image *loaded_image_info,
+ const char *env_var)
+{
+ size_t size;
+ const char *env = env_get(env_var);
+
+ loaded_image_info->load_options = NULL;
+ loaded_image_info->load_options_size = 0;
+ if (!env)
+ return;
+ size = strlen(env) + 1;
+ loaded_image_info->load_options = calloc(size, sizeof(u16));
+ if (!loaded_image_info->load_options) {
+ printf("ERROR: Out of memory\n");
+ return;
+ }
+ utf8_to_utf16(loaded_image_info->load_options, (u8 *)env, size);
+ loaded_image_info->load_options_size = size * 2;
+}
+
static void *copy_fdt(void *fdt)
{
u64 fdt_size = fdt_totalsize(fdt);
return new_fdt;
}
-static ulong efi_do_enter(void *image_handle,
- struct efi_system_table *st,
- asmlinkage ulong (*entry)(void *image_handle,
- struct efi_system_table *st))
+static efi_status_t efi_do_enter(
+ void *image_handle, struct efi_system_table *st,
+ asmlinkage ulong (*entry)(void *image_handle,
+ struct efi_system_table *st))
{
efi_status_t ret = EFI_LOAD_ERROR;
}
#ifdef CONFIG_ARM64
-static unsigned long efi_run_in_el2(asmlinkage ulong (*entry)(
+static efi_status_t efi_run_in_el2(asmlinkage ulong (*entry)(
void *image_handle, struct efi_system_table *st),
void *image_handle, struct efi_system_table *st)
{
* Load an EFI payload into a newly allocated piece of memory, register all
* EFI objects it would want to access and jump to it.
*/
-static unsigned long do_bootefi_exec(void *efi, void *fdt,
- struct efi_device_path *device_path,
- struct efi_device_path *image_path)
+static efi_status_t do_bootefi_exec(void *efi, void *fdt,
+ struct efi_device_path *device_path,
+ struct efi_device_path *image_path)
{
struct efi_loaded_image loaded_image_info = {};
struct efi_object loaded_image_info_obj = {};
efi_install_configuration_table(&fdt_guid, NULL);
}
+ /* Transfer environment variable bootargs as load options */
+ set_load_options(&loaded_image_info, "bootargs");
/* Load the EFI payload */
entry = efi_load_pe(efi, &loaded_image_info);
if (!entry) {
dcache_disable(); /* flush cache before switch to EL2 */
/* Move into EL2 and keep running there */
- armv8_switch_to_el2((ulong)entry, (ulong)&loaded_image_info,
+ armv8_switch_to_el2((ulong)entry,
+ (ulong)&loaded_image_info_obj.handle,
(ulong)&systab, 0, (ulong)efi_run_in_el2,
ES_TO_AARCH64);
}
#endif
- ret = efi_do_enter(&loaded_image_info, &systab, entry);
+ ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry);
exit:
/* image has returned, loaded-image obj goes *poof*: */
{
char *saddr, *sfdt;
unsigned long addr, fdt_addr = 0;
- unsigned long r;
+ efi_status_t r;
if (argc < 2)
return CMD_RET_USAGE;
struct efi_loaded_image loaded_image_info = {};
struct efi_object loaded_image_info_obj = {};
+ /* Construct a dummy device path. */
+ bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+ (uintptr_t)&efi_selftest,
+ (uintptr_t)&efi_selftest);
+ bootefi_image_path = efi_dp_from_file(NULL, 0, "\\selftest");
+
efi_setup_loaded_image(&loaded_image_info,
&loaded_image_info_obj,
bootefi_device_path, bootefi_image_path);
/* Initialize and populate EFI object list */
if (!efi_obj_list_initalized)
efi_init_obj_list();
- return efi_selftest(&loaded_image_info, &systab);
+ /* Transfer environment variable efi_selftest as load options */
+ set_load_options(&loaded_image_info, "efi_selftest");
+ /* Execute the test */
+ r = efi_selftest(loaded_image_info_obj.handle, &systab);
+ efi_restore_gd();
+ free(loaded_image_info.load_options);
+ list_del(&loaded_image_info_obj.link);
+ return r != EFI_SUCCESS;
} else
#endif
if (!strcmp(argv[1], "bootmgr")) {
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
"bootefi selftest\n"
" - boot an EFI selftest application stored within U-Boot\n"
+ " Use environment variable efi_selftest to select a single test.\n"
+ " Use 'setenv efi_selftest list' to enumerate all tests.\n"
#endif
"bootmgr [fdt addr]\n"
" - load and boot EFI payload based on BootOrder/BootXXXX variables.\n"
int part;
desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
+ if (!desc)
+ return;
part = parse_partnum(devnr);
bootefi_device_path = efi_dp_from_part(desc, part);
config FASTBOOT_FLASH
bool "Enable FASTBOOT FLASH command"
+ default y if ARCH_SUNXI
help
The fastboot protocol includes a "flash" command for writing
the downloaded image to a non-volatile storage device. Define
uint chip;
u_char data[128];
u_char cksum;
- int j;
+ int j, ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
static const char *decode_CAS_DDR2[] = {
" TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
*/
chip = simple_strtoul (argv[1], NULL, 16);
- if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, data, sizeof(data));
+#else
+ ret = i2c_read(chip, 0, 1, data, sizeof(data));
+#endif
+ if (ret) {
puts ("No SDRAM Serial Presence Detect found.\n");
return 1;
}
#include <cramfs/cramfs_fs.h>
#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <nand.h>
#endif
/*
- * (C) Copyright 2002-2007
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
*
- * Code used from linux/kernel/printk.c
- * Copyright (C) 1991, 1992 Linus Torvalds
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Comments:
- *
- * After relocating the code, the environment variable "loglevel" is
- * copied to console_loglevel. The functionality is similar to the
- * handling in the Linux kernel, i.e. messages logged with a priority
- * less than console_loglevel are also output to stdout.
- *
- * If you want messages with the default level (e.g. POST messages) to
- * appear on stdout also, make sure the environment variable
- * "loglevel" is set at boot time to a number higher than
- * default_message_loglevel below.
- */
-
-/*
- * Logbuffer handling routines
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
-#include <stdio_dev.h>
-#include <post.h>
-#include <logbuff.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Local prototypes */
-static void logbuff_putc(struct stdio_dev *dev, const char c);
-static void logbuff_puts(struct stdio_dev *dev, const char *s);
-static int logbuff_printk(const char *line);
-
-static char buf[1024];
-
-/* This combination will not print messages with the default loglevel */
-static unsigned console_loglevel = 3;
-static unsigned default_message_loglevel = 4;
-static unsigned log_version = 1;
-#ifdef CONFIG_ALT_LB_ADDR
-static volatile logbuff_t *log;
-#else
-static logbuff_t *log;
-#endif
-static char *lbuf;
-
-unsigned long __logbuffer_base(void)
-{
- return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
-}
-unsigned long logbuffer_base(void)
-__attribute__((weak, alias("__logbuffer_base")));
+#include <dm.h>
+#include <log.h>
-void logbuff_init_ptrs(void)
+static int do_log_level(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
- unsigned long tag, post_word;
- char *s;
-
-#ifdef CONFIG_ALT_LB_ADDR
- log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
- lbuf = (char *)CONFIG_ALT_LB_ADDR;
-#else
- log = (logbuff_t *)(logbuffer_base()) - 1;
- lbuf = (char *)log->buf;
-#endif
-
- /* Set up log version */
- s = env_get("logversion");
- if (s)
- log_version = (int)simple_strtoul(s, NULL, 10);
-
- if (log_version == 2)
- tag = log->v2.tag;
+ if (argc > 1)
+ gd->default_log_level = simple_strtol(argv[1], NULL, 10);
else
- tag = log->v1.tag;
- post_word = post_word_load();
-#ifdef CONFIG_POST
- /* The post routines have setup the word so we can simply test it */
- if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT))
- logbuff_reset();
-#else
- /* No post routines, so we do our own checking */
- if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
- logbuff_reset ();
- post_word_store (LOGBUFF_MAGIC);
- }
-#endif
- if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
- log->v2.start = log->v2.con;
-
- /* Initialize default loglevel if present */
- s = env_get("loglevel");
- if (s)
- console_loglevel = (int)simple_strtoul(s, NULL, 10);
+ printf("Default log level: %d\n", gd->default_log_level);
- gd->flags |= GD_FLG_LOGINIT;
+ return 0;
}
-void logbuff_reset(void)
-{
-#ifndef CONFIG_ALT_LB_ADDR
- memset(log, 0, sizeof(logbuff_t));
-#endif
- if (log_version == 2) {
- log->v2.tag = LOGBUFF_MAGIC;
-#ifdef CONFIG_ALT_LB_ADDR
- log->v2.start = 0;
- log->v2.con = 0;
- log->v2.end = 0;
- log->v2.chars = 0;
+static cmd_tbl_t log_sub[] = {
+ U_BOOT_CMD_MKENT(level, CONFIG_SYS_MAXARGS, 1, do_log_level, "", ""),
+#ifdef CONFIG_LOG_TEST
+ U_BOOT_CMD_MKENT(test, 2, 1, do_log_test, "", ""),
#endif
- } else {
- log->v1.tag = LOGBUFF_MAGIC;
-#ifdef CONFIG_ALT_LB_ADDR
- log->v1.dummy = 0;
- log->v1.start = 0;
- log->v1.size = 0;
- log->v1.chars = 0;
-#endif
- }
-}
+};
-int drv_logbuff_init(void)
+static int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct stdio_dev logdev;
- int rc;
-
- /* Device initialization */
- memset (&logdev, 0, sizeof (logdev));
-
- strcpy (logdev.name, "logbuff");
- logdev.ext = 0; /* No extensions */
- logdev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- logdev.putc = logbuff_putc; /* 'putc' function */
- logdev.puts = logbuff_puts; /* 'puts' function */
-
- rc = stdio_register(&logdev);
+ cmd_tbl_t *cp;
- return (rc == 0) ? 1 : rc;
-}
+ if (argc < 2)
+ return CMD_RET_USAGE;
-static void logbuff_putc(struct stdio_dev *dev, const char c)
-{
- char buf[2];
- buf[0] = c;
- buf[1] = '\0';
- logbuff_printk(buf);
-}
+ /* drop initial "log" arg */
+ argc--;
+ argv++;
-static void logbuff_puts(struct stdio_dev *dev, const char *s)
-{
- logbuff_printk (s);
-}
+ cp = find_cmd_tbl(argv[0], log_sub, ARRAY_SIZE(log_sub));
+ if (cp)
+ return cp->cmd(cmdtp, flag, argc, argv);
-void logbuff_log(char *msg)
-{
- if ((gd->flags & GD_FLG_LOGINIT)) {
- logbuff_printk(msg);
- } else {
- /*
- * Can happen only for pre-relocated errors as logging
- * at that stage should be disabled
- */
- puts (msg);
- }
+ return CMD_RET_USAGE;
}
-/*
- * Subroutine: do_log
- *
- * Description: Handler for 'log' command..
- *
- * Inputs: argv[1] contains the subcommand
- *
- * Return: None
- *
- */
-int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct stdio_dev *sdev = NULL;
- char *s;
- unsigned long i, start, size;
-
- if (strcmp(argv[1], "append") == 0) {
- /* Log concatenation of all arguments separated by spaces */
- for (i = 2; i < argc; i++) {
- logbuff_printk(argv[i]);
- logbuff_putc(sdev, (i < argc - 1) ? ' ' : '\n');
- }
- return 0;
- }
-
- switch (argc) {
-
- case 2:
- if (strcmp(argv[1], "show") == 0) {
- if (log_version == 2) {
- start = log->v2.start;
- size = log->v2.end - log->v2.start;
- } else {
- start = log->v1.start;
- size = log->v1.size;
- }
- if (size > LOGBUFF_LEN)
- size = LOGBUFF_LEN;
- for (i = 0; i < size; i++) {
- s = lbuf + ((start + i) & LOGBUFF_MASK);
- putc(*s);
- }
- return 0;
- } else if (strcmp(argv[1], "reset") == 0) {
- logbuff_reset();
- return 0;
- } else if (strcmp(argv[1], "info") == 0) {
- printf("Logbuffer at %08lx\n", (unsigned long)lbuf);
- if (log_version == 2) {
- printf("log_start = %08lx\n",
- log->v2.start);
- printf("log_end = %08lx\n", log->v2.end);
- printf("log_con = %08lx\n", log->v2.con);
- printf("logged_chars = %08lx\n",
- log->v2.chars);
- }
- else {
- printf("log_start = %08lx\n",
- log->v1.start);
- printf("log_size = %08lx\n",
- log->v1.size);
- printf("logged_chars = %08lx\n",
- log->v1.chars);
- }
- return 0;
- }
- return CMD_RET_USAGE;
-
- default:
- return CMD_RET_USAGE;
- }
-}
+#ifdef CONFIG_SYS_LONGHELP
+static char log_help_text[] =
+ "level - get/set log level\n"
+#ifdef CONFIG_LOG_TEST
+ "log test - run log tests\n"
+#endif
+ ;
+#endif
U_BOOT_CMD(
- log, 255, 1, do_log,
- "manipulate logbuffer",
- "info - show pointer details\n"
- "log reset - clear contents\n"
- "log show - show contents\n"
- "log append <msg> - append <msg> to the logbuffer"
+ log, CONFIG_SYS_MAXARGS, 1, do_log,
+ "log system", log_help_text
);
-
-static int logbuff_printk(const char *line)
-{
- int i;
- char *msg, *p, *buf_end;
- int line_feed;
- static signed char msg_level = -1;
-
- strcpy(buf + 3, line);
- i = strlen(line);
- buf_end = buf + 3 + i;
- for (p = buf + 3; p < buf_end; p++) {
- msg = p;
- if (msg_level < 0) {
- if (
- p[0] != '<' ||
- p[1] < '0' ||
- p[1] > '7' ||
- p[2] != '>'
- ) {
- p -= 3;
- p[0] = '<';
- p[1] = default_message_loglevel + '0';
- p[2] = '>';
- } else {
- msg += 3;
- }
- msg_level = p[1] - '0';
- }
- line_feed = 0;
- for (; p < buf_end; p++) {
- if (log_version == 2) {
- lbuf[log->v2.end & LOGBUFF_MASK] = *p;
- log->v2.end++;
- if (log->v2.end - log->v2.start > LOGBUFF_LEN)
- log->v2.start++;
- log->v2.chars++;
- } else {
- lbuf[(log->v1.start + log->v1.size) &
- LOGBUFF_MASK] = *p;
- if (log->v1.size < LOGBUFF_LEN)
- log->v1.size++;
- else
- log->v1.start++;
- log->v1.chars++;
- }
- if (*p == '\n') {
- line_feed = 1;
- break;
- }
- }
- if (msg_level < console_loglevel) {
- printf("%s", msg);
- }
- if (line_feed)
- msg_level = -1;
- }
- return i;
-}
#include <linux/mtd/mtd.h>
#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <nand.h>
#endif
return 1;
}
-#ifdef DEBUG
pend = strchr(p, ';');
-#endif
debug("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
id->type, MTD_DEV_TYPE(id->type),
id->num, id->mtd_id);
debug("parsing partitions %.*s\n", (int)(pend ? pend - p : strlen(p)), p);
-
/* parse partitions */
num_parts = 0;
printf(" %s", pre);
#ifdef CONFIG_DM_USB
has_child = device_has_active_children(dev->dev);
+ if (device_get_uclass_id(dev->dev) == UCLASS_MASS_STORAGE) {
+ struct udevice *child;
+
+ for (device_find_first_child(dev->dev, &child);
+ child;
+ device_find_next_child(&child)) {
+ if (device_get_uclass_id(child) == UCLASS_BLK)
+ has_child = 0;
+ }
+ }
#else
/* check if the device has connected children */
int i;
udev = dev_get_parent_priv(child);
- /* Ignore emulators, we only want real devices */
- if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
+ /*
+ * Ignore emulators and block child devices, we only want
+ * real devices
+ */
+ if ((device_get_uclass_id(child) != UCLASS_USB_EMUL) &&
+ (device_get_uclass_id(child) != UCLASS_BLK)) {
usb_show_tree_graph(udev, pre);
pre[index] = 0;
}
for (device_find_first_child(udev->dev, &child);
child;
device_find_next_child(&child)) {
- if (device_active(child)) {
+ if (device_active(child) &&
+ (device_get_uclass_id(child) != UCLASS_USB_EMUL) &&
+ (device_get_uclass_id(child) != UCLASS_BLK)) {
udev = dev_get_parent_priv(child);
usb_show_info(udev);
}
endmenu
+menu "Logging"
+
+config LOG
+ bool "Enable logging support"
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+config SPL_LOG
+ bool "Enable logging support in SPL"
+ help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+config LOG_MAX_LEVEL
+ int "Maximum log level to record"
+ depends on LOG
+ default 5
+ help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
+
+ 0 - panic
+ 1 - critical
+ 2 - error
+ 3 - warning
+ 4 - note
+ 5 - info
+ 6 - detail
+ 7 - debug
+
+config SPL_LOG_MAX_LEVEL
+ int "Maximum log level to record in SPL"
+ depends on SPL_LOG
+ default 3
+ help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
+
+ 0 - panic
+ 1 - critical
+ 2 - error
+ 3 - warning
+ 4 - note
+ 5 - info
+ 6 - detail
+ 7 - debug
+
+config LOG_CONSOLE
+ bool "Allow log output to the console"
+ depends on LOG
+ default y
+ help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+config LOG_SPL_CONSOLE
+ bool "Allow log output to the console in SPL"
+ depends on LOG_SPL
+ default y
+ help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+config LOG_TEST
+ bool "Provide a test for logging"
+ depends on LOG
+ default y if SANDBOX
+ help
+ This enables a 'log test' command to test logging. It is normally
+ executed from a pytest and simply outputs logging information
+ in various different ways to test that the logging system works
+ correctly with varoius settings.
+
+endmenu
+
config DEFAULT_FDT_FILE
string "Default fdt file"
help
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
obj-$(CONFIG_CMD_DFU) += dfu.o
obj-y += command.o
+obj-$(CONFIG_$(SPL_)LOG) += log.o
+obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o
obj-y += s_record.o
obj-y += xyzModem.o
#include <i2c.h>
#include <initcall.h>
#include <init_helpers.h>
-#include <logbuff.h>
#include <malloc.h>
#include <mapmem.h>
#include <os.h>
return 0;
}
-#if defined(CONFIG_LOGBUFFER)
-static int reserve_logbuffer(void)
-{
-#ifndef CONFIG_ALT_LB_ADDR
- /* reserve kernel log buffer */
- gd->relocaddr -= LOGBUFF_RESERVE;
- debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
- gd->relocaddr);
-#endif
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_PRAM
/* reserve protected RAM */
static int reserve_pram(void)
trace_early_init,
#endif
initf_malloc,
+ log_init,
initf_bootstage, /* uses its own timer, so does not need DM */
initf_console_record,
#if defined(CONFIG_HAVE_FSP)
* - board info struct
*/
setup_dest_addr,
-#if defined(CONFIG_LOGBUFFER)
- reserve_logbuffer,
-#endif
#ifdef CONFIG_PRAM
reserve_pram,
#endif
* The pre-relocation drivers may be using memory that has now gone
* away. Mark serial as unavailable - this will fall back to the debug
* UART if available.
+ *
+ * Do the same with log drivers since the memory may not be available.
*/
- gd->flags &= ~GD_FLG_SERIAL_READY;
+ gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
#ifdef CONFIG_TIMER
gd->timer = NULL;
#endif
#if defined(CONFIG_CMD_KGDB)
#include <kgdb.h>
#endif
-#include <logbuff.h>
#include <malloc.h>
#include <mapmem.h>
#ifdef CONFIG_BITBANGMII
}
#endif
-#ifdef CONFIG_LOGBUFFER
-unsigned long logbuffer_base(void)
-{
- return gd->ram_top - LOGBUFF_LEN;
-}
-
-static int initr_logbuffer(void)
-{
- logbuff_init_ptrs();
- return 0;
-}
-#endif
-
#ifdef CONFIG_POST
static int initr_post_backlog(void)
{
}
#endif
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
+#if defined(CONFIG_PRAM)
/*
* Export available size of memory for Linux, taking into account the
* protected RAM at top of memory
# ifdef CONFIG_PRAM
pram = env_get_ulong("pram", 10, CONFIG_PRAM);
-# endif
-# if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
- /* Also take the logbuffer into account (pram is in kB) */
- pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
# endif
sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram));
env_set("mem", memsz);
#endif
initr_barrier,
initr_malloc,
+ log_init,
initr_bootstage, /* Needs malloc() but has its own timer */
initr_console_record,
#ifdef CONFIG_SYS_NONCACHED_MEMORY
board_early_init_r,
#endif
INIT_FUNC_WATCHDOG_RESET
-#ifdef CONFIG_LOGBUFFER
- initr_logbuffer,
-#endif
#ifdef CONFIG_POST
initr_post_backlog,
#endif
INIT_FUNC_WATCHDOG_RESET
initr_bedbug,
#endif
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
+#if defined(CONFIG_PRAM)
initr_mem,
#endif
#ifdef CONFIG_PS2KBD
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
gd = new_gd;
#endif
+ gd->flags &= ~GD_FLG_LOG_READY;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
#endif
#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
/* find bitstreams */
ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
NULL, NULL);
return len;
}
-static char tmp_buf[CONFIG_SYS_CBSIZE]; /* copy of console I/O buffer */
+static char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */
int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
{
void putc(const char c)
{
+#ifdef CONFIG_SANDBOX
+ /* sandbox can send characters to stdout before it has a console */
+ if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
+ os_putc(c);
+ return;
+ }
+#endif
#ifdef CONFIG_DEBUG_UART
/* if we don't have a console yet, use the debug UART */
if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
return p - (char *)buf;
}
+int fdt_record_loadable(void *blob, u32 index, const char *name,
+ uintptr_t load_addr, u32 size, uintptr_t entry_point,
+ const char *type, const char *os)
+{
+ int err, node;
+
+ err = fdt_check_header(blob);
+ if (err < 0) {
+ printf("%s: %s\n", __func__, fdt_strerror(err));
+ return err;
+ }
+
+ /* find or create "/fit-images" node */
+ node = fdt_find_or_add_subnode(blob, 0, "fit-images");
+ if (node < 0)
+ return node;
+
+ /* find or create "/fit-images/<name>" node */
+ node = fdt_find_or_add_subnode(blob, node, name);
+ if (node < 0)
+ return node;
+
+ /*
+ * We record these as 32bit entities, possibly truncating addresses.
+ * However, spl_fit.c is not 64bit safe either: i.e. we should not
+ * have an issue here.
+ */
+ fdt_setprop_u32(blob, node, "load-addr", load_addr);
+ if (entry_point != -1)
+ fdt_setprop_u32(blob, node, "entry-point", entry_point);
+ fdt_setprop_u32(blob, node, "size", size);
+ if (type)
+ fdt_setprop_string(blob, node, "type", type);
+ if (os)
+ fdt_setprop_string(blob, node, "os", os);
+
+ return node;
+}
+
#ifdef CONFIG_NR_DRAM_BANKS
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
return 0;
}
+/**
+ * Get 'data-position' property from a given image node.
+ *
+ * @fit: pointer to the FIT image header
+ * @noffset: component image node offset
+ * @data_position: holds the data-position property
+ *
+ * returns:
+ * 0, on success
+ * -ENOENT if the property could not be found
+ */
+int fit_image_get_data_position(const void *fit, int noffset,
+ int *data_position)
+{
+ const fdt32_t *val;
+
+ val = fdt_getprop(fit, noffset, FIT_DATA_POSITION_PROP, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *data_position = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
/**
* Get 'data-size' property from a given image node.
*
#include <status_led.h>
#endif
-#ifdef CONFIG_LOGBUFFER
-#include <logbuff.h>
-#endif
-
#include <rtc.h>
#include <environment.h>
static const table_entry_t uimage_os[] = {
{ IH_OS_INVALID, "invalid", "Invalid OS", },
+ { IH_OS_ARM_TRUSTED_FIRMWARE, "arm-trusted-firmware", "ARM Trusted Firmware" },
{ IH_OS_LINUX, "linux", "Linux", },
#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
{ IH_OS_LYNXOS, "lynxos", "LynxOS", },
}
-#ifdef CONFIG_LOGBUFFER
- /* Prevent initrd from overwriting logbuffer */
- lmb_reserve(lmb, logbuffer_base() - LOGBUFF_OVERHEAD, LOGBUFF_RESERVE);
-#endif
-
debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
initrd_high, initrd_copy_to_ram);
* AMP boot scenarios in which we might not be
* HW cache coherent
*/
- flush_cache((unsigned long)*initrd_start, rd_len);
+ flush_cache((unsigned long)*initrd_start,
+ ALIGN(rd_len, ARCH_DMA_MINALIGN));
#endif
puts("OK\n");
}
}
#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
const char *uname, *name;
int err;
int devnum = 0; /* TODO support multi fpga platforms */
- const fpga_desc * const desc = fpga_get_desc(devnum);
- xilinx_desc *desc_xilinx = desc->devdesc;
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
return fit_img_result;
}
- if (img_len >= desc_xilinx->size) {
+ if (!fpga_is_partial_data(devnum, img_len)) {
name = "full";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_FULL);
--- /dev/null
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <log.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct log_device *log_device_find_by_name(const char *drv_name)
+{
+ struct log_device *ldev;
+
+ list_for_each_entry(ldev, &gd->log_head, sibling_node) {
+ if (!strcmp(drv_name, ldev->drv->name))
+ return ldev;
+ }
+
+ return NULL;
+}
+
+/**
+ * log_has_cat() - check if a log category exists within a list
+ *
+ * @cat_list: List of categories to check, at most LOGF_MAX_CATEGORIES entries
+ * long, terminated by LC_END if fewer
+ * @cat: Category to search for
+ * @return true if @cat is in @cat_list, else false
+ */
+static bool log_has_cat(enum log_category_t cat_list[], enum log_category_t cat)
+{
+ int i;
+
+ for (i = 0; i < LOGF_MAX_CATEGORIES && cat_list[i] != LOGC_END; i++) {
+ if (cat_list[i] == cat)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * log_has_file() - check if a file is with a list
+ *
+ * @file_list: List of files to check, separated by comma
+ * @file: File to check for. This string is matched against the end of each
+ * file in the list, i.e. ignoring any preceding path. The list is
+ * intended to consist of relative pathnames, e.g. common/main.c,cmd/log.c
+ * @return true if @file is in @file_list, else false
+ */
+static bool log_has_file(const char *file_list, const char *file)
+{
+ int file_len = strlen(file);
+ const char *s, *p;
+ int substr_len;
+
+ for (s = file_list; *s; s = p + (*p != '\0')) {
+ p = strchrnul(s, ',');
+ substr_len = p - s;
+ if (file_len >= substr_len &&
+ !strncmp(file + file_len - substr_len, s, substr_len))
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * log_passes_filters() - check if a log record passes the filters for a device
+ *
+ * @ldev: Log device to check
+ * @rec: Log record to check
+ * @return true if @rec is not blocked by the filters in @ldev, false if it is
+ */
+static bool log_passes_filters(struct log_device *ldev, struct log_rec *rec)
+{
+ struct log_filter *filt;
+
+ /* If there are no filters, filter on the default log level */
+ if (list_empty(&ldev->filter_head)) {
+ if (rec->level > gd->default_log_level)
+ return false;
+ return true;
+ }
+
+ list_for_each_entry(filt, &ldev->filter_head, sibling_node) {
+ if (rec->level > filt->max_level)
+ continue;
+ if ((filt->flags & LOGFF_HAS_CAT) &&
+ !log_has_cat(filt->cat_list, rec->cat))
+ continue;
+ if (filt->file_list &&
+ !log_has_file(filt->file_list, rec->file))
+ continue;
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * log_dispatch() - Send a log record to all log devices for processing
+ *
+ * The log record is sent to each log device in turn, skipping those which have
+ * filters which block the record
+ *
+ * @rec: Log record to dispatch
+ * @return 0 (meaning success)
+ */
+static int log_dispatch(struct log_rec *rec)
+{
+ struct log_device *ldev;
+
+ list_for_each_entry(ldev, &gd->log_head, sibling_node) {
+ if (log_passes_filters(ldev, rec))
+ ldev->drv->emit(ldev, rec);
+ }
+
+ return 0;
+}
+
+int _log(enum log_category_t cat, enum log_level_t level, const char *file,
+ int line, const char *func, const char *fmt, ...)
+{
+ char buf[CONFIG_SYS_CBSIZE];
+ struct log_rec rec;
+ va_list args;
+
+ rec.cat = cat;
+ rec.level = level;
+ rec.file = file;
+ rec.line = line;
+ rec.func = func;
+ va_start(args, fmt);
+ vsnprintf(buf, sizeof(buf), fmt, args);
+ va_end(args);
+ rec.msg = buf;
+ if (!gd || !(gd->flags & GD_FLG_LOG_READY)) {
+ if (gd)
+ gd->log_drop_count++;
+ return -ENOSYS;
+ }
+ log_dispatch(&rec);
+
+ return 0;
+}
+
+int log_add_filter(const char *drv_name, enum log_category_t cat_list[],
+ enum log_level_t max_level, const char *file_list)
+{
+ struct log_filter *filt;
+ struct log_device *ldev;
+ int i;
+
+ ldev = log_device_find_by_name(drv_name);
+ if (!ldev)
+ return -ENOENT;
+ filt = (struct log_filter *)calloc(1, sizeof(*filt));
+ if (!filt)
+ return -ENOMEM;
+
+ if (cat_list) {
+ filt->flags |= LOGFF_HAS_CAT;
+ for (i = 0; ; i++) {
+ if (i == ARRAY_SIZE(filt->cat_list))
+ return -ENOSPC;
+ filt->cat_list[i] = cat_list[i];
+ if (cat_list[i] == LOGC_END)
+ break;
+ }
+ }
+ filt->max_level = max_level;
+ if (file_list) {
+ filt->file_list = strdup(file_list);
+ if (!filt->file_list)
+ goto nomem;
+ }
+ filt->filter_num = ldev->next_filter_num++;
+ list_add_tail(&filt->sibling_node, &ldev->filter_head);
+
+ return filt->filter_num;
+
+nomem:
+ free(filt);
+ return -ENOMEM;
+}
+
+int log_remove_filter(const char *drv_name, int filter_num)
+{
+ struct log_filter *filt;
+ struct log_device *ldev;
+
+ ldev = log_device_find_by_name(drv_name);
+ if (!ldev)
+ return -ENOENT;
+
+ list_for_each_entry(filt, &ldev->filter_head, sibling_node) {
+ if (filt->filter_num == filter_num) {
+ list_del(&filt->sibling_node);
+ free(filt);
+
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+int log_init(void)
+{
+ struct log_driver *drv = ll_entry_start(struct log_driver, log_driver);
+ const int count = ll_entry_count(struct log_driver, log_driver);
+ struct log_driver *end = drv + count;
+
+ /*
+ * We cannot add runtime data to the driver since it is likely stored
+ * in rodata. Instead, set up a 'device' corresponding to each driver.
+ * We only support having a single device.
+ */
+ INIT_LIST_HEAD((struct list_head *)&gd->log_head);
+ while (drv < end) {
+ struct log_device *ldev;
+
+ ldev = calloc(1, sizeof(*ldev));
+ if (!ldev) {
+ debug("%s: Cannot allocate memory\n", __func__);
+ return -ENOMEM;
+ }
+ INIT_LIST_HEAD(&ldev->filter_head);
+ ldev->drv = drv;
+ list_add_tail(&ldev->sibling_node,
+ (struct list_head *)&gd->log_head);
+ drv++;
+ }
+ gd->flags |= GD_FLG_LOG_READY;
+ gd->default_log_level = LOGL_INFO;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <log.h>
+
+static int log_console_emit(struct log_device *ldev, struct log_rec *rec)
+{
+ puts(rec->msg);
+
+ return 0;
+}
+
+LOG_DRIVER(console) = {
+ .name = "console",
+ .emit = log_console_emit,
+};
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
+config SPL_FIT_IMAGE_TINY
+ bool "Remove functionality from SPL FIT loading to reduce size"
+ depends on SPL_FIT
+ default y if MACH_SUN50I || MACH_SUN50I_H5
+ help
+ Enable this to reduce the size of the FIT image loading code
+ in SPL, if space for the SPL binary is very tight.
+
+ This removes the detection of image types (which forces the
+ first image to be treated as having a U-Boot style calling
+ convention) and skips the recording of each loaded payload
+ (i.e. loadable) into the FDT (modifying the loaded FDT to
+ ensure this information is available to the next image
+ invoked).
+
config SPL_CPU_SUPPORT
bool "Support CPU drivers"
help
means of transmitting U-Boot over a serial line for using in SPL,
with a checksum to ensure correctness.
-config SPL_ATF_SUPPORT
+config SPL_ATF
bool "Support ARM Trusted Firmware"
depends on ARM64
help
is loaded by SPL(which is considered as BL2 in ATF terminology).
More detail at: https://github.com/ARM-software/arm-trusted-firmware
-config SPL_ATF_TEXT_BASE
- depends on SPL_ATF_SUPPORT
- hex "ATF BL31 base address"
- help
- This is the base address in memory for ATF BL31 text and entry point.
-
config TPL
bool
depends on SUPPORT_TPL
obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
-obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o
+obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
*/
#include <common.h>
+#include <binman_sym.h>
#include <dm.h>
#include <spl.h>
#include <asm/u-boot.h>
u32 *boot_params_ptr = NULL;
+/* See spl.h for information about this */
+binman_sym_declare(ulong, u_boot_any, pos);
+
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
spl_image->size = CONFIG_SYS_MONITOR_LEN;
- spl_image->entry_point = CONFIG_SYS_UBOOT_START;
- spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ if (u_boot_pos != BINMAN_SYM_MISSING) {
+ /* biman does not support separate entry addresses at present */
+ spl_image->entry_point = u_boot_pos;
+ spl_image->load_addr = u_boot_pos;
+ } else {
+ spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+ spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ }
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
}
case IH_OS_U_BOOT:
debug("Jumping to U-Boot\n");
break;
+#if CONFIG_IS_ENABLED(ATF)
+ case IH_OS_ARM_TRUSTED_FIRMWARE:
+ debug("Jumping to U-Boot via ARM Trusted Firmware\n");
+ spl_invoke_atf(&spl_image);
+ break;
+#endif
#ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
debug("Failed to stash bootstage: err=%d\n", ret);
#endif
- if (CONFIG_IS_ENABLED(ATF_SUPPORT)) {
- debug("loaded - jumping to U-Boot via ATF BL31.\n");
- bl31_entry();
- }
-
debug("loaded - jumping to U-Boot...\n");
spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
* reserved.
* Copyright (C) 2016 Rockchip Electronic Co.,Ltd
* Written by Kever Yang <kever.yang@rock-chips.com>
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: BSD-3-Clause
*/
*
* @return bl31 params structure pointer
*/
-struct bl31_params *bl2_plat_get_bl31_params(void)
+static struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl33_entry)
{
struct entry_point_info *bl33_ep_info;
/* BL33 expects to receive the primary CPU MPID (through x0) */
bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
- bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE;
+ bl33_ep_info->pc = bl33_entry;
bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXECPTIONS);
return bl2_to_bl31_params;
}
-void raw_write_daif(unsigned int daif)
+static inline void raw_write_daif(unsigned int daif)
{
__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
}
-void bl31_entry(void)
+typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
+
+static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl33_entry,
+ uintptr_t fdt_addr)
{
struct bl31_params *bl31_params;
- void (*entry)(struct bl31_params *params, void *plat_params) = NULL;
+ atf_entry_t atf_entry = (atf_entry_t)bl31_entry;
- bl31_params = bl2_plat_get_bl31_params();
- entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
+ bl31_params = bl2_plat_get_bl31_params(bl33_entry);
raw_write_daif(SPSR_EXCEPTION_MASK);
dcache_disable();
- entry(bl31_params, NULL);
+ atf_entry((void *)bl31_params, (void *)fdt_addr);
+}
+
+static int spl_fit_images_find_uboot(void *blob)
+{
+ int parent, node, ndepth;
+ const void *data;
+
+ if (!blob)
+ return -FDT_ERR_BADMAGIC;
+
+ parent = fdt_path_offset(blob, "/fit-images");
+ if (parent < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ for (node = fdt_next_node(blob, parent, &ndepth);
+ (node >= 0) && (ndepth > 0);
+ node = fdt_next_node(blob, node, &ndepth)) {
+ if (ndepth != 1)
+ continue;
+
+ data = fdt_getprop(blob, node, FIT_OS_PROP, NULL);
+ if (!data)
+ continue;
+
+ if (genimg_get_os_id(data) == IH_OS_U_BOOT)
+ return node;
+ };
+
+ return -FDT_ERR_NOTFOUND;
+}
+
+uintptr_t spl_fit_images_get_entry(void *blob, int node)
+{
+ ulong val;
+
+ val = fdt_getprop_u32(blob, node, "entry-point");
+ if (val == FDT_ERROR)
+ val = fdt_getprop_u32(blob, node, "load-addr");
+
+ debug("%s: entry point 0x%lx\n", __func__, val);
+ return val;
+}
+
+void spl_invoke_atf(struct spl_image_info *spl_image)
+{
+ uintptr_t bl33_entry = CONFIG_SYS_TEXT_BASE;
+ void *blob = spl_image->fdt_addr;
+ int node;
+
+ /*
+ * Find the U-Boot binary (in /fit-images) load addreess or
+ * entry point (if different) and pass it as the BL3-3 entry
+ * point.
+ * This will need to be extended to support Falcon mode.
+ */
+
+ node = spl_fit_images_find_uboot(blob);
+ if (node >= 0)
+ bl33_entry = spl_fit_images_get_entry(blob, node);
+
+ /*
+ * We don't provide a BL3-2 entry yet, but this will be possible
+ * using similar logic.
+ */
+ bl31_entry(spl_image->entry_point, bl33_entry, (uintptr_t)blob);
}
* Copyright (C) 2016 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#endif
/**
- * spl_fit_get_image_node(): By using the matching configuration subnode,
+ * spl_fit_get_image_name(): By using the matching configuration subnode,
* retrieve the name of an image, specified by a property name and an index
* into that.
* @fit: Pointer to the FDT blob.
* @images: Offset of the /images subnode.
* @type: Name of the property within the configuration subnode.
* @index: Index into the list of strings in this property.
+ * @outname: Name of the image
*
- * Return: the node offset of the respective image node or a negative
- * error number.
+ * Return: 0 on success, or a negative error number
*/
-static int spl_fit_get_image_node(const void *fit, int images,
- const char *type, int index)
+static int spl_fit_get_image_name(const void *fit, int images,
+ const char *type, int index,
+ char **outname)
{
const char *name, *str;
- int node, conf_node;
+ __maybe_unused int node;
+ int conf_node;
int len, i;
conf_node = fit_find_config_node(fit);
}
}
+ *outname = (char *)str;
+ return 0;
+}
+
+/**
+ * spl_fit_get_image_node(): By using the matching configuration subnode,
+ * retrieve the name of an image, specified by a property name and an index
+ * into that.
+ * @fit: Pointer to the FDT blob.
+ * @images: Offset of the /images subnode.
+ * @type: Name of the property within the configuration subnode.
+ * @index: Index into the list of strings in this property.
+ *
+ * Return: the node offset of the respective image node or a negative
+ * error number.
+ */
+static int spl_fit_get_image_node(const void *fit, int images,
+ const char *type, int index)
+{
+ char *str;
+ int err;
+ int node;
+
+ err = spl_fit_get_image_name(fit, images, type, index, &str);
+ if (err)
+ return err;
+
debug("%s: '%s'\n", type, str);
+
node = fdt_subnode_offset(fit, images, str);
if (node < 0) {
debug("cannot find image node '%s': %d\n", str, node);
* @info: points to information about the device to load data from
* @sector: the start sector of the FIT image on the device
* @fit: points to the flattened device tree blob describing the FIT
- * image
+ * image
* @base_offset: the beginning of the data area containing the actual
* image data, relative to the beginning of the FIT
* @node: offset of the DT node describing the image to load (relative
- * to @fit)
+ * to @fit)
* @image_info: will be filled with information about the loaded image
- * If the FIT node does not contain a "load" (address) property,
- * the image gets loaded to the address pointed to by the
- * load_addr member in this struct.
+ * If the FIT node does not contain a "load" (address) property,
+ * the image gets loaded to the address pointed to by the
+ * load_addr member in this struct.
*
* Return: 0 on success or a negative error number.
*/
int align_len = ARCH_DMA_MINALIGN - 1;
uint8_t image_comp = -1, type = -1;
const void *data;
+ bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, &image_comp))
if (fit_image_get_load(fit, node, &load_addr))
load_addr = image_info->load_addr;
- if (!fit_image_get_data_offset(fit, node, &offset)) {
- /* External data */
+ if (!fit_image_get_data_position(fit, node, &offset)) {
+ external_data = true;
+ } else if (!fit_image_get_data_offset(fit, node, &offset)) {
offset += base_offset;
+ external_data = true;
+ }
+
+ if (external_data) {
+ /* External data */
if (fit_image_get_data_size(fit, node, &len))
return -ENOENT;
return 0;
}
+static int spl_fit_append_fdt(struct spl_image_info *spl_image,
+ struct spl_load_info *info, ulong sector,
+ void *fit, int images, ulong base_offset)
+{
+ struct spl_image_info image_info;
+ int node, ret;
+
+ /* Figure out which device tree the board wants to use */
+ node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+ if (node < 0) {
+ debug("%s: cannot find FDT node\n", __func__);
+ return node;
+ }
+
+ /*
+ * Read the device tree and place it after the image.
+ * Align the destination address to ARCH_DMA_MINALIGN.
+ */
+ image_info.load_addr = spl_image->load_addr + spl_image->size;
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ &image_info);
+
+ if (ret < 0)
+ return ret;
+
+ /* Make the load-address of the FDT available for the SPL framework */
+ spl_image->fdt_addr = (void *)image_info.load_addr;
+#if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+ /* Try to make space, so we can inject details on the loadables */
+ ret = fdt_shrink_to_minimum(spl_image->fdt_addr, 8192);
+#endif
+
+ return ret;
+}
+
+static int spl_fit_record_loadable(const void *fit, int images, int index,
+ void *blob, struct spl_image_info *image)
+{
+ int ret = 0;
+#if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+ char *name;
+ int node;
+
+ ret = spl_fit_get_image_name(fit, images, "loadables",
+ index, &name);
+ if (ret < 0)
+ return ret;
+
+ node = spl_fit_get_image_node(fit, images, "loadables", index);
+
+ ret = fdt_record_loadable(blob, index, name, image->load_addr,
+ image->size, image->entry_point,
+ fdt_getprop(fit, node, "type", NULL),
+ fdt_getprop(fit, node, "os", NULL));
+#endif
+ return ret;
+}
+
+static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
+{
+#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+ return -ENOTSUPP;
+#else
+ return fit_image_get_os(fit, noffset, os);
+#endif
+}
+
int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
{
ulong size;
unsigned long count;
struct spl_image_info image_info;
- bool boot_os = false;
int node = -1;
int images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
return -1;
}
+ /*
+ * Find the U-Boot image using the following search order:
+ * - start at 'firmware' (e.g. an ARM Trusted Firmware)
+ * - fall back 'kernel' (e.g. a Falcon-mode OS boot
+ * - fall back to using the first 'loadables' entry
+ */
+ if (node < 0)
+ node = spl_fit_get_image_node(fit, images, "firmware", 0);
#ifdef CONFIG_SPL_OS_BOOT
- /* Find OS image first */
- node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
if (node < 0)
- debug("No kernel image.\n");
- else
- boot_os = true;
+ node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
#endif
- /* find the U-Boot image */
- if (node < 0)
- node = spl_fit_get_image_node(fit, images, "firmware", 0);
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
if (ret)
return ret;
-#ifdef CONFIG_SPL_OS_BOOT
- if (!fit_image_get_os(fit, node, &spl_image->os))
+ /*
+ * For backward compatibility, we treat the first node that is
+ * as a U-Boot image, if no OS-type has been declared.
+ */
+ if (!spl_fit_image_get_os(fit, node, &spl_image->os))
debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
-#else
- spl_image->os = IH_OS_U_BOOT;
+#if !defined(CONFIG_SPL_OS_BOOT)
+ else
+ spl_image->os = IH_OS_U_BOOT;
#endif
- if (!boot_os) {
- /* Figure out which device tree the board wants to use */
- node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
- if (node < 0) {
- debug("%s: cannot find FDT node\n", __func__);
- return node;
- }
-
- /*
- * Read the device tree and place it after the image.
- * Align the destination address to ARCH_DMA_MINALIGN.
- */
- image_info.load_addr = spl_image->load_addr + spl_image->size;
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- &image_info);
- if (ret < 0)
- return ret;
- }
+ /*
+ * Booting a next-stage U-Boot may require us to append the FDT.
+ * We allow this to fail, as the U-Boot image might embed its FDT.
+ */
+ if (spl_image->os == IH_OS_U_BOOT)
+ spl_fit_append_fdt(spl_image, info, sector, fit,
+ images, base_offset);
/* Now check if there are more images for us to load */
for (; ; index++) {
+ uint8_t os_type = IH_OS_INVALID;
+
node = spl_fit_get_image_node(fit, images, "loadables", index);
if (node < 0)
break;
if (ret < 0)
continue;
+ if (!spl_fit_image_get_os(fit, node, &os_type))
+ debug("Loadable is %s\n", genimg_get_os_name(os_type));
+
+ if (os_type == IH_OS_U_BOOT) {
+ spl_fit_append_fdt(&image_info, info, sector,
+ fit, images, base_offset);
+ spl_image->fdt_addr = image_info.fdt_addr;
+ }
+
/*
* If the "firmware" image did not provide an entry point,
* use the first valid entry point from the loadables.
if (spl_image->entry_point == FDT_ERROR &&
image_info.entry_point != FDT_ERROR)
spl_image->entry_point = image_info.entry_point;
+
+ /* Record our loadables into the FDT */
+ if (spl_image->fdt_addr)
+ spl_fit_record_loadable(fit, images, index,
+ spl_image->fdt_addr,
+ &image_info);
}
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <binman_sym.h>
+#include <mapmem.h>
#include <spl.h>
#include <libfdt.h>
load.read = spl_ram_load_read;
spl_load_simple_fit(spl_image, &load, 0, header);
} else {
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
debug("Legacy image\n");
/*
* Get the header. It will point to an address defined by
* handoff which will tell where the image located inside
- * the flash. For now, it will temporary fixed to address
- * pointed by U-Boot.
+ * the flash.
*/
- header = (struct image_header *)
- (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+ debug("u_boot_pos = %lx\n", u_boot_pos);
+ if (u_boot_pos == BINMAN_SYM_MISSING) {
+ /*
+ * No binman support or no information. For now, fix it
+ * to the address pointed to by U-Boot.
+ */
+ u_boot_pos = CONFIG_SYS_TEXT_BASE -
+ sizeof(struct image_header);
+ }
+ header = (struct image_header *)map_sysmem(u_boot_pos, 0);
spl_parse_image_header(spl_image, header);
}
#include <malloc.h>
#include <stdio_dev.h>
#include <serial.h>
-#ifdef CONFIG_LOGBUFFER
-#include <logbuff.h>
-#endif
#if defined(CONFIG_SYS_I2C)
#include <i2c.h>
#endif /* CONFIG_DM_VIDEO */
#if defined(CONFIG_KEYBOARD) && !defined(CONFIG_DM_KEYBOARD)
drv_keyboard_init ();
-#endif
-#ifdef CONFIG_LOGBUFFER
- drv_logbuff_init ();
#endif
drv_system_init ();
serial_stdio_init ();
static LIST_HEAD(usb_scan_list);
-__weak void usb_hub_reset_devices(int port)
+__weak void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
return;
}
short hubCharacteristics;
struct usb_hub_descriptor *descriptor;
struct usb_hub_device *hub;
- __maybe_unused struct usb_hub_status *hubsts;
+ struct usb_hub_status *hubsts;
int ret;
hub = usb_get_hub_device(dev);
return ret;
}
-#ifdef DEBUG
hubsts = (struct usb_hub_status *)buffer;
-#endif
debug("get_hub_status returned status %X, change %X\n",
le16_to_cpu(hubsts->wHubStatus),
* should occur in the board file of the device.
*/
for (i = 0; i < dev->maxchild; i++)
- usb_hub_reset_devices(i + 1);
+ usb_hub_reset_devices(hub, i + 1);
/*
* Only add the connected USB devices, including potential hubs,
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SCSI_AHCI=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DM_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
+CONFIG_FSL_SATA=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+CONFIG_SCSI_AHCI=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+CONFIG_SCSI_AHCI=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_BMP=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SCSI=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_FASTBOOT_FLASH=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SATA_SIL3114=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_NDS32=y
+CONFIG_FTSDC010=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
-CONFIG_NDS_AE3XX_SPI=y
+CONFIG_ATCSPI200_SPI=y
CONFIG_TIMER=y
-CONFIG_AE3XX_TIMER=y
+CONFIG_ATCPIT100_TIMER=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_NDS32=y
+CONFIG_FTSDC010=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
CONFIG_ISO_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_PHYLIB=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_AM33XX=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_AM33XX=y
CONFIG_NOR=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_NOR_BOOT=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_AM33XX=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_PHYLIB=y
CONFIG_DM_GPIO=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_PHYLIB=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_CMD_PCA953X=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_STORAGE=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_AHCI=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SCSI_AHCI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffb0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_SATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_SATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SATA_MV=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 factory > "
-CONFIG_BOOTCMD_OVERRIDE=y
-CONFIG_BOOTCOMMAND="run factory"
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_PM8916_GPIO=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_MMC=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT2=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3128=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT_BUF_ADDR=0x60800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3128=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_DEBUG_UART=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SPL_ATF_SUPPORT=y
-CONFIG_SPL_ATF_TEXT_BASE=0x00010000
+CONFIG_SPL_ATF=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_NVRAM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_SCSI=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
CONFIG_CRC32_VERIFY=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ISIOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ISIOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6UL_ISIOT=y
+CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXL=y
+CONFIG_TARGET_KHADAS_VIM=y
+CONFIG_IDENT_STRING=" khadas-vim"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXL=y
+CONFIG_TARGET_LIBRETECH_CC=y
+CONFIG_IDENT_STRING=" libretech-cc"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
-CONFIG_SPL_ATF_SUPPORT=y
-CONFIG_SPL_ATF_TEXT_BASE=0x10000
+CONFIG_SPL_ATF=y
CONFIG_TPL=y
CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_PARTITIONS=y
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_BUILD=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_PARTITIONS=y
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_BUILD=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
-CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
-CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1024k(u-boot),512k(env1),512k(env2),14m(boot),240m(data),-@2048k(UBI)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DWC_AHSATA=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SYS_NS16550=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin"
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_TARGET_MX53PPD=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_EXT=y
+CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
+CONFIG_NETDEVICES=y
+CONFIG_RTC_S35392A=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc1,115200 "
+CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
-CONFIG_IDENT_STRING=" for ODROID-XU3"
+CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1"
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MPUCLK=720
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
-CONFIG_LOGLEVEL=3
+CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
-CONFIG_LOGLEVEL=3
+CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
-CONFIG_LOGLEVEL=3
+CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_IDENT_STRING=" p212"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212"
CONFIG_DEBUG_UART=y
-CONFIG_ENV_IS_NOWHERE=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_PHY_MESON_GXL=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_FASTBOOT_FLASH=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_TARGET_PUMA_RK3399=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD=y
+CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77970=y
+CONFIG_TARGET_EAGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77995=y
+CONFIG_TARGET_DRAAK=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3188=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
-# CONFIG_TPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_0_W=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_DM_ETH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
-CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_USB_ETHER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
-CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_USB_ETHER=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=6
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_NETCONSOLE=y
CONFIG_CLK=y
CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PINCTRL_STM32=y
CONFIG_RAM=y
CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
CONFIG_STM32X7_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="opalkelly"
+CONFIG_SYS_CONFIG_NAME="syzygy_hub"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_DM_THERMAL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_TYPE=7
+CONFIG_DRAM_CLK=648
+CONFIG_DRAM_ZQ=15355
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH11"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_AXP_DCDC5_VOLT=1200
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SATA_MV=y
CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_MISC=y
CONFIG_ATSHA204A=y
CONFIG_MMC_SDHCI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
-CONFIG_NAND_OMAP_GPMC_PREFETCH=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_NETDEVICES=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_LOGLEVEL=6
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_MMC_UNIPHIER=y
CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_NETDEVICES=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_LOGLEVEL=6
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_MMC_UNIPHIER=y
CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_NETDEVICES=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_LOGLEVEL=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CONFIG=y
CONFIG_CMD_IMLS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_WB45N=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_LZMA=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_WB50N=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_LZMA=y
+CONFIG_OF_LIBFDT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_CMD_THOR_DOWNLOAD=y
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_DM_MMC=y
CONFIG_NAND=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_PCA953X=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+# CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
+CONFIG_DEBUG_UART=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_SPL is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_CLK is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SPL_BLK is not set
+# CONFIG_ZYNQ_GPIO is not set
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART_ARM_DCC=y
+CONFIG_DEBUG_UART_BASE=0x0
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_ZYNQ_QSPI=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_CACHE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_ZYNQ=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_CACHE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
common when EFI is the bootloader. Note 2TB partition limit;
see disk/part_efi.c
+config EFI_PARTITION_ENTRIES_NUMBERS
+ int "Number of the EFI partition entries"
+ depends on EFI_PARTITION
+ default 56 if ARCH_SUNXI
+ default 128
+ help
+ Specify the number of partition entries in the GPT. This is
+ meant to allow less than the standard specifies for devices
+ that might need to place their first-stage bootloader in the
+ middle of a regular GPT.
+
+ If unsure, leave at 128 entries, which is the standard
+ number.
+
config EFI_PARTITION_ENTRIES_OFF
int "Offset (in bytes) of the EFI partition entries"
depends on EFI_PARTITION
static int set_protective_mbr(struct blk_desc *dev_desc)
{
/* Setup the Protective MBR */
- ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, dev_desc->blksz);
memset(p_mbr, 0, sizeof(*p_mbr));
if (p_mbr == NULL) {
return 0;
}
- ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, dev_desc->blksz);
/* Read MBR Header from device */
if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) {
--- /dev/null
+Logging in U-Boot
+=================
+
+Introduction
+------------
+
+U-Boot's internal operation involves many different steps and actions. From
+setting up the board to displaying a start-up screen to loading an Operating
+System, there are many component parts each with many actions.
+
+Most of the time this internal detail is not useful. Displaying it on the
+console would delay booting (U-Boot's primary purpose) and confuse users.
+
+But for digging into what is happening in a particular area, or for debugging
+a problem it is often useful to see what U-Boot is doing in more detail than
+is visible from the basic console output.
+
+U-Boot's logging feature aims to satisfy this goal for both users and
+developers.
+
+
+Logging levels
+--------------
+
+There are a number logging levels available, in increasing order of verbosity:
+
+ LOGL_EMERG - Printed before U-Boot halts
+ LOGL_ALERT - Indicates action must be taken immediate or U-Boot will crash
+ LOGL_CRIT - Indicates a critical error that will cause boot failure
+ LOGL_ERR - Indicates an error that may cause boot failure
+ LOGL_WARNING - Warning about an unexpected condition
+ LOGL_NOTE - Important information about progress
+ LOGL_INFO - Information about normal boot progress
+ LOGL_DEBUG - Debug information (useful for debugging a driver or subsystem)
+ LOGL_DEBUG_CONTENT - Debug message showing full message content
+ LOGL_DEBUG_IO - Debug message showing hardware I/O access
+
+
+Logging category
+----------------
+
+Logging can come from a wide variety of places within U-Boot. Each log message
+has a category which is intended to allow messages to be filtered according to
+their source.
+
+The following main categories are defined:
+
+ LOGC_NONE - Unknown category (e.g. a debug() statement)
+ UCLASS_... - Related to a particular uclass (e.g. UCLASS_USB)
+ LOGC_ARCH - Related to architecture-specific code
+ LOGC_BOARD - Related to board-specific code
+ LOGC_CORE - Related to core driver-model support
+ LOGC_DT - Related to device tree control
+
+
+Enabling logging
+----------------
+
+The following options are used to enable logging at compile time:
+
+ CONFIG_LOG - Enables the logging system
+ CONFIG_MAX_LOG_LEVEL - Max log level to build (anything higher is compiled
+ out)
+ CONFIG_LOG_CONSOLE - Enable writing log records to the console
+
+If CONFIG_LOG is not set, then no logging will be available.
+
+The above have SPL versions also, e.g. CONFIG_SPL_MAX_LOG_LEVEL.
+
+
+Using DEBUG
+-----------
+
+U-Boot has traditionally used a #define called DEBUG to enable debugging on a
+file-by-file basis. The debug() macro compiles to a printf() statement if
+DEBUG is enabled, and an empty statement if not.
+
+With logging enabled, debug() statements are interpreted as logging output
+with a level of LOGL_DEBUG and a category of LOGC_NONE.
+
+The logging facilities are intended to replace DEBUG, but if DEBUG is defined
+at the top of a file, then it takes precedence. This means that debug()
+statements will result in output to the console and this output will not be
+logged.
+
+
+Logging destinations
+--------------------
+
+If logging information goes nowhere then it serves no purpose. U-Boot provides
+several possible determinations for logging information, all of which can be
+enabled or disabled independently:
+
+ console - goes to stdout
+
+
+Filters
+-------
+
+Filters are attached to log drivers to control what those drivers emit. Only
+records that pass through the filter make it to the driver.
+
+Filters can be based on several criteria:
+
+ - maximum log level
+ - in a set of categories
+ - in a set of files
+
+If no filters are attached to a driver then a default filter is used, which
+limits output to records with a level less than CONFIG_LOG_MAX_LEVEL.
+
+
+Logging statements
+------------------
+
+The main logging function is:
+
+ log(category, level, format_string, ...)
+
+Also debug() and error() will generate log records - these use LOG_CATEGORY
+as the category, so you should #define this right at the top of the source
+file to ensure the category is correct.
+
+
+Code size
+---------
+
+Code size impact depends largely on what is enabled. The following numbers are
+for snow, which is a Thumb-2 board:
+
+This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0
+CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text +1048.0
+CONFIG_LOG_MAX_LEVEL=7: bss +188.0 data +4.0 rodata +49183.0 text +98124.0
+
+The last option turns every debug() statement into a logging call, which
+bloats the code hugely. The advantage is that it is then possible to enable
+all logging within U-Boot.
+
+
+To Do
+-----
+
+There are lots of useful additions that could be made. None of the below is
+implemented! If you do one, please add a test in test/py/tests/test_log.py
+
+Convenience functions to support setting the category:
+
+ log_arch(level, format_string, ...) - category LOGC_ARCH
+ log_board(level, format_string, ...) - category LOGC_BOARD
+ log_core(level, format_string, ...) - category LOGC_CORE
+ log_dt(level, format_string, ...) - category LOGC_DT
+
+Convenience functions to support a category defined for a single file, for
+example:
+
+ #define LOG_CATEGORY UCLASS_USB
+
+all of these can use LOG_CATEGORY as the category, and a log level
+corresponding to the function name:
+
+ logc(level, format_string, ...)
+
+More logging destinations:
+
+ device - goes to a device (e.g. serial)
+ buffer - recorded in a memory buffer
+
+Convert debug() statements in the code to log() statements
+
+Support making printf() emit log statements a L_INFO level
+
+Convert error() statements in the code to log() statements
+
+Figure out what to do with BUG(), BUG_ON() and warn_non_spl()
+
+Figure out what to do with assert()
+
+Add a way to browse log records
+
+Add a way to record log records for browsing using an external tool
+
+Add commands to add and remove filters
+
+Add commands to add and remove log devices
+
+Allow sharing of printf format strings in log records to reduce storage size
+for large numbers of log records
+
+Add a command-line option to sandbox to set the default logging level
+
+Convert core driver model code to use logging
+
+Convert uclasses to use logging with the correct category
+
+Consider making log() calls emit an automatic newline, perhaps with a logn()
+ function to avoid that
+
+Passing log records through to linux (e.g. via device tree /chosen)
+
+Provide a command to access the number of log records generated, and the
+number dropped due to them being generated before the log system was ready.
+
+Add a printf() format string pragma so that log statements are checked properly
+
+Enhance the log console driver to show level / category / file / line
+information
+
+Add a command to add new log records and delete existing records.
+
+Provide additional log() functions - e.g. logc() to specify the category
+
+--
+Simon Glass <sjg@chromium.org>
+15-Sep-17
The bootrom of rk3188 expects to find a small 1kb loader which returns
control to the bootrom, after which it will load the real loader, which
-can then be up to 29kb in size and does the regular ddr init.
+can then be up to 29kb in size and does the regular ddr init. This is
+handled by a single image (built as the SPL stage) that tests whether
+it is handled for the first or second time via code executed from the
+boot0-hook.
Additionally the rk3188 requires everything the bootrom loads to be
rc4-encrypted. Except for the very first stage the bootrom always reads
and decodes 2kb pages, so files should be sized accordingly.
# copy tpl, pad to 1020 bytes and append spl
-cat tpl/u-boot-tpl.bin > tplspl.bin
-truncate -s 1020 tplspl.bin
-cat spl/u-boot-spl.bin >> tplspl.bin
-tools/mkimage -n rk3188 -T rksd -d tplspl.bin out
+tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out
# truncate, encode and append u-boot.bin
truncate -s %2048 u-boot.bin
--- /dev/null
+* Synopsys HSDK clock generation unit
+
+The Synopsys HSDK clock controller generates and supplies clock to various
+controllers and peripherals within the SoC.
+
+Required Properties:
+
+- compatible: should be "snps,hsdk-cgu-clock"
+- reg: the pair of physical base address and length of clock generation unit
+ memory mapped region and creg arc core divider memory mapped region.
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
+used in device tree sources.
+
+Example: Clock controller node:
+
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+controller:
+
+ uart0: serial0@f0005000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0005000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cgu_clk CLK_SYS_UART_REF>;
+ };
If present (and SPL is controlled by the device-tree), this allows
to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value
from the device-tree.
+
+sysreset-gpio
+ If present (and supported by the specific board), indicates a
+ GPIO that can be set to trigger a system reset. It is assumed
+ that such a system reset will effect a complete platform reset,
+ being roughly equivalent to a power-on reset.
--- /dev/null
+Altera SOCFPGA Arria10 FPGA Manager
+
+Required properties:
+- compatible : should contain "altr,socfpga-a10-fpga-mgr"
+- reg : base address and size for memory mapped io.
+ - The first index is for FPGA manager register access.
+ - The second index is for writing FPGA configuration data.
+- resets : Phandle and reset specifier for the device's reset.
+- clocks : Clocks used by the device.
+
+Example:
+
+ fpga_mgr: fpga-mgr@ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ };
Binding:
The regulator devices don't use the "compatible" property. The binding is done
-by the prefix of regulator node's name. Usually the pmic I/O driver will provide
+by the prefix of regulator node's name, or, if this fails, by the prefix of the
+regulator's "regulator-name" property. Usually the pmic I/O driver will provide
the array of 'struct pmic_child_info' with the prefixes and compatible drivers.
The bind is done by calling function: pmic_bind_childs().
Example drivers:
Example the prefix "ldo" will pass for: "ldo1", "ldo@1", "ldoreg@1, ...
+Binding by means of the node's name is preferred. However if the node names
+would produce ambiguous prefixes (like "regulator@1" and "regualtor@11") and you
+can't or do not want to change them then binding against the "regulator-name"
+property is possible. The syntax for the prefix of the "regulator-name" property
+is the same as the one for the regulator's node name.
+Use case: a regulator named "regulator@1" to be bound to a driver named
+"LDO_DRV" and a regulator named "regualator@11" to be bound to an other driver
+named "BOOST_DRV". Using prefix "regualtor@1" for driver matching would load
+the same driver for both regulators, hence the prefix is ambiguous.
+
Optional properties:
-- regulator-name: a string, required by the regulator uclass
+- regulator-name: a string, required by the regulator uclass, used for driver
+ binding if binding by node's name prefix fails
- regulator-min-microvolt: a minimum allowed Voltage value
- regulator-max-microvolt: a maximum allowed Voltage value
- regulator-min-microamp: a minimum allowed Current value
--- /dev/null
+Andestech ATCSPI200 SPI controller Device Tree Bindings
+-------------------------------------------------------
+ATCSPI200 is a Serial Peripheral Interface (SPI) controller
+which serves as a SPI master or a SPI slave.
+
+It is often be embedded in AE3XX and AE250 platforms.
+
+Required properties:
+- compatible: has to be "andestech,atcspi200".
+- reg: Base address and size of the controllers memory area.
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: Clock phandles (see clock bindings for details).
+- spi-max-frequency: Maximum SPI clocking speed of device in Hz.
+
+Optional properties:
+- num-cs: Number of chip selects used.
+
+Example:
+
+ spi: spi@f0b00000 {
+ compatible = "andestech,atcspi200";
+ reg = <0xf0b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ clocks = <&spiclk>;
+ interrupts = <3 4>;
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
--- /dev/null
+Andestech ATCPIT100 timer
+------------------------------------------------------------------
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX, AE250 platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible : Should be "andestech,atcpit100"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer
+
+Examples:
+
+timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2 4>;
+ clock-frequency = <30000000>;
+}:
alias spmi uboot, mateusz
alias ubi uboot, hs
alias usb uboot, marex
+alias xhci uboot, bmeng
alias video uboot, ag
alias patman uboot, sjg
alias buildman uboot, sjg
The 'data-offset' property can be substituted with 'data-position', which
defines an absolute position or address as the offset. This is helpful when
-booting U-Boot proper before performing relocation.
+booting U-Boot proper before performing relocation. Pass '-p [offset]' to
+mkimage to enable 'data-position'.
Normal kernel FIT image has data embedded within FIT structure. U-Boot image
for SPL boot has external data. Existence of 'data-offset' can be used to
source "drivers/block/Kconfig"
+source "drivers/bootcount/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"
See also CMD_SATA which provides command-line support.
+config LIBATA
+ bool
+ help
+ Select this to build and link the libata helper functions.
+
+config SCSI_AHCI
+ bool "Enable SCSI interface to SATA devices"
+ select LIBATA
+ help
+ Enable this to allow interfacing SATA devices via the SCSI layer.
+
menu "SATA/SCSI device support"
config AHCI_PCI
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
+config DWC_AHSATA
+ bool "Enable DWC AHSATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the DWC AHSATA SATA controller found
+ in i.MX5 and i.MX6 SoCs.
+
+config FSL_SATA
+ bool "Enable Freescale SATA controller driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SATA controller found in
+ some Freescale PowerPC SoCs.
+
+config MVSATA_IDE
+ bool "Enable Marvell SATA controller driver support via IDE interface"
+ help
+ Enable this driver to support the SATA controller found in
+ some Marvell SoCs, running in IDE compatibility mode using PIO.
+
+config SATA_MV
+ bool "Enable Marvell SATA controller driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SATA controller found in
+ some Marvell SoCs.
+
+config SATA_SIL
+ bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SIL3131, SIL3132 and SIL3124
+ SATA controllers.
+
+config SATA_SIL3114
+ bool "Enable Silicon Image SIL3114 SATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SIL3114 SATA controllers.
+
endmenu
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
-obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
-obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
#ifndef CONFIG_SCSI_AHCI_PLAT
# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
-int achi_init_one_dm(struct udevice *dev)
+int ahci_init_one_dm(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
#endif
#endif
-int achi_start_ports_dm(struct udevice *dev)
+int ahci_start_ports_dm(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
if (ret)
return ret;
- return achi_start_ports_dm(dev);
+ return ahci_start_ports_dm(dev);
}
static const struct udevice_id dwc_ahci_ids[] = {
+++ /dev/null
-/*
- * Freescale iMX51 ATA driver
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on code by:
- * Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
- *
- * Based on code from original FSL ATA driver, which is
- * part of eCos, the Embedded Configurable Operating System.
- * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <ide.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-/* MXC ATA register offsets */
-struct mxc_ata_config_regs {
- u8 time_off; /* 0x00 */
- u8 time_on;
- u8 time_1;
- u8 time_2w;
- u8 time_2r;
- u8 time_ax;
- u8 time_pio_rdx;
- u8 time_4;
- u8 time_9;
- u8 time_m;
- u8 time_jn;
- u8 time_d;
- u8 time_k;
- u8 time_ack;
- u8 time_env;
- u8 time_udma_rdx;
- u8 time_zah; /* 0x10 */
- u8 time_mlix;
- u8 time_dvh;
- u8 time_dzfs;
- u8 time_dvs;
- u8 time_cvh;
- u8 time_ss;
- u8 time_cyc;
- u32 fifo_data_32; /* 0x18 */
- u32 fifo_data_16;
- u32 fifo_fill;
- u32 ata_control;
- u32 interrupt_pending;
- u32 interrupt_enable;
- u32 interrupt_clear;
- u32 fifo_alarm;
-};
-
-struct mxc_data_hdd_regs {
- u32 drive_data; /* 0xa0 */
- u32 drive_features;
- u32 drive_sector_count;
- u32 drive_sector_num;
- u32 drive_cyl_low;
- u32 drive_cyl_high;
- u32 drive_dev_head;
- u32 command;
- u32 status;
- u32 alt_status;
-};
-
-/* PIO timing table */
-#define NR_PIO_SPECS 5
-static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
-static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
-static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
-static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
-static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
-
-#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
-static void set_ata_bus_timing(unsigned char mode)
-{
- uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
-
- struct mxc_ata_config_regs *ata_regs;
- ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
-
- if (mode >= NR_PIO_SPECS)
- return;
-
- /* Write TIME_OFF/ON/1/2W */
- writeb(3, &ata_regs->time_off);
- writeb(3, &ata_regs->time_on);
- writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
- writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
-
- /* Write TIME_2R/AX/RDX/4 */
- writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
- writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
- writeb(1, &ata_regs->time_pio_rdx);
- writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
-
- /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
- writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
-}
-
-int ide_preinit(void)
-{
- struct mxc_ata_config_regs *ata_regs;
- ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
-
- /* 46.3.3.4 @ FSL iMX51 manual */
- /* FIFO normal op., drive reset */
- writel(0x80, &ata_regs->ata_control);
- /* FIFO normal op., drive not reset */
- writel(0xc0, &ata_regs->ata_control);
-
- /* Configure the PIO timing */
- set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
-
- /* 46.3.3.4 @ FSL iMX51 manual */
- /* Drive not reset, IORDY handshake */
- writel(0x41, &ata_regs->ata_control);
-
- return 0;
-}
ceva_init_sata(plat->base);
- ret = achi_init_one_dm(dev);
+ ret = ahci_init_one_dm(dev);
if (ret)
return ret;
- return achi_start_ports_dm(dev);
+ return ahci_start_ports_dm(dev);
}
static const struct udevice_id sata_ceva_ids[] = {
+++ /dev/null
-/*
- * sata_dwc.c
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <linux/dma-direction.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <ata.h>
-#include <sata.h>
-#include <linux/ctype.h>
-
-#include "sata_dwc.h"
-
-#define DMA_NUM_CHANS 1
-#define DMA_NUM_CHAN_REGS 8
-
-#define AHB_DMA_BRST_DFLT 16
-
-struct dmareg {
- u32 low;
- u32 high;
-};
-
-struct dma_chan_regs {
- struct dmareg sar;
- struct dmareg dar;
- struct dmareg llp;
- struct dmareg ctl;
- struct dmareg sstat;
- struct dmareg dstat;
- struct dmareg sstatar;
- struct dmareg dstatar;
- struct dmareg cfg;
- struct dmareg sgr;
- struct dmareg dsr;
-};
-
-struct dma_interrupt_regs {
- struct dmareg tfr;
- struct dmareg block;
- struct dmareg srctran;
- struct dmareg dsttran;
- struct dmareg error;
-};
-
-struct ahb_dma_regs {
- struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
- struct dma_interrupt_regs interrupt_raw;
- struct dma_interrupt_regs interrupt_status;
- struct dma_interrupt_regs interrupt_mask;
- struct dma_interrupt_regs interrupt_clear;
- struct dmareg statusInt;
- struct dmareg rq_srcreg;
- struct dmareg rq_dstreg;
- struct dmareg rq_sgl_srcreg;
- struct dmareg rq_sgl_dstreg;
- struct dmareg rq_lst_srcreg;
- struct dmareg rq_lst_dstreg;
- struct dmareg dma_cfg;
- struct dmareg dma_chan_en;
- struct dmareg dma_id;
- struct dmareg dma_test;
- struct dmareg res1;
- struct dmareg res2;
- /* DMA Comp Params
- * Param 6 = dma_param[0], Param 5 = dma_param[1],
- * Param 4 = dma_param[2] ...
- */
- struct dmareg dma_params[6];
-};
-
-#define DMA_EN 0x00000001
-#define DMA_DI 0x00000000
-#define DMA_CHANNEL(ch) (0x00000001 << (ch))
-#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
- ((0x000000001 << (ch)) << 8))
-#define DMA_DISABLE_CHAN(ch) (0x00000000 | \
- ((0x000000001 << (ch)) << 8))
-
-#define SATA_DWC_MAX_PORTS 1
-#define SATA_DWC_SCR_OFFSET 0x24
-#define SATA_DWC_REG_OFFSET 0x64
-
-struct sata_dwc_regs {
- u32 fptagr;
- u32 fpbor;
- u32 fptcr;
- u32 dmacr;
- u32 dbtsr;
- u32 intpr;
- u32 intmr;
- u32 errmr;
- u32 llcr;
- u32 phycr;
- u32 physr;
- u32 rxbistpd;
- u32 rxbistpd1;
- u32 rxbistpd2;
- u32 txbistpd;
- u32 txbistpd1;
- u32 txbistpd2;
- u32 bistcr;
- u32 bistfctr;
- u32 bistsr;
- u32 bistdecr;
- u32 res[15];
- u32 testr;
- u32 versionr;
- u32 idr;
- u32 unimpl[192];
- u32 dmadr[256];
-};
-
-#define SATA_DWC_TXFIFO_DEPTH 0x01FF
-#define SATA_DWC_RXFIFO_DEPTH 0x01FF
-
-#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
-#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
- SATA_DWC_RXFIFO_DEPTH) << 16)
-#define SATA_DWC_INTPR_DMAT 0x00000001
-#define SATA_DWC_INTPR_NEWFP 0x00000002
-#define SATA_DWC_INTPR_PMABRT 0x00000004
-#define SATA_DWC_INTPR_ERR 0x00000008
-#define SATA_DWC_INTPR_NEWBIST 0x00000010
-#define SATA_DWC_INTPR_IPF 0x10000000
-#define SATA_DWC_INTMR_DMATM 0x00000001
-#define SATA_DWC_INTMR_NEWFPM 0x00000002
-#define SATA_DWC_INTMR_PMABRTM 0x00000004
-#define SATA_DWC_INTMR_ERRM 0x00000008
-#define SATA_DWC_INTMR_NEWBISTM 0x00000010
-
-#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
-#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
-
-#define SATA_DWC_QCMD_MAX 32
-
-#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
-
-#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
- (ap)->private_data
-
-struct sata_dwc_device {
- struct device *dev;
- struct ata_probe_ent *pe;
- struct ata_host *host;
- u8 *reg_base;
- struct sata_dwc_regs *sata_dwc_regs;
- int irq_dma;
-};
-
-struct sata_dwc_device_port {
- struct sata_dwc_device *hsdev;
- int cmd_issued[SATA_DWC_QCMD_MAX];
- u32 dma_chan[SATA_DWC_QCMD_MAX];
- int dma_pending[SATA_DWC_QCMD_MAX];
-};
-
-enum {
- SATA_DWC_CMD_ISSUED_NOT = 0,
- SATA_DWC_CMD_ISSUED_PEND = 1,
- SATA_DWC_CMD_ISSUED_EXEC = 2,
- SATA_DWC_CMD_ISSUED_NODATA = 3,
-
- SATA_DWC_DMA_PENDING_NONE = 0,
- SATA_DWC_DMA_PENDING_TX = 1,
- SATA_DWC_DMA_PENDING_RX = 2,
-};
-
-#define msleep(a) udelay(a * 1000)
-#define ssleep(a) msleep(a * 1000)
-
-static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
-
-enum sata_dev_state {
- SATA_INIT = 0,
- SATA_READY = 1,
- SATA_NODEVICE = 2,
- SATA_ERROR = 3,
-};
-enum sata_dev_state dev_state = SATA_INIT;
-
-static struct ahb_dma_regs *sata_dma_regs = 0;
-static struct ata_host *phost;
-static struct ata_port ap;
-static struct ata_port *pap = ≈
-static struct ata_device ata_device;
-static struct sata_dwc_device_port dwc_devp;
-
-static void *scr_addr_sstatus;
-static u32 temp_n_block = 0;
-
-static unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout);
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable,u8 feature);
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors);
-static u8 ata_irq_on(struct ata_port *ap);
-static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag);
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq);
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
-static u8 ata_check_altstatus(struct ata_port *ap);
-static u8 ata_check_status(struct ata_port *ap);
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep);
-static void ata_qc_issue(struct ata_queued_cmd *qc);
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static int ata_dev_read_sectors(unsigned char* pdata,
- unsigned long datalen, u32 block, u32 n_block);
-static int ata_dev_write_sectors(unsigned char* pdata,
- unsigned long datalen , u32 block, u32 n_block);
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
-static void ata_qc_complete(struct ata_queued_cmd *qc);
-static void __ata_qc_complete(struct ata_queued_cmd *qc);
-static void fill_result_tf(struct ata_queued_cmd *qc);
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
-static void ata_mmio_data_xfer(struct ata_device *dev,
- unsigned char *buf,
- unsigned int buflen,int do_write);
-static void ata_pio_task(struct ata_port *arg_ap);
-static void __ata_port_freeze(struct ata_port *ap);
-static int ata_port_freeze(struct ata_port *ap);
-static void ata_qc_free(struct ata_queued_cmd *qc);
-static void ata_pio_sectors(struct ata_queued_cmd *qc);
-static void ata_pio_sector(struct ata_queued_cmd *qc);
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay);
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
-static int sata_dwc_softreset(struct ata_port *ap);
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id);
-static int check_sata_dev_state(void);
-
-static const struct ata_port_info sata_dwc_port_info[] = {
- {
- .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
- ATA_FLAG_SRST | ATA_FLAG_NCQ,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
- .udma_mask = 0x7f,
- },
-};
-
-int init_sata(int dev)
-{
- struct sata_dwc_device hsdev;
- struct ata_host host;
- struct ata_port_info pi = sata_dwc_port_info[0];
- struct ata_link *link;
- struct sata_dwc_device_port hsdevp = dwc_devp;
- u8 *base = 0;
- u8 *sata_dma_regs_addr = 0;
- u8 status;
- unsigned long base_addr = 0;
- int chan = 0;
- int rc;
- int i;
-
- phost = &host;
-
- base = (u8*)SATA_BASE_ADDR;
-
- hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
-
- host.n_ports = SATA_DWC_MAX_PORTS;
-
- for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
- ap.pflags |= ATA_PFLAG_INITIALIZING;
- ap.flags = ATA_FLAG_DISABLED;
- ap.print_id = -1;
- ap.ctl = ATA_DEVCTL_OBS;
- ap.host = &host;
- ap.last_ctl = 0xFF;
-
- link = &ap.link;
- link->ap = ≈
- link->pmp = 0;
- link->active_tag = ATA_TAG_POISON;
- link->hw_sata_spd_limit = 0;
-
- ap.port_no = i;
- host.ports[i] = ≈
- }
-
- ap.pio_mask = pi.pio_mask;
- ap.mwdma_mask = pi.mwdma_mask;
- ap.udma_mask = pi.udma_mask;
- ap.flags |= pi.flags;
- ap.link.flags |= pi.link_flags;
-
- host.ports[0]->ioaddr.cmd_addr = base;
- host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
- scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
-
- base_addr = (unsigned long)base;
-
- host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
- host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
-
- host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
- host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
-
- host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
-
- host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
- host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
- host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
-
- host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
- host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
- host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
-
- host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
- host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
-
- sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
- sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
-
- status = ata_check_altstatus(&ap);
-
- if (status == 0x7f) {
- printf("Hard Disk not found.\n");
- dev_state = SATA_NODEVICE;
- rc = false;
- return rc;
- }
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- rc = false;
- return rc;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- rc = sata_dwc_softreset(&ap);
-
- if (rc) {
- printf("sata_dwc : error. soft reset failed\n");
- return rc;
- }
-
- for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
- out_le32(&(sata_dma_regs->interrupt_mask.error.low),
- DMA_DISABLE_CHAN(chan));
-
- out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
- DMA_DISABLE_CHAN(chan));
- }
-
- out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
-
- out_le32(&hsdev.sata_dwc_regs->intmr,
- SATA_DWC_INTMR_ERRM |
- SATA_DWC_INTMR_PMABRTM);
-
- /* Unmask the error bits that should trigger
- * an error interrupt by setting the error mask register.
- */
- out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
-
- hsdev.host = ap.host;
- memset(&hsdevp, 0, sizeof(hsdevp));
- hsdevp.hsdev = &hsdev;
-
- for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
- hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
-
- out_le32((void __iomem *)scr_addr_sstatus + 4,
- in_le32((void __iomem *)scr_addr_sstatus + 4));
-
- rc = 0;
- return rc;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-static u8 ata_check_altstatus(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.altstatus_addr);
- return val;
-}
-
-static int sata_dwc_softreset(struct ata_port *ap)
-{
- u8 nsect,lbal = 0;
- u8 tmp = 0;
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
-
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
- writeb(0xaa, ioaddr->nsect_addr);
- writeb(0x55, ioaddr->lbal_addr);
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- if ((nsect == 0x55) && (lbal == 0xaa)) {
- printf("Device found\n");
- } else {
- printf("No device found\n");
- dev_state = SATA_NODEVICE;
- return false;
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- udelay(200);
-
- writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
-
- udelay(200);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- msleep(150);
- ata_check_status(ap);
-
- msleep(50);
- ata_check_status(ap);
-
- while (1) {
- u8 status = ata_check_status(ap);
-
- if (!(status & ATA_BUSY))
- break;
-
- printf("Hard Disk status is BUSY.\n");
- msleep(50);
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- return 0;
-}
-
-static u8 ata_check_status(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.status_addr);
- return val;
-}
-
-static int ata_id_has_hipm(const u16 *id)
-{
- u16 val = id[76];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 9);
-}
-
-static int ata_id_has_dipm(const u16 *id)
-{
- u16 val = id[78];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 3);
-}
-
-int scan_sata(int dev)
-{
- int i;
- int rc;
- u8 status;
- const u16 *id;
- struct ata_device *ata_dev = &ata_device;
- unsigned long pio_mask, mwdma_mask;
- char revbuf[7];
- u16 iobuf[ATA_SECTOR_WORDS];
-
- memset(iobuf, 0, sizeof(iobuf));
-
- if (dev_state == SATA_NODEVICE)
- return 1;
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- return 1;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- udelay(1000);
-
- rc = ata_dev_read_id(ata_dev, &ata_dev->class,
- ATA_READID_POSTRESET,ata_dev->id);
- if (rc) {
- printf("sata_dwc : error. failed sata scan\n");
- return 1;
- }
-
- /* SATA drives indicate we have a bridge. We don't know which
- * end of the link the bridge is which is a problem
- */
- if (ata_id_is_sata(ata_dev->id))
- ap.cbl = ATA_CBL_SATA;
-
- id = ata_dev->id;
-
- ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
- ata_dev->max_sectors = 0;
- ata_dev->cdb_len = 0;
- ata_dev->n_sectors = 0;
- ata_dev->cylinders = 0;
- ata_dev->heads = 0;
- ata_dev->sectors = 0;
-
- if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
- pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
- pio_mask <<= 3;
- pio_mask |= 0x7;
- } else {
- /* If word 64 isn't valid then Word 51 high byte holds
- * the PIO timing number for the maximum. Turn it into
- * a mask.
- */
- u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
- if (mode < 5) {
- pio_mask = (2 << mode) - 1;
- } else {
- pio_mask = 1;
- }
- }
-
- mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
-
- if (ata_id_is_cfa(id)) {
- int pio = id[163] & 0x7;
- int dma = (id[163] >> 3) & 7;
-
- if (pio)
- pio_mask |= (1 << 5);
- if (pio > 1)
- pio_mask |= (1 << 6);
- if (dma)
- mwdma_mask |= (1 << 3);
- if (dma > 1)
- mwdma_mask |= (1 << 4);
- }
-
- if (ata_dev->class == ATA_DEV_ATA) {
- if (ata_id_is_cfa(id)) {
- if (id[162] & 1)
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- strcpy(revbuf, "CFA");
- } else {
- if (ata_id_has_tpm(id))
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- }
-
- ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
-
- if (ata_dev->id[59] & 0x100)
- ata_dev->multi_count = ata_dev->id[59] & 0xff;
-
- if (ata_id_has_lba(id)) {
- char ncq_desc[20];
-
- ata_dev->flags |= ATA_DFLAG_LBA;
- if (ata_id_has_lba48(id)) {
- ata_dev->flags |= ATA_DFLAG_LBA48;
-
- if (ata_dev->n_sectors >= (1UL << 28) &&
- ata_id_has_flush_ext(id))
- ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
- }
- if (!ata_id_has_ncq(ata_dev->id))
- ncq_desc[0] = '\0';
-
- if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
- strcpy(ncq_desc, "NCQ (not used)");
-
- if (ap.flags & ATA_FLAG_NCQ)
- ata_dev->flags |= ATA_DFLAG_NCQ;
- }
- ata_dev->cdb_len = 16;
- }
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- if (ata_dev->flags & ATA_DFLAG_LBA48)
- ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
-
- if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
- if (ata_id_has_hipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_HIPM;
- if (ata_id_has_dipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_DIPM;
- }
-
- if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
- ata_dev->udma_mask &= ATA_UDMA5;
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- }
-
- if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
- printf("Drive reports diagnostics failure."
- "This may indicate a drive\n");
- printf("fault or invalid emulation."
- "Contact drive vendor for information.\n");
- }
-
- rc = check_sata_dev_state();
-
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].revision,
- ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].vendor,
- ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].product,
- ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
-
- sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
-
-#ifdef CONFIG_LBA48
- if (ata_dev->id[83] & (1 << 10)) {
- sata_dev_desc[dev].lba48 = 1;
- } else {
- sata_dev_desc[dev].lba48 = 0;
- }
-#endif
-
- return 0;
-}
-
-static u8 ata_busy_wait(struct ata_port *ap,
- unsigned int bits,unsigned int max)
-{
- u8 status;
-
- do {
- udelay(10);
- status = ata_check_status(ap);
- max--;
- } while (status != 0xff && (status & bits) && (max > 0));
-
- return status;
-}
-
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id)
-{
- struct ata_port *ap = pap;
- unsigned int class = *p_class;
- struct ata_taskfile tf;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1, tried_spinup = 0;
- u8 status;
- int rc;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = false;
- return rc;
- }
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_ID_ATA;
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
-
- /* Device presence detection is unreliable on some
- * controllers. Always poll IDENTIFY if available.
- */
- tf.flags |= ATA_TFLAG_POLLING;
-
- temp_n_block = 1;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
- sizeof(id[0]) * ATA_ID_WORDS, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
- rc = -EIO;
- reason = "I/O error";
- goto err_out;
- }
-
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- unsigned int id_cnt;
-
- for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
- id[id_cnt] = le16_to_cpu(id[id_cnt]);
-
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
- if (class == ATA_DEV_ATA) {
- if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
- goto err_out;
- } else {
- if (ata_id_is_ata(id))
- goto err_out;
- }
- if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
- tried_spinup = 1;
- /*
- * Drive powered-up in standby mode, and requires a specific
- * SET_FEATURES spin-up subcommand before it will accept
- * anything other than the original IDENTIFY command.
- */
- err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
- if (err_mask && id[2] != 0x738c) {
- rc = -EIO;
- reason = "SPINUP failed";
- goto err_out;
- }
- /*
- * If the drive initially returned incomplete IDENTIFY info,
- * we now must reissue the IDENTIFY command.
- */
- if (id[2] == 0x37c8)
- goto retry;
- }
-
- if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
- /*
- * The exact sequence expected by certain pre-ATA4 drives is:
- * SRST RESET
- * IDENTIFY (optional in early ATA)
- * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
- * anything else..
- * Some drives were very specific about that exact sequence.
- *
- * Note that ATA4 says lba is mandatory so the second check
- * shoud never trigger.
- */
- if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
- err_mask = ata_dev_init_params(dev, id[3], id[6]);
- if (err_mask) {
- rc = -EIO;
- reason = "INIT_DEV_PARAMS failed";
- goto err_out;
- }
-
- /* current CHS translation info (id[53-58]) might be
- * changed. reread the identify device info.
- */
- flags &= ~ATA_READID_POSTRESET;
- goto retry;
- }
- }
-
- *p_class = class;
- return 0;
-
-err_out:
- printf("failed to READ ID (%s, err_mask=0x%x)\n", reason, err_mask);
- return rc;
-}
-
-static u8 ata_wait_idle(struct ata_port *ap)
-{
- u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
- return status;
-}
-
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep)
-{
- if (wait)
- ata_wait_idle(ap);
-
- ata_std_dev_select(ap, device);
-
- if (wait)
- ata_wait_idle(ap);
-}
-
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
-{
- u8 tmp;
-
- if (device == 0) {
- tmp = ATA_DEVICE_OBS;
- } else {
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
- }
-
- writeb(tmp, ap->ioaddr.device_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static int waiting_for_reg_state(volatile u8 *offset,
- int timeout_msec,
- u32 sign)
-{
- int i;
- u32 status;
-
- for (i = 0; i < timeout_msec; i++) {
- status = readl(offset);
- if ((status & sign) != 0)
- break;
- msleep(1);
- }
-
- return (i < timeout_msec) ? 0 : -1;
-}
-
-static void ata_qc_reinit(struct ata_queued_cmd *qc)
-{
- qc->dma_dir = DMA_NONE;
- qc->flags = 0;
- qc->nbytes = qc->extrabytes = qc->curbytes = 0;
- qc->n_elem = 0;
- qc->err_mask = 0;
- qc->sect_size = ATA_SECT_SIZE;
- qc->nbytes = ATA_SECT_SIZE * temp_n_block;
-
- memset(&qc->tf, 0, sizeof(qc->tf));
- qc->tf.ctl = 0;
- qc->tf.device = ATA_DEVICE_OBS;
-
- qc->result_tf.command = ATA_DRDY;
- qc->result_tf.feature = 0;
-}
-
-struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag)
-{
- if (tag < ATA_MAX_QUEUE)
- return &ap->qcmd[tag];
- return NULL;
-}
-
-static void __ata_port_freeze(struct ata_port *ap)
-{
- printf("set port freeze.\n");
- ap->pflags |= ATA_PFLAG_FROZEN;
-}
-
-static int ata_port_freeze(struct ata_port *ap)
-{
- __ata_port_freeze(ap);
- return 0;
-}
-
-unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout)
-{
- struct ata_link *link = dev->link;
- struct ata_port *ap = pap;
- struct ata_queued_cmd *qc;
- unsigned int tag, preempted_tag;
- u32 preempted_sactive, preempted_qc_active;
- int preempted_nr_active_links;
- unsigned int err_mask;
- int rc = 0;
- u8 status;
-
- status = ata_busy_wait(ap, ATA_BUSY, 300000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = false;
- return rc;
- }
-
- if (ap->pflags & ATA_PFLAG_FROZEN)
- return AC_ERR_SYSTEM;
-
- tag = ATA_TAG_INTERNAL;
-
- if (test_and_set_bit(tag, &ap->qc_allocated)) {
- rc = false;
- return rc;
- }
-
- qc = __ata_qc_from_tag(ap, tag);
- qc->tag = tag;
- qc->ap = ap;
- qc->dev = dev;
-
- ata_qc_reinit(qc);
-
- preempted_tag = link->active_tag;
- preempted_sactive = link->sactive;
- preempted_qc_active = ap->qc_active;
- preempted_nr_active_links = ap->nr_active_links;
- link->active_tag = ATA_TAG_POISON;
- link->sactive = 0;
- ap->qc_active = 0;
- ap->nr_active_links = 0;
-
- qc->tf = *tf;
- if (cdb)
- memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
- qc->flags |= ATA_QCFLAG_RESULT_TF;
- qc->dma_dir = dma_dir;
- qc->private_data = 0;
-
- ata_qc_issue(qc);
-
- if (!timeout)
- timeout = ata_probe_timeout * 1000 / HZ;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- printf("altstatus = 0x%x.\n", status);
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
- u8 status = 0;
- u8 errorStatus = 0;
-
- status = readb(ap->ioaddr.altstatus_addr);
- if ((status & 0x01) != 0) {
- errorStatus = readb(ap->ioaddr.feature_addr);
- if (errorStatus == 0x04 &&
- qc->tf.command == ATA_CMD_PIO_READ_EXT){
- printf("Hard Disk doesn't support LBA48\n");
- dev_state = SATA_ERROR;
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
- }
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- ata_pio_task(ap);
-
- if (!rc) {
- if (qc->flags & ATA_QCFLAG_ACTIVE) {
- qc->err_mask |= AC_ERR_TIMEOUT;
- ata_port_freeze(ap);
- }
- }
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (qc->result_tf.command & (ATA_ERR | ATA_DF))
- qc->err_mask |= AC_ERR_DEV;
-
- if (!qc->err_mask)
- qc->err_mask |= AC_ERR_OTHER;
-
- if (qc->err_mask & ~AC_ERR_OTHER)
- qc->err_mask &= ~AC_ERR_OTHER;
- }
-
- *tf = qc->result_tf;
- err_mask = qc->err_mask;
- ata_qc_free(qc);
- link->active_tag = preempted_tag;
- link->sactive = preempted_sactive;
- ap->qc_active = preempted_qc_active;
- ap->nr_active_links = preempted_nr_active_links;
-
- if (ap->flags & ATA_FLAG_DISABLED) {
- err_mask |= AC_ERR_SYSTEM;
- ap->flags &= ~ATA_FLAG_DISABLED;
- }
-
- return err_mask;
-}
-
-static void ata_qc_issue(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
- u8 prot = qc->tf.protocol;
-
- if (ata_is_ncq(prot)) {
- if (!link->sactive)
- ap->nr_active_links++;
- link->sactive |= 1 << qc->tag;
- } else {
- ap->nr_active_links++;
- link->active_tag = qc->tag;
- }
-
- qc->flags |= ATA_QCFLAG_ACTIVE;
- ap->qc_active |= 1 << qc->tag;
-
- if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
- msleep(1);
- return;
- }
-
- qc->err_mask |= ata_qc_issue_prot(qc);
- if (qc->err_mask)
- goto err;
-
- return;
-err:
- ata_qc_complete(qc);
-}
-
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- if (ap->flags & ATA_FLAG_PIO_POLLING) {
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- case ATA_PROT_NODATA:
- case ATAPI_PROT_PIO:
- case ATAPI_PROT_NODATA:
- qc->tf.flags |= ATA_TFLAG_POLLING;
- break;
- default:
- break;
- }
- }
-
- ata_dev_select(ap, qc->dev->devno, 1, 0);
-
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- qc->tf.ctl |= ATA_NIEN;
-
- ata_tf_to_host(ap, &qc->tf);
-
- ap->hsm_task_state = HSM_ST;
-
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- ata_pio_queue_task(ap, qc, 0);
-
- break;
-
- default:
- return AC_ERR_SYSTEM;
- }
-
- return 0;
-}
-
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- ata_tf_load(ap, tf);
- ata_exec_command(ap, tf);
-}
-
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- if (tf->ctl != ap->last_ctl) {
- if (ioaddr->ctl_addr)
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- ata_wait_idle(ap);
- }
-
- if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
- writeb(tf->hob_feature, ioaddr->feature_addr);
- writeb(tf->hob_nsect, ioaddr->nsect_addr);
- writeb(tf->hob_lbal, ioaddr->lbal_addr);
- writeb(tf->hob_lbam, ioaddr->lbam_addr);
- writeb(tf->hob_lbah, ioaddr->lbah_addr);
- }
-
- if (is_addr) {
- writeb(tf->feature, ioaddr->feature_addr);
- writeb(tf->nsect, ioaddr->nsect_addr);
- writeb(tf->lbal, ioaddr->lbal_addr);
- writeb(tf->lbam, ioaddr->lbam_addr);
- writeb(tf->lbah, ioaddr->lbah_addr);
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- writeb(tf->device, ioaddr->device_addr);
-
- ata_wait_idle(ap);
-}
-
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- writeb(tf->command, ap->ioaddr.command_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay)
-{
- ap->port_task_data = data;
-}
-
-static unsigned int ac_err_mask(u8 status)
-{
- if (status & (ATA_BUSY | ATA_DRQ))
- return AC_ERR_HSM;
- if (status & (ATA_ERR | ATA_DF))
- return AC_ERR_DEV;
- return 0;
-}
-
-static unsigned int __ac_err_mask(u8 status)
-{
- unsigned int mask = ac_err_mask(status);
- if (mask == 0)
- return AC_ERR_OTHER;
- return mask;
-}
-
-static void ata_pio_task(struct ata_port *arg_ap)
-{
- struct ata_port *ap = arg_ap;
- struct ata_queued_cmd *qc = ap->port_task_data;
- u8 status;
- int poll_next;
-
-fsm_start:
- /*
- * This is purely heuristic. This is a fast path.
- * Sometimes when we enter, BSY will be cleared in
- * a chk-status or two. If not, the drive is probably seeking
- * or something. Snooze for a couple msecs, then
- * chk-status again. If still busy, queue delayed work.
- */
- status = ata_busy_wait(ap, ATA_BUSY, 5);
- if (status & ATA_BUSY) {
- msleep(2);
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
- return;
- }
- }
-
- poll_next = ata_hsm_move(ap, qc, status, 1);
-
- /* another command or interrupt handler
- * may be running at this point.
- */
- if (poll_next)
- goto fsm_start;
-}
-
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq)
-{
- int poll_next;
-
-fsm_start:
- switch (ap->hsm_task_state) {
- case HSM_ST_FIRST:
- poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
-
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- qc->err_mask |= AC_ERR_HSM;
- }
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- /* Device should not ask for data transfer (DRQ=1)
- * when it finds something wrong.
- * We ignore DRQ here and stop the HSM by
- * changing hsm_task_state to HSM_ST_ERR and
- * let the EH abort the command or reset the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
- printf("DRQ=1 with device error, "
- "dev_stat 0x%X\n", status);
- qc->err_mask |= AC_ERR_HSM;
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- }
-
- if (qc->tf.protocol == ATA_PROT_PIO) {
- /* PIO data out protocol.
- * send first data block.
- */
- /* ata_pio_sectors() might change the state
- * to HSM_ST_LAST. so, the state is changed here
- * before ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST;
- ata_pio_sectors(qc);
- } else {
- printf("protocol is not ATA_PROT_PIO \n");
- }
- break;
-
- case HSM_ST:
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- /* HSM violation. Let EH handle this.
- * Phantom devices also trigger this
- * condition. Mark hint.
- */
- qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
- }
-
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- /* For PIO reads, some devices may ask for
- * data transfer (DRQ=1) alone with ERR=1.
- * We respect DRQ here and transfer one
- * block of junk data before changing the
- * hsm_task_state to HSM_ST_ERR.
- *
- * For PIO writes, ERR=1 DRQ=1 doesn't make
- * sense since the data block has been
- * transferred to the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
-
- if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
- ata_pio_sectors(qc);
- status = ata_wait_idle(ap);
- }
-
- if (status & (ATA_BUSY | ATA_DRQ))
- qc->err_mask |= AC_ERR_HSM;
-
- /* ata_pio_sectors() might change the
- * state to HSM_ST_LAST. so, the state
- * is changed after ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ata_pio_sectors(qc);
- if (ap->hsm_task_state == HSM_ST_LAST &&
- (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
- status = ata_wait_idle(ap);
- goto fsm_start;
- }
-
- poll_next = 1;
- break;
-
- case HSM_ST_LAST:
- if (!ata_ok(status)) {
- qc->err_mask |= __ac_err_mask(status);
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
-
- case HSM_ST_ERR:
- /* make sure qc->err_mask is available to
- * know what's wrong and recover
- */
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
- default:
- poll_next = 0;
- }
-
- return poll_next;
-}
-
-static void ata_pio_sectors(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap;
- ap = pap;
- qc->pdata = ap->pdata;
-
- ata_pio_sector(qc);
-
- readb(qc->ap->ioaddr.altstatus_addr);
- udelay(1);
-}
-
-static void ata_pio_sector(struct ata_queued_cmd *qc)
-{
- int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
- struct ata_port *ap = qc->ap;
- unsigned int offset;
- unsigned char *buf;
- char temp_data_buf[512];
-
- if (qc->curbytes == qc->nbytes - qc->sect_size)
- ap->hsm_task_state = HSM_ST_LAST;
-
- offset = qc->curbytes;
-
- switch (qc->tf.command) {
- case ATA_CMD_ID_ATA:
- buf = (unsigned char *)&ata_device.id[0];
- break;
- case ATA_CMD_PIO_READ_EXT:
- case ATA_CMD_PIO_READ:
- case ATA_CMD_PIO_WRITE_EXT:
- case ATA_CMD_PIO_WRITE:
- buf = qc->pdata + offset;
- break;
- default:
- buf = (unsigned char *)&temp_data_buf[0];
- }
-
- ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
-
- qc->curbytes += qc->sect_size;
-
-}
-
-static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
- unsigned int buflen, int do_write)
-{
- struct ata_port *ap = pap;
- void __iomem *data_addr = ap->ioaddr.data_addr;
- unsigned int words = buflen >> 1;
- u16 *buf16 = (u16 *)buf;
- unsigned int i = 0;
-
- udelay(100);
- if (do_write) {
- for (i = 0; i < words; i++)
- writew(le16_to_cpu(buf16[i]), data_addr);
- } else {
- for (i = 0; i < words; i++)
- buf16[i] = cpu_to_le16(readw(data_addr));
- }
-
- if (buflen & 0x01) {
- __le16 align_buf[1] = { 0 };
- unsigned char *trailing_buf = buf + buflen - 1;
-
- if (do_write) {
- memcpy(align_buf, trailing_buf, 1);
- writew(le16_to_cpu(align_buf[0]), data_addr);
- } else {
- align_buf[0] = cpu_to_le16(readw(data_addr));
- memcpy(trailing_buf, align_buf, 1);
- }
- }
-}
-
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
-{
- struct ata_port *ap = qc->ap;
-
- if (in_wq) {
- /* EH might have kicked in while host lock is
- * released.
- */
- qc = &ap->qcmd[qc->tag];
- if (qc) {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_irq_on(ap);
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
- } else {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
-}
-
-static u8 ata_irq_on(struct ata_port *ap)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- u8 tmp;
-
- ap->ctl &= ~ATA_NIEN;
- ap->last_ctl = ap->ctl;
-
- if (ioaddr->ctl_addr)
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- tmp = ata_wait_idle(ap);
-
- return tmp;
-}
-
-static unsigned int ata_tag_internal(unsigned int tag)
-{
- return tag == ATA_MAX_QUEUE - 1;
-}
-
-static void ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_device *dev = qc->dev;
- if (qc->err_mask)
- qc->flags |= ATA_QCFLAG_FAILED;
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (!ata_tag_internal(qc->tag)) {
- fill_result_tf(qc);
- return;
- }
- }
- if (qc->flags & ATA_QCFLAG_RESULT_TF)
- fill_result_tf(qc);
-
- /* Some commands need post-processing after successful
- * completion.
- */
- switch (qc->tf.command) {
- case ATA_CMD_SET_FEATURES:
- if (qc->tf.feature != SETFEATURES_WC_ON &&
- qc->tf.feature != SETFEATURES_WC_OFF)
- break;
- case ATA_CMD_INIT_DEV_PARAMS:
- case ATA_CMD_SET_MULTI:
- break;
-
- case ATA_CMD_SLEEP:
- dev->flags |= ATA_DFLAG_SLEEPING;
- break;
- }
-
- __ata_qc_complete(qc);
-}
-
-static void fill_result_tf(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- qc->result_tf.flags = qc->tf.flags;
- ata_tf_read(ap, &qc->result_tf);
-}
-
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- tf->command = ata_check_status(ap);
- tf->feature = readb(ioaddr->error_addr);
- tf->nsect = readb(ioaddr->nsect_addr);
- tf->lbal = readb(ioaddr->lbal_addr);
- tf->lbam = readb(ioaddr->lbam_addr);
- tf->lbah = readb(ioaddr->lbah_addr);
- tf->device = readb(ioaddr->device_addr);
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- if (ioaddr->ctl_addr) {
- writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
-
- tf->hob_feature = readb(ioaddr->error_addr);
- tf->hob_nsect = readb(ioaddr->nsect_addr);
- tf->hob_lbal = readb(ioaddr->lbal_addr);
- tf->hob_lbam = readb(ioaddr->lbam_addr);
- tf->hob_lbah = readb(ioaddr->lbah_addr);
-
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- } else {
- printf("sata_dwc warnning register read.\n");
- }
- }
-}
-
-static void __ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
-
- link->active_tag = ATA_TAG_POISON;
- ap->nr_active_links--;
-
- if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
- ap->excl_link = NULL;
-
- qc->flags &= ~ATA_QCFLAG_ACTIVE;
- ap->qc_active &= ~(1 << qc->tag);
-}
-
-static void ata_qc_free(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- unsigned int tag;
- qc->flags = 0;
- tag = qc->tag;
- if (tag < ATA_MAX_QUEUE) {
- qc->tag = ATA_TAG_POISON;
- clear_bit(tag, &ap->qc_allocated);
- }
-}
-
-static int check_sata_dev_state(void)
-{
- unsigned long datalen;
- unsigned char *pdata;
- int ret = 0;
- int i = 0;
- char temp_data_buf[512];
-
- while (1) {
- udelay(10000);
-
- pdata = (unsigned char*)&temp_data_buf[0];
- datalen = 512;
-
- ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
-
- if (ret == true)
- break;
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
- dev_state = SATA_NODEVICE;
- return false;
- }
-
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- dev_state = SATA_READY;
-
- return true;
-}
-
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable, u8 feature)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
-
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_SET_FEATURES;
- tf.feature = enable;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = feature;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- return err_mask;
-}
-
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
- return AC_ERR_INVALID;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_INIT_DEV_PARAMS;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = sectors;
- tf.device |= (heads - 1) & 0x0f;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
- err_mask = 0;
-
- return err_mask;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_READ_BLK 0xFF
-#else
-#define SATA_MAX_READ_BLK 0xFFFF
-#endif
-
-ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_READ_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- smallblks = SATA_MAX_READ_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_READ_BLK;
- blks -= SATA_MAX_READ_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
-
- if (dev_state == SATA_ERROR)
- return false;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_READ_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_READ;
- tf.flags |= ATA_TFLAG_LBA ;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- reason = "I/O error";
- goto err_out;
- }
-
- return true;
-
-err_out:
- printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return false;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_WRITE_BLK 0xFF
-#else
-#define SATA_MAX_WRITE_BLK 0xFFFF
-#endif
-
-ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_WRITE_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
- smallblks = SATA_MAX_WRITE_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_WRITE_BLK;
- blks -= SATA_MAX_WRITE_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
-
- if (dev_state == SATA_ERROR)
- return false;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_WRITE_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_WRITE;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- reason = "I/O error";
- goto err_out;
- }
-
- return true;
-
-err_out:
- printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return false;
-}
+++ /dev/null
-/*
- * sata_dwc.h
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-
-#ifndef _SATA_DWC_H_
-#define _SATA_DWC_H_
-
-#define __U_BOOT__
-
-#define HZ 100
-#define READ 0
-#define WRITE 1
-
-enum {
- ATA_READID_POSTRESET = (1 << 0),
-
- ATA_DNXFER_PIO = 0,
- ATA_DNXFER_DMA = 1,
- ATA_DNXFER_40C = 2,
- ATA_DNXFER_FORCE_PIO = 3,
- ATA_DNXFER_FORCE_PIO0 = 4,
-
- ATA_DNXFER_QUIET = (1 << 31),
-};
-
-enum hsm_task_states {
- HSM_ST_IDLE,
- HSM_ST_FIRST,
- HSM_ST,
- HSM_ST_LAST,
- HSM_ST_ERR,
-};
-
-#define ATA_SHORT_PAUSE ((HZ >> 6) + 1)
-
-struct ata_queued_cmd {
- struct ata_port *ap;
- struct ata_device *dev;
-
- struct ata_taskfile tf;
- u8 cdb[ATAPI_CDB_LEN];
- unsigned long flags;
- unsigned int tag;
- unsigned int n_elem;
-
- int dma_dir;
- unsigned int sect_size;
-
- unsigned int nbytes;
- unsigned int extrabytes;
- unsigned int curbytes;
-
- unsigned int err_mask;
- struct ata_taskfile result_tf;
-
- void *private_data;
-#ifndef __U_BOOT__
- void *lldd_task;
-#endif
- unsigned char *pdata;
-};
-
-typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
-
-#define ATA_TAG_POISON 0xfafbfcfdU
-
-enum {
- LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
- LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4,
- ATA_MAX_PORTS = 8,
- ATA_DEF_QUEUE = 1,
- ATA_MAX_QUEUE = 32,
- ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
- ATA_MAX_BUS = 2,
- ATA_DEF_BUSY_WAIT = 10000,
-
- ATAPI_MAX_DRAIN = 16 << 10,
-
- ATA_SHT_EMULATED = 1,
- ATA_SHT_CMD_PER_LUN = 1,
- ATA_SHT_THIS_ID = -1,
- ATA_SHT_USE_CLUSTERING = 1,
-
- ATA_DFLAG_LBA = (1 << 0),
- ATA_DFLAG_LBA48 = (1 << 1),
- ATA_DFLAG_CDB_INTR = (1 << 2),
- ATA_DFLAG_NCQ = (1 << 3),
- ATA_DFLAG_FLUSH_EXT = (1 << 4),
- ATA_DFLAG_ACPI_PENDING = (1 << 5),
- ATA_DFLAG_ACPI_FAILED = (1 << 6),
- ATA_DFLAG_AN = (1 << 7),
- ATA_DFLAG_HIPM = (1 << 8),
- ATA_DFLAG_DIPM = (1 << 9),
- ATA_DFLAG_DMADIR = (1 << 10),
- ATA_DFLAG_CFG_MASK = (1 << 12) - 1,
-
- ATA_DFLAG_PIO = (1 << 12),
- ATA_DFLAG_NCQ_OFF = (1 << 13),
- ATA_DFLAG_SPUNDOWN = (1 << 14),
- ATA_DFLAG_SLEEPING = (1 << 15),
- ATA_DFLAG_DUBIOUS_XFER = (1 << 16),
- ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
-
- ATA_DFLAG_DETACH = (1 << 24),
- ATA_DFLAG_DETACHED = (1 << 25),
-
- ATA_LFLAG_HRST_TO_RESUME = (1 << 0),
- ATA_LFLAG_SKIP_D2H_BSY = (1 << 1),
- ATA_LFLAG_NO_SRST = (1 << 2),
- ATA_LFLAG_ASSUME_ATA = (1 << 3),
- ATA_LFLAG_ASSUME_SEMB = (1 << 4),
- ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
- ATA_LFLAG_NO_RETRY = (1 << 5),
- ATA_LFLAG_DISABLED = (1 << 6),
-
- ATA_FLAG_SLAVE_POSS = (1 << 0),
- ATA_FLAG_SATA = (1 << 1),
- ATA_FLAG_NO_LEGACY = (1 << 2),
- ATA_FLAG_MMIO = (1 << 3),
- ATA_FLAG_SRST = (1 << 4),
- ATA_FLAG_SATA_RESET = (1 << 5),
- ATA_FLAG_NO_ATAPI = (1 << 6),
- ATA_FLAG_PIO_DMA = (1 << 7),
- ATA_FLAG_PIO_LBA48 = (1 << 8),
- ATA_FLAG_PIO_POLLING = (1 << 9),
- ATA_FLAG_NCQ = (1 << 10),
- ATA_FLAG_DEBUGMSG = (1 << 13),
- ATA_FLAG_IGN_SIMPLEX = (1 << 15),
- ATA_FLAG_NO_IORDY = (1 << 16),
- ATA_FLAG_ACPI_SATA = (1 << 17),
- ATA_FLAG_AN = (1 << 18),
- ATA_FLAG_PMP = (1 << 19),
- ATA_FLAG_IPM = (1 << 20),
-
- ATA_FLAG_DISABLED = (1 << 23),
-
- ATA_PFLAG_EH_PENDING = (1 << 0),
- ATA_PFLAG_EH_IN_PROGRESS = (1 << 1),
- ATA_PFLAG_FROZEN = (1 << 2),
- ATA_PFLAG_RECOVERED = (1 << 3),
- ATA_PFLAG_LOADING = (1 << 4),
- ATA_PFLAG_UNLOADING = (1 << 5),
- ATA_PFLAG_SCSI_HOTPLUG = (1 << 6),
- ATA_PFLAG_INITIALIZING = (1 << 7),
- ATA_PFLAG_RESETTING = (1 << 8),
- ATA_PFLAG_SUSPENDED = (1 << 17),
- ATA_PFLAG_PM_PENDING = (1 << 18),
-
- ATA_QCFLAG_ACTIVE = (1 << 0),
- ATA_QCFLAG_DMAMAP = (1 << 1),
- ATA_QCFLAG_IO = (1 << 3),
- ATA_QCFLAG_RESULT_TF = (1 << 4),
- ATA_QCFLAG_CLEAR_EXCL = (1 << 5),
- ATA_QCFLAG_QUIET = (1 << 6),
-
- ATA_QCFLAG_FAILED = (1 << 16),
- ATA_QCFLAG_SENSE_VALID = (1 << 17),
- ATA_QCFLAG_EH_SCHEDULED = (1 << 18),
-
- ATA_HOST_SIMPLEX = (1 << 0),
- ATA_HOST_STARTED = (1 << 1),
-
- ATA_TMOUT_BOOT = 30 * 100,
- ATA_TMOUT_BOOT_QUICK = 7 * 100,
- ATA_TMOUT_INTERNAL = 30 * 100,
- ATA_TMOUT_INTERNAL_QUICK = 5 * 100,
-
- /* FIXME: GoVault needs 2s but we can't afford that without
- * parallel probing. 800ms is enough for iVDR disk
- * HHD424020F7SV00. Increase to 2secs when parallel probing
- * is in place.
- */
- ATA_TMOUT_FF_WAIT = 4 * 100 / 5,
-
- BUS_UNKNOWN = 0,
- BUS_DMA = 1,
- BUS_IDLE = 2,
- BUS_NOINTR = 3,
- BUS_NODATA = 4,
- BUS_TIMER = 5,
- BUS_PIO = 6,
- BUS_EDD = 7,
- BUS_IDENTIFY = 8,
- BUS_PACKET = 9,
-
- PORT_UNKNOWN = 0,
- PORT_ENABLED = 1,
- PORT_DISABLED = 2,
-
- /* encoding various smaller bitmaps into a single
- * unsigned long bitmap
- */
- ATA_NR_PIO_MODES = 7,
- ATA_NR_MWDMA_MODES = 5,
- ATA_NR_UDMA_MODES = 8,
-
- ATA_SHIFT_PIO = 0,
- ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
- ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
-
- ATA_DMA_PAD_SZ = 4,
-
- ATA_ERING_SIZE = 32,
-
- ATA_DEFER_LINK = 1,
- ATA_DEFER_PORT = 2,
-
- ATA_EH_DESC_LEN = 80,
-
- ATA_EH_REVALIDATE = (1 << 0),
- ATA_EH_SOFTRESET = (1 << 1),
- ATA_EH_HARDRESET = (1 << 2),
- ATA_EH_ENABLE_LINK = (1 << 3),
- ATA_EH_LPM = (1 << 4),
-
- ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
- ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
-
- ATA_EHI_HOTPLUGGED = (1 << 0),
- ATA_EHI_RESUME_LINK = (1 << 1),
- ATA_EHI_NO_AUTOPSY = (1 << 2),
- ATA_EHI_QUIET = (1 << 3),
-
- ATA_EHI_DID_SOFTRESET = (1 << 16),
- ATA_EHI_DID_HARDRESET = (1 << 17),
- ATA_EHI_PRINTINFO = (1 << 18),
- ATA_EHI_SETMODE = (1 << 19),
- ATA_EHI_POST_SETMODE = (1 << 20),
-
- ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
- ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK,
-
- ATA_EH_MAX_TRIES = 5,
-
- ATA_PROBE_MAX_TRIES = 3,
- ATA_EH_DEV_TRIES = 3,
- ATA_EH_PMP_TRIES = 5,
- ATA_EH_PMP_LINK_TRIES = 3,
-
- SATA_PMP_SCR_TIMEOUT = 250,
-
- /* Horkage types. May be set by libata or controller on drives
- (some horkage may be drive/controller pair dependant */
-
- ATA_HORKAGE_DIAGNOSTIC = (1 << 0),
- ATA_HORKAGE_NODMA = (1 << 1),
- ATA_HORKAGE_NONCQ = (1 << 2),
- ATA_HORKAGE_MAX_SEC_128 = (1 << 3),
- ATA_HORKAGE_BROKEN_HPA = (1 << 4),
- ATA_HORKAGE_SKIP_PM = (1 << 5),
- ATA_HORKAGE_HPA_SIZE = (1 << 6),
- ATA_HORKAGE_IPM = (1 << 7),
- ATA_HORKAGE_IVB = (1 << 8),
- ATA_HORKAGE_STUCK_ERR = (1 << 9),
-
- ATA_DMA_MASK_ATA = (1 << 0),
- ATA_DMA_MASK_ATAPI = (1 << 1),
- ATA_DMA_MASK_CFA = (1 << 2),
-
- ATAPI_READ = 0,
- ATAPI_WRITE = 1,
- ATAPI_READ_CD = 2,
- ATAPI_PASS_THRU = 3,
- ATAPI_MISC = 4,
-};
-
-enum ata_completion_errors {
- AC_ERR_DEV = (1 << 0),
- AC_ERR_HSM = (1 << 1),
- AC_ERR_TIMEOUT = (1 << 2),
- AC_ERR_MEDIA = (1 << 3),
- AC_ERR_ATA_BUS = (1 << 4),
- AC_ERR_HOST_BUS = (1 << 5),
- AC_ERR_SYSTEM = (1 << 6),
- AC_ERR_INVALID = (1 << 7),
- AC_ERR_OTHER = (1 << 8),
- AC_ERR_NODEV_HINT = (1 << 9),
- AC_ERR_NCQ = (1 << 10),
-};
-
-enum ata_xfer_mask {
- ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO,
- ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA,
- ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA,
-};
-
-struct ata_port_info {
-#ifndef __U_BOOT__
- struct scsi_host_template *sht;
-#endif
- unsigned long flags;
- unsigned long link_flags;
- unsigned long pio_mask;
- unsigned long mwdma_mask;
- unsigned long udma_mask;
-#ifndef __U_BOOT__
- const struct ata_port_operations *port_ops;
- void *private_data;
-#endif
-};
-
-struct ata_ioports {
- void __iomem *cmd_addr;
- void __iomem *data_addr;
- void __iomem *error_addr;
- void __iomem *feature_addr;
- void __iomem *nsect_addr;
- void __iomem *lbal_addr;
- void __iomem *lbam_addr;
- void __iomem *lbah_addr;
- void __iomem *device_addr;
- void __iomem *status_addr;
- void __iomem *command_addr;
- void __iomem *altstatus_addr;
- void __iomem *ctl_addr;
-#ifndef __U_BOOT__
- void __iomem *bmdma_addr;
-#endif
- void __iomem *scr_addr;
-};
-
-struct ata_host {
-#ifndef __U_BOOT__
- void __iomem * const *iomap;
- void *private_data;
- const struct ata_port_operations *ops;
- unsigned long flags;
- struct ata_port *simplex_claimed;
-#endif
- unsigned int n_ports;
- struct ata_port *ports[0];
-};
-
-#ifndef __U_BOOT__
-struct ata_port_stats {
- unsigned long unhandled_irq;
- unsigned long idle_irq;
- unsigned long rw_reqbuf;
-};
-#endif
-
-struct ata_device {
- struct ata_link *link;
- unsigned int devno;
- unsigned long flags;
- unsigned int horkage;
-#ifndef __U_BOOT__
- struct scsi_device *sdev;
-#ifdef CONFIG_ATA_ACPI
- acpi_handle acpi_handle;
- union acpi_object *gtf_cache;
-#endif
-#endif
- u64 n_sectors;
- unsigned int class;
-
- union {
- u16 id[ATA_ID_WORDS];
- u32 gscr[SATA_PMP_GSCR_DWORDS];
- };
-#ifndef __U_BOOT__
- u8 pio_mode;
- u8 dma_mode;
- u8 xfer_mode;
- unsigned int xfer_shift;
-#endif
- unsigned int multi_count;
- unsigned int max_sectors;
- unsigned int cdb_len;
-#ifndef __U_BOOT__
- unsigned long pio_mask;
- unsigned long mwdma_mask;
-#endif
- unsigned long udma_mask;
- u16 cylinders;
- u16 heads;
- u16 sectors;
-#ifndef __U_BOOT__
- int spdn_cnt;
-#endif
-};
-
-struct ata_link {
- struct ata_port *ap;
- int pmp;
- unsigned int active_tag;
- u32 sactive;
- unsigned int flags;
- unsigned int hw_sata_spd_limit;
-#ifndef __U_BOOT__
- unsigned int sata_spd_limit;
- unsigned int sata_spd;
- struct ata_device device[2];
-#endif
-};
-
-struct ata_port {
- unsigned long flags;
- unsigned int pflags;
- unsigned int print_id;
- unsigned int port_no;
-
- struct ata_ioports ioaddr;
-
- u8 ctl;
- u8 last_ctl;
- unsigned int pio_mask;
- unsigned int mwdma_mask;
- unsigned int udma_mask;
- unsigned int cbl;
-
- struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
- unsigned long qc_allocated;
- unsigned int qc_active;
- int nr_active_links;
-
- struct ata_link link;
-#ifndef __U_BOOT__
- int nr_pmp_links;
- struct ata_link *pmp_link;
-#endif
- struct ata_link *excl_link;
- int nr_pmp_links;
-#ifndef __U_BOOT__
- struct ata_port_stats stats;
- struct device *dev;
- u32 msg_enable;
-#endif
- struct ata_host *host;
- void *port_task_data;
-
- unsigned int hsm_task_state;
- void *private_data;
- unsigned char *pdata;
-};
-
-#endif
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/uclass-internal.h>
static const char *if_typename_str[IF_TYPE_COUNT] = {
[IF_TYPE_IDE] = "ide",
struct blk_desc *desc;
int ret;
- ret = uclass_first_device(UCLASS_BLK, devp);
+ ret = uclass_find_first_device(UCLASS_BLK, devp);
if (ret)
return ret;
if (!*devp)
desc = dev_get_uclass_platdata(*devp);
if (desc->if_type == if_type)
return 0;
- ret = uclass_next_device(devp);
+ ret = uclass_find_next_device(devp);
if (ret)
return ret;
} while (*devp);
desc = dev_get_uclass_platdata(*devp);
if_type = desc->if_type;
do {
- ret = uclass_next_device(devp);
+ ret = uclass_find_next_device(devp);
if (ret)
return ret;
if (!*devp)
--- /dev/null
+#
+# Boot count configuration
+#
+
+menu "Boot count support"
+
+config BOOTCOUNT
+ bool "Enable Boot count support"
+ help
+ Enable boot count support, which provides the ability to store the
+ number of times the board has booted on a number of different
+ persistent storage mediums.
+
+if BOOTCOUNT
+
+config BOOTCOUNT_EXT
+ bool "Boot counter on EXT filesystem"
+ help
+ Add support for maintaining boot count in a file on an EXT
+ filesystem.
+
+if BOOTCOUNT_EXT
+
+config SYS_BOOTCOUNT_EXT_INTERFACE
+ string "Interface on which to find boot counter EXT filesystem"
+ default "mmc"
+ depends on BOOTCOUNT_EXT
+ help
+ Set the interface to use when locating the filesystem to use for the
+ boot counter.
+
+config SYS_BOOTCOUNT_EXT_DEVPART
+ string "Partition of the boot counter EXT filesystem"
+ default "0:1"
+ depends on BOOTCOUNT_EXT
+ help
+ Set the partition to use when locating the filesystem to use for the
+ boot counter.
+
+config SYS_BOOTCOUNT_EXT_NAME
+ string "Path and filename of the EXT filesystem based boot counter"
+ default "/boot/failures"
+ depends on BOOTCOUNT_EXT
+ help
+ Set the filename and path of the file used to store the boot counter.
+
+config SYS_BOOTCOUNT_ADDR
+ hex "RAM address used for reading and writing the boot counter"
+ default 0x7000A000
+ depends on BOOTCOUNT_EXT
+ help
+ Set the address used for reading and writing the boot counter.
+
+endif
+
+endif
+
+endmenu
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
+obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o
--- /dev/null
+/*
+ * Copyright (c) 2017 General Electric Company. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <bootcount.h>
+#include <fs.h>
+#include <mapmem.h>
+
+#define BC_MAGIC 0xbc
+
+void bootcount_store(ulong a)
+{
+ u8 *buf;
+ loff_t len;
+ int ret;
+
+ if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE,
+ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
+ puts("Error selecting device\n");
+ return;
+ }
+
+ buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2);
+ buf[0] = BC_MAGIC;
+ buf[1] = (a & 0xff);
+ unmap_sysmem(buf);
+
+ ret = fs_write(CONFIG_SYS_BOOTCOUNT_EXT_NAME,
+ CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len);
+ if (ret != 0)
+ puts("Error storing bootcount\n");
+}
+
+ulong bootcount_load(void)
+{
+ u8 *buf;
+ loff_t len_read;
+ int ret;
+
+ if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE,
+ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) {
+ puts("Error selecting device\n");
+ return 0;
+ }
+
+ ret = fs_read(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR,
+ 0, 2, &len_read);
+ if (ret != 0 || len_read != 2) {
+ puts("Error loading bootcount\n");
+ return 0;
+ }
+
+ buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2);
+ if (buf[0] == BC_MAGIC)
+ ret = buf[1];
+
+ unmap_sysmem(buf);
+
+ return ret;
+}
help
Enable this to support the clocks
+config CLK_STM32F
+ bool "Enable clock driver support for STM32F family"
+ depends on CLK && (STM32F7 || STM32F4)
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32F4 and STM32F7 SoCs.
+
+config CLK_HSDK
+ bool "Enable cgu clock driver for HSDK"
+ depends on CLK
+ help
+ Enable this to support the cgu clocks on Synopsys ARC HSDK
+
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_STM32F7) += clk_stm32f7.o
+obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
config AT91_UTMI
bool "Support UTMI PLL Clock"
- depends on CLK_AT91 && SPL_DM
+ depends on CLK_AT91
select REGMAP
- select SPL_REGMAP
+ select SPL_REGMAP if SPL_DM
select SYSCON
- select SPL_SYSCON
+ select SPL_SYSCON if SPL_DM
help
This option is used to enable the AT91 UTMI PLL clock
driver. It is the clock provider of USB, and UPLLCK is the
struct clk parent;
ulong clk_rate;
u32 tmp, gckdiv;
- u8 parent_id;
+ u8 clock_source, parent_index;
int ret;
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
- parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
+ clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
AT91_PMC_PCR_GCKCSS_MASK;
gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
- ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent);
+ parent_index = clock_source - 1;
+ ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
if (ret)
return 0;
ulong tmp_rate, best_rate = rate, parent_rate;
int tmp_diff, best_diff = -1;
u32 div, best_div = 0;
- u8 best_parent_id = 0;
+ u8 best_parent_index, best_clock_source = 0;
u8 i;
u32 tmp;
int ret;
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
- if (rate < tmp_rate)
- continue;
- tmp_diff = rate - tmp_rate;
+ tmp_diff = abs(rate - tmp_rate);
if (best_diff < 0 || best_diff > tmp_diff) {
best_rate = tmp_rate;
best_div = div - 1;
best_parent = parent;
- best_parent_id = i;
+ best_parent_index = i;
+ best_clock_source = best_parent_index + 1;
}
if (!best_diff || tmp_rate < rate)
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
- tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) |
+ tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
AT91_PMC_PCR_CMD_WRITE |
AT91_PMC_PCR_GCKDIV_(best_div) |
AT91_PMC_PCR_GCKEN;
--- /dev/null
+/*
+ * Synopsys HSDK SDP CGU clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/io.h>
+
+/*
+ * Synopsys ARC HSDK clock tree.
+ *
+ * ------------------
+ * | 33.33 MHz xtal |
+ * ------------------
+ * |
+ * | -----------
+ * |-->| ARC PLL |
+ * | -----------
+ * | |
+ * | |-->|CGU_ARC_IDIV|----------->
+ * | |-->|CREG_CORE_IF_DIV|------->
+ * |
+ * | --------------
+ * |-->| SYSTEM PLL |
+ * | --------------
+ * | |
+ * | |-->|CGU_SYS_IDIV_APB|------->
+ * | |-->|CGU_SYS_IDIV_AXI|------->
+ * | |-->|CGU_SYS_IDIV_*|--------->
+ * | |-->|CGU_SYS_IDIV_EBI_REF|--->
+ * |
+ * | --------------
+ * |-->| TUNNEL PLL |
+ * | --------------
+ * | |
+ * | |-->|CGU_TUN_IDIV|----------->
+ * |
+ * | ------------
+ * |-->| HDMI PLL |
+ * | ------------
+ * | |
+ * | |-->|CGU_HDMI_IDIV_APB|------>
+ * |
+ * | -----------
+ * |-->| DDR PLL |
+ * -----------
+ * |
+ * |---------------------------->
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CGU_ARC_IDIV 0x080
+#define CGU_TUN_IDIV 0x380
+#define CGU_HDMI_IDIV_APB 0x480
+#define CGU_SYS_IDIV_APB 0x180
+#define CGU_SYS_IDIV_AXI 0x190
+#define CGU_SYS_IDIV_ETH 0x1A0
+#define CGU_SYS_IDIV_USB 0x1B0
+#define CGU_SYS_IDIV_SDIO 0x1C0
+#define CGU_SYS_IDIV_HDMI 0x1D0
+#define CGU_SYS_IDIV_GFX_CORE 0x1E0
+#define CGU_SYS_IDIV_GFX_DMA 0x1F0
+#define CGU_SYS_IDIV_GFX_CFG 0x200
+#define CGU_SYS_IDIV_DMAC_CORE 0x210
+#define CGU_SYS_IDIV_DMAC_CFG 0x220
+#define CGU_SYS_IDIV_SDIO_REF 0x230
+#define CGU_SYS_IDIV_SPI_REF 0x240
+#define CGU_SYS_IDIV_I2C_REF 0x250
+#define CGU_SYS_IDIV_UART_REF 0x260
+#define CGU_SYS_IDIV_EBI_REF 0x270
+
+#define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
+
+#define CGU_ARC_PLL 0x0
+#define CGU_SYS_PLL 0x10
+#define CGU_DDR_PLL 0x20
+#define CGU_TUN_PLL 0x30
+#define CGU_HDMI_PLL 0x40
+
+#define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
+#define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
+#define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
+#define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
+
+#define CGU_PLL_CTRL_ODIV_SHIFT 2
+#define CGU_PLL_CTRL_IDIV_SHIFT 4
+#define CGU_PLL_CTRL_FBDIV_SHIFT 9
+#define CGU_PLL_CTRL_BAND_SHIFT 20
+
+#define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
+#define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
+#define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
+
+#define CGU_PLL_CTRL_PD BIT(0)
+#define CGU_PLL_CTRL_BYPASS BIT(1)
+
+#define CGU_PLL_STATUS_LOCK BIT(0)
+#define CGU_PLL_STATUS_ERR BIT(1)
+
+#define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
+
+#define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
+#define CORE_IF_CLK_THRESHOLD_HZ 500000000
+#define CREG_CORE_IF_CLK_DIV_1 0x0
+#define CREG_CORE_IF_CLK_DIV_2 0x1
+
+#define PARENT_RATE 33333333 /* fixed clock - xtal */
+#define CGU_MAX_CLOCKS 24
+
+struct hsdk_pll_cfg {
+ u32 rate;
+ u32 idiv;
+ u32 fbdiv;
+ u32 odiv;
+ u32 band;
+};
+
+static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
+ { 100000000, 0, 11, 3, 0 },
+ { 125000000, 0, 14, 3, 0 },
+ { 133000000, 0, 15, 3, 0 },
+ { 150000000, 0, 17, 3, 0 },
+ { 200000000, 1, 47, 3, 0 },
+ { 233000000, 1, 27, 2, 0 },
+ { 300000000, 1, 35, 2, 0 },
+ { 333000000, 1, 39, 2, 0 },
+ { 400000000, 1, 47, 2, 0 },
+ { 500000000, 0, 14, 1, 0 },
+ { 600000000, 0, 17, 1, 0 },
+ { 700000000, 0, 20, 1, 0 },
+ { 800000000, 0, 23, 1, 0 },
+ { 900000000, 1, 26, 0, 0 },
+ { 1000000000, 1, 29, 0, 0 },
+ { 1100000000, 1, 32, 0, 0 },
+ { 1200000000, 1, 35, 0, 0 },
+ { 1300000000, 1, 38, 0, 0 },
+ { 1400000000, 1, 41, 0, 0 },
+ { 1500000000, 1, 44, 0, 0 },
+ { 1600000000, 1, 47, 0, 0 },
+ {}
+};
+
+static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
+ { 297000000, 0, 21, 2, 0 },
+ { 540000000, 0, 19, 1, 0 },
+ { 594000000, 0, 21, 1, 0 },
+ {}
+};
+
+struct hsdk_cgu_clk {
+ /* CGU block register */
+ void __iomem *cgu_regs;
+ /* CREG block register */
+ void __iomem *creg_regs;
+
+ /* PLLs registers */
+ void __iomem *regs;
+ /* PLLs special registers */
+ void __iomem *spec_regs;
+ /* PLLs devdata */
+ const struct hsdk_pll_devdata *pll_devdata;
+
+ /* Dividers registers */
+ void __iomem *idiv_regs;
+};
+
+struct hsdk_pll_devdata {
+ const struct hsdk_pll_cfg *pll_cfg;
+ int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
+ const struct hsdk_pll_cfg *cfg);
+};
+
+static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
+ const struct hsdk_pll_cfg *);
+static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
+ const struct hsdk_pll_cfg *);
+
+static const struct hsdk_pll_devdata core_pll_dat = {
+ .pll_cfg = asdt_pll_cfg,
+ .update_rate = hsdk_pll_core_update_rate,
+};
+
+static const struct hsdk_pll_devdata sdt_pll_dat = {
+ .pll_cfg = asdt_pll_cfg,
+ .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static const struct hsdk_pll_devdata hdmi_pll_dat = {
+ .pll_cfg = hdmi_pll_cfg,
+ .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static ulong idiv_set(struct clk *, ulong);
+static ulong idiv_get(struct clk *);
+static int idiv_off(struct clk *);
+static ulong pll_set(struct clk *, ulong);
+static ulong pll_get(struct clk *);
+
+struct hsdk_cgu_clock_map {
+ u32 cgu_pll_oft;
+ u32 creg_div_oft;
+ u32 cgu_div_oft;
+ const struct hsdk_pll_devdata *pll_devdata;
+ ulong (*get_rate)(struct clk *clk);
+ ulong (*set_rate)(struct clk *clk, ulong rate);
+ int (*disable)(struct clk *clk);
+};
+
+static const struct hsdk_cgu_clock_map clock_map[] = {
+ { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
+ { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
+};
+
+static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
+{
+ iowrite32(val, clk->idiv_regs);
+}
+
+static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
+{
+ return ioread32(clk->idiv_regs);
+}
+
+static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
+{
+ iowrite32(val, clk->regs + reg);
+}
+
+static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
+{
+ return ioread32(clk->regs + reg);
+}
+
+static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
+{
+ iowrite32(val, clk->spec_regs + reg);
+}
+
+static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
+{
+ return ioread32(clk->spec_regs + reg);
+}
+
+static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
+ const struct hsdk_pll_cfg *cfg)
+{
+ u32 val = 0;
+
+ /* Powerdown and Bypass bits should be cleared */
+ val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+ val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+ val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+ val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+
+ pr_debug("write configurarion: %#x\n", val);
+
+ hsdk_pll_write(clk, CGU_PLL_CTRL, val);
+}
+
+static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
+{
+ return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
+}
+
+static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
+{
+ return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
+}
+
+static ulong pll_get(struct clk *sclk)
+{
+ u32 val;
+ u64 rate;
+ u32 idiv, fbdiv, odiv;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ val = hsdk_pll_read(clk, CGU_PLL_CTRL);
+
+ pr_debug("current configurarion: %#x\n", val);
+
+ /* Check if PLL is disabled */
+ if (val & CGU_PLL_CTRL_PD)
+ return 0;
+
+ /* Check if PLL is bypassed */
+ if (val & CGU_PLL_CTRL_BYPASS)
+ return PARENT_RATE;
+
+ /* input divider = reg.idiv + 1 */
+ idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
+ /* fb divider = 2*(reg.fbdiv + 1) */
+ fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
+ /* output divider = 2^(reg.odiv) */
+ odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
+
+ rate = (u64)PARENT_RATE * fbdiv;
+ do_div(rate, idiv * odiv);
+
+ return rate;
+}
+
+static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
+{
+ int i;
+ unsigned long best_rate;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+ if (pll_cfg[0].rate == 0)
+ return -EINVAL;
+
+ best_rate = pll_cfg[0].rate;
+
+ for (i = 1; pll_cfg[i].rate != 0; i++) {
+ if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
+ best_rate = pll_cfg[i].rate;
+ }
+
+ pr_debug("chosen best rate: %lu\n", best_rate);
+
+ return best_rate;
+}
+
+static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
+ unsigned long rate,
+ const struct hsdk_pll_cfg *cfg)
+{
+ hsdk_pll_set_cfg(clk, cfg);
+
+ /*
+ * Wait until CGU relocks and check error status.
+ * If after timeout CGU is unlocked yet return error.
+ */
+ udelay(HSDK_PLL_MAX_LOCK_TIME);
+ if (!hsdk_pll_is_locked(clk))
+ return -ETIMEDOUT;
+
+ if (hsdk_pll_is_err(clk))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
+ unsigned long rate,
+ const struct hsdk_pll_cfg *cfg)
+{
+ /*
+ * When core clock exceeds 500MHz, the divider for the interface
+ * clock must be programmed to div-by-2.
+ */
+ if (rate > CORE_IF_CLK_THRESHOLD_HZ)
+ hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
+
+ hsdk_pll_set_cfg(clk, cfg);
+
+ /*
+ * Wait until CGU relocks and check error status.
+ * If after timeout CGU is unlocked yet return error.
+ */
+ udelay(HSDK_PLL_MAX_LOCK_TIME);
+ if (!hsdk_pll_is_locked(clk))
+ return -ETIMEDOUT;
+
+ if (hsdk_pll_is_err(clk))
+ return -EINVAL;
+
+ /*
+ * Program divider to div-by-1 if we succesfuly set core clock below
+ * 500MHz threshold.
+ */
+ if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
+ hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
+
+ return 0;
+}
+
+static ulong pll_set(struct clk *sclk, ulong rate)
+{
+ int i;
+ unsigned long best_rate;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+ best_rate = hsdk_pll_round_rate(sclk, rate);
+
+ for (i = 0; pll_cfg[i].rate != 0; i++) {
+ if (pll_cfg[i].rate == best_rate) {
+ return clk->pll_devdata->update_rate(clk, best_rate,
+ &pll_cfg[i]);
+ }
+ }
+
+ pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+
+ return -EINVAL;
+}
+
+static int idiv_off(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ hsdk_idiv_write(clk, 0);
+
+ return 0;
+}
+
+static ulong idiv_get(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong parent_rate = pll_get(sclk);
+ u32 div_factor = hsdk_idiv_read(clk);
+
+ div_factor &= CGU_IDIV_MASK;
+
+ pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
+
+ if (div_factor == 0)
+ return 0;
+
+ return parent_rate / div_factor;
+}
+
+static ulong idiv_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong parent_rate = pll_get(sclk);
+ u32 div_factor;
+
+ div_factor = parent_rate / rate;
+ if (abs(rate - parent_rate / (div_factor + 1)) <=
+ abs(rate - parent_rate / div_factor)) {
+ div_factor += 1;
+ }
+
+ if (div_factor & ~CGU_IDIV_MASK) {
+ pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+ rate, parent_rate, div_factor, CGU_IDIV_MASK);
+
+ div_factor = CGU_IDIV_MASK;
+ }
+
+ if (div_factor == 0) {
+ pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+ rate, parent_rate, div_factor);
+
+ div_factor = 1;
+ }
+
+ hsdk_idiv_write(clk, div_factor);
+
+ return 0;
+}
+
+static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ if (sclk->id >= CGU_MAX_CLOCKS)
+ return -EINVAL;
+
+ clk->pll_devdata = clock_map[sclk->id].pll_devdata;
+ clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
+ clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
+ clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
+
+ return 0;
+}
+
+static ulong hsdk_cgu_get_rate(struct clk *sclk)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ return clock_map[sclk->id].get_rate(sclk);
+}
+
+static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ return clock_map[sclk->id].set_rate(sclk, rate);
+}
+
+static int hsdk_cgu_disable(struct clk *sclk)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ if (clock_map[sclk->id].disable)
+ return clock_map[sclk->id].disable(sclk);
+
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops hsdk_cgu_ops = {
+ .set_rate = hsdk_cgu_set_rate,
+ .get_rate = hsdk_cgu_get_rate,
+ .disable = hsdk_cgu_disable,
+};
+
+static int hsdk_cgu_clk_probe(struct udevice *dev)
+{
+ struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
+
+ BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
+
+ pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
+ if (!pll_clk->cgu_regs)
+ return -EINVAL;
+
+ pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
+ if (!pll_clk->creg_regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id hsdk_cgu_clk_id[] = {
+ { .compatible = "snps,hsdk-cgu-clock" },
+ { }
+};
+
+U_BOOT_DRIVER(hsdk_cgu_clk) = {
+ .name = "hsdk-cgu-clk",
+ .id = UCLASS_CLK,
+ .of_match = hsdk_cgu_clk_id,
+ .probe = hsdk_cgu_clk_probe,
+ .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .ops = &hsdk_cgu_ops,
+};
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <stm32_rcc.h>
+
#include <asm/io.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
#define RCC_CR_CSSON BIT(19)
#define RCC_CR_PLLON BIT(24)
#define RCC_CR_PLLRDY BIT(25)
+#define RCC_CR_PLLSAION BIT(28)
+#define RCC_CR_PLLSAIRDY BIT(29)
#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
+#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
+#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
+#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
+#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
+#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
+
+#define RCC_DCKCFGRX_CK48MSEL BIT(27)
+#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
+#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
+
+#define RCC_APB2ENR_SAI1EN BIT(22)
+
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
+
/*
- * Offsets of some PWR registers
+ * RCC APB1ENR specific definitions
*/
-#define PWR_CR1_ODEN BIT(16)
-#define PWR_CR1_ODSWEN BIT(17)
-#define PWR_CSR1_ODRDY BIT(16)
-#define PWR_CSR1_ODSWRDY BIT(17)
-
-struct pll_psc {
- u8 pll_m;
- u16 pll_n;
- u8 pll_p;
- u8 pll_q;
- u8 ahb_psc;
- u8 apb1_psc;
- u8 apb2_psc;
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_PWREN BIT(28)
+
+/*
+ * RCC APB2ENR specific definitions
+ */
+#define RCC_APB2ENR_SYSCFGEN BIT(14)
+
+struct stm32_clk_info stm32f4_clk_info = {
+ /* 180 MHz */
+ .sys_pll_psc = {
+ .pll_m = 8,
+ .pll_n = 360,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = false,
+ .v2 = false,
};
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
-
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
+struct stm32_clk_info stm32f7_clk_info = {
+ /* 200 MHz */
+ .sys_pll_psc = {
+ .pll_m = 25,
+ .pll_n = 400,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = true,
+ .v2 = true,
+};
struct stm32_clk {
struct stm32_rcc_regs *base;
+ struct stm32_pwr_regs *pwr_regs;
+ struct stm32_clk_info *info;
};
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 25000000)
-#if (CONFIG_SYS_CLK_FREQ == 200000000)
-/* 200 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 25,
- .pll_n = 400,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
+ struct stm32_pwr_regs *pwr = priv->pwr_regs;
+ struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
+ u32 pllsaicfgr = 0;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
writel(0, ®s->cfgr); /* Reset CFGR */
clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
+ | RCC_CR_PLLON | RCC_CR_PLLSAION));
writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
clrbits_le32(®s->cr, RCC_CR_HSEBYP);
writel(0, ®s->cir); /* Disable all interrupts */
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
+ /* Configure the SAI PLL to get a 48 MHz source */
+ pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
+ RCC_PLLSAICFGR_PLLSAIP_4;
+ pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
+ writel(pllsaicfgr, ®s->pllsaicfgr);
+
/* Enable the main PLL */
setbits_le32(®s->cr, RCC_CR_PLLON);
while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
- /* Enable high performance mode, System frequency up to 200 MHz */
- setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
- /* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
- ;
- /* Enable the Over-drive switch */
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
- /* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
+ if (priv->info->v2) { /*stm32f7 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
+
+ /* select 48MHz as SDMMC2 clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
+ } else { /* stm32f4 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
+ }
+
+ /* Enable the SAI PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLSAION);
+ while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
;
+ setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
+
+ if (priv->info->has_overdrive) {
+ /*
+ * Enable high performance mode
+ * System frequency up to 200 MHz
+ */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
+ ;
+ /* Enable the Over-drive switch */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
+ ;
+ }
+
stm32_flash_latency_cfg(5);
clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
+ /* gate the SAI clock, needed for MMC 1&2 clocks */
+ setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
return 0;
}
+static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
+ u32 sysclk)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pllq, pllm, pllsain, pllsaip;
+ bool pllsai;
+
+ pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
+ >> RCC_PLLCFGR_PLLQ_SHIFT;
+
+ if (priv->info->v2) /*stm32f7 case */
+ pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
+ else
+ pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
+
+ if (pllsai) {
+ /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+ pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
+ return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip;
+ }
+ /* PLL48CLK is selected from PLLQ */
+ return sysclk / pllq;
+}
+
static unsigned long stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0;
u32 shift = 0;
+ u16 pllm, plln, pllp;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
(readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
- break;
/* APB1 CLOCK */
case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
shift = apb_psc_table[(
(readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
- break;
/* APB2 CLOCK */
case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
+ /*
+ * particular case for SDMMC1 and SDMMC2 :
+ * 48Mhz source clock can be from main PLL or from
+ * SAI PLL
+ */
+ switch (clk->id) {
+ case STM32F7_APB2_CLOCK(SDMMC1):
+ if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
+ /* System clock is selected as SDMMC1 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ case STM32F7_APB2_CLOCK(SDMMC2):
+ if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
+ /* System clock is selected as SDMMC2 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ }
+
shift = apb_psc_table[(
(readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
- break;
default:
pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
- break;
}
}
static int stm32_clk_probe(struct udevice *dev)
{
- debug("%s: stm32_clk_probe\n", __func__);
+ struct ofnode_phandle_args args;
+ int err;
+
+ debug("%s\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = (struct stm32_rcc_regs *)addr;
+ switch (dev_get_driver_data(dev)) {
+ case STM32F4:
+ priv->info = &stm32f4_clk_info;
+ break;
+ case STM32F7:
+ priv->info = &stm32f7_clk_info;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (priv->info->has_overdrive) {
+ err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (err) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ err);
+ return err;
+ }
+
+ priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
+ }
+
configure_clocks(dev);
return 0;
.get_rate = stm32_clk_get_rate,
};
-static const struct udevice_id stm32_clk_ids[] = {
- { .compatible = "st,stm32f42xx-rcc"},
- {}
-};
-
-U_BOOT_DRIVER(stm32f7_clk) = {
- .name = "stm32f7_clk",
+U_BOOT_DRIVER(stm32fx_clk) = {
+ .name = "stm32fx_rcc_clock",
.id = UCLASS_CLK,
- .of_match = stm32_clk_ids,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
.priv_auto_alloc_size = sizeof(struct stm32_clk),
Enable support for clock present on Renesas RCar SoCs.
config CLK_RCAR_GEN3
- bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver"
+ bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
help
- Enable this to support the clocks on Renesas RCar Gen3
- R8A7795 and R8A7796 SoC.
+ Enable this to support the clocks on Renesas RCar Gen3 SoC.
/*
- * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
+ * Renesas RCar Gen3 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#define CPG_RST_MODEMR 0x0060
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
/*
* Definitions of Module Clocks
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_Z2,
};
struct rcar_gen3_cpg_pll_config {
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
+ DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
+ DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
+static const struct cpg_core_clk r8a77970_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
+
+ DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+ DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
+ DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("thermal", 522, R8A77970_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
+ DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
+ DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
+ DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
+ DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
+ DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
+ DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
+};
+
+static const struct cpg_core_clk r8a77995_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
+ DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
+ DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
+ DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
+ DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+ DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("cmt3", 300, R8A77995_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77995_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77995_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77995_CLK_R),
+ DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
+ DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
+ DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A77995_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77995_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
+ DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
+ DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
+ DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
+ DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
+ DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+};
+
/*
* CPG Clock Data
*/
return rate;
case CLK_TYPE_FF:
+ case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
__func__, __LINE__,
enum gen3_clk_model {
CLK_R8A7795,
CLK_R8A7796,
+ CLK_R8A77970,
+ CLK_R8A77995,
};
static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
break;
+ case CLK_R8A77970:
+ priv->core_clk = r8a77970_core_clks;
+ priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
+ priv->mod_clk = r8a77970_mod_clks;
+ priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "renesas,r8a77970-rst");
+ if (ret < 0)
+ return ret;
+ break;
+ case CLK_R8A77995:
+ priv->core_clk = r8a77995_core_clks;
+ priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
+ priv->mod_clk = r8a77995_mod_clks;
+ priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "renesas,r8a77995-rst");
+ if (ret < 0)
+ return ret;
+ break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
- ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
- if (ret < 0)
- return ret;
+ if (model != CLK_R8A77995) {
+ ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+struct mstp_stop_table {
+ u32 dis;
+ u32 en;
+};
+
+static struct mstp_stop_table r8a7795_mstp_table[] = {
+ { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
+ { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
+ { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
+ { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
+};
+
+static struct mstp_stop_table r8a7796_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static struct mstp_stop_table r8a77970_mstp_table[] = {
+ { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static struct mstp_stop_table r8a77995_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+#define TSTR0 0x04
+#define TSTR0_STR0 BIT(0)
+
+static int gen3_clk_remove(struct udevice *dev)
+{
+ struct gen3_clk_priv *priv = dev_get_priv(dev);
+ enum gen3_clk_model model = dev_get_driver_data(dev);
+ struct mstp_stop_table *tbl;
+ unsigned int i, tbl_size;
+
+ switch (model) {
+ case CLK_R8A7795:
+ tbl = r8a7795_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a7795_mstp_table);
+ break;
+ case CLK_R8A7796:
+ tbl = r8a7796_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
+ break;
+ case CLK_R8A77970:
+ tbl = r8a77970_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
+ break;
+ case CLK_R8A77995:
+ tbl = r8a77995_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Stop TMU0 */
+ clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
+
+ /* Stop module clock */
+ for (i = 0; i < tbl_size; i++) {
+ clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en);
+ clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0);
+ }
return 0;
}
static const struct udevice_id gen3_clk_ids[] = {
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
+ { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
+ { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
{ }
};
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
};
#
-# Copyright (c) 2016 Google, Inc
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
static int rk3036_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
- if (ret)
- debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return 0;
}
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3128.h>
+#include <asm/arch/hardware.h>
+#include <bitfield.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3128-cru.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ VCO_MAX_HZ = 2400U * 1000000,
+ VCO_MIN_HZ = 600 * 1000000,
+ OUTPUT_MAX_HZ = 2400U * 1000000,
+ OUTPUT_MIN_HZ = 24 * 1000000,
+};
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+ .refdiv = _refdiv,\
+ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
+ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
+
+/* use integer mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3128_pll *pll = &cru->pll[pll_id];
+
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
+ uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
+
+ debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
+ pll, div->fbdiv, div->refdiv, div->postdiv1,
+ div->postdiv2, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
+
+ /* use integer mode */
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ /* Power down */
+ rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
+ (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+ div->refdiv << PLL_REFDIV_SHIFT));
+
+ /* Power Up */
+ rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ /* waiting for pll lock */
+ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+ udelay(1);
+
+ return 0;
+}
+
+static int pll_para_config(u32 freq_hz, struct pll_div *div)
+{
+ u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
+ u32 postdiv1, postdiv2 = 1;
+ u32 fref_khz;
+ u32 diff_khz, best_diff_khz;
+ const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
+ const u32 max_postdiv1 = 7, max_postdiv2 = 7;
+ u32 vco_khz;
+ u32 freq_khz = freq_hz / 1000;
+
+ if (!freq_hz) {
+ printf("%s: the frequency can't be 0 Hz\n", __func__);
+ return -1;
+ }
+
+ postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
+ if (postdiv1 > max_postdiv1) {
+ postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
+ postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
+ }
+
+ vco_khz = freq_khz * postdiv1 * postdiv2;
+
+ if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
+ postdiv2 > max_postdiv2) {
+ printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
+ __func__, freq_hz);
+ return -1;
+ }
+
+ div->postdiv1 = postdiv1;
+ div->postdiv2 = postdiv2;
+
+ best_diff_khz = vco_khz;
+ for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
+ fref_khz = ref_khz / refdiv;
+
+ fbdiv = vco_khz / fref_khz;
+ if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
+ continue;
+ diff_khz = vco_khz - fbdiv * fref_khz;
+ if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
+ fbdiv++;
+ diff_khz = fref_khz - diff_khz;
+ }
+
+ if (diff_khz >= best_diff_khz)
+ continue;
+
+ best_diff_khz = diff_khz;
+ div->refdiv = refdiv;
+ div->fbdiv = fbdiv;
+ }
+
+ if (best_diff_khz > 4 * (1000)) {
+ printf("%s: Failed to match output frequency %u bestis %u Hz\n",
+ __func__, freq_hz,
+ best_diff_khz * 1000);
+ return -1;
+ }
+ return 0;
+}
+
+static void rkclk_init(struct rk3128_cru *cru)
+{
+ u32 aclk_div;
+ u32 hclk_div;
+ u32 pclk_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+
+ /*
+ * select apll as cpu/core clock pll source and
+ * set up dependent divisors for PERI and ACLK clocks.
+ * core hz : apll = 1:1
+ */
+ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
+ assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
+
+ pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
+ assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
+ CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+ 0 << CORE_DIV_CON_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
+ aclk_div << CORE_ACLK_DIV_SHIFT |
+ pclk_div << CORE_PERI_DIV_SHIFT);
+
+ /*
+ * select gpll as pd_bus bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+ assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
+
+ pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
+ assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
+
+ hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
+ assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
+ BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
+ aclk_div << BUS_ACLK_DIV_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
+ pclk_div << BUS_PCLK_DIV_SHIFT |
+ hclk_div << BUS_HCLK_DIV_SHIFT);
+
+ /*
+ * select gpll as pd_peri bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (hclk_div < 0x4));
+
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && pclk_div < 0x8);
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
+ PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
+ PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
+ GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+ APLL_MODE_NORM << APLL_MODE_SHIFT |
+ CPLL_MODE_NORM << CPLL_MODE_SHIFT);
+
+ /*fix NAND controller working clock max to 150Mhz */
+ rk_clrsetreg(&cru->cru_clksel_con[2],
+ NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
+ NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
+ 3 << NANDC_CLK_DIV_SHIFT);
+}
+
+/* Get pll rate by id */
+static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ u32 refdiv, fbdiv, postdiv1, postdiv2;
+ u32 con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3128_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+ GPLL_MODE_SHIFT, 0xff
+ };
+ static u32 clk_mask[CLK_COUNT] = {
+ 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
+ GPLL_MODE_MASK, 0xff
+ };
+ uint shift;
+ uint mask;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ mask = clk_mask[clk_id];
+
+ switch ((con & mask) >> shift) {
+ case GPLL_MODE_SLOW:
+ return OSC_HZ;
+ case GPLL_MODE_NORM:
+ /* normal mode */
+ con = readl(&pll->con0);
+ postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
+ fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
+ con = readl(&pll->con1);
+ postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
+ refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
+ return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+ case GPLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
+ int periph)
+{
+ uint src_rate;
+ uint div, mux;
+ u32 con;
+
+ switch (periph) {
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ case SCLK_EMMC_SAMPLE:
+ con = readl(&cru->cru_clksel_con[12]);
+ mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+ div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+ div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
+ return DIV_TO_RATE(src_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
+ int periph, uint freq)
+{
+ int src_clk_div;
+ int mux;
+
+ debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
+
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
+
+ if (src_clk_div > 128) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ mux = EMMC_SEL_24M;
+ } else {
+ mux = EMMC_SEL_GPLL;
+ }
+
+ switch (periph) {
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_PLL_MASK | EMMC_DIV_MASK,
+ mux << EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << EMMC_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_PLL_MASK | MMC0_DIV_MASK,
+ mux << MMC0_PLL_SHIFT |
+ (src_clk_div - 1) << MMC0_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+}
+
+static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
+{
+ u32 div, con;
+
+ switch (clk_id) {
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ con = readl(&cru->cru_clksel_con[10]);
+ div = con >> 12 & 0x3;
+ break;
+ default:
+ printf("do not support this peripheral bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PERI_ACLK_HZ, div);
+}
+
+static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = PERI_ACLK_HZ / hz;
+ assert(src_clk_div - 1 < 4);
+
+ switch (clk_id) {
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ rk_setreg(&cru->cru_clksel_con[10],
+ ((src_clk_div - 1) << 12));
+ break;
+ default:
+ printf("do not support this peripheral bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
+}
+
+static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(&cru->cru_clksel_con[24]);
+ div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
+ SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(&cru->cru_clksel_con[24],
+ SARADC_DIV_CON_MASK,
+ src_clk_div << SARADC_DIV_CON_SHIFT);
+
+ return rk3128_saradc_get_clk(cru);
+}
+
+static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
+{
+ int src_clk_div;
+ struct pll_div cpll_config = {0};
+
+ src_clk_div = GPLL_HZ / hz;
+ assert(src_clk_div - 1 < 31);
+
+ switch (clk_id) {
+ case ACLK_VIO0:
+ rk_clrsetreg(&cru->cru_clksel_con[31],
+ VIO0_PLL_MASK | VIO0_DIV_MASK,
+ VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
+ (src_clk_div - 1) << VIO0_DIV_SHIFT);
+ break;
+ case ACLK_VIO1:
+ rk_clrsetreg(&cru->cru_clksel_con[31],
+ VIO1_PLL_MASK | VIO1_DIV_MASK,
+ VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
+ (src_clk_div - 1) << VIO1_DIV_SHIFT);
+ break;
+ case DCLK_LCDC:
+ if (pll_para_config(hz, &cpll_config))
+ return -1;
+ rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
+
+ rk_clrsetreg(&cru->cru_clksel_con[27],
+ DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
+ DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
+ (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
+ break;
+ default:
+ printf("do not support this vop freq\n");
+ return -EINVAL;
+ }
+
+ return hz;
+}
+
+static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
+{
+ u32 div, con, parent;
+
+ switch (clk_id) {
+ case ACLK_VIO0:
+ con = readl(&cru->cru_clksel_con[31]);
+ div = con & 0x1f;
+ parent = GPLL_HZ;
+ break;
+ case ACLK_VIO1:
+ con = readl(&cru->cru_clksel_con[31]);
+ div = (con >> 8) & 0x1f;
+ parent = GPLL_HZ;
+ break;
+ case DCLK_LCDC:
+ con = readl(&cru->cru_clksel_con[27]);
+ div = (con >> 8) & 0xfff;
+ parent = rkclk_pll_get_rate(cru, CLK_CODEC);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3128_clk_get_rate(struct clk *clk)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case 0 ... 63:
+ return rkclk_pll_get_rate(priv->cru, clk->id);
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ return rk3128_peri_get_pclk(priv->cru, clk->id);
+ case SCLK_SARADC:
+ return rk3128_saradc_get_clk(priv->cru);
+ case DCLK_LCDC:
+ case ACLK_VIO0:
+ case ACLK_VIO1:
+ return rk3128_vop_get_rate(priv->cru, clk->id);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case 0 ... 63:
+ return 0;
+ case DCLK_LCDC:
+ case ACLK_VIO0:
+ case ACLK_VIO1:
+ new_rate = rk3128_vop_set_clk(priv->cru,
+ clk->id, rate);
+ break;
+ case HCLK_EMMC:
+ new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+ clk->id, rate);
+ break;
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_PWM:
+ new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
+ break;
+ case SCLK_SARADC:
+ new_rate = rk3128_saradc_set_clk(priv->cru, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk3128_clk_ops = {
+ .get_rate = rk3128_clk_get_rate,
+ .set_rate = rk3128_clk_set_rate,
+};
+
+static int rk3128_clk_probe(struct udevice *dev)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static int rk3128_clk_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id rk3128_clk_ids[] = {
+ { .compatible = "rockchip,rk3128-cru" },
+ { .compatible = "rockchip,rk3126-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3128_cru) = {
+ .name = "clk_rk3128",
+ .id = UCLASS_CLK,
+ .of_match = rk3128_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
+ .ops = &rk3128_clk_ops,
+ .bind = rk3128_clk_bind,
+ .probe = rk3128_clk_probe,
+};
static int rk3188_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
- if (ret)
- debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return 0;
}
static int rk322x_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
- if (ret)
- debug("Warning: No RK322x reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return 0;
}
static int rk3288_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
- if (ret)
- debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
+ cru_glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
+ cru_glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return 0;
}
static int rk3328_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev);
- if (ret)
- printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
+ glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
+ glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return ret;
}
static int rk3368_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
- if (ret)
- pr_err("bind RK3368 reset driver failed: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
+ glb_srst_fst_val);
+ priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
+ glb_srst_snd_val);
+ sys_child->priv = priv;
+ }
return ret;
}
.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
};
-static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
-{
- return (val >> shift) & ((1 << width) - 1);
-}
-
static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
const struct spi_clkreg *spiclk = NULL;
}
val = readl(&cru->clksel_con[spiclk->reg]);
- div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
+ div = bitfield_extract(val, spiclk->div_shift,
+ CLK_SPI_PLL_DIV_CON_WIDTH);
return DIV_TO_RATE(GPLL_HZ, div);
}
static int rk3399_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev);
- if (ret)
- printf("Warning: No RK3399 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
+ glb_srst_fst_value);
+ priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
+ glb_srst_snd_value);
+ sys_child->priv = priv;
+ }
return 0;
}
static int rv1108_clk_bind(struct udevice *dev)
{
int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev);
- if (ret)
- pr_err("No Rv1108 reset driver: ret=%d\n", ret);
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
+ glb_srst_fst_val);
+ priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
+ glb_srst_snd_val);
+ sys_child->priv = priv;
+ }
return 0;
}
#include <libfdt.h>
#include <linux/arm-smccc.h>
#include <linux/errno.h>
+#include <linux/printk.h>
#include <linux/psci.h>
psci_fn *invoke_psci_fn;
ret = device_bind_driver(dev, "psci-sysreset", "psci-sysreset",
NULL);
if (ret)
- debug("PSCI System Reset was not bound.\n");
+ pr_debug("PSCI System Reset was not bound.\n");
}
return 0;
method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev), "method",
0, NULL);
if (!method) {
- printf("missing \"method\" property\n");
+ pr_warn("missing \"method\" property\n");
return -ENXIO;
}
} else if (!strcmp("smc", method)) {
invoke_psci_fn = __invoke_psci_fn_smc;
} else {
- printf("invalid \"method\" property: %s\n", method);
+ pr_warn("invalid \"method\" property: %s\n", method);
return -EINVAL;
}
return devnum;
}
+/*
+ * Return 1 if the fpga data is partial.
+ * This is only required for fpga drivers that support bitstream_type.
+ */
+int __weak fpga_is_partial_data(int devnum, size_t img_len)
+{
+ return 0;
+}
+
/*
* Convert bitstream data and load into the fpga
*/
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
asm volatile(
+ " cmp %2, #0\n"
+ " beq 2f\n"
"1: ldmia %0!, {r0-r7}\n"
" stmia %1!, {r0-r7}\n"
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
+ "2: cmp %3, #0\n"
+ " beq 4f\n"
+ "3: ldr %2, [%0], #4\n"
" str %2, [%1]\n"
" subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
+ " bne 3b\n"
+ "4: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
/* ------------------------------------------------------------------------- */
+int fpga_is_partial_data(int devnum, size_t img_len)
+{
+ const fpga_desc * const desc = fpga_get_desc(devnum);
+ xilinx_desc *desc_xilinx = desc->devdesc;
+
+ /* Check datasize against FPGA size */
+ if (img_len >= desc_xilinx->size)
+ return 0;
+
+ /* datasize is smaller, must be partial data */
+ return 1;
+}
+
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{
help
This driver supports i.MX7ULP Rapid GPIO2P controller.
+config HSDK_CREG_GPIO
+ bool "HSDK CREG GPIO griver"
+ depends on DM_GPIO
+ default n
+ help
+ This driver supports CREG GPIOs on Synopsys HSDK SOC.
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
+obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include "../pinctrl/renesas/sh_pfc.h"
#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
DECLARE_GLOBAL_DATA_PTR;
struct rcar_gpio_priv {
- void __iomem *regs;
+ void __iomem *regs;
+ int pfc_offset;
};
static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
return GPIOF_INPUT;
}
+static int rcar_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
+{
+ struct rcar_gpio_priv *priv = dev_get_priv(dev);
+ struct udevice *pctldev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev);
+ if (ret)
+ return ret;
+
+ return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset);
+}
+
static const struct dm_gpio_ops rcar_gpio_ops = {
+ .request = rcar_gpio_request,
.direction_input = rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
+ priv->pfc_offset = ret == 0 ? args.args[1] : -1;
uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
ret = clk_get_by_index(dev, 0, &clk);
static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a7795" },
{ .compatible = "renesas,gpio-r8a7796" },
+ { .compatible = "renesas,gpio-r8a77970" },
+ { .compatible = "renesas,gpio-r8a77995" },
+ { .compatible = "renesas,rcar-gen3-gpio" },
{ /* sentinel */ }
};
#include <linux/errno.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
-
-#define UNIPHIER_GPIO_LINES_PER_BANK 8
+#include <dt-bindings/gpio/uniphier-gpio.h>
#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
--- /dev/null
+/*
+ * Synopsys HSDK SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/printk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HSDK_CREG_MAX_GPIO 8
+
+#define GPIO_ACTIVATE 0x2
+#define GPIO_DEACTIVATE 0x3
+#define GPIO_PIN_MASK 0x3
+#define BIT_PER_GPIO 2
+
+struct hsdk_creg_gpio {
+ uint32_t *regs;
+};
+
+static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
+{
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ uint32_t reg = readl(hcg->regs);
+ uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+
+ reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
+ reg |= (cmd << (oft * BIT_PER_GPIO));
+
+ writel(reg, hcg->regs);
+
+ return 0;
+}
+
+static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
+ int val)
+{
+ hsdk_creg_gpio_set_value(dev, oft, val);
+
+ return 0;
+}
+
+static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+ pr_err("hsdk-creg-gpio can't be used as input!\n");
+
+ return -ENOTSUPP;
+}
+
+static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
+{
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ uint32_t val = readl(hcg->regs);
+
+ val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
+ return (val == GPIO_DEACTIVATE) ? 1 : 0;
+}
+
+static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
+ .direction_output = hsdk_creg_gpio_direction_output,
+ .direction_input = hsdk_creg_gpio_direction_input,
+ .set_value = hsdk_creg_gpio_set_value,
+ .get_value = hsdk_creg_gpio_get_value,
+};
+
+static int hsdk_creg_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+
+ hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
+
+ uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
+ if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
+ uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+ if (!uc_priv->bank_name)
+ uc_priv->bank_name = dev_read_name(dev);
+
+ pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
+ uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
+
+ return 0;
+}
+
+static const struct udevice_id hsdk_creg_gpio_ids[] = {
+ { .compatible = "snps,hsdk-creg-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_hsdk_creg) = {
+ .name = "gpio_hsdk_creg",
+ .id = UCLASS_GPIO,
+ .ops = &hsdk_creg_gpio_ops,
+ .probe = hsdk_creg_gpio_probe,
+ .of_match = hsdk_creg_gpio_ids,
+ .platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio),
+};
*/
#include <common.h>
-#include <asm/bitops.h>
+#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#include <asm/arch/gpio.h>
bool "Amlogic Meson I2C driver"
depends on DM_I2C && ARCH_MESON
help
- Add support for the Amlogic Meson I2C driver.
+ Add support for the I2C controller available in Amlogic Meson
+ SoCs. The controller supports programmable bus speed including
+ standard (100kbits/s) and fast (400kbit/s) speed and allows the
+ software to define a flexible format of the bit streams. It has an
+ internal buffer holding up to 8 bytes for transfers and supports
+ both 7-bit and 10-bit addresses.
config SYS_I2C_MXC
bool "NXP i.MX I2C driver"
help
Add support for the OMAP2+ I2C driver.
+config SYS_I2C_RCAR_IIC
+ bool "Renesas RCar Gen3 IIC driver"
+ depends on RCAR_GEN3 && DM_I2C
+ help
+ Support for Renesas RCar Gen3 IIC controller.
+
config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
} else {
writel(msg->buf[0], ®->thr);
+ ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
+
for (i = 1; !ret && (i < msg->len); i++) {
writel(msg->buf[i], ®->thr);
ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
return 0;
}
-static int at91_i2c_probe_chip(struct udevice *dev, uint chip, uint chip_flags)
-{
- struct at91_i2c_bus *bus = dev_get_priv(dev);
- struct at91_i2c_regs *reg = bus->regs;
- int ret;
-
- ret = at91_i2c_enable_clk(dev);
- if (ret)
- return ret;
-
- writel(TWI_CR_SWRST, ®->cr);
-
- at91_calc_i2c_clock(dev, bus->clock_frequency);
-
- writel(bus->cwgr_val, ®->cwgr);
- writel(TWI_CR_MSEN, ®->cr);
- writel(TWI_CR_SVDIS, ®->cr);
-
- return 0;
-}
-
static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
struct at91_i2c_bus *bus = dev_get_priv(dev);
static const struct dm_i2c_ops at91_i2c_ops = {
.xfer = at91_i2c_xfer,
- .probe_chip = at91_i2c_probe_chip,
.set_bus_speed = at91_i2c_set_bus_speed,
.get_bus_speed = at91_i2c_get_bus_speed,
};
#include <dm.h>
#include <i2c.h>
-#define I2C_TIMEOUT_MS 500
+#define I2C_TIMEOUT_MS 100
/* Control register fields */
#define REG_CTRL_START BIT(0)
struct meson_i2c {
struct i2c_regs *regs;
- struct i2c_msg *msg;
- bool last;
- uint count;
- uint pos;
- u32 tokens[2];
- uint num_tokens;
+ struct i2c_msg *msg; /* Current I2C message */
+ bool last; /* Whether the message is the last */
+ uint count; /* Number of bytes in the current transfer */
+ uint pos; /* Position of current transfer in message */
+ u32 tokens[2]; /* Sequence of tokens to be written */
+ uint num_tokens; /* Number of tokens to be written */
};
static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
i2c->num_tokens++;
}
+/*
+ * Retrieve data for the current transfer (which can be at most 8
+ * bytes) from the device internal buffer.
+ */
static void meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len)
{
u32 rdata0, rdata1;
*buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
}
+/*
+ * Write data for the current transfer (which can be at most 8 bytes)
+ * to the device internal buffer.
+ */
static void meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len)
{
u32 wdata0 = 0, wdata1 = 0;
debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len);
}
+/*
+ * Prepare the next transfer: pick the next 8 bytes in the remaining
+ * part of message and write tokens and data (if needed) to the
+ * device.
+ */
static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
{
bool write = !(i2c->msg->flags & I2C_M_RD);
if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) {
debug("meson i2c: error\n");
- return -ENXIO;
+ return -EREMOTEIO;
}
if ((msg->flags & I2C_M_RD) && i2c->count) {
for (i = 0; i < nmsgs; i++) {
ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1);
if (ret)
- return -EREMOTEIO;
+ return ret;
}
return 0;
temp |= I2CR_MTX | I2CR_TX_NO_AK;
writeb(temp, base + (I2CR << reg_shift));
- /* write slave address */
- ret = tx_byte(i2c_bus, chip << 1);
- if (ret < 0)
- return ret;
-
- while (alen--) {
- ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
+ if (alen >= 0) {
+ /* write slave address */
+ ret = tx_byte(i2c_bus, chip << 1);
if (ret < 0)
return ret;
+
+ while (alen--) {
+ ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
+ if (ret < 0)
+ return ret;
+ }
}
+
return 0;
}
if (ret < 0)
return ret;
- temp = readb(base + (I2CR << reg_shift));
- temp |= I2CR_RSTA;
- writeb(temp, base + (I2CR << reg_shift));
+ if (alen >= 0) {
+ temp = readb(base + (I2CR << reg_shift));
+ temp |= I2CR_RSTA;
+ writeb(temp, base + (I2CR << reg_shift));
+ }
ret = tx_byte(i2c_bus, (chip << 1) | 1);
if (ret < 0) {
--- /dev/null
+/*
+ * Renesas RCar IIC driver
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2011, 2013 Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+struct rcar_iic_priv {
+ void __iomem *base;
+ struct clk clk;
+ u8 iccl;
+ u8 icch;
+};
+
+#define RCAR_IIC_ICDR 0x00
+#define RCAR_IIC_ICCR 0x04
+#define RCAR_IIC_ICSR 0x08
+#define RCAR_IIC_ICIC 0x0c
+#define RCAR_IIC_ICCL 0x10
+#define RCAR_IIC_ICCH 0x14
+
+/* ICCR */
+#define RCAR_IIC_ICCR_ICE BIT(7)
+#define RCAR_IIC_ICCR_RACK BIT(6)
+#define RCAR_IIC_ICCR_RTS BIT(4)
+#define RCAR_IIC_ICCR_BUSY BIT(2)
+#define RCAR_IIC_ICCR_SCP BIT(0)
+
+/* ICSR / ICIC */
+#define RCAR_IC_BUSY BIT(4)
+#define RCAR_IC_TACK BIT(2)
+#define RCAR_IC_DTE BIT(0)
+
+#define IRQ_WAIT 1000
+
+static void sh_irq_dte(struct udevice *dev)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
+ break;
+ udelay(10);
+ }
+}
+
+static int sh_irq_dte_with_tack(struct udevice *dev)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
+ break;
+ if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR))
+ return -ETIMEDOUT;
+ udelay(10);
+ }
+ return 0;
+}
+
+static void sh_irq_busy(struct udevice *dev)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < IRQ_WAIT; i++) {
+ if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR)))
+ break;
+ udelay(10);
+ }
+}
+
+static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+
+ clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
+ setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
+
+ writeb(priv->iccl, priv->base + RCAR_IIC_ICCL);
+ writeb(priv->icch, priv->base + RCAR_IIC_ICCH);
+ writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC);
+
+ writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY,
+ priv->base + RCAR_IIC_ICCR);
+ sh_irq_dte(dev);
+
+ clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK);
+ writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR);
+ return sh_irq_dte_with_tack(dev);
+}
+
+static void rcar_iic_finish(struct udevice *dev)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+
+ writeb(0, priv->base + RCAR_IIC_ICSR);
+ clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
+}
+
+static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int i, ret = -EREMOTEIO;
+
+ if (rcar_iic_set_addr(dev, msg->addr, 1) != 0)
+ goto err;
+
+ udelay(10);
+
+ writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
+ priv->base + RCAR_IIC_ICCR);
+
+ for (i = 0; i < msg->len; i++) {
+ if (sh_irq_dte_with_tack(dev) != 0)
+ goto err;
+
+ msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff;
+
+ if (msg->len - 1 == i) {
+ writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK,
+ priv->base + RCAR_IIC_ICCR);
+ }
+ }
+
+ sh_irq_busy(dev);
+ ret = 0;
+
+err:
+ rcar_iic_finish(dev);
+ return ret;
+}
+
+static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int i, ret = -EREMOTEIO;
+
+ if (rcar_iic_set_addr(dev, msg->addr, 0) != 0)
+ goto err;
+
+ udelay(10);
+
+ for (i = 0; i < msg->len; i++) {
+ writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR);
+ if (sh_irq_dte_with_tack(dev) != 0)
+ goto err;
+ }
+
+ if (msg->flags & I2C_M_STOP) {
+ writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS,
+ priv->base + RCAR_IIC_ICCR);
+ if (sh_irq_dte_with_tack(dev) != 0)
+ goto err;
+ }
+
+ sh_irq_busy(dev);
+ ret = 0;
+
+err:
+ rcar_iic_finish(dev);
+ return ret;
+}
+
+static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
+{
+ int ret;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD)
+ ret = rcar_iic_read_common(dev, msg);
+ else
+ ret = rcar_iic_write_common(dev, msg);
+
+ if (ret)
+ return -EREMOTEIO;
+ }
+
+ return ret;
+}
+
+static int rcar_iic_set_speed(struct udevice *dev, uint speed)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ const unsigned int ratio_high = 4;
+ const unsigned int ratio_low = 5;
+ int clkrate, denom;
+
+ clkrate = clk_get_rate(&priv->clk);
+ if (clkrate < 0)
+ return clkrate;
+
+ /*
+ * Calculate the value for ICCL and ICCH. From the data sheet:
+ * iccl = (p-clock / transfer-rate) * (L / (L + H))
+ * icch = (p clock / transfer rate) * (H / (L + H))
+ * where L and H are the SCL low and high ratio.
+ */
+ denom = speed * (ratio_high + ratio_low);
+ priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom);
+ priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom);
+
+ return 0;
+}
+
+static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ rcar_iic_set_addr(dev, addr, 1);
+ writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
+ priv->base + RCAR_IIC_ICCR);
+ ret = sh_irq_dte_with_tack(dev);
+ rcar_iic_finish(dev);
+
+ return ret;
+}
+
+static int rcar_iic_probe(struct udevice *dev)
+{
+ struct rcar_iic_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+
+ rcar_iic_finish(dev);
+
+ return rcar_iic_set_speed(dev, 100000);
+}
+
+static const struct dm_i2c_ops rcar_iic_ops = {
+ .xfer = rcar_iic_xfer,
+ .probe_chip = rcar_iic_probe_chip,
+ .set_bus_speed = rcar_iic_set_speed,
+};
+
+static const struct udevice_id rcar_iic_ids[] = {
+ { .compatible = "renesas,rmobile-iic" },
+ { }
+};
+
+U_BOOT_DRIVER(iic_rcar) = {
+ .name = "iic_rcar",
+ .id = UCLASS_I2C,
+ .of_match = rcar_iic_ids,
+ .probe = rcar_iic_probe,
+ .priv_auto_alloc_size = sizeof(struct rcar_iic_priv),
+ .ops = &rcar_iic_ops,
+};
#include <common.h>
#include <dm.h>
#include <misc.h>
+#include <stm32_rcc.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
+struct stm32_rcc_clk stm32_rcc_clk_f4 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F4,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_f7 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F7,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_h7 = {
+ .drv_name = "stm32h7_rcc_clock",
+};
+
static int stm32_rcc_bind(struct udevice *dev)
{
- int ret;
struct udevice *child;
+ struct driver *drv;
+ struct stm32_rcc_clk *rcc_clk =
+ (struct stm32_rcc_clk *)dev_get_driver_data(dev);
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
- ret = device_bind_driver_to_node(dev, "stm32h7_rcc_clock",
- "stm32h7_rcc_clock",
- dev_ofnode(dev), &child);
+ drv = lists_driver_lookup_name(rcc_clk->drv_name);
+ if (!drv) {
+ debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
+ rcc_clk->soc,
+ dev_ofnode(dev), &child);
+
if (ret)
return ret;
+#ifdef CONFIG_SPL_BUILD
+ return 0;
+#else
return device_bind_driver_to_node(dev, "stm32_rcc_reset",
"stm32_rcc_reset",
dev_ofnode(dev), &child);
+#endif
}
static const struct misc_ops stm32_rcc_ops = {
};
static const struct udevice_id stm32_rcc_ids[] = {
- {.compatible = "st,stm32h743-rcc"},
+ {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 },
+ {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
+ {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{ }
};
If you have a board based on such a SoC and with a SD/MMC slot,
say Y or M here.
+config MMC_NDS32
+ bool "Andestech SD/MMC controller support"
+ depends on DM_MMC && OF_CONTROL && BLK && FTSDC010
+ help
+ This enables support for the Andestech SD/MMM controller, which is
+ based on Faraday IP.
+
+config FTSDC010
+ bool "Ftsdc010 SD/MMC controller Support"
+ help
+ This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP.
+
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
#include <asm/arch/clk.h>
#define ATMEL_SDHC_MIN_FREQ 400000
+#define ATMEL_SDHC_GCK_RATE 240000000
#ifndef CONFIG_DM_MMC
int atmel_sdhci_init(void *regbase, u32 id)
struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
u32 max_clk;
- u32 caps, caps_1;
- u32 clk_base, clk_mul;
- ulong gck_rate;
struct clk clk;
int ret;
host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
- caps = sdhci_readl(host, SDHCI_CAPABILITIES);
- clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
- gck_rate = clk_base * 1000000 * (clk_mul + 1);
-
ret = clk_get_by_index(dev, 1, &clk);
if (ret)
return ret;
- ret = clk_set_rate(&clk, gck_rate);
+ ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
if (ret)
return ret;
#include <part.h>
#include <mmc.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <faraday/ftsdc010.h>
+#include "ftsdc010_mci.h"
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
-struct ftsdc010_chip {
- void __iomem *regs;
- uint32_t wprot; /* write protected (locked) */
- uint32_t rate; /* actual SD clock in Hz */
- uint32_t sclk; /* FTSDC010 source clock in Hz */
- uint32_t fifo; /* fifo depth in bytes */
- uint32_t acmd;
- struct mmc_config cfg; /* mmc configuration */
-};
-
static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
struct ftsdc010_chip *chip = mmc->priv;
static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
{
int ret = -ETIMEDOUT;
- uint32_t st, ts;
-
- for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ uint32_t st, timeout = 10000000;
+ while (timeout--) {
st = readl(®s->status);
if (!(st & mask))
continue;
break;
}
- if (ret)
+ if (ret){
debug("ftsdc010: wait st(0x%x) timeout\n", mask);
+ }
return ret;
}
/*
* u-boot mmc api
*/
-
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+#endif
int ret = -EOPNOTSUPP;
uint32_t len = 0;
struct ftsdc010_chip *chip = mmc->priv;
if (!ret) {
ret = ftsdc010_wait(regs,
- FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
+ FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
}
return ret;
}
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_set_ios(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int ftsdc010_set_ios(struct mmc *mmc)
{
+#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
return 0;
}
-static int ftsdc010_init(struct mmc *mmc)
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_get_cd(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int ftsdc010_get_cd(struct mmc *mmc)
{
+#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
- uint32_t ts;
-
- if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT)
- return -ENOMEDIUM;
+ return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT);
+}
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_get_wp(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int ftsdc010_get_wp(struct mmc *mmc)
+{
+#endif
+ struct ftsdc010_chip *chip = mmc->priv;
+ struct ftsdc010_mmc __iomem *regs = chip->regs;
if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
printf("ftsdc010: write protected\n");
chip->wprot = 1;
}
+ return 0;
+}
+
+static int ftsdc010_init(struct mmc *mmc)
+{
+ struct ftsdc010_chip *chip = mmc->priv;
+ struct ftsdc010_mmc __iomem *regs = chip->regs;
+ uint32_t ts;
+
chip->fifo = (readl(®s->feature) & 0xff) << 2;
/* 1. chip reset */
return 0;
}
+#ifdef CONFIG_DM_MMC
+int ftsdc010_probe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ return ftsdc010_init(mmc);
+}
+
+const struct dm_mmc_ops dm_ftsdc010_ops = {
+ .send_cmd = ftsdc010_request,
+ .set_ios = ftsdc010_set_ios,
+ .get_cd = ftsdc010_get_cd,
+ .get_wp = ftsdc010_get_wp,
+};
+
+#else
static const struct mmc_ops ftsdc010_ops = {
.send_cmd = ftsdc010_request,
.set_ios = ftsdc010_set_ios,
+ .getcd = ftsdc010_get_cd,
+ .getwp = ftsdc010_get_wp,
.init = ftsdc010_init,
};
+#endif
+
+void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk)
+{
+ cfg->name = name;
+ cfg->f_min = min_clk;
+ cfg->f_max = max_clk;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->host_caps = caps;
+ if (buswidth == 8) {
+ cfg->host_caps |= MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
+ } else {
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+ }
+ cfg->part_type = PART_TYPE_DOS;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
+
+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg)
+{
+ switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
+ case FTSDC010_BWR_CAPS_4BIT:
+ cfg->host_caps |= MMC_MODE_4BIT;
+ break;
+ case FTSDC010_BWR_CAPS_8BIT:
+ cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef CONFIG_BLK
+int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
int ftsdc010_mmc_init(int devid)
{
#endif
chip->cfg.name = "ftsdc010";
+#ifndef CONFIG_DM_MMC
chip->cfg.ops = &ftsdc010_ops;
+#endif
chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
- switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
- case FTSDC010_BWR_CAPS_4BIT:
- chip->cfg.host_caps |= MMC_MODE_4BIT;
- break;
- case FTSDC010_BWR_CAPS_8BIT:
- chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
- break;
- default:
- break;
- }
-
+ set_bus_width(regs , &chip->cfg);
chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
chip->cfg.f_max = chip->sclk / 2;
chip->cfg.f_min = chip->sclk / 0x100;
return 0;
}
+#endif
--- /dev/null
+/*
+ * Faraday FTSDC010 Secure Digital Memory Card Host Controller
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <mmc.h>
+
+#ifndef __FTSDC010_MCI_H
+#define __FTSDC010_MCI_H
+
+struct ftsdc010_chip {
+ void __iomem *regs;
+ uint32_t wprot; /* write protected (locked) */
+ uint32_t rate; /* actual SD clock in Hz */
+ uint32_t sclk; /* FTSDC010 source clock in Hz */
+ uint32_t fifo; /* fifo depth in bytes */
+ uint32_t acmd;
+ struct mmc_config cfg; /* mmc configuration */
+ const char *name;
+ void *ioaddr;
+ unsigned int caps;
+ unsigned int version;
+ unsigned int clock;
+ unsigned int bus_hz;
+ unsigned int div;
+ int dev_index;
+ int dev_id;
+ int buswidth;
+ u32 fifoth_val;
+ struct mmc *mmc;
+ void *priv;
+ bool fifo_mode;
+};
+
+
+#ifdef CONFIG_DM_MMC
+/* Export the operations to drivers */
+int ftsdc010_probe(struct udevice *dev);
+extern const struct dm_mmc_ops dm_ftsdc010_ops;
+#endif
+void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk);
+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg);
+
+#ifdef CONFIG_BLK
+int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+#endif
+
+
+#endif /* __FTSDC010_MCI_H */
--- /dev/null
+/*
+ * Andestech ATFSDC010 SD/MMC driver
+ *
+ * (C) Copyright 2017
+ * Rick Chen, NDS32 Software Engineering, rick@andestech.com
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <mmc.h>
+#include <pwrseq.h>
+#include <syscon.h>
+#include <linux/err.h>
+#include <faraday/ftsdc010.h>
+#include "ftsdc010_mci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct nds_mmc {
+ fdt32_t bus_width;
+ bool cap_mmc_highspeed;
+ bool cap_sd_highspeed;
+ fdt32_t clock_freq_min_max[2];
+ struct phandle_2_cell clocks[4];
+ fdt32_t fifo_depth;
+ fdt32_t reg[2];
+};
+#endif
+
+struct nds_mmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct nds_mmc dtplat;
+#endif
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct ftsdc_priv {
+ struct clk clk;
+ struct ftsdc010_chip chip;
+ int fifo_depth;
+ bool fifo_mode;
+ u32 minmax[2];
+};
+
+static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ chip->name = dev->name;
+ chip->ioaddr = (void *)devfdt_get_addr(dev);
+ chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-depth", 0);
+ priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-mode");
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
+ "clock-freq-min-max", priv->minmax, 2)) {
+ int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-frequency", -EINVAL);
+ if (val < 0)
+ return val;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ priv->minmax[1] = val;
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+ }
+#endif
+ chip->sclk = priv->minmax[1];
+ chip->regs = chip->ioaddr;
+ return 0;
+}
+
+static int nds32_mmc_probe(struct udevice *dev)
+{
+ struct nds_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ struct udevice *pwr_dev __maybe_unused;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ int ret;
+ struct nds_mmc *dtplat = &plat->dtplat;
+ chip->name = dev->name;
+ chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ chip->buswidth = dtplat->bus_width;
+ chip->priv = dev;
+ chip->dev_index = 1;
+ memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+ ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+ if (ret < 0)
+ return ret;
+#endif
+ ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
+ priv->minmax[1] , priv->minmax[0]);
+ chip->mmc = &plat->mmc;
+ chip->mmc->priv = &priv->chip;
+ chip->mmc->dev = dev;
+ upriv->mmc = chip->mmc;
+ return ftsdc010_probe(dev);
+}
+
+static int nds32_mmc_bind(struct udevice *dev)
+{
+ struct nds_mmc_plat *plat = dev_get_platdata(dev);
+ return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id nds32_mmc_ids[] = {
+ { .compatible = "andestech,atsdc010" },
+ { }
+};
+
+U_BOOT_DRIVER(nds32_mmc_drv) = {
+ .name = "nds32_mmc",
+ .id = UCLASS_MMC,
+ .of_match = nds32_mmc_ids,
+ .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
+ .ops = &dm_ftsdc010_ops,
+ .bind = nds32_mmc_bind,
+ .probe = nds32_mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
+ .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
+};
static const struct udevice_id uniphier_sd_match[] = {
{ .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
+ { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT },
+ { .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
{ /* sentinel */ }
};
{
ushort bankId = 0;
uchar manuId;
- uchar lsbits;
+ uchar feature;
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_unlock_seq(info, 0);
}
info->manufacturer_id = manuId;
- lsbits = flash_read_uchar(info, FLASH_OFFSET_LOWER_SW_BITS);
- info->sr_supported = lsbits & BIT(0);
+ debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n",
+ info->ext_addr, info->cfi_version);
+ if (info->ext_addr && info->cfi_version >= 0x3134) {
+ /* read software feature (at 0x53) */
+ feature = flash_read_uchar(info, info->ext_addr + 0x13);
+ debug("feature = 0x%x\n", feature);
+ info->sr_supported = feature & 0x1;
+ }
switch (info->chipwidth){
case FLASH_CFI_8BIT:
}
EXPORT_SYMBOL_GPL(mtd_read_oob);
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!mtd || section < 0)
+ return -EINVAL;
+
+ if (!mtd->ooblayout || !mtd->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return mtd->ooblayout->ecc(mtd, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!mtd || section < 0)
+ return -EINVAL;
+
+ if (!mtd->ooblayout || !mtd->ooblayout->free)
+ return -ENOTSUPP;
+
+ return mtd->ooblayout->free(mtd, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_get_eccbytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
/*
* Method to access the protection register area, present in some flash
* devices. The user data is one time programmable but the factory data is read
NAND initialization process.
config NAND_DENALI
- bool "Support Denali NAND controller"
+ bool
select SYS_NAND_SELF_INIT
imply CMD_NAND
- help
- Enable support for the Denali NAND controller.
config NAND_DENALI_DT
bool "Support Denali NAND controller as a DT device"
- depends on NAND_DENALI && OF_CONTROL && DM
+ select NAND_DENALI
+ depends on OF_CONTROL && DM
help
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
-config SYS_NAND_DENALI_64BIT
- bool "Use 64-bit variant of Denali NAND controller"
- depends on NAND_DENALI
- help
- The Denali NAND controller IP has some variations in terms of
- the bus interface. The DMA setup sequence is completely differenct
- between 32bit / 64bit AXI bus variants.
-
- If your Denali NAND controller is the 64-bit variant, say Y.
- Otherwise (32 bit), say N.
-
config NAND_DENALI_SPARE_AREA_SKIP_BYTES
int "Number of bytes skipped in OOB area"
depends on NAND_DENALI
This enables Nand driver support for Nand flash controller
found on Zynq SoC.
+config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+ bool "Enable use of 1st stage bootloader timing for NAND"
+ depends on NAND_ZYNQ
+ help
+ This flag prevent U-boot reconfigure NAND flash controller and reuse
+ the NAND timing from 1st stage bootloader.
+
comment "Generic NAND options"
# Enhance depends when converting drivers to Kconfig which use this config
#include <asm/io.h>
#include <linux/errno.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand_ecc.h>
#include <asm/arch/hardware.h>
* @buf: the data to write
* @oob_required: must write chip->oob_poi to OOB
* @page: page number to write
- * @cached: cached programming
* @raw: use _raw version of write_page
*/
static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, int data_len,
const uint8_t *buf, int oob_required,
- int page, int cached, int raw)
+ int page, int raw)
{
int status;
int ret = 0;
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
status = chip->waitfunc(mtd, chip);
- /*
- * See if operation failed and additional status checks are
- * available.
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_WRITING, status, page);
-
if (status & NAND_STATUS_FAIL) {
ret = -EIO;
goto err;
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <nand.h>
+#include <linux/bitfield.h>
+#include <linux/dma-direction.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
#include "denali.h"
-#define NAND_DEFAULT_TIMINGS -1
-
-static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
-
-/*
- * We define a macro here that combines all interrupts this driver uses into
- * a single constant value, for convenience.
- */
-#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
- INTR_STATUS__ECC_TRANSACTION_DONE | \
- INTR_STATUS__ECC_ERR | \
- INTR_STATUS__PROGRAM_FAIL | \
- INTR_STATUS__LOAD_COMP | \
- INTR_STATUS__PROGRAM_COMP | \
- INTR_STATUS__TIME_OUT | \
- INTR_STATUS__ERASE_FAIL | \
- INTR_STATUS__RST_COMP | \
- INTR_STATUS__ERASE_COMP | \
- INTR_STATUS__ECC_UNCOR_ERR | \
- INTR_STATUS__INT_ACT | \
- INTR_STATUS__LOCKED_BLK)
+static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
+ enum dma_data_direction dir)
+{
+ unsigned long addr = (unsigned long)ptr;
-/*
- * indicates whether or not the internal value for the flash bank is
- * valid or not
- */
-#define CHIP_SELECT_INVALID -1
+ if (dir == DMA_FROM_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
+ else
+ flush_dcache_range(addr, addr + size);
-#define SUPPORT_8BITECC 1
+ return addr;
+}
-/*
- * this macro allows us to convert from an MTD structure to our own
- * device context (denali) structure.
- */
-static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
+static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
+ enum dma_data_direction dir)
{
- return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
+ if (dir != DMA_TO_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
}
-/*
- * These constants are defined by the driver to enable common driver
- * configuration options.
- */
-#define SPARE_ACCESS 0x41
-#define MAIN_ACCESS 0x42
-#define MAIN_SPARE_ACCESS 0x43
-#define PIPELINE_ACCESS 0x2000
-
-#define DENALI_UNLOCK_START 0x10
-#define DENALI_UNLOCK_END 0x11
-#define DENALI_LOCK 0x21
-#define DENALI_LOCK_TIGHT 0x31
-#define DENALI_BUFFER_LOAD 0x60
-#define DENALI_BUFFER_WRITE 0x62
-
-#define DENALI_READ 0
-#define DENALI_WRITE 0x100
-
-/* types of device accesses. We can issue commands and get status */
-#define COMMAND_CYCLE 0
-#define ADDR_CYCLE 1
-#define STATUS_CYCLE 2
-
-/*
- * this is a helper macro that allows us to
- * format the bank into the proper bits for the controller
- */
-#define BANK(x) ((x) << 24)
-
-/* Interrupts are cleared by writing a 1 to the appropriate status bit */
-static inline void clear_interrupt(struct denali_nand_info *denali,
- uint32_t irq_mask)
+static int dma_mapping_error(void *dev, dma_addr_t addr)
{
- uint32_t intr_status_reg;
-
- intr_status_reg = INTR_STATUS(denali->flash_bank);
-
- writel(irq_mask, denali->flash_reg + intr_status_reg);
+ return 0;
}
-static uint32_t read_interrupt_status(struct denali_nand_info *denali)
-{
- uint32_t intr_status_reg;
+#define DENALI_NAND_NAME "denali-nand"
- intr_status_reg = INTR_STATUS(denali->flash_bank);
+/* for Indexed Addressing */
+#define DENALI_INDEXED_CTRL 0x00
+#define DENALI_INDEXED_DATA 0x10
- return readl(denali->flash_reg + intr_status_reg);
-}
+#define DENALI_MAP00 (0 << 26) /* direct access to buffer */
+#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
+#define DENALI_MAP10 (2 << 26) /* high-level control plane */
+#define DENALI_MAP11 (3 << 26) /* direct controller access */
-static void clear_interrupts(struct denali_nand_info *denali)
-{
- uint32_t status;
+/* MAP11 access cycle type */
+#define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
+#define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
+#define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
- status = read_interrupt_status(denali);
- clear_interrupt(denali, status);
+/* MAP10 commands */
+#define DENALI_ERASE 0x01
- denali->irq_status = 0;
-}
+#define DENALI_BANK(denali) ((denali)->active_bank << 24)
-static void denali_irq_enable(struct denali_nand_info *denali,
- uint32_t int_mask)
-{
- int i;
+#define DENALI_INVALID_BANK -1
+#define DENALI_NR_BANKS 4
- for (i = 0; i < denali->max_banks; ++i)
- writel(int_mask, denali->flash_reg + INTR_EN(i));
-}
+/*
+ * The bus interface clock, clk_x, is phase aligned with the core clock. The
+ * clk_x is an integral multiple N of the core clk. The value N is configured
+ * at IP delivery time, and its available value is 4, 5, or 6. We need to align
+ * to the largest value to make it work with any possible configuration.
+ */
+#define DENALI_CLK_X_MULT 6
-static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
+static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
{
- unsigned long timeout = 1000000;
- uint32_t intr_status;
-
- do {
- intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
- if (intr_status & irq_mask) {
- denali->irq_status &= ~irq_mask;
- /* our interrupt was detected */
- break;
- }
- udelay(1);
- timeout--;
- } while (timeout != 0);
-
- if (timeout == 0) {
- /* timeout */
- printf("Denali timeout with interrupt status %08x\n",
- read_interrupt_status(denali));
- intr_status = 0;
- }
- return intr_status;
+ return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
}
/*
- * Certain operations for the denali NAND controller use an indexed mode to
- * read/write data. The operation is performed by writing the address value
- * of the command to the device memory followed by the data. This function
- * abstracts this common operation.
+ * Direct Addressing - the slave address forms the control information (command
+ * type, bank, block, and page address). The slave data is the actual data to
+ * be transferred. This mode requires 28 bits of address region allocated.
*/
-static void index_addr(struct denali_nand_info *denali,
- uint32_t address, uint32_t data)
+static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
{
- writel(address, denali->flash_mem + INDEX_CTRL_REG);
- writel(data, denali->flash_mem + INDEX_DATA_REG);
+ return ioread32(denali->host + addr);
}
-/* Perform an indexed read of the device */
-static void index_addr_read_data(struct denali_nand_info *denali,
- uint32_t address, uint32_t *pdata)
+static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
+ u32 data)
{
- writel(address, denali->flash_mem + INDEX_CTRL_REG);
- *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
+ iowrite32(data, denali->host + addr);
}
/*
- * We need to buffer some data for some of the NAND core routines.
- * The operations manage buffering that data.
+ * Indexed Addressing - address translation module intervenes in passing the
+ * control information. This mode reduces the required address range. The
+ * control information and transferred data are latched by the registers in
+ * the translation module.
*/
-static void reset_buf(struct denali_nand_info *denali)
+static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
{
- denali->buf.head = 0;
- denali->buf.tail = 0;
+ iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
+ return ioread32(denali->host + DENALI_INDEXED_DATA);
}
-static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
+static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
+ u32 data)
{
- denali->buf.buf[denali->buf.tail++] = byte;
+ iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
+ iowrite32(data, denali->host + DENALI_INDEXED_DATA);
}
-/* resets a specific device connected to the core */
-static void reset_bank(struct denali_nand_info *denali)
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void denali_detect_max_banks(struct denali_nand_info *denali)
{
- uint32_t irq_status;
- uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
-
- clear_interrupts(denali);
+ uint32_t features = ioread32(denali->reg + FEATURES);
- writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
+ denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
- irq_status = wait_for_irq(denali, irq_mask);
- if (irq_status & INTR_STATUS__TIME_OUT)
- debug("reset bank failed.\n");
+ /* the encoding changed from rev 5.0 to 5.1 */
+ if (denali->revision < 0x0501)
+ denali->max_banks <<= 1;
}
-/* Reset the flash controller */
-static uint32_t denali_nand_reset(struct denali_nand_info *denali)
+static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
{
int i;
- for (i = 0; i < denali->max_banks; i++)
- writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
- denali->flash_reg + INTR_STATUS(i));
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ iowrite32(U32_MAX, denali->reg + INTR_EN(i));
+ iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
+}
- for (i = 0; i < denali->max_banks; i++) {
- writel(1 << i, denali->flash_reg + DEVICE_RESET);
- while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
- (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
- if (readl(denali->flash_reg + INTR_STATUS(i)) &
- INTR_STATUS__TIME_OUT)
- debug("NAND Reset operation timed out on bank"
- " %d\n", i);
- }
+static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
+{
+ int i;
- for (i = 0; i < denali->max_banks; i++)
- writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
- denali->flash_reg + INTR_STATUS(i));
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ iowrite32(0, denali->reg + INTR_EN(i));
+ iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
+}
- return 0;
+static void denali_clear_irq(struct denali_nand_info *denali,
+ int bank, uint32_t irq_status)
+{
+ /* write one to clear bits */
+ iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
}
-/*
- * this routine calculates the ONFI timing values for a given mode and
- * programs the clocking register accordingly. The mode is determined by
- * the get_onfi_nand_para routine.
- */
-static void nand_onfi_timing_set(struct denali_nand_info *denali,
- uint16_t mode)
+static void denali_clear_irq_all(struct denali_nand_info *denali)
{
- uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
- uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
- uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
- uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
- uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
- uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
- uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
- uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
- uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
- uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
- uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
- uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
-
- uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
- uint32_t dv_window = 0;
- uint32_t en_lo, en_hi;
- uint32_t acc_clks;
- uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
-
- en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
- en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
- if ((en_hi * CLK_X) < (treh[mode] + 2))
- en_hi++;
-
- if ((en_lo + en_hi) * CLK_X < trc[mode])
- en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
- CLK_X);
-
- if ((en_lo + en_hi) < CLK_MULTI)
- en_lo += CLK_MULTI - en_lo - en_hi;
-
- while (dv_window < 8) {
- data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
-
- data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
-
- data_invalid = data_invalid_rhoh < data_invalid_rloh ?
- data_invalid_rhoh : data_invalid_rloh;
-
- dv_window = data_invalid - trea[mode];
-
- if (dv_window < 8)
- en_lo++;
- }
+ int i;
- acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ denali_clear_irq(denali, i, U32_MAX);
+}
- while (acc_clks * CLK_X - trea[mode] < 3)
- acc_clks++;
+static void __denali_check_irq(struct denali_nand_info *denali)
+{
+ uint32_t irq_status;
+ int i;
- if (data_invalid - acc_clks * CLK_X < 2)
- debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
+ for (i = 0; i < DENALI_NR_BANKS; i++) {
+ irq_status = ioread32(denali->reg + INTR_STATUS(i));
+ denali_clear_irq(denali, i, irq_status);
- addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
- re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
- re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
- we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
- cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
- if (cs_cnt == 0)
- cs_cnt = 1;
+ if (i != denali->active_bank)
+ continue;
- if (tcea[mode]) {
- while (cs_cnt * CLK_X + trea[mode] < tcea[mode])
- cs_cnt++;
+ denali->irq_status |= irq_status;
}
+}
- /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
- if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 &&
- readl(denali->flash_reg + DEVICE_ID) == 0x88)
- acc_clks = 6;
-
- writel(acc_clks, denali->flash_reg + ACC_CLKS);
- writel(re_2_we, denali->flash_reg + RE_2_WE);
- writel(re_2_re, denali->flash_reg + RE_2_RE);
- writel(we_2_re, denali->flash_reg + WE_2_RE);
- writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
- writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
- writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
- writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
+static void denali_reset_irq(struct denali_nand_info *denali)
+{
+ denali->irq_status = 0;
+ denali->irq_mask = 0;
}
-/* queries the NAND device to see what ONFI modes it supports. */
-static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
+static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
+ uint32_t irq_mask)
{
- int i;
+ unsigned long time_left = 1000000;
- /*
- * we needn't to do a reset here because driver has already
- * reset all the banks before
- */
- if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
- ONFI_TIMING_MODE__VALUE))
- return -EIO;
+ while (time_left) {
+ __denali_check_irq(denali);
- for (i = 5; i > 0; i--) {
- if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
- (0x01 << i))
- break;
+ if (irq_mask & denali->irq_status)
+ return denali->irq_status;
+ udelay(1);
+ time_left--;
}
- nand_onfi_timing_set(denali, i);
-
- /*
- * By now, all the ONFI devices we know support the page cache
- * rw feature. So here we enable the pipeline_rw_ahead feature
- */
+ if (!time_left) {
+ dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
+ irq_mask);
+ return 0;
+ }
- return 0;
+ return denali->irq_status;
}
-static void get_samsung_nand_para(struct denali_nand_info *denali,
- uint8_t device_id)
+static uint32_t denali_check_irq(struct denali_nand_info *denali)
{
- if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
- /* Set timing register values according to datasheet */
- writel(5, denali->flash_reg + ACC_CLKS);
- writel(20, denali->flash_reg + RE_2_WE);
- writel(12, denali->flash_reg + WE_2_RE);
- writel(14, denali->flash_reg + ADDR_2_DATA);
- writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
- writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
- writel(2, denali->flash_reg + CS_SETUP_CNT);
- }
+ __denali_check_irq(denali);
+
+ return denali->irq_status;
}
-static void get_toshiba_nand_para(struct denali_nand_info *denali)
+static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
- uint32_t tmp;
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ int i;
- /*
- * Workaround to fix a controller bug which reports a wrong
- * spare area size for some kind of Toshiba NAND device
- */
- if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
- (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
- writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
- readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
- }
+ for (i = 0; i < len; i++)
+ buf[i] = denali->host_read(denali, addr);
}
-static void get_hynix_nand_para(struct denali_nand_info *denali,
- uint8_t device_id)
+static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
- uint32_t main_size, spare_size;
-
- switch (device_id) {
- case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
- case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
- writel(128, denali->flash_reg + PAGES_PER_BLOCK);
- writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
- writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- main_size = 4096 *
- readl(denali->flash_reg + DEVICES_CONNECTED);
- spare_size = 224 *
- readl(denali->flash_reg + DEVICES_CONNECTED);
- writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
- writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
- writel(0, denali->flash_reg + DEVICE_WIDTH);
- break;
- default:
- debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
- "Will use default parameter values instead.\n",
- device_id);
- }
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ int i;
+
+ for (i = 0; i < len; i++)
+ denali->host_write(denali, addr, buf[i]);
}
-/*
- * determines how many NAND chips are connected to the controller. Note for
- * Intel CE4100 devices we don't support more than one device.
- */
-static void find_valid_banks(struct denali_nand_info *denali)
+static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
- uint32_t id[denali->max_banks];
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ uint16_t *buf16 = (uint16_t *)buf;
int i;
- denali->total_used_banks = 1;
- for (i = 0; i < denali->max_banks; i++) {
- index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
- index_addr(denali, MODE_11 | (i << 24) | 1, 0);
- index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
+ for (i = 0; i < len / 2; i++)
+ buf16[i] = denali->host_read(denali, addr);
+}
- if (i == 0) {
- if (!(id[i] & 0x0ff))
- break;
- } else {
- if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
- denali->total_used_banks++;
- else
- break;
- }
- }
+static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ const uint16_t *buf16 = (const uint16_t *)buf;
+ int i;
+
+ for (i = 0; i < len / 2; i++)
+ denali->host_write(denali, addr, buf16[i]);
}
-/*
- * Use the configuration feature register to determine the maximum number of
- * banks that the hardware supports.
- */
-static void detect_max_banks(struct denali_nand_info *denali)
+static uint8_t denali_read_byte(struct mtd_info *mtd)
{
- uint32_t features = ioread32(denali->flash_reg + FEATURES);
+ uint8_t byte;
- denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+ denali_read_buf(mtd, &byte, 1);
- /* the encoding changed from rev 5.0 to 5.1 */
- if (denali->revision < 0x0501)
- denali->max_banks <<= 1;
+ return byte;
}
-static void detect_partition_feature(struct denali_nand_info *denali)
+static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
{
- /*
- * For MRST platform, denali->fwblks represent the
- * number of blocks firmware is taken,
- * FW is in protect partition and MTD driver has no
- * permission to access it. So let driver know how many
- * blocks it can't touch.
- */
- if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
- if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
- PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
- denali->fwblks =
- ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
- MIN_MAX_BANK__MIN_VALUE) *
- denali->blksperchip)
- +
- (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
- MIN_BLK_ADDR__VALUE);
- } else {
- denali->fwblks = SPECTRA_START_BLOCK;
- }
- } else {
- denali->fwblks = SPECTRA_START_BLOCK;
- }
+ denali_write_buf(mtd, &byte, 1);
}
-static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
+static uint16_t denali_read_word(struct mtd_info *mtd)
{
- uint32_t id_bytes[8], addr;
- uint8_t maf_id, device_id;
- int i;
+ uint16_t word;
- /*
- * Use read id method to get device ID and other params.
- * For some NAND chips, controller can't report the correct
- * device ID by reading from DEVICE_ID register
- */
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, 0x90);
- index_addr(denali, addr | 1, 0);
- for (i = 0; i < 8; i++)
- index_addr_read_data(denali, addr | 2, &id_bytes[i]);
- maf_id = id_bytes[0];
- device_id = id_bytes[1];
-
- if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
- ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
- if (get_onfi_nand_para(denali))
- return -EIO;
- } else if (maf_id == 0xEC) { /* Samsung NAND */
- get_samsung_nand_para(denali, device_id);
- } else if (maf_id == 0x98) { /* Toshiba NAND */
- get_toshiba_nand_para(denali);
- } else if (maf_id == 0xAD) { /* Hynix NAND */
- get_hynix_nand_para(denali, device_id);
- }
+ denali_read_buf16(mtd, (uint8_t *)&word, 2);
- find_valid_banks(denali);
+ return word;
+}
- detect_partition_feature(denali);
+static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t type;
+
+ if (ctrl & NAND_CLE)
+ type = DENALI_MAP11_CMD;
+ else if (ctrl & NAND_ALE)
+ type = DENALI_MAP11_ADDR;
+ else
+ return;
/*
- * If the user specified to override the default timings
- * with a specific ONFI mode, we apply those changes here.
+ * Some commands are followed by chip->dev_ready or chip->waitfunc.
+ * irq_status must be cleared here to catch the R/B# interrupt later.
*/
- if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
- nand_onfi_timing_set(denali, onfi_timing_mode);
+ if (ctrl & NAND_CTRL_CHANGE)
+ denali_reset_irq(denali);
- return 0;
+ denali->host_write(denali, DENALI_BANK(denali) | type, dat);
}
-/*
- * validation function to verify that the controlling software is making
- * a valid request
- */
-static inline bool is_flash_bank_valid(int flash_bank)
+static int denali_dev_ready(struct mtd_info *mtd)
{
- return flash_bank >= 0 && flash_bank < 4;
-}
-
-static void denali_irq_init(struct denali_nand_info *denali)
-{
- uint32_t int_mask;
- int i;
-
- /* Disable global interrupts */
- writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
-
- int_mask = DENALI_IRQ_ALL;
-
- /* Clear all status bits */
- for (i = 0; i < denali->max_banks; ++i)
- writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
- denali_irq_enable(denali, int_mask);
+ return !!(denali_check_irq(denali) & INTR__INT_ACT);
}
-/*
- * This helper function setups the registers for ECC and whether or not
- * the spare area will be transferred.
- */
-static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
- bool transfer_spare)
+static int denali_check_erased_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf,
+ unsigned long uncor_ecc_flags,
+ unsigned int max_bitflips)
{
- int ecc_en_flag, transfer_spare_flag;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ int i, ret, stat;
+
+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+ chip->ecc.total);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ecc_steps; i++) {
+ if (!(uncor_ecc_flags & BIT(i)))
+ continue;
+
+ stat = nand_check_erased_ecc_chunk(buf, ecc_size,
+ ecc_code, ecc_bytes,
+ NULL, 0,
+ chip->ecc.strength);
+ if (stat < 0) {
+ mtd->ecc_stats.failed++;
+ } else {
+ mtd->ecc_stats.corrected += stat;
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
- /* set ECC, transfer spare bits if needed */
- ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
- transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
+ buf += ecc_size;
+ ecc_code += ecc_bytes;
+ }
- /* Enable spare area/ECC per user's request. */
- writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
- /* applicable for MAP01 only */
- writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
+ return max_bitflips;
}
-/*
- * sends a pipeline command operation to the controller. See the Denali NAND
- * controller's user guide for more information (section 4.2.3.6).
- */
-static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
- bool ecc_en, bool transfer_spare,
- int access_type, int op)
+static int denali_hw_ecc_fixup(struct mtd_info *mtd,
+ struct denali_nand_info *denali,
+ unsigned long *uncor_ecc_flags)
{
- uint32_t addr, cmd, irq_status;
- static uint32_t page_count = 1;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bank = denali->active_bank;
+ uint32_t ecc_cor;
+ unsigned int max_bitflips;
- setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
+ ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
+ ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
- clear_interrupts(denali);
-
- addr = BANK(denali->flash_bank) | denali->page;
+ if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
+ /*
+ * This flag is set when uncorrectable error occurs at least in
+ * one ECC sector. We can not know "how many sectors", or
+ * "which sector(s)". We need erase-page check for all sectors.
+ */
+ *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
+ return 0;
+ }
- /* setup the acccess type */
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, access_type);
+ max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
- /* setup the pipeline command */
- index_addr(denali, cmd, 0x2000 | op | page_count);
+ /*
+ * The register holds the maximum of per-sector corrected bitflips.
+ * This is suitable for the return value of the ->read_page() callback.
+ * Unfortunately, we can not know the total number of corrected bits in
+ * the page. Increase the stats by max_bitflips. (compromised solution)
+ */
+ mtd->ecc_stats.corrected += max_bitflips;
- cmd = MODE_01 | addr;
- writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
+ return max_bitflips;
+}
- if (op == DENALI_READ) {
- /* wait for command to be accepted */
- irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
+static int denali_sw_ecc_fixup(struct mtd_info *mtd,
+ struct denali_nand_info *denali,
+ unsigned long *uncor_ecc_flags, uint8_t *buf)
+{
+ unsigned int ecc_size = denali->nand.ecc.size;
+ unsigned int bitflips = 0;
+ unsigned int max_bitflips = 0;
+ uint32_t err_addr, err_cor_info;
+ unsigned int err_byte, err_sector, err_device;
+ uint8_t err_cor_value;
+ unsigned int prev_sector = 0;
+ uint32_t irq_status;
- if (irq_status == 0)
- return -EIO;
- }
+ denali_reset_irq(denali);
- return 0;
-}
+ do {
+ err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
+ err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
+ err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
+
+ err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
+ err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
+ err_cor_info);
+ err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
+ err_cor_info);
+
+ /* reset the bitflip counter when crossing ECC sector */
+ if (err_sector != prev_sector)
+ bitflips = 0;
+
+ if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
+ /*
+ * Check later if this is a real ECC error, or
+ * an erased sector.
+ */
+ *uncor_ecc_flags |= BIT(err_sector);
+ } else if (err_byte < ecc_size) {
+ /*
+ * If err_byte is larger than ecc_size, means error
+ * happened in OOB, so we ignore it. It's no need for
+ * us to correct it err_device is represented the NAND
+ * error bits are happened in if there are more than
+ * one NAND connected.
+ */
+ int offset;
+ unsigned int flips_in_byte;
+
+ offset = (err_sector * ecc_size + err_byte) *
+ denali->devs_per_cs + err_device;
+
+ /* correct the ECC error */
+ flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
+ buf[offset] ^= err_cor_value;
+ mtd->ecc_stats.corrected += flips_in_byte;
+ bitflips += flips_in_byte;
+
+ max_bitflips = max(max_bitflips, bitflips);
+ }
-/* helper function that simply writes a buffer to the flash */
-static int write_data_to_flash_mem(struct denali_nand_info *denali,
- const uint8_t *buf, int len)
-{
- uint32_t *buf32;
- int i;
+ prev_sector = err_sector;
+ } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
/*
- * verify that the len is a multiple of 4.
- * see comment in read_data_from_flash_mem()
+ * Once handle all ECC errors, controller will trigger an
+ * ECC_TRANSACTION_DONE interrupt.
*/
- BUG_ON((len % 4) != 0);
+ irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
+ if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
+ return -EIO;
- /* write the data to the flash memory */
- buf32 = (uint32_t *)buf;
- for (i = 0; i < len / 4; i++)
- writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
- return i * 4; /* intent is to return the number of bytes read */
+ return max_bitflips;
}
-/* helper function that simply reads a buffer from the flash */
-static int read_data_from_flash_mem(struct denali_nand_info *denali,
- uint8_t *buf, int len)
+static void denali_setup_dma64(struct denali_nand_info *denali,
+ dma_addr_t dma_addr, int page, int write)
{
- uint32_t *buf32;
- int i;
+ uint32_t mode;
+ const int page_count = 1;
- /*
- * we assume that len will be a multiple of 4, if not it would be nice
- * to know about it ASAP rather than have random failures...
- * This assumption is based on the fact that this function is designed
- * to be used to read flash pages, which are typically multiples of 4.
- */
- BUG_ON((len % 4) != 0);
+ mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
- /* transfer the data from the flash */
- buf32 = (uint32_t *)buf;
- for (i = 0; i < len / 4; i++)
- *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
+ /* DMA is a three step process */
- return i * 4; /* intent is to return the number of bytes read */
-}
+ /*
+ * 1. setup transfer type, interrupt when complete,
+ * burst len = 64 bytes, the number of pages
+ */
+ denali->host_write(denali, mode,
+ 0x01002000 | (64 << 16) | (write << 8) | page_count);
-static void denali_mode_main_access(struct denali_nand_info *denali)
-{
- uint32_t addr, cmd;
+ /* 2. set memory low address */
+ denali->host_write(denali, mode, lower_32_bits(dma_addr));
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_ACCESS);
+ /* 3. set memory high address */
+ denali->host_write(denali, mode, upper_32_bits(dma_addr));
}
-static void denali_mode_main_spare_access(struct denali_nand_info *denali)
+static void denali_setup_dma32(struct denali_nand_info *denali,
+ dma_addr_t dma_addr, int page, int write)
{
- uint32_t addr, cmd;
+ uint32_t mode;
+ const int page_count = 1;
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_SPARE_ACCESS);
-}
+ mode = DENALI_MAP10 | DENALI_BANK(denali);
-/* writes OOB data to the device */
-static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_status;
- uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
- INTR_STATUS__PROGRAM_FAIL;
- int status = 0;
+ /* DMA is a four step process */
- denali->page = page;
+ /* 1. setup transfer type and # of pages */
+ denali->host_write(denali, mode | page,
+ 0x2000 | (write << 8) | page_count);
- if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
- DENALI_WRITE) == 0) {
- write_data_to_flash_mem(denali, buf, mtd->oobsize);
+ /* 2. set memory high address bits 23:8 */
+ denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
- /* wait for operation to complete */
- irq_status = wait_for_irq(denali, irq_mask);
+ /* 3. set memory low address bits 23:8 */
+ denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
- if (irq_status == 0) {
- dev_err(denali->dev, "OOB write failed\n");
- status = -EIO;
- }
- } else {
- printf("unable to send pipeline command\n");
- status = -EIO;
- }
- return status;
+ /* 4. interrupt when complete, burst len = 64 bytes */
+ denali->host_write(denali, mode | 0x14000, 0x2400);
}
-/* reads OOB data from the device */
-static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+static int denali_pio_read(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
- uint32_t irq_status, addr, cmd;
+ u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
+ uint32_t *buf32 = (uint32_t *)buf;
+ uint32_t irq_status, ecc_err_mask;
+ int i;
- denali->page = page;
+ if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
+ ecc_err_mask = INTR__ECC_UNCOR_ERR;
+ else
+ ecc_err_mask = INTR__ECC_ERR;
- if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
- DENALI_READ) == 0) {
- read_data_from_flash_mem(denali, buf, mtd->oobsize);
+ denali_reset_irq(denali);
- /*
- * wait for command to be accepted
- * can always use status0 bit as the
- * mask is identical for each bank.
- */
- irq_status = wait_for_irq(denali, irq_mask);
+ for (i = 0; i < size / 4; i++)
+ *buf32++ = denali->host_read(denali, addr);
- if (irq_status == 0)
- printf("page on OOB timeout %d\n", denali->page);
+ irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
+ if (!(irq_status & INTR__PAGE_XFER_INC))
+ return -EIO;
- /*
- * We set the device back to MAIN_ACCESS here as I observed
- * instability with the controller if you do a block erase
- * and the last transaction was a SPARE_ACCESS. Block erase
- * is reliable (according to the MTD test infrastructure)
- * if you are in MAIN_ACCESS.
- */
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_ACCESS);
- }
+ if (irq_status & INTR__ERASED_PAGE)
+ memset(buf, 0xff, size);
+
+ return irq_status & ecc_err_mask ? -EBADMSG : 0;
}
-/*
- * this function examines buffers to see if they contain data that
- * indicate that the buffer is part of an erased region of flash.
- */
-static bool is_erased(uint8_t *buf, int len)
+static int denali_pio_write(struct denali_nand_info *denali,
+ const void *buf, size_t size, int page, int raw)
{
+ u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
+ const uint32_t *buf32 = (uint32_t *)buf;
+ uint32_t irq_status;
int i;
- for (i = 0; i < len; i++)
- if (buf[i] != 0xFF)
- return false;
- return true;
+ denali_reset_irq(denali);
+
+ for (i = 0; i < size / 4; i++)
+ denali->host_write(denali, addr, *buf32++);
+
+ irq_status = denali_wait_for_irq(denali,
+ INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
+ if (!(irq_status & INTR__PROGRAM_COMP))
+ return -EIO;
+
+ return 0;
}
-/* programs the controller to either enable/disable DMA transfers */
-static void denali_enable_dma(struct denali_nand_info *denali, bool en)
+static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
- readl(denali->flash_reg + DMA_ENABLE);
+ if (write)
+ return denali_pio_write(denali, buf, size, page, raw);
+ else
+ return denali_pio_read(denali, buf, size, page, raw);
}
-/* setups the HW to perform the data DMA */
-static void denali_setup_dma(struct denali_nand_info *denali, int op)
+static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- uint32_t mode;
- const int page_count = 1;
- uint64_t addr = (unsigned long)denali->buf.dma_buf;
-
- flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
-
-/* For Denali controller that is 64 bit bus IP core */
-#ifdef CONFIG_SYS_NAND_DENALI_64BIT
- mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
-
- /* DMA is a three step process */
+ dma_addr_t dma_addr;
+ uint32_t irq_mask, irq_status, ecc_err_mask;
+ enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+ int ret = 0;
+
+ dma_addr = dma_map_single(denali->dev, buf, size, dir);
+ if (dma_mapping_error(denali->dev, dma_addr)) {
+ dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
+ return denali_pio_xfer(denali, buf, size, page, raw, write);
+ }
- /* 1. setup transfer type, interrupt when complete,
- burst len = 64 bytes, the number of pages */
- index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
+ if (write) {
+ /*
+ * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
+ * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
+ * when the page program is completed.
+ */
+ irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
+ ecc_err_mask = 0;
+ } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
+ irq_mask = INTR__DMA_CMD_COMP;
+ ecc_err_mask = INTR__ECC_UNCOR_ERR;
+ } else {
+ irq_mask = INTR__DMA_CMD_COMP;
+ ecc_err_mask = INTR__ECC_ERR;
+ }
- /* 2. set memory low address bits 31:0 */
- index_addr(denali, mode, addr);
+ iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
- /* 3. set memory high address bits 64:32 */
- index_addr(denali, mode, addr >> 32);
-#else
- mode = MODE_10 | BANK(denali->flash_bank);
+ denali_reset_irq(denali);
+ denali->setup_dma(denali, dma_addr, page, write);
- /* DMA is a four step process */
+ irq_status = denali_wait_for_irq(denali, irq_mask);
+ if (!(irq_status & INTR__DMA_CMD_COMP))
+ ret = -EIO;
+ else if (irq_status & ecc_err_mask)
+ ret = -EBADMSG;
- /* 1. setup transfer type and # of pages */
- index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
+ iowrite32(0, denali->reg + DMA_ENABLE);
- /* 2. set memory high address bits 23:8 */
- index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200);
+ dma_unmap_single(denali->dev, dma_addr, size, dir);
- /* 3. set memory low address bits 23:8 */
- index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
+ if (irq_status & INTR__ERASED_PAGE)
+ memset(buf, 0xff, size);
- /* 4. interrupt when complete, burst len = 64 bytes */
- index_addr(denali, mode | 0x14000, 0x2400);
-#endif
+ return ret;
}
-/* Common DMA function */
-static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
- uint32_t ops, bool raw_xfer,
- uint32_t irq_mask, int oob_required)
+static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- uint32_t irq_status = 0;
- /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
- setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
+ iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
+ iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
+ denali->reg + TRANSFER_SPARE_REG);
- /* clear any previous interrupt flags */
- clear_interrupts(denali);
-
- /* enable the DMA */
- denali_enable_dma(denali, true);
-
- /* setup the DMA */
- denali_setup_dma(denali, ops);
-
- /* wait for operation to complete */
- irq_status = wait_for_irq(denali, irq_mask);
-
- /* if ECC fault happen, seems we need delay before turning off DMA.
- * If not, the controller will go into non responsive condition */
- if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
- udelay(100);
-
- /* disable the DMA */
- denali_enable_dma(denali, false);
-
- return irq_status;
+ if (denali->dma_avail)
+ return denali_dma_xfer(denali, buf, size, page, raw, write);
+ else
+ return denali_pio_xfer(denali, buf, size, page, raw, write);
}
-static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, bool raw_xfer, int oob_required)
+static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int write)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
+ unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ uint8_t *bufpoi = chip->oob_poi;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int i, pos, len;
+
+ /* BBM at the beginning of the OOB area */
+ chip->cmdfunc(mtd, start_cmd, writesize, page);
+ if (write)
+ chip->write_buf(mtd, bufpoi, oob_skip);
+ else
+ chip->read_buf(mtd, bufpoi, oob_skip);
+ bufpoi += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ chip->cmdfunc(mtd, rnd_cmd, pos, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+ bufpoi += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+ bufpoi += len;
+ }
+ }
- uint32_t irq_status = 0;
- uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
-
- denali->status = 0;
-
- /* copy buffer into DMA buffer */
- memcpy(denali->buf.dma_buf, buf, mtd->writesize);
+ /* OOB free */
+ len = oobsize - (bufpoi - chip->oob_poi);
+ chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+}
- /* need extra memcpy for raw transfer */
- if (raw_xfer)
- memcpy(denali->buf.dma_buf + mtd->writesize,
- chip->oob_poi, mtd->oobsize);
+static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = denali->buf;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int ret, i, pos, len;
+
+ ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
+ if (ret)
+ return ret;
+
+ /* Arrange the buffer for syndrome payload/ecc layout */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(buf, tmp_buf + pos, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(buf, tmp_buf + writesize + oob_skip,
+ len);
+ buf += len;
+ }
+ }
+ }
- /* setting up DMA */
- irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
- irq_mask, oob_required);
+ if (oob_required) {
+ uint8_t *oob = chip->oob_poi;
+
+ /* BBM at the beginning of the OOB area */
+ memcpy(oob, tmp_buf + writesize, oob_skip);
+ oob += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(oob, tmp_buf + pos, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(oob, tmp_buf + writesize + oob_skip,
+ len);
+ oob += len;
+ }
+ }
- /* if timeout happen, error out */
- if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
- debug("DMA timeout for denali write_page\n");
- denali->status = NAND_STATUS_FAIL;
- return -EIO;
+ /* OOB free */
+ len = oobsize - (oob - chip->oob_poi);
+ memcpy(oob, tmp_buf + size - len, len);
}
- if (irq_status & INTR_STATUS__LOCKED_BLK) {
- debug("Failed as write to locked block\n");
- denali->status = NAND_STATUS_FAIL;
- return -EIO;
- }
return 0;
}
-/* NAND core entry points */
-
-/*
- * this is the callback that the NAND core calls to write a page. Since
- * writing a page with ECC or without is similar, all the work is done
- * by write_page above.
- */
-static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required, int page)
+static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
+ denali_oob_xfer(mtd, chip, page, 0);
- /*
- * for regular page writes, we let HW handle all the ECC
- * data written to the device.
- */
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
-
- return write_page(mtd, chip, buf, false, oob_required);
+ return 0;
}
-/*
- * This is the callback that the NAND core calls to write a page without ECC.
- * raw access is similar to ECC page writes, so all the work is done in the
- * write_page() function above.
- */
-static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required,
- int page)
+static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int status;
- /*
- * for raw page writes, we want to disable ECC and simply write
- * whatever data is in the buffer.
- */
+ denali_reset_irq(denali);
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
+ denali_oob_xfer(mtd, chip, page, 1);
- return write_page(mtd, chip, buf, true, oob_required);
-}
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
-static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page)
-{
- return write_oob_data(mtd, chip->oob_poi, page);
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
}
-/* raw include ECC value and all the spare area */
-static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
+static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ unsigned long uncor_ecc_flags = 0;
+ int stat = 0;
+ int ret;
- uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+ ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
+ if (ret && ret != -EBADMSG)
+ return ret;
- if (denali->page != page) {
- debug("Missing NAND_CMD_READ0 command\n");
- return -EIO;
- }
+ if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
+ stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
+ else if (ret == -EBADMSG)
+ stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
+ if (stat < 0)
+ return stat;
- /* setting up the DMA where ecc_enable is false */
- irq_status = denali_dma_configuration(denali, DENALI_READ, true,
- irq_mask, oob_required);
+ if (uncor_ecc_flags) {
+ ret = denali_read_oob(mtd, chip, page);
+ if (ret)
+ return ret;
- /* if timeout happen, error out */
- if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
- debug("DMA timeout for denali_read_page_raw\n");
- return -EIO;
+ stat = denali_check_erased_page(mtd, chip, buf,
+ uncor_ecc_flags, stat);
}
- /* splitting the content to destination buffer holder */
- memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
- mtd->oobsize);
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
-
- return 0;
+ return stat;
}
-static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
+static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = denali->buf;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int i, pos, len;
- if (denali->page != page) {
- debug("Missing NAND_CMD_READ0 command\n");
- return -EIO;
+ /*
+ * Fill the buffer with 0xff first except the full page transfer.
+ * This simplifies the logic.
+ */
+ if (!buf || !oob_required)
+ memset(tmp_buf, 0xff, size);
+
+ /* Arrange the buffer for syndrome payload/ecc layout */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, buf, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(tmp_buf + writesize + oob_skip, buf,
+ len);
+ buf += len;
+ }
+ }
}
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
-
- /* setting up the DMA where ecc_enable is true */
- irq_status = denali_dma_configuration(denali, DENALI_READ, false,
- irq_mask, oob_required);
-
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
-
- /* check whether any ECC error */
- if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
- /* is the ECC cause by erase page, check using read_page_raw */
- debug(" Uncorrected ECC detected\n");
- denali_read_page_raw(mtd, chip, buf, oob_required,
- denali->page);
-
- if (is_erased(buf, mtd->writesize) == true &&
- is_erased(chip->oob_poi, mtd->oobsize) == true) {
- debug(" ECC error cause by erased block\n");
- /* false alarm, return the 0xFF */
- } else {
- return -EBADMSG;
+ if (oob_required) {
+ const uint8_t *oob = chip->oob_poi;
+
+ /* BBM at the beginning of the OOB area */
+ memcpy(tmp_buf + writesize, oob, oob_skip);
+ oob += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, oob, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(tmp_buf + writesize + oob_skip, oob,
+ len);
+ oob += len;
+ }
}
+
+ /* OOB free */
+ len = oobsize - (oob - chip->oob_poi);
+ memcpy(tmp_buf + size - len, oob, len);
}
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
- return 0;
+
+ return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
}
-static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page)
+static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required, int page)
{
- read_oob_data(mtd, chip->oob_poi, page);
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
- return 0;
+ return denali_data_xfer(denali, (void *)buf, mtd->writesize,
+ page, 0, 1);
}
-static uint8_t denali_read_byte(struct mtd_info *mtd)
+static void denali_select_chip(struct mtd_info *mtd, int chip)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t addr, result;
- addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
- index_addr_read_data(denali, addr | 2, &result);
- return (uint8_t)result & 0xFF;
+ denali->active_bank = chip;
}
-static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t i, addr, result;
-
- /* delay for tR (data transfer from Flash array to data register) */
- udelay(25);
+ uint32_t irq_status;
- /* ensure device completed else additional delay and polling */
- wait_for_irq(denali, INTR_STATUS__INT_ACT);
+ /* R/B# pin transitioned from low to high? */
+ irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
- addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
- for (i = 0; i < len; i++) {
- index_addr_read_data(denali, (uint32_t)addr | 2, &result);
- write_byte_to_buf(denali, result);
- }
- memcpy(buf, denali->buf.buf, len);
+ return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
}
-static void denali_select_chip(struct mtd_info *mtd, int chip)
+static int denali_erase(struct mtd_info *mtd, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_status;
- denali->flash_bank = chip;
-}
+ denali_reset_irq(denali);
-static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
-{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- int status = denali->status;
+ denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
+ DENALI_ERASE);
- denali->status = 0;
+ /* wait for erase to complete or failure to occur */
+ irq_status = denali_wait_for_irq(denali,
+ INTR__ERASE_COMP | INTR__ERASE_FAIL);
- return status;
+ return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
}
-static int denali_erase(struct mtd_info *mtd, int page)
+static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ const struct nand_sdr_timings *timings;
+ unsigned long t_clk;
+ int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
+ int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
+ int addr_2_data_mask;
+ uint32_t tmp;
- uint32_t cmd, irq_status;
+ timings = nand_get_sdr_timings(conf);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
- clear_interrupts(denali);
+ /* clk_x period in picoseconds */
+ t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
+ if (!t_clk)
+ return -EINVAL;
- /* setup page read request for access type */
- cmd = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, cmd, 0x1);
+ if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
- /* wait for erase to complete or failure to occur */
- irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
- INTR_STATUS__ERASE_FAIL);
+ /* tREA -> ACC_CLKS */
+ acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
+ acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
+
+ tmp = ioread32(denali->reg + ACC_CLKS);
+ tmp &= ~ACC_CLKS__VALUE;
+ tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
+ iowrite32(tmp, denali->reg + ACC_CLKS);
- if (irq_status & INTR_STATUS__ERASE_FAIL ||
- irq_status & INTR_STATUS__LOCKED_BLK)
- return NAND_STATUS_FAIL;
+ /* tRWH -> RE_2_WE */
+ re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
+ re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
+
+ tmp = ioread32(denali->reg + RE_2_WE);
+ tmp &= ~RE_2_WE__VALUE;
+ tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
+ iowrite32(tmp, denali->reg + RE_2_WE);
+
+ /* tRHZ -> RE_2_RE */
+ re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
+ re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
+
+ tmp = ioread32(denali->reg + RE_2_RE);
+ tmp &= ~RE_2_RE__VALUE;
+ tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
+ iowrite32(tmp, denali->reg + RE_2_RE);
+
+ /*
+ * tCCS, tWHR -> WE_2_RE
+ *
+ * With WE_2_RE properly set, the Denali controller automatically takes
+ * care of the delay; the driver need not set NAND_WAIT_TCCS.
+ */
+ we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
+ t_clk);
+ we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
+
+ tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
+ tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
+ tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
+ iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
+
+ /* tADL -> ADDR_2_DATA */
+
+ /* for older versions, ADDR_2_DATA is only 6 bit wide */
+ addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
+ if (denali->revision < 0x0501)
+ addr_2_data_mask >>= 1;
+
+ addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
+ addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
+
+ tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
+ tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
+ tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
+ iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
+
+ /* tREH, tWH -> RDWR_EN_HI_CNT */
+ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
+ t_clk);
+ rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
+ tmp &= ~RDWR_EN_HI_CNT__VALUE;
+ tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
+ iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
+
+ /* tRP, tWP -> RDWR_EN_LO_CNT */
+ rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
+ t_clk);
+ rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
+ t_clk);
+ rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
+ rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
+ rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
+ tmp &= ~RDWR_EN_LO_CNT__VALUE;
+ tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
+ iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
+
+ /* tCS, tCEA -> CS_SETUP_CNT */
+ cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
+ (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
+ 0);
+ cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + CS_SETUP_CNT);
+ tmp &= ~CS_SETUP_CNT__VALUE;
+ tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
+ iowrite32(tmp, denali->reg + CS_SETUP_CNT);
return 0;
}
-static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
- int page)
+static void denali_reset_banks(struct denali_nand_info *denali)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t addr;
-
- switch (cmd) {
- case NAND_CMD_PAGEPROG:
- break;
- case NAND_CMD_STATUS:
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- break;
- case NAND_CMD_READID:
- case NAND_CMD_PARAM:
- reset_buf(denali);
- /*
- * sometimes ManufactureId read from register is not right
- * e.g. some of Micron MT29F32G08QAA MLC NAND chips
- * So here we send READID cmd to NAND insteand
- */
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- index_addr(denali, addr | 1, col & 0xFF);
- if (cmd == NAND_CMD_PARAM)
- udelay(50);
- break;
- case NAND_CMD_RNDOUT:
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- index_addr(denali, addr | 1, col & 0xFF);
- index_addr(denali, addr | 1, col >> 8);
- index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
- break;
- case NAND_CMD_READ0:
- case NAND_CMD_SEQIN:
- denali->page = page;
- break;
- case NAND_CMD_RESET:
- reset_bank(denali);
- break;
- case NAND_CMD_READOOB:
- /* TODO: Read OOB data */
- break;
- case NAND_CMD_ERASE1:
- /*
- * supporting block erase only, not multiblock erase as
- * it will cross plane and software need complex calculation
- * to identify the block count for the cross plane
- */
- denali_erase(mtd, page);
- break;
- case NAND_CMD_ERASE2:
- /* nothing to do here as it was done during NAND_CMD_ERASE1 */
- break;
- case NAND_CMD_UNLOCK1:
- addr = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, addr | 0, DENALI_UNLOCK_START);
- break;
- case NAND_CMD_UNLOCK2:
- addr = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, addr | 0, DENALI_UNLOCK_END);
- break;
- case NAND_CMD_LOCK:
- addr = MODE_10 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, DENALI_LOCK);
- break;
- default:
- printf(": unsupported command received 0x%x\n", cmd);
- break;
+ u32 irq_status;
+ int i;
+
+ for (i = 0; i < denali->max_banks; i++) {
+ denali->active_bank = i;
+
+ denali_reset_irq(denali);
+
+ iowrite32(DEVICE_RESET__BANK(i),
+ denali->reg + DEVICE_RESET);
+
+ irq_status = denali_wait_for_irq(denali,
+ INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
+ if (!(irq_status & INTR__INT_ACT))
+ break;
}
+
+ dev_dbg(denali->dev, "%d chips connected\n", i);
+ denali->max_banks = i;
}
-/* end NAND core entry points */
-/* Initialization code to bring the device up to a known good state */
static void denali_hw_init(struct denali_nand_info *denali)
{
/*
* override it.
*/
if (!denali->revision)
- denali->revision = swab16(ioread32(denali->flash_reg + REVISION));
+ denali->revision = swab16(ioread32(denali->reg + REVISION));
/*
* tell driver how many bit controller will skip before writing
* ECC code in OOB. This is normally used for bad block marker
*/
- writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
- denali->flash_reg + SPARE_AREA_SKIP_BYTES);
- detect_max_banks(denali);
- denali_nand_reset(denali);
- writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
- writel(CHIP_EN_DONT_CARE__FLAG,
- denali->flash_reg + CHIP_ENABLE_DONT_CARE);
- writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
-
- /* Should set value for these registers when init */
- writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
- writel(1, denali->flash_reg + ECC_ENABLE);
- denali_nand_timing_set(denali);
- denali_irq_init(denali);
+ denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES;
+ iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES);
+ denali_detect_max_banks(denali);
+ iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
+ iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
+
+ iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
}
-static struct nand_ecclayout nand_oob;
+int denali_calc_ecc_bytes(int step_size, int strength)
+{
+ /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
+ return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
+}
+EXPORT_SYMBOL(denali_calc_ecc_bytes);
-int denali_init(struct denali_nand_info *denali)
+static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
+ struct denali_nand_info *denali)
{
- struct mtd_info *mtd = nand_to_mtd(&denali->nand);
+ int oobavail = mtd->oobsize - denali->oob_skip_bytes;
int ret;
- denali_hw_init(denali);
-
- mtd->name = "denali-nand";
- mtd->owner = THIS_MODULE;
-
- /* register the driver with the NAND core subsystem */
- denali->nand.select_chip = denali_select_chip;
- denali->nand.cmdfunc = denali_cmdfunc;
- denali->nand.read_byte = denali_read_byte;
- denali->nand.read_buf = denali_read_buf;
- denali->nand.waitfunc = denali_waitfunc;
-
/*
- * scan for NAND devices attached to the controller
- * this is the first stage in a two step process to register
- * with the nand subsystem
+ * If .size and .strength are already set (usually by DT),
+ * check if they are supported by this controller.
*/
- if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
- ret = -ENXIO;
- goto fail;
- }
+ if (chip->ecc.size && chip->ecc.strength)
+ return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- /* check whether flash got BBT table (located at end of flash). As we
- * use NAND_BBT_NO_OOB, the BBT page will start with
- * bbt_pattern. We will have mirror pattern too */
- denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
/*
- * We are using main + spare with ECC support. As BBT need ECC support,
- * we need to ensure BBT code don't write to OOB for the BBT pattern.
- * All BBT info will be stored into data area with ECC support.
+ * We want .size and .strength closest to the chip's requirement
+ * unless NAND_ECC_MAXIMIZE is requested.
*/
- denali->nand.bbt_options |= NAND_BBT_NO_OOB;
-#endif
+ if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
+ ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
+ if (!ret)
+ return 0;
+ }
- denali->nand.ecc.mode = NAND_ECC_HW;
- denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+ /* Max ECC strength is the last thing we can do */
+ return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
+}
- /* no subpage writes on denali */
- denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
+static struct nand_ecclayout nand_oob;
+
+static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = denali->oob_skip_bytes;
+ oobregion->length = chip->ecc.total;
+
+ return 0;
+}
+
+static int denali_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
+ oobregion->length = mtd->oobsize - oobregion->offset;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
+ .ecc = denali_ooblayout_ecc,
+ .free = denali_ooblayout_free,
+};
+
+static int denali_multidev_fixup(struct denali_nand_info *denali)
+{
+ struct nand_chip *chip = &denali->nand;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ /*
+ * Support for multi device:
+ * When the IP configuration is x16 capable and two x8 chips are
+ * connected in parallel, DEVICES_CONNECTED should be set to 2.
+ * In this case, the core framework knows nothing about this fact,
+ * so we should tell it the _logical_ pagesize and anything necessary.
+ */
+ denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
/*
- * Tell driver the ecc strength. This register may be already set
- * correctly. So we read this value out.
+ * On some SoCs, DEVICES_CONNECTED is not auto-detected.
+ * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
*/
- denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
- switch (denali->nand.ecc.size) {
- case 512:
- denali->nand.ecc.bytes =
- (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
- break;
- case 1024:
- denali->nand.ecc.bytes =
- (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
- break;
- default:
- pr_err("Unsupported ECC size\n");
- ret = -EINVAL;
- goto fail;
+ if (denali->devs_per_cs == 0) {
+ denali->devs_per_cs = 1;
+ iowrite32(1, denali->reg + DEVICES_CONNECTED);
}
- nand_oob.eccbytes = denali->nand.ecc.bytes;
- denali->nand.ecc.layout = &nand_oob;
- writel(mtd->erasesize / mtd->writesize,
- denali->flash_reg + PAGES_PER_BLOCK);
- writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
- denali->flash_reg + DEVICE_WIDTH);
- writel(mtd->writesize,
- denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
- writel(mtd->oobsize,
- denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
- writel(1, denali->flash_reg + DEVICES_CONNECTED);
-
- /* override the default operations */
- denali->nand.ecc.read_page = denali_read_page;
- denali->nand.ecc.read_page_raw = denali_read_page_raw;
- denali->nand.ecc.write_page = denali_write_page;
- denali->nand.ecc.write_page_raw = denali_write_page_raw;
- denali->nand.ecc.read_oob = denali_read_oob;
- denali->nand.ecc.write_oob = denali_write_oob;
-
- if (nand_scan_tail(mtd)) {
- ret = -ENXIO;
- goto fail;
+ if (denali->devs_per_cs == 1)
+ return 0;
+
+ if (denali->devs_per_cs != 2) {
+ dev_err(denali->dev, "unsupported number of devices %d\n",
+ denali->devs_per_cs);
+ return -EINVAL;
}
- ret = nand_register(0, mtd);
+ /* 2 chips in parallel */
+ mtd->size <<= 1;
+ mtd->erasesize <<= 1;
+ mtd->writesize <<= 1;
+ mtd->oobsize <<= 1;
+ chip->chipsize <<= 1;
+ chip->page_shift += 1;
+ chip->phys_erase_shift += 1;
+ chip->bbt_erase_shift += 1;
+ chip->chip_shift += 1;
+ chip->pagemask <<= 1;
+ chip->ecc.size <<= 1;
+ chip->ecc.bytes <<= 1;
+ chip->ecc.strength <<= 1;
+ denali->oob_skip_bytes <<= 1;
-fail:
- return ret;
+ return 0;
}
-#ifndef CONFIG_NAND_DENALI_DT
-static int __board_nand_init(void)
+int denali_init(struct denali_nand_info *denali)
{
- struct denali_nand_info *denali;
+ struct nand_chip *chip = &denali->nand;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ u32 features = ioread32(denali->reg + FEATURES);
+ int ret;
- denali = kzalloc(sizeof(*denali), GFP_KERNEL);
- if (!denali)
- return -ENOMEM;
+ denali_hw_init(denali);
+
+ denali_clear_irq_all(denali);
+
+ denali_reset_banks(denali);
+
+ denali->active_bank = DENALI_INVALID_BANK;
+
+ chip->flash_node = dev_of_offset(denali->dev);
+ /* Fallback to the default name if DT did not give "label" property */
+ if (!mtd->name)
+ mtd->name = "denali-nand";
+
+ chip->select_chip = denali_select_chip;
+ chip->read_byte = denali_read_byte;
+ chip->write_byte = denali_write_byte;
+ chip->read_word = denali_read_word;
+ chip->cmd_ctrl = denali_cmd_ctrl;
+ chip->dev_ready = denali_dev_ready;
+ chip->waitfunc = denali_waitfunc;
+
+ if (features & FEATURES__INDEX_ADDR) {
+ denali->host_read = denali_indexed_read;
+ denali->host_write = denali_indexed_write;
+ } else {
+ denali->host_read = denali_direct_read;
+ denali->host_write = denali_direct_write;
+ }
+
+ /* clk rate info is needed for setup_data_interface */
+ if (denali->clk_x_rate)
+ chip->setup_data_interface = denali_setup_data_interface;
+
+ ret = nand_scan_ident(mtd, denali->max_banks, NULL);
+ if (ret)
+ return ret;
+
+ if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
+ denali->dma_avail = 1;
+
+ if (denali->dma_avail) {
+ chip->buf_align = 16;
+ if (denali->caps & DENALI_CAP_DMA_64BIT)
+ denali->setup_dma = denali_setup_dma64;
+ else
+ denali->setup_dma = denali_setup_dma32;
+ } else {
+ chip->buf_align = 4;
+ }
+
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
+ chip->bbt_options |= NAND_BBT_USE_FLASH;
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+ denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
+
+ /* no subpage writes on denali */
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+
+ ret = denali_ecc_setup(mtd, chip, denali);
+ if (ret) {
+ dev_err(denali->dev, "Failed to setup ECC settings.\n");
+ return ret;
+ }
+
+ dev_dbg(denali->dev,
+ "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+ chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+ iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
+ FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
+ denali->reg + ECC_CORRECTION);
+ iowrite32(mtd->erasesize / mtd->writesize,
+ denali->reg + PAGES_PER_BLOCK);
+ iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
+ denali->reg + DEVICE_WIDTH);
+ iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
+ denali->reg + TWO_ROW_ADDR_CYCLES);
+ iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
+ iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
+
+ iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
+ iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
+ /* chip->ecc.steps is set by nand_scan_tail(); not available here */
+ iowrite32(mtd->writesize / chip->ecc.size,
+ denali->reg + CFG_NUM_DATA_BLOCKS);
+
+ mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
+
+ nand_oob.eccbytes = denali->nand.ecc.bytes;
+ denali->nand.ecc.layout = &nand_oob;
+
+ if (chip->options & NAND_BUSWIDTH_16) {
+ chip->read_buf = denali_read_buf16;
+ chip->write_buf = denali_write_buf16;
+ } else {
+ chip->read_buf = denali_read_buf;
+ chip->write_buf = denali_write_buf;
+ }
+ chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
+ chip->ecc.read_page = denali_read_page;
+ chip->ecc.read_page_raw = denali_read_page_raw;
+ chip->ecc.write_page = denali_write_page;
+ chip->ecc.write_page_raw = denali_write_page_raw;
+ chip->ecc.read_oob = denali_read_oob;
+ chip->ecc.write_oob = denali_write_oob;
+ chip->erase = denali_erase;
+
+ ret = denali_multidev_fixup(denali);
+ if (ret)
+ return ret;
/*
- * In the future, these base addresses should be taken from
- * Device Tree or platform data.
+ * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
+ * use devm_kmalloc() because the memory allocated by devm_ does not
+ * guarantee DMA-safe alignment.
*/
- denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
+ if (!denali->buf)
+ return -ENOMEM;
- return denali_init(denali);
-}
+ ret = nand_scan_tail(mtd);
+ if (ret)
+ goto free_buf;
-void board_nand_init(void)
-{
- if (__board_nand_init() < 0)
- pr_warn("Failed to initialize Denali NAND controller.\n");
+ ret = nand_register(0, mtd);
+ if (ret) {
+ dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
+ goto free_buf;
+ }
+ return 0;
+
+free_buf:
+ kfree(denali->buf);
+
+ return ret;
}
-#endif
#ifndef __DENALI_H__
#define __DENALI_H__
-#include <linux/mtd/nand.h>
+#include <linux/bitops.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/types.h>
#define DEVICE_RESET 0x0
-#define DEVICE_RESET__BANK0 0x0001
-#define DEVICE_RESET__BANK1 0x0002
-#define DEVICE_RESET__BANK2 0x0004
-#define DEVICE_RESET__BANK3 0x0008
+#define DEVICE_RESET__BANK(bank) BIT(bank)
#define TRANSFER_SPARE_REG 0x10
-#define TRANSFER_SPARE_REG__FLAG 0x0001
+#define TRANSFER_SPARE_REG__FLAG BIT(0)
#define LOAD_WAIT_CNT 0x20
-#define LOAD_WAIT_CNT__VALUE 0xffff
+#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
#define PROGRAM_WAIT_CNT 0x30
-#define PROGRAM_WAIT_CNT__VALUE 0xffff
+#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
#define ERASE_WAIT_CNT 0x40
-#define ERASE_WAIT_CNT__VALUE 0xffff
+#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
#define INT_MON_CYCCNT 0x50
-#define INT_MON_CYCCNT__VALUE 0xffff
+#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
#define RB_PIN_ENABLED 0x60
-#define RB_PIN_ENABLED__BANK0 0x0001
-#define RB_PIN_ENABLED__BANK1 0x0002
-#define RB_PIN_ENABLED__BANK2 0x0004
-#define RB_PIN_ENABLED__BANK3 0x0008
+#define RB_PIN_ENABLED__BANK(bank) BIT(bank)
#define MULTIPLANE_OPERATION 0x70
-#define MULTIPLANE_OPERATION__FLAG 0x0001
+#define MULTIPLANE_OPERATION__FLAG BIT(0)
#define MULTIPLANE_READ_ENABLE 0x80
-#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
+#define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
#define COPYBACK_DISABLE 0x90
-#define COPYBACK_DISABLE__FLAG 0x0001
+#define COPYBACK_DISABLE__FLAG BIT(0)
#define CACHE_WRITE_ENABLE 0xa0
-#define CACHE_WRITE_ENABLE__FLAG 0x0001
+#define CACHE_WRITE_ENABLE__FLAG BIT(0)
#define CACHE_READ_ENABLE 0xb0
-#define CACHE_READ_ENABLE__FLAG 0x0001
+#define CACHE_READ_ENABLE__FLAG BIT(0)
#define PREFETCH_MODE 0xc0
-#define PREFETCH_MODE__PREFETCH_EN 0x0001
-#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
+#define PREFETCH_MODE__PREFETCH_EN BIT(0)
+#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
#define CHIP_ENABLE_DONT_CARE 0xd0
-#define CHIP_EN_DONT_CARE__FLAG 0x01
+#define CHIP_EN_DONT_CARE__FLAG BIT(0)
#define ECC_ENABLE 0xe0
-#define ECC_ENABLE__FLAG 0x0001
+#define ECC_ENABLE__FLAG BIT(0)
#define GLOBAL_INT_ENABLE 0xf0
-#define GLOBAL_INT_EN_FLAG 0x01
+#define GLOBAL_INT_EN_FLAG BIT(0)
-#define WE_2_RE 0x100
-#define WE_2_RE__VALUE 0x003f
+#define TWHR2_AND_WE_2_RE 0x100
+#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
+#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
-#define ADDR_2_DATA 0x110
-#define ADDR_2_DATA__VALUE 0x003f
+#define TCWAW_AND_ADDR_2_DATA 0x110
+/* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
+#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
+#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
#define RE_2_WE 0x120
-#define RE_2_WE__VALUE 0x003f
+#define RE_2_WE__VALUE GENMASK(5, 0)
#define ACC_CLKS 0x130
-#define ACC_CLKS__VALUE 0x000f
+#define ACC_CLKS__VALUE GENMASK(3, 0)
#define NUMBER_OF_PLANES 0x140
-#define NUMBER_OF_PLANES__VALUE 0x0007
+#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
#define PAGES_PER_BLOCK 0x150
-#define PAGES_PER_BLOCK__VALUE 0xffff
+#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
#define DEVICE_WIDTH 0x160
-#define DEVICE_WIDTH__VALUE 0x0003
+#define DEVICE_WIDTH__VALUE GENMASK(1, 0)
#define DEVICE_MAIN_AREA_SIZE 0x170
-#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
+#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
#define DEVICE_SPARE_AREA_SIZE 0x180
-#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
+#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
#define TWO_ROW_ADDR_CYCLES 0x190
-#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
+#define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
#define MULTIPLANE_ADDR_RESTRICT 0x1a0
-#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
+#define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
#define ECC_CORRECTION 0x1b0
-#define ECC_CORRECTION__VALUE 0x001f
+#define ECC_CORRECTION__VALUE GENMASK(4, 0)
+#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
#define READ_MODE 0x1c0
-#define READ_MODE__VALUE 0x000f
+#define READ_MODE__VALUE GENMASK(3, 0)
#define WRITE_MODE 0x1d0
-#define WRITE_MODE__VALUE 0x000f
+#define WRITE_MODE__VALUE GENMASK(3, 0)
#define COPYBACK_MODE 0x1e0
-#define COPYBACK_MODE__VALUE 0x000f
+#define COPYBACK_MODE__VALUE GENMASK(3, 0)
#define RDWR_EN_LO_CNT 0x1f0
-#define RDWR_EN_LO_CNT__VALUE 0x001f
+#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
#define RDWR_EN_HI_CNT 0x200
-#define RDWR_EN_HI_CNT__VALUE 0x001f
+#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
#define MAX_RD_DELAY 0x210
-#define MAX_RD_DELAY__VALUE 0x000f
+#define MAX_RD_DELAY__VALUE GENMASK(3, 0)
#define CS_SETUP_CNT 0x220
-#define CS_SETUP_CNT__VALUE 0x001f
+#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
+#define CS_SETUP_CNT__TWB GENMASK(17, 12)
#define SPARE_AREA_SKIP_BYTES 0x230
-#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
+#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
#define SPARE_AREA_MARKER 0x240
-#define SPARE_AREA_MARKER__VALUE 0xffff
+#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
#define DEVICES_CONNECTED 0x250
-#define DEVICES_CONNECTED__VALUE 0x0007
+#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
#define DIE_MASK 0x260
-#define DIE_MASK__VALUE 0x00ff
+#define DIE_MASK__VALUE GENMASK(7, 0)
#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
-#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
+#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
#define WRITE_PROTECT 0x280
-#define WRITE_PROTECT__FLAG 0x0001
+#define WRITE_PROTECT__FLAG BIT(0)
#define RE_2_RE 0x290
-#define RE_2_RE__VALUE 0x003f
+#define RE_2_RE__VALUE GENMASK(5, 0)
#define MANUFACTURER_ID 0x300
-#define MANUFACTURER_ID__VALUE 0x00ff
+#define MANUFACTURER_ID__VALUE GENMASK(7, 0)
#define DEVICE_ID 0x310
-#define DEVICE_ID__VALUE 0x00ff
+#define DEVICE_ID__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_0 0x320
-#define DEVICE_PARAM_0__VALUE 0x00ff
+#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_1 0x330
-#define DEVICE_PARAM_1__VALUE 0x00ff
+#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_2 0x340
-#define DEVICE_PARAM_2__VALUE 0x00ff
+#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
#define LOGICAL_PAGE_DATA_SIZE 0x350
-#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
+#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
#define LOGICAL_PAGE_SPARE_SIZE 0x360
-#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
+#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
#define REVISION 0x370
-#define REVISION__VALUE 0xffff
+#define REVISION__VALUE GENMASK(15, 0)
#define ONFI_DEVICE_FEATURES 0x380
-#define ONFI_DEVICE_FEATURES__VALUE 0x003f
+#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
#define ONFI_OPTIONAL_COMMANDS 0x390
-#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
+#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
#define ONFI_TIMING_MODE 0x3a0
-#define ONFI_TIMING_MODE__VALUE 0x003f
+#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
-#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
+#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
-#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
-#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
+#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
+#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
-#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
-#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
-
-#define FEATURES 0x3f0
-#define FEATURES__N_BANKS 0x0003
-#define FEATURES__ECC_MAX_ERR 0x003c
-#define FEATURES__DMA 0x0040
-#define FEATURES__CMD_DMA 0x0080
-#define FEATURES__PARTITION 0x0100
-#define FEATURES__XDMA_SIDEBAND 0x0200
-#define FEATURES__GPREG 0x0400
-#define FEATURES__INDEX_ADDR 0x0800
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
+
+#define FEATURES 0x3f0
+#define FEATURES__N_BANKS GENMASK(1, 0)
+#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
+#define FEATURES__DMA BIT(6)
+#define FEATURES__CMD_DMA BIT(7)
+#define FEATURES__PARTITION BIT(8)
+#define FEATURES__XDMA_SIDEBAND BIT(9)
+#define FEATURES__GPREG BIT(10)
+#define FEATURES__INDEX_ADDR BIT(11)
#define TRANSFER_MODE 0x400
-#define TRANSFER_MODE__VALUE 0x0003
-
-#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
-#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
-
-/*
- * Some versions of the IP have the ECC fixup handled in hardware. In this
- * configuration we only get interrupted when the error is uncorrectable.
- * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
- * old IP.
- */
-#define INTR_STATUS__ECC_UNCOR_ERR 0x0001
-#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
-#define INTR_STATUS__ECC_ERR 0x0002
-#define INTR_STATUS__DMA_CMD_COMP 0x0004
-#define INTR_STATUS__TIME_OUT 0x0008
-#define INTR_STATUS__PROGRAM_FAIL 0x0010
-#define INTR_STATUS__ERASE_FAIL 0x0020
-#define INTR_STATUS__LOAD_COMP 0x0040
-#define INTR_STATUS__PROGRAM_COMP 0x0080
-#define INTR_STATUS__ERASE_COMP 0x0100
-#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
-#define INTR_STATUS__LOCKED_BLK 0x0400
-#define INTR_STATUS__UNSUP_CMD 0x0800
-#define INTR_STATUS__INT_ACT 0x1000
-#define INTR_STATUS__RST_COMP 0x2000
-#define INTR_STATUS__PIPE_CMD_ERR 0x4000
-#define INTR_STATUS__PAGE_XFER_INC 0x8000
-
-#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
-#define INTR_EN__ECC_ERR 0x0002
-#define INTR_EN__DMA_CMD_COMP 0x0004
-#define INTR_EN__TIME_OUT 0x0008
-#define INTR_EN__PROGRAM_FAIL 0x0010
-#define INTR_EN__ERASE_FAIL 0x0020
-#define INTR_EN__LOAD_COMP 0x0040
-#define INTR_EN__PROGRAM_COMP 0x0080
-#define INTR_EN__ERASE_COMP 0x0100
-#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
-#define INTR_EN__LOCKED_BLK 0x0400
-#define INTR_EN__UNSUP_CMD 0x0800
-#define INTR_EN__INT_ACT 0x1000
-#define INTR_EN__RST_COMP 0x2000
-#define INTR_EN__PIPE_CMD_ERR 0x4000
-#define INTR_EN__PAGE_XFER_INC 0x8000
-
-#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
-#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
-#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
-
-#define DATA_INTR 0x550
-#define DATA_INTR__WRITE_SPACE_AV 0x0001
-#define DATA_INTR__READ_DATA_AV 0x0002
-
-#define DATA_INTR_EN 0x560
-#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
-#define DATA_INTR_EN__READ_DATA_AV 0x0002
-
-#define GPREG_0 0x570
-#define GPREG_0__VALUE 0xffff
-
-#define GPREG_1 0x580
-#define GPREG_1__VALUE 0xffff
-
-#define GPREG_2 0x590
-#define GPREG_2__VALUE 0xffff
-
-#define GPREG_3 0x5a0
-#define GPREG_3__VALUE 0xffff
+#define TRANSFER_MODE__VALUE GENMASK(1, 0)
+
+#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
+#define INTR_EN(bank) (0x420 + (bank) * 0x50)
+/* bit[1:0] is used differently depending on IP version */
+#define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
+#define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
+#define INTR__ECC_ERR BIT(1) /* old IP */
+#define INTR__DMA_CMD_COMP BIT(2)
+#define INTR__TIME_OUT BIT(3)
+#define INTR__PROGRAM_FAIL BIT(4)
+#define INTR__ERASE_FAIL BIT(5)
+#define INTR__LOAD_COMP BIT(6)
+#define INTR__PROGRAM_COMP BIT(7)
+#define INTR__ERASE_COMP BIT(8)
+#define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
+#define INTR__LOCKED_BLK BIT(10)
+#define INTR__UNSUP_CMD BIT(11)
+#define INTR__INT_ACT BIT(12)
+#define INTR__RST_COMP BIT(13)
+#define INTR__PIPE_CMD_ERR BIT(14)
+#define INTR__PAGE_XFER_INC BIT(15)
+#define INTR__ERASED_PAGE BIT(16)
+
+#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
+#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
+#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
#define ECC_THRESHOLD 0x600
-#define ECC_THRESHOLD__VALUE 0x03ff
+#define ECC_THRESHOLD__VALUE GENMASK(9, 0)
#define ECC_ERROR_BLOCK_ADDRESS 0x610
-#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
+#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
#define ECC_ERROR_PAGE_ADDRESS 0x620
-#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
-#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
+#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
+#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
#define ECC_ERROR_ADDRESS 0x630
-#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
-#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
+#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
+#define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)
#define ERR_CORRECTION_INFO 0x640
-#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
-#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
-#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
-#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
+#define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
+#define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)
+#define ERR_CORRECTION_INFO__UNCOR BIT(14)
+#define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
+
+#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
+#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
+#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
+#define ECC_COR_INFO__UNCOR_ERR BIT(7)
+
+#define CFG_DATA_BLOCK_SIZE 0x6b0
+
+#define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
+
+#define CFG_NUM_DATA_BLOCKS 0x6d0
+
+#define CFG_META_DATA_SIZE 0x6e0
#define DMA_ENABLE 0x700
-#define DMA_ENABLE__FLAG 0x0001
+#define DMA_ENABLE__FLAG BIT(0)
#define IGNORE_ECC_DONE 0x710
-#define IGNORE_ECC_DONE__FLAG 0x0001
+#define IGNORE_ECC_DONE__FLAG BIT(0)
#define DMA_INTR 0x720
-#define DMA_INTR__TARGET_ERROR 0x0001
-#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
-#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
-#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
-#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
-#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
-
#define DMA_INTR_EN 0x730
-#define DMA_INTR_EN__TARGET_ERROR 0x0001
-#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
-#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
-#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
-#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
-#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
+#define DMA_INTR__TARGET_ERROR BIT(0)
+#define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
+#define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
+#define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
+#define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
+#define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
#define TARGET_ERR_ADDR_LO 0x740
-#define TARGET_ERR_ADDR_LO__VALUE 0xffff
+#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
#define TARGET_ERR_ADDR_HI 0x750
-#define TARGET_ERR_ADDR_HI__VALUE 0xffff
+#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
#define CHNL_ACTIVE 0x760
-#define CHNL_ACTIVE__CHANNEL0 0x0001
-#define CHNL_ACTIVE__CHANNEL1 0x0002
-#define CHNL_ACTIVE__CHANNEL2 0x0004
-#define CHNL_ACTIVE__CHANNEL3 0x0008
-
-#define ACTIVE_SRC_ID 0x800
-#define ACTIVE_SRC_ID__VALUE 0x00ff
-
-#define PTN_INTR 0x810
-#define PTN_INTR__CONFIG_ERROR 0x0001
-#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
-#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
-#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
-#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
-#define PTN_INTR__REG_ACCESS_ERROR 0x0020
-
-#define PTN_INTR_EN 0x820
-#define PTN_INTR_EN__CONFIG_ERROR 0x0001
-#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
-#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
-#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
-#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
-#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
-
-#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
-#define PERM_SRC_ID__SRCID 0x00ff
-#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
-#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
-#define PERM_SRC_ID__READ_ACTIVE 0x4000
-#define PERM_SRC_ID__PARTITION_VALID 0x8000
-
-#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
-#define MIN_BLK_ADDR__VALUE 0xffff
-
-#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
-#define MAX_BLK_ADDR__VALUE 0xffff
-
-#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
-#define MIN_MAX_BANK__MIN_VALUE 0x0003
-#define MIN_MAX_BANK__MAX_VALUE 0x000c
-
-/* lld.h */
-#define GOOD_BLOCK 0
-#define DEFECTIVE_BLOCK 1
-#define READ_ERROR 2
-
-#define CLK_X 5
-#define CLK_MULTI 4
-
-/* spectraswconfig.h */
-#define CMD_DMA 0
-
-#define SPECTRA_PARTITION_ID 0
-/**** Block Table and Reserved Block Parameters *****/
-#define SPECTRA_START_BLOCK 3
-#define NUM_FREE_BLOCKS_GATE 30
-
-/* KBV - Updated to LNW scratch register address */
-#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
-#define SCRATCH_REG_SIZE 64
-
-#define GLOB_HWCTL_DEFAULT_BLKS 2048
-
-#define CUSTOM_CONF_PARAMS 0
-
-#define INDEX_CTRL_REG 0x0
-#define INDEX_DATA_REG 0x10
-
-#define MODE_00 0x00000000
-#define MODE_01 0x04000000
-#define MODE_10 0x08000000
-#define MODE_11 0x0C000000
-
-
-#define DATA_TRANSFER_MODE 0
-#define PROTECTION_PER_BLOCK 1
-#define LOAD_WAIT_COUNT 2
-#define PROGRAM_WAIT_COUNT 3
-#define ERASE_WAIT_COUNT 4
-#define INT_MONITOR_CYCLE_COUNT 5
-#define READ_BUSY_PIN_ENABLED 6
-#define MULTIPLANE_OPERATION_SUPPORT 7
-#define PRE_FETCH_MODE 8
-#define CE_DONT_CARE_SUPPORT 9
-#define COPYBACK_SUPPORT 10
-#define CACHE_WRITE_SUPPORT 11
-#define CACHE_READ_SUPPORT 12
-#define NUM_PAGES_IN_BLOCK 13
-#define ECC_ENABLE_SELECT 14
-#define WRITE_ENABLE_2_READ_ENABLE 15
-#define ADDRESS_2_DATA 16
-#define READ_ENABLE_2_WRITE_ENABLE 17
-#define TWO_ROW_ADDRESS_CYCLES 18
-#define MULTIPLANE_ADDRESS_RESTRICT 19
-#define ACC_CLOCKS 20
-#define READ_WRITE_ENABLE_LOW_COUNT 21
-#define READ_WRITE_ENABLE_HIGH_COUNT 22
-
-#define ECC_SECTOR_SIZE 512
-
-#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
-
-struct nand_buf {
- int head;
- int tail;
- /* seprating dma_buf as buf can be used for status read purpose */
- uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64);
- uint8_t buf[DENALI_BUF_SIZE];
-};
+#define CHNL_ACTIVE__CHANNEL0 BIT(0)
+#define CHNL_ACTIVE__CHANNEL1 BIT(1)
+#define CHNL_ACTIVE__CHANNEL2 BIT(2)
+#define CHNL_ACTIVE__CHANNEL3 BIT(3)
-#define INTEL_CE4100 1
-#define INTEL_MRST 2
-#define DT 3
+struct udevice;
struct denali_nand_info {
struct nand_chip nand;
unsigned long clk_x_rate; /* bus interface clock rate */
- int flash_bank; /* currently selected chip */
- int status;
- int platform;
- struct nand_buf buf;
- struct device *dev;
- int total_used_banks;
- uint32_t block; /* stored for future use */
+ int active_bank; /* currently selected bank */
+ struct udevice *dev;
uint32_t page;
- void __iomem *flash_reg; /* Mapped io reg base address */
- void __iomem *flash_mem; /* Mapped io reg base address */
-
- /* elements used by ISR */
- /*struct completion complete;*/
-
- uint32_t irq_status;
- int irq_debug_array[32];
- int idx;
+ void __iomem *reg; /* Register Interface */
+ void __iomem *host; /* Host Data/Command Interface */
+ u32 irq_mask; /* interrupts we are waiting for */
+ u32 irq_status; /* interrupts that have happened */
int irq;
-
- uint32_t devnum; /* represent how many nands connected */
- uint32_t fwblks; /* represent how many blocks FW used */
- uint32_t totalblks;
- uint32_t blksperchip;
- uint32_t bbtskipbytes;
- uint32_t max_banks;
- unsigned int revision;
- unsigned int caps;
+ void *buf; /* for syndrome layout conversion */
+ dma_addr_t dma_addr;
+ int dma_avail; /* can support DMA? */
+ int devs_per_cs; /* devices connected in parallel */
+ int oob_skip_bytes; /* number of bytes reserved for BBM */
+ int max_banks;
+ unsigned int revision; /* IP revision */
+ unsigned int caps; /* IP capability (or quirk) */
+ const struct nand_ecc_caps *ecc_caps;
+ u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
+ void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
+ void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
+ int page, int write);
};
#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
#define DENALI_CAP_DMA_64BIT BIT(1)
+int denali_calc_ecc_bytes(int step_size, int strength);
int denali_init(struct denali_nand_info *denali);
#endif /* __DENALI_H__ */
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <clk.h>
#include <dm.h>
#include <linux/io.h>
#include <linux/ioport.h>
+#include <linux/printk.h>
#include "denali.h"
struct denali_dt_data {
unsigned int revision;
unsigned int caps;
+ const struct nand_ecc_caps *ecc_caps;
};
+NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
+ 512, 8, 15);
static const struct denali_dt_data denali_socfpga_data = {
.caps = DENALI_CAP_HW_ECC_FIXUP,
+ .ecc_caps = &denali_socfpga_ecc_caps,
};
+NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
+ 1024, 8, 16, 24);
static const struct denali_dt_data denali_uniphier_v5a_data = {
.caps = DENALI_CAP_HW_ECC_FIXUP |
DENALI_CAP_DMA_64BIT,
+ .ecc_caps = &denali_uniphier_v5a_ecc_caps,
};
+NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
+ 1024, 8, 16);
static const struct denali_dt_data denali_uniphier_v5b_data = {
.revision = 0x0501,
.caps = DENALI_CAP_HW_ECC_FIXUP |
DENALI_CAP_DMA_64BIT,
+ .ecc_caps = &denali_uniphier_v5b_ecc_caps,
};
static const struct udevice_id denali_nand_dt_ids[] = {
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
+ denali->ecc_caps = data->ecc_caps;
}
+ denali->dev = dev;
+
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
- denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res));
+ denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
- denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));
+ denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
DM_GET_DRIVER(denali_nand_dt),
&dev);
if (ret && ret != -ENODEV)
- printf("Failed to initialize Denali NAND controller. (error %d)\n",
+ pr_err("Failed to initialize Denali NAND controller. (error %d)\n",
ret);
}
#include <common.h>
#include <asm/io.h>
#include <asm/unaligned.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include "denali.h"
+#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
+#define DENALI_MAP10 (2 << 26) /* high-level control plane */
+
+#define INDEX_CTRL_REG 0x0
+#define INDEX_DATA_REG 0x10
+
#define SPARE_ACCESS 0x41
#define MAIN_ACCESS 0x42
#define PIPELINE_ACCESS 0x2000
do {
intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
- if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
+ if (intr_status & INTR__ECC_UNCOR_ERR) {
debug("Uncorrected ECC detected\n");
return -EBADMSG;
}
addr = BANK(flash_bank) | page;
/* setup the acccess type */
- cmd = MODE_10 | addr;
+ cmd = DENALI_MAP10 | addr;
index_addr(cmd, access_type);
/* setup the pipeline command */
index_addr(cmd, PIPELINE_ACCESS | page_count);
- cmd = MODE_01 | addr;
+ cmd = DENALI_MAP01 | addr;
writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
- return wait_for_irq(INTR_STATUS__LOAD_COMP);
+ return wait_for_irq(INTR__LOAD_COMP);
}
static int nand_read_oob(void *buf, int page)
#include <nand.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand_ecc.h>
#include <asm/io.h>
#include <nand.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand_ecc.h>
#include <asm/io.h>
#include <common.h>
#include <asm/io.h>
#include <fsl_ifc.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#include <common.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/types.h>
#include <malloc.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/nand_bch.h>
#ifdef CONFIG_MTD_PARTITIONS
chip->cmd_ctrl(mtd, page_addr, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
- /* One more address cycle for devices > 32MiB */
- if (chip->chipsize > (32 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
}
chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd, page_addr, ctrl);
chip->cmd_ctrl(mtd, page_addr >> 8,
NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB */
- if (chip->chipsize > (128 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16,
NAND_NCE | NAND_ALE);
}
return status;
}
-#define BITS_PER_BYTE 8
+/**
+ * nand_reset_data_interface - Reset data interface and timings
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Reset the Data interface and timings to ONFI mode 0.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_data_interface *conf;
+ int ret;
+
+ if (!chip->setup_data_interface)
+ return 0;
+
+ /*
+ * The ONFI specification says:
+ * "
+ * To transition from NV-DDR or NV-DDR2 to the SDR data
+ * interface, the host shall use the Reset (FFh) command
+ * using SDR timing mode 0. A device in any timing mode is
+ * required to recognize Reset (FFh) command issued in SDR
+ * timing mode 0.
+ * "
+ *
+ * Configure the data interface in SDR mode and set the
+ * timings to timing mode 0.
+ */
+
+ conf = nand_get_default_data_interface();
+ ret = chip->setup_data_interface(mtd, chipnr, conf);
+ if (ret)
+ pr_err("Failed to configure data interface to SDR timing mode 0\n");
+
+ return ret;
+}
+
+/**
+ * nand_setup_data_interface - Setup the best data interface and timings
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Find and configure the best data interface and NAND timings supported by
+ * the chip and the driver.
+ * First tries to retrieve supported timing modes from ONFI information,
+ * and if the NAND chip does not support ONFI, relies on the
+ * ->onfi_timing_mode_default specified in the nand_ids table.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ if (!chip->setup_data_interface || !chip->data_interface)
+ return 0;
+
+ /*
+ * Ensure the timing mode has been changed on the chip side
+ * before changing timings on the controller side.
+ */
+ if (chip->onfi_version) {
+ u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
+ chip->onfi_timing_mode_default,
+ };
+
+ ret = chip->onfi_set_features(mtd, chip,
+ ONFI_FEATURE_ADDR_TIMING_MODE,
+ tmode_param);
+ if (ret)
+ goto err;
+ }
+
+ ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
+err:
+ return ret;
+}
+
+/**
+ * nand_init_data_interface - find the best data interface and timings
+ * @chip: The NAND chip
+ *
+ * Find the best data interface and NAND timings supported by the chip
+ * and the driver.
+ * First tries to retrieve supported timing modes from ONFI information,
+ * and if the NAND chip does not support ONFI, relies on the
+ * ->onfi_timing_mode_default specified in the nand_ids table. After this
+ * function nand_chip->data_interface is initialized with the best timing mode
+ * available.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_init_data_interface(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int modes, mode, ret;
+
+ if (!chip->setup_data_interface)
+ return 0;
+
+ /*
+ * First try to identify the best timings from ONFI parameters and
+ * if the NAND does not support ONFI, fallback to the default ONFI
+ * timing mode.
+ */
+ modes = onfi_get_async_timing_mode(chip);
+ if (modes == ONFI_TIMING_MODE_UNKNOWN) {
+ if (!chip->onfi_timing_mode_default)
+ return 0;
+
+ modes = GENMASK(chip->onfi_timing_mode_default, 0);
+ }
+
+ chip->data_interface = kzalloc(sizeof(*chip->data_interface),
+ GFP_KERNEL);
+ if (!chip->data_interface)
+ return -ENOMEM;
+
+ for (mode = fls(modes) - 1; mode >= 0; mode--) {
+ ret = onfi_init_data_interface(chip, chip->data_interface,
+ NAND_SDR_IFACE, mode);
+ if (ret)
+ continue;
+
+ /* Pass -1 to only */
+ ret = chip->setup_data_interface(mtd,
+ NAND_DATA_IFACE_CHECK_ONLY,
+ chip->data_interface);
+ if (!ret) {
+ chip->onfi_timing_mode_default = mode;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
+{
+ kfree(chip->data_interface);
+}
+
+/**
+ * nand_reset - Reset and initialize a NAND device
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Returns 0 for success or negative error code otherwise
+ */
+int nand_reset(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ ret = nand_reset_data_interface(chip, chipnr);
+ if (ret)
+ return ret;
+
+ /*
+ * The CS line has to be released before we can apply the new NAND
+ * interface settings, hence this weird ->select_chip() dance.
+ */
+ chip->select_chip(mtd, chipnr);
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ chip->select_chip(mtd, -1);
+
+ chip->select_chip(mtd, chipnr);
+ ret = nand_setup_data_interface(chip, chipnr);
+ chip->select_chip(mtd, -1);
+ if (ret)
+ return ret;
+
+ return 0;
+}
/**
* nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
if (!aligned)
use_bufpoi = 1;
+ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+ use_bufpoi = !IS_ALIGNED((unsigned long)buf,
+ chip->buf_align);
else
use_bufpoi = 0;
__func__, buf);
read_retry:
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc))
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
/*
* Now read the page into the buffer. Absent an error,
* @buf: the data to write
* @oob_required: must write chip->oob_poi to OOB
* @page: page number to write
- * @cached: cached programming
* @raw: use _raw version of write_page
*/
static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, int data_len, const uint8_t *buf,
- int oob_required, int page, int cached, int raw)
+ int oob_required, int page, int raw)
{
int status, subpage;
else
subpage = 0;
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc))
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
if (unlikely(raw))
status = chip->ecc.write_page_raw(mtd, chip, buf,
if (status < 0)
return status;
- /*
- * Cached progamming disabled for now. Not sure if it's worth the
- * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
- */
- cached = 0;
-
- if (!cached || !NAND_HAS_CACHEPROG(chip)) {
-
+ if (nand_standard_page_accessors(&chip->ecc)) {
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
- /*
- * See if operation failed and additional status checks are
- * available.
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_WRITING, status,
- page);
+ status = chip->waitfunc(mtd, chip);
if (status & NAND_STATUS_FAIL)
return -EIO;
- } else {
- chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
}
return 0;
static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
- int chipnr, realpage, page, blockmask, column;
+ int chipnr, realpage, page, column;
struct nand_chip *chip = mtd_to_nand(mtd);
uint32_t writelen = ops->len;
realpage = (int)(to >> chip->page_shift);
page = realpage & chip->pagemask;
- blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
/* Invalidate the page cache, when we write to the cached page */
if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
while (1) {
int bytes = mtd->writesize;
- int cached = writelen > bytes && page != blockmask;
uint8_t *wbuf = buf;
int use_bufpoi;
int part_pagewr = (column || writelen < mtd->writesize);
if (part_pagewr)
use_bufpoi = 1;
+ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+ use_bufpoi = !IS_ALIGNED((unsigned long)buf,
+ chip->buf_align);
else
use_bufpoi = 0;
if (use_bufpoi) {
pr_debug("%s: using write bounce buffer for buf@%p\n",
__func__, buf);
- cached = 0;
if (part_pagewr)
bytes = min_t(int, bytes - column, writelen);
chip->pagebuf = -1;
memset(chip->oob_poi, 0xff, mtd->oobsize);
}
ret = chip->write_page(mtd, chip, column, bytes, wbuf,
- oob_required, page, cached,
+ oob_required, page,
(ops->mode == MTD_OPS_RAW));
if (ret)
break;
}
chipnr = (int)(to >> chip->chip_shift);
- chip->select_chip(mtd, chipnr);
-
- /* Shift to get page */
- page = (int)(to >> chip->page_shift);
/*
* Reset the chip. Some chips (like the Toshiba TC5832DC found in one
* if we don't do this. I have no clue why, but I seem to have 'fixed'
* it in the doc2000 driver in August 1999. dwmw2.
*/
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, chipnr);
+
+ chip->select_chip(mtd, chipnr);
+
+ /* Shift to get page */
+ page = (int)(to >> chip->page_shift);
/* Check, if it is write protected */
if (nand_check_wp(mtd)) {
status = chip->erase(mtd, page & chip->pagemask);
- /*
- * See if operation failed and additional status checks are
- * available
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_ERASING,
- status, page);
-
/* See if block erase succeeded */
if (status & NAND_STATUS_FAIL) {
pr_debug("%s: failed erase, page 0x%08x\n",
init_waitqueue_head(&chip->controller->wq);
}
+ if (!chip->buf_align)
+ chip->buf_align = 1;
}
/* Sanitize ONFI strings so we can safely print them */
int i, maf_idx;
u8 id_data[8];
- /* Select the device */
- chip->select_chip(mtd, 0);
-
/*
* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
* after power-up.
*/
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, 0);
+
+ /* Select the device */
+ chip->select_chip(mtd, 0);
/* Send the command for reading device ID */
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
chip->chip_shift += 32 - 1;
}
+ if (chip->chip_shift - chip->page_shift > 16)
+ chip->options |= NAND_ROW_ADDR_3;
+
chip->badblockbits = 8;
chip->erase = single_erase;
if (ecc_step > 0)
chip->ecc.size = ecc_step;
+ if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
+ chip->ecc.options |= NAND_ECC_MAXIMIZE;
+
return 0;
}
#else
return PTR_ERR(type);
}
+ /* Initialize the ->data_interface field. */
+ ret = nand_init_data_interface(chip);
+ if (ret)
+ return ret;
+
+ /*
+ * Setup the data interface correctly on the chip and controller side.
+ * This explicit call to nand_setup_data_interface() is only required
+ * for the first die, because nand_reset() has been called before
+ * ->data_interface and ->default_onfi_timing_mode were set.
+ * For the other dies, nand_reset() will automatically switch to the
+ * best mode for us.
+ */
+ ret = nand_setup_data_interface(chip, 0);
+ if (ret)
+ return ret;
+
chip->select_chip(mtd, -1);
/* Check for a chip array */
for (i = 1; i < maxchips; i++) {
- chip->select_chip(mtd, i);
/* See comment in nand_get_flash_type for reset */
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, i);
+
+ chip->select_chip(mtd, i);
/* Send the command for reading device ID */
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
/* Read manufacturer and device IDs */
}
EXPORT_SYMBOL(nand_scan_ident);
+/**
+ * nand_check_ecc_caps - check the sanity of preset ECC settings
+ * @chip: nand chip info structure
+ * @caps: ECC caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * When ECC step size and strength are already set, check if they are supported
+ * by the controller and the calculated ECC bytes fit within the chip's OOB.
+ * On success, the calculated ECC bytes is set.
+ */
+int nand_check_ecc_caps(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int preset_step = chip->ecc.size;
+ int preset_strength = chip->ecc.strength;
+ int nsteps, ecc_bytes;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ if (!preset_step || !preset_strength)
+ return -ENODATA;
+
+ nsteps = mtd->writesize / preset_step;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+
+ if (stepinfo->stepsize != preset_step)
+ continue;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ if (stepinfo->strengths[j] != preset_strength)
+ continue;
+
+ ecc_bytes = caps->calc_ecc_bytes(preset_step,
+ preset_strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ return ecc_bytes;
+
+ if (ecc_bytes * nsteps > oobavail) {
+ pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
+ preset_step, preset_strength);
+ return -ENOSPC;
+ }
+
+ chip->ecc.bytes = ecc_bytes;
+
+ return 0;
+ }
+ }
+
+ pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
+ preset_step, preset_strength);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
+
+/**
+ * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
+ * @chip: nand chip info structure
+ * @caps: ECC engine caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * If a chip's ECC requirement is provided, try to meet it with the least
+ * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
+ * On success, the chosen ECC settings are set.
+ */
+int nand_match_ecc_req(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int req_step = chip->ecc_step_ds;
+ int req_strength = chip->ecc_strength_ds;
+ int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
+ int best_step, best_strength, best_ecc_bytes;
+ int best_ecc_bytes_total = INT_MAX;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ /* No information provided by the NAND chip */
+ if (!req_step || !req_strength)
+ return -ENOTSUPP;
+
+ /* number of correctable bits the chip requires in a page */
+ req_corr = mtd->writesize / req_step * req_strength;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+ step_size = stepinfo->stepsize;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ strength = stepinfo->strengths[j];
+
+ /*
+ * If both step size and strength are smaller than the
+ * chip's requirement, it is not easy to compare the
+ * resulted reliability.
+ */
+ if (step_size < req_step && strength < req_strength)
+ continue;
+
+ if (mtd->writesize % step_size)
+ continue;
+
+ nsteps = mtd->writesize / step_size;
+
+ ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ continue;
+ ecc_bytes_total = ecc_bytes * nsteps;
+
+ if (ecc_bytes_total > oobavail ||
+ strength * nsteps < req_corr)
+ continue;
+
+ /*
+ * We assume the best is to meet the chip's requrement
+ * with the least number of ECC bytes.
+ */
+ if (ecc_bytes_total < best_ecc_bytes_total) {
+ best_ecc_bytes_total = ecc_bytes_total;
+ best_step = step_size;
+ best_strength = strength;
+ best_ecc_bytes = ecc_bytes;
+ }
+ }
+ }
+
+ if (best_ecc_bytes_total == INT_MAX)
+ return -ENOTSUPP;
+
+ chip->ecc.size = best_step;
+ chip->ecc.strength = best_strength;
+ chip->ecc.bytes = best_ecc_bytes;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_match_ecc_req);
+
+/**
+ * nand_maximize_ecc - choose the max ECC strength available
+ * @chip: nand chip info structure
+ * @caps: ECC engine caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * Choose the max ECC strength that is supported on the controller, and can fit
+ * within the chip's OOB. On success, the chosen ECC settings are set.
+ */
+int nand_maximize_ecc(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int step_size, strength, nsteps, ecc_bytes, corr;
+ int best_corr = 0;
+ int best_step = 0;
+ int best_strength, best_ecc_bytes;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+ step_size = stepinfo->stepsize;
+
+ /* If chip->ecc.size is already set, respect it */
+ if (chip->ecc.size && step_size != chip->ecc.size)
+ continue;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ strength = stepinfo->strengths[j];
+
+ if (mtd->writesize % step_size)
+ continue;
+
+ nsteps = mtd->writesize / step_size;
+
+ ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ continue;
+
+ if (ecc_bytes * nsteps > oobavail)
+ continue;
+
+ corr = strength * nsteps;
+
+ /*
+ * If the number of correctable bits is the same,
+ * bigger step_size has more reliability.
+ */
+ if (corr > best_corr ||
+ (corr == best_corr && step_size > best_step)) {
+ best_corr = corr;
+ best_step = step_size;
+ best_strength = strength;
+ best_ecc_bytes = ecc_bytes;
+ }
+ }
+ }
+
+ if (!best_corr)
+ return -ENOTSUPP;
+
+ chip->ecc.size = best_step;
+ chip->ecc.strength = best_strength;
+ chip->ecc.bytes = best_ecc_bytes;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_maximize_ecc);
+
/*
* Check if the chip configuration meet the datasheet requirements.
return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
}
+static bool invalid_ecc_page_accessors(struct nand_chip *chip)
+{
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ if (nand_standard_page_accessors(ecc))
+ return false;
+
+ /*
+ * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
+ * controller driver implements all the page accessors because
+ * default helpers are not suitable when the core does not
+ * send the READ0/PAGEPROG commands.
+ */
+ return (!ecc->read_page || !ecc->write_page ||
+ !ecc->read_page_raw || !ecc->write_page_raw ||
+ (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
+ (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
+ ecc->hwctl && ecc->calculate));
+}
+
/**
* nand_scan_tail - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
!(chip->bbt_options & NAND_BBT_USE_FLASH));
+ if (invalid_ecc_page_accessors(chip)) {
+ pr_err("Invalid ECC page accessors setup\n");
+ return -EINVAL;
+ }
+
if (!(chip->options & NAND_OWN_BUFFERS)) {
nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
chip->buffers = nbuf;
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/bbm.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/bitops.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand_bch.h>
#include <linux/bch.h>
#include <malloc.h>
*
*/
#include <common.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/sizes.h>
#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
*/
#include <common.h>
#include <linux/kernel.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
-static const struct nand_sdr_timings onfi_sdr_timings[] = {
+static const struct nand_data_interface onfi_sdr_timings[] = {
/* Mode 0 */
{
- .tADL_min = 200000,
- .tALH_min = 20000,
- .tALS_min = 50000,
- .tAR_min = 25000,
- .tCEA_max = 100000,
- .tCEH_min = 20000,
- .tCH_min = 20000,
- .tCHZ_max = 100000,
- .tCLH_min = 20000,
- .tCLR_min = 20000,
- .tCLS_min = 50000,
- .tCOH_min = 0,
- .tCS_min = 70000,
- .tDH_min = 20000,
- .tDS_min = 40000,
- .tFEAT_max = 1000000,
- .tIR_min = 10000,
- .tITC_max = 1000000,
- .tRC_min = 100000,
- .tREA_max = 40000,
- .tREH_min = 30000,
- .tRHOH_min = 0,
- .tRHW_min = 200000,
- .tRHZ_max = 200000,
- .tRLOH_min = 0,
- .tRP_min = 50000,
- .tRST_max = 250000000000ULL,
- .tWB_max = 200000,
- .tRR_min = 40000,
- .tWC_min = 100000,
- .tWH_min = 30000,
- .tWHR_min = 120000,
- .tWP_min = 50000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 20000,
+ .tALS_min = 50000,
+ .tAR_min = 25000,
+ .tCEA_max = 100000,
+ .tCEH_min = 20000,
+ .tCH_min = 20000,
+ .tCHZ_max = 100000,
+ .tCLH_min = 20000,
+ .tCLR_min = 20000,
+ .tCLS_min = 50000,
+ .tCOH_min = 0,
+ .tCS_min = 70000,
+ .tDH_min = 20000,
+ .tDS_min = 40000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 10000,
+ .tITC_max = 1000000,
+ .tRC_min = 100000,
+ .tREA_max = 40000,
+ .tREH_min = 30000,
+ .tRHOH_min = 0,
+ .tRHW_min = 200000,
+ .tRHZ_max = 200000,
+ .tRLOH_min = 0,
+ .tRP_min = 50000,
+ .tRR_min = 40000,
+ .tRST_max = 250000000000ULL,
+ .tWB_max = 200000,
+ .tWC_min = 100000,
+ .tWH_min = 30000,
+ .tWHR_min = 120000,
+ .tWP_min = 50000,
+ .tWW_min = 100000,
+ },
},
/* Mode 1 */
{
- .tADL_min = 100000,
- .tALH_min = 10000,
- .tALS_min = 25000,
- .tAR_min = 10000,
- .tCEA_max = 45000,
- .tCEH_min = 20000,
- .tCH_min = 10000,
- .tCHZ_max = 50000,
- .tCLH_min = 10000,
- .tCLR_min = 10000,
- .tCLS_min = 25000,
- .tCOH_min = 15000,
- .tCS_min = 35000,
- .tDH_min = 10000,
- .tDS_min = 20000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 50000,
- .tREA_max = 30000,
- .tREH_min = 15000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRP_min = 25000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 45000,
- .tWH_min = 15000,
- .tWHR_min = 80000,
- .tWP_min = 25000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 10000,
+ .tALS_min = 25000,
+ .tAR_min = 10000,
+ .tCEA_max = 45000,
+ .tCEH_min = 20000,
+ .tCH_min = 10000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 10000,
+ .tCLR_min = 10000,
+ .tCLS_min = 25000,
+ .tCOH_min = 15000,
+ .tCS_min = 35000,
+ .tDH_min = 10000,
+ .tDS_min = 20000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 50000,
+ .tREA_max = 30000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRP_min = 25000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 45000,
+ .tWH_min = 15000,
+ .tWHR_min = 80000,
+ .tWP_min = 25000,
+ .tWW_min = 100000,
+ },
},
/* Mode 2 */
{
- .tADL_min = 100000,
- .tALH_min = 10000,
- .tALS_min = 15000,
- .tAR_min = 10000,
- .tCEA_max = 30000,
- .tCEH_min = 20000,
- .tCH_min = 10000,
- .tCHZ_max = 50000,
- .tCLH_min = 10000,
- .tCLR_min = 10000,
- .tCLS_min = 15000,
- .tCOH_min = 15000,
- .tCS_min = 25000,
- .tDH_min = 5000,
- .tDS_min = 15000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 35000,
- .tREA_max = 25000,
- .tREH_min = 15000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tRP_min = 17000,
- .tWC_min = 35000,
- .tWH_min = 15000,
- .tWHR_min = 80000,
- .tWP_min = 17000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 10000,
+ .tALS_min = 15000,
+ .tAR_min = 10000,
+ .tCEA_max = 30000,
+ .tCEH_min = 20000,
+ .tCH_min = 10000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 10000,
+ .tCLR_min = 10000,
+ .tCLS_min = 15000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 15000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 35000,
+ .tREA_max = 25000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tRP_min = 17000,
+ .tWC_min = 35000,
+ .tWH_min = 15000,
+ .tWHR_min = 80000,
+ .tWP_min = 17000,
+ .tWW_min = 100000,
+ },
},
/* Mode 3 */
{
- .tADL_min = 100000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 50000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 25000,
- .tDH_min = 5000,
- .tDS_min = 10000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 30000,
- .tREA_max = 20000,
- .tREH_min = 10000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRP_min = 15000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 30000,
- .tWH_min = 10000,
- .tWHR_min = 80000,
- .tWP_min = 15000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 10000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 30000,
+ .tREA_max = 20000,
+ .tREH_min = 10000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRP_min = 15000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 30000,
+ .tWH_min = 10000,
+ .tWHR_min = 80000,
+ .tWP_min = 15000,
+ .tWW_min = 100000,
+ },
},
/* Mode 4 */
{
- .tADL_min = 70000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 30000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 20000,
- .tDH_min = 5000,
- .tDS_min = 10000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 25000,
- .tREA_max = 20000,
- .tREH_min = 10000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 5000,
- .tRP_min = 12000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 25000,
- .tWH_min = 10000,
- .tWHR_min = 80000,
- .tWP_min = 12000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 30000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 20000,
+ .tDH_min = 5000,
+ .tDS_min = 10000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 25000,
+ .tREA_max = 20000,
+ .tREH_min = 10000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 5000,
+ .tRP_min = 12000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 25000,
+ .tWH_min = 10000,
+ .tWHR_min = 80000,
+ .tWP_min = 12000,
+ .tWW_min = 100000,
+ },
},
/* Mode 5 */
{
- .tADL_min = 70000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 30000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 15000,
- .tDH_min = 5000,
- .tDS_min = 7000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 20000,
- .tREA_max = 16000,
- .tREH_min = 7000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 5000,
- .tRP_min = 10000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 20000,
- .tWH_min = 7000,
- .tWHR_min = 80000,
- .tWP_min = 10000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 30000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 15000,
+ .tDH_min = 5000,
+ .tDS_min = 7000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 20000,
+ .tREA_max = 16000,
+ .tREH_min = 7000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 5000,
+ .tRP_min = 10000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 20000,
+ .tWH_min = 7000,
+ .tWHR_min = 80000,
+ .tWP_min = 10000,
+ .tWW_min = 100000,
+ },
},
};
if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
return ERR_PTR(-EINVAL);
- return &onfi_sdr_timings[mode];
+ return &onfi_sdr_timings[mode].timings.sdr;
}
EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
+
+/**
+ * onfi_init_data_interface - [NAND Interface] Initialize a data interface from
+ * given ONFI mode
+ * @iface: The data interface to be initialized
+ * @mode: The ONFI timing mode
+ */
+int onfi_init_data_interface(struct nand_chip *chip,
+ struct nand_data_interface *iface,
+ enum nand_data_interface_type type,
+ int timing_mode)
+{
+ if (type != NAND_SDR_IFACE)
+ return -EINVAL;
+
+ if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
+ return -EINVAL;
+
+ *iface = onfi_sdr_timings[timing_mode];
+
+ /*
+ * Initialize timings that cannot be deduced from timing mode:
+ * tR, tPROG, tCCS, ...
+ * These information are part of the ONFI parameter page.
+ */
+ if (chip->onfi_version) {
+ struct nand_onfi_params *params = &chip->onfi_params;
+ struct nand_sdr_timings *timings = &iface->timings.sdr;
+
+ /* microseconds -> picoseconds */
+ timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog);
+ timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers);
+ timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r);
+
+ /* nanoseconds -> picoseconds */
+ timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(onfi_init_data_interface);
+
+/**
+ * nand_get_default_data_interface - [NAND Interface] Retrieve NAND
+ * data interface for mode 0. This is used as default timing after
+ * reset.
+ */
+const struct nand_data_interface *nand_get_default_data_interface(void)
+{
+ return &onfi_sdr_timings[0];
+}
+EXPORT_SYMBOL(nand_get_default_data_interface);
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/types.h>
#include "pxa3xx_nand.h"
{ 0xba20, 16, 16, &timing[3] },
};
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
.maxblocks = 8, /* Last 8 blocks in each chip */
.pattern = bbt_mirror_pattern
};
+#endif
static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
.eccbytes = 32,
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <malloc.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <nand.h>
#include <linux/errno.h>
#include <nand.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand_ecc.h>
#include <asm/arch/hardware.h>
(0x1 << 4) | /* Clear interrupt */ \
(0x1 << 6)) /* Disable ECC interrupt */
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+
/* Assuming 50MHz clock (20ns cycle time) and 3V operation */
#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
(0x2 << 17) | /* t_ar from nand_cycles */ \
(0x2 << 8) | /* t_rea from nand_cycles */ \
(0x5 << 4) | /* t_wc from nand_cycles */ \
(0x5 << 0)) /* t_rc from nand_cycles */
+#endif
#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
+#ifndef NAND_CMD_LOCK_TIGHT
+#define NAND_CMD_LOCK_TIGHT 0x2c
+#endif
+
+#ifndef NAND_CMD_LOCK_STATUS
+#define NAND_CMD_LOCK_STATUS 0x7a
+#endif
/* SMC register set */
struct zynq_nand_smc_regs {
{NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
+ {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
+ {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
+ {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
+ {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
+ {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
/* Add all the flash commands supported by the flash device */
};
/* disable interrupts */
writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
/* Initialize the NAND interface by setting cycles and operation mode */
writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+#endif
if (option & NAND_BUSWIDTH_16)
writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
else
return 0;
}
-static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct zynq_nand_info *xnand;
struct mtd_info *mtd;
return err;
}
+#ifdef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-void board_nand_init(void)
+void __weak board_nand_init(void)
{
struct nand_chip *nand = &nand_chip[0];
if (zynq_nand_init(nand, 0))
puts("ZYNQ NAND init failed\n");
}
+#endif
help
Enable the support for Sun7i GMAC Ethernet controller
+config SUN7I_GMAC_FORCE_TXERR
+ bool "Force PA17 as gmac function"
+ depends on SUN7I_GMAC
+ help
+ Some ethernet phys needs TXERR control. Since the GMAC
+ doesn't have such signal, setting PA17 as GMAC function
+ makes the pin output low, which enables data transmission.
+
config SUN4I_EMAC
bool "Allwinner Sun4i Ethernet MAC support"
depends on DM_ETH
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
- * Author: German Rivera <German.Rivera@freescale.com>
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
}
int dpbp_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
const struct dpbp_cfg *cfg,
- uint16_t *token)
+ uint32_t *obj_id)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
cmd_flags,
- 0);
+ dprc_token);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
return err;
/* retrieve response parameters */
- *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+ MC_CMD_READ_OBJ_ID(cmd, *obj_id);
return 0;
}
int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
- uint16_t token)
+ uint32_t obj_id)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
cmd_flags,
- token);
+ dprc_token);
+
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
return 0;
}
+
+int dpbp_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
+ cmd_flags, 0);
+
+ /* send command to mc */
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+ return 0;
+}
/*
- * Copyright (C) 2013-2015 Freescale Semiconductor
+ * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
int dpio_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
- int dpio_id,
+ uint32_t dpio_id,
uint16_t *token)
{
struct mc_command cmd = { 0 };
}
int dpio_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
const struct dpio_cfg *cfg,
- uint16_t *token)
+ uint32_t *obj_id)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
cmd_flags,
- 0);
+ dprc_token);
DPIO_CMD_CREATE(cmd, cfg);
/* send command to mc*/
return err;
/* retrieve response parameters */
- *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+ MC_CMD_READ_OBJ_ID(cmd, *obj_id);
return 0;
}
int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
- uint16_t token)
+ uint32_t obj_id)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
cmd_flags,
- token);
+ dprc_token);
+
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
return 0;
}
+
+int dpio_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
+ cmd_flags, 0);
+
+ /* send command to mc */
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+ return 0;
+}
* LS2080A SoC and its personalities has qbman cotroller version 4.0
* New SoCs like LS2088A, LS1088A has qbman conroller version 4.1
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A) {
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) {
*major = 4;
*minor = 0;
} else {
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
}
int dpmac_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
const struct dpmac_cfg *cfg,
- uint16_t *token)
+ uint32_t *obj_id)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
cmd_flags,
- 0);
+ dprc_token);
DPMAC_CMD_CREATE(cmd, cfg);
/* send command to mc*/
return err;
/* retrieve response parameters */
- *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+ MC_CMD_READ_OBJ_ID(cmd, *obj_id);
return 0;
}
int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
- uint16_t token)
+ uint32_t obj_id)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
cmd_flags,
- token);
+ dprc_token);
+
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
return 0;
}
+
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
+ cmd_flags, 0);
+
+ /* send command to mc */
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+ return 0;
+}
/*
- * Copyright (C) 2013-2015 Freescale Semiconductor
+ * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dpni.h>
-int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
- uint8_t *ext_cfg_buf)
+int dpni_prepare_cfg(const struct dpni_cfg *cfg,
+ uint8_t *cfg_buf)
{
- uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+ uint64_t *params = (uint64_t *)cfg_buf;
- DPNI_PREP_EXTENDED_CFG(ext_params, cfg);
+ DPNI_PREP_CFG(params, cfg);
return 0;
}
-int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
- const uint8_t *ext_cfg_buf)
+int dpni_extract_cfg(struct dpni_cfg *cfg,
+ const uint8_t *cfg_buf)
{
- uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+ uint64_t *params = (uint64_t *)cfg_buf;
- DPNI_EXT_EXTENDED_CFG(ext_params, cfg);
+ DPNI_EXT_CFG(params, cfg);
return 0;
}
}
int dpni_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
const struct dpni_cfg *cfg,
- uint16_t *token)
+ uint32_t *obj_id)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
cmd_flags,
- 0);
+ dprc_token);
DPNI_CMD_CREATE(cmd, cfg);
/* send command to mc*/
return err;
/* retrieve response parameters */
- *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+ MC_CMD_READ_OBJ_ID(cmd, *obj_id);
return 0;
}
int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
- uint16_t token)
+ uint32_t obj_id)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
cmd_flags,
- token);
+ dprc_token);
+
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
cmd_flags,
token);
- DPNI_CMD_GET_ATTR(cmd, attr);
-
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
if (err)
return mc_send_command(mc_io, &cmd);
}
-int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout)
-{
- struct mc_command cmd = { 0 };
- int err;
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_BUFFER_LAYOUT,
- cmd_flags,
- token);
-
- /* send command to mc*/
- err = mc_send_command(mc_io, &cmd);
- if (err)
- return err;
-
- /* retrieve response parameters */
- DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout);
-
- return 0;
-}
-
-int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout)
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const struct dpni_buffer_layout *layout,
+ enum dpni_queue_type type)
{
struct mc_command cmd = { 0 };
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_BUFFER_LAYOUT,
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT,
cmd_flags,
token);
- DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout);
-
- /* send command to mc*/
- return mc_send_command(mc_io, &cmd);
-}
-
-int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout)
-{
- struct mc_command cmd = { 0 };
- int err;
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_BUFFER_LAYOUT,
- cmd_flags,
- token);
-
- /* send command to mc*/
- err = mc_send_command(mc_io, &cmd);
- if (err)
- return err;
-
- /* retrieve response parameters */
- DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout);
-
- return 0;
-}
-
-int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout)
-{
- struct mc_command cmd = { 0 };
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_BUFFER_LAYOUT,
- cmd_flags,
- token);
- DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout);
-
- /* send command to mc*/
- return mc_send_command(mc_io, &cmd);
-}
-
-int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout)
-{
- struct mc_command cmd = { 0 };
- int err;
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT,
- cmd_flags,
- token);
-
- /* send command to mc*/
- err = mc_send_command(mc_io, &cmd);
- if (err)
- return err;
-
- /* retrieve response parameters */
- DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout);
-
- return 0;
-}
-
-int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout)
-{
- struct mc_command cmd = { 0 };
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT,
- cmd_flags,
- token);
- DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout);
+ DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, type);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
return 0;
}
-int dpni_get_counter(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- enum dpni_counter counter,
- uint64_t *value)
-{
- struct mc_command cmd = { 0 };
- int err;
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_COUNTER,
- cmd_flags,
- token);
- DPNI_CMD_GET_COUNTER(cmd, counter);
-
- /* send command to mc*/
- err = mc_send_command(mc_io, &cmd);
- if (err)
- return err;
-
- /* retrieve response parameters */
- DPNI_RSP_GET_COUNTER(cmd, *value);
-
- return 0;
-}
-
-int dpni_set_counter(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- enum dpni_counter counter,
- uint64_t value)
-{
- struct mc_command cmd = { 0 };
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_COUNTER,
- cmd_flags,
- token);
- DPNI_CMD_SET_COUNTER(cmd, counter, value);
-
- /* send command to mc*/
- return mc_send_command(mc_io, &cmd);
-}
-
int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
return mc_send_command(mc_io, &cmd);
}
-int dpni_set_tx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t *flow_id,
- const struct dpni_tx_flow_cfg *cfg)
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_FLOW,
- cmd_flags,
- token);
- DPNI_CMD_SET_TX_FLOW(cmd, *flow_id, cfg);
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
+ cmd_flags, 0);
- /* send command to mc*/
+ /* send command to mc */
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
- DPNI_RSP_SET_TX_FLOW(cmd, *flow_id);
+ mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
return 0;
}
-int dpni_get_tx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- struct dpni_tx_flow_attr *attr)
+int dpni_set_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type type,
+ uint8_t tc,
+ uint8_t index,
+ const struct dpni_queue *queue)
+{
+ struct mc_command cmd = { 0 };
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type type,
+ uint8_t tc,
+ uint8_t index,
+ struct dpni_queue *queue)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_FLOW,
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE,
cmd_flags,
token);
- DPNI_CMD_GET_TX_FLOW(cmd, flow_id);
+ DPNI_CMD_GET_QUEUE(cmd, type, tc, index);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
return err;
/* retrieve response parameters */
- DPNI_RSP_GET_TX_FLOW(cmd, attr);
-
+ DPNI_RSP_GET_QUEUE(cmd, queue);
return 0;
}
-int dpni_set_rx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint8_t tc_id,
- uint16_t flow_id,
- const struct dpni_queue_cfg *cfg)
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_confirmation_mode mode)
{
+ struct dpni_tx_confirmation_mode *cmd_params;
struct mc_command cmd = { 0 };
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FLOW,
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE,
cmd_flags,
token);
- DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg);
+
+ cmd_params = (struct dpni_tx_confirmation_mode *)cmd.params;
+ cmd_params->confirmation_mode = mode;
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
-int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint8_t tc_id,
- uint16_t flow_id,
- struct dpni_queue_attr *attr)
+int dpni_get_statistics(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t page,
+ struct dpni_statistics *stat)
{
struct mc_command cmd = { 0 };
int err;
+
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_FLOW,
- cmd_flags,
- token);
- DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id);
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS,
+ cmd_flags, token);
+ DPNI_CMD_GET_STATISTICS(cmd, page);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
return err;
/* retrieve response parameters */
- DPNI_RSP_GET_RX_FLOW(cmd, attr);
+ DPNI_RSP_GET_STATISTICS(cmd, stat);
return 0;
}
-int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- const struct dpni_tx_conf_cfg *cfg)
+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF,
- cmd_flags,
- token);
- DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg);
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS,
+ cmd_flags, token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
-int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- struct dpni_tx_conf_attr *attr)
-{
- struct mc_command cmd = { 0 };
- int err;
-
- /* prepare command */
- cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF,
- cmd_flags,
- token);
- DPNI_CMD_GET_TX_CONF(cmd, flow_id);
-
- /* send command to mc*/
- err = mc_send_command(mc_io, &cmd);
- if (err)
- return err;
-
- DPNI_RSP_GET_TX_CONF(cmd, attr);
-
- return 0;
-}
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
- * Author: German Rivera <German.Rivera@freescale.com>
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
return 0;
}
+
+int dprc_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
+ cmd_flags, 0);
+
+ /* send command to mc */
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+ return 0;
+}
-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define __FSL_DPMNG_CMD_H
/* Command IDs */
-#define DPMNG_CMDID_GET_VERSION 0x831
+#define DPMNG_CMDID_GET_VERSION 0x8311
/* cmd, param, offset, width, type, arg_name */
#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
{
- struct dprc_attributes attr;
int error;
+ uint16_t major_ver, minor_ver;
- memset(&attr, 0, sizeof(struct dprc_attributes));
- error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr);
- if (error == 0) {
- if ((attr.version.major != DPRC_VER_MAJOR) ||
- (attr.version.minor != DPRC_VER_MINOR)) {
- printf("DPRC version mismatch found %u.%u,",
- attr.version.major,
- attr.version.minor);
- printf("supported version is %u.%u\n",
- DPRC_VER_MAJOR, DPRC_VER_MINOR);
- }
+ error = dprc_get_api_version(mc_io, 0,
+ &major_ver,
+ &minor_ver);
+ if (error < 0) {
+ printf("dprc_get_api_version() failed: %d\n", error);
+ return error;
+ }
+
+ if (major_ver < DPRC_VER_MAJOR || (major_ver == DPRC_VER_MAJOR &&
+ minor_ver < DPRC_VER_MINOR)) {
+ printf("DPRC version mismatch found %u.%u,",
+ major_ver, minor_ver);
+ printf("supported version is %u.%u\n",
+ DPRC_VER_MAJOR, DPRC_VER_MINOR);
}
+
return error;
}
struct dpio_attr attr;
struct dpio_cfg dpio_cfg;
int err = 0;
+ uint16_t major_ver, minor_ver;
dflt_dpio = (struct fsl_dpio_obj *)calloc(
sizeof(struct fsl_dpio_obj), 1);
err = -ENOMEM;
goto err_calloc;
}
-
dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
dpio_cfg.num_priorities = 8;
- err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg,
- &dflt_dpio->dpio_handle);
+ err = dpio_create(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ &dpio_cfg,
+ &dflt_dpio->dpio_id);
if (err < 0) {
printf("dpio_create() failed: %d\n", err);
err = -ENODEV;
goto err_create;
}
+ err = dpio_get_api_version(dflt_mc_io, 0,
+ &major_ver,
+ &minor_ver);
+ if (err < 0) {
+ printf("dpio_get_api_version() failed: %d\n", err);
+ goto err_get_api_ver;
+ }
+
+ if (major_ver < DPIO_VER_MAJOR || (major_ver == DPIO_VER_MAJOR &&
+ minor_ver < DPIO_VER_MINOR)) {
+ printf("DPRC version mismatch found %u.%u,",
+ major_ver,
+ minor_ver);
+ }
+
+ err = dpio_open(dflt_mc_io,
+ MC_CMD_NO_FLAGS,
+ dflt_dpio->dpio_id,
+ &dflt_dpio->dpio_handle);
+ if (err) {
+ printf("dpio_open() failed\n");
+ goto err_open;
+ }
+
memset(&attr, 0, sizeof(struct dpio_attr));
err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpio->dpio_handle, &attr);
goto err_get_attr;
}
- if ((attr.version.major != DPIO_VER_MAJOR) ||
- (attr.version.minor != DPIO_VER_MINOR)) {
- printf("DPIO version mismatch found %u.%u,",
- attr.version.major, attr.version.minor);
- printf("supported version is %u.%u\n",
- DPIO_VER_MAJOR, DPIO_VER_MINOR);
+ if (dflt_dpio->dpio_id != attr.id) {
+ printf("dnpi object id and attribute id are not same\n");
+ goto err_attr_not_same;
}
- dflt_dpio->dpio_id = attr.id;
#ifdef DEBUG
printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
#endif
dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_get_enable:
err_get_attr:
+err_attr_not_same:
dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
- dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+err_open:
+err_get_api_ver:
+ dpio_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ dflt_dpio->dpio_id);
err_create:
free(dflt_dpio);
err_calloc:
goto err;
}
- err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_close() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ dflt_dpio->dpio_id);
if (err < 0) {
printf("dpio_destroy() failed: %d\n", err);
goto err;
child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
+
#ifdef DEBUG
printf("MC portal of child DPRC container: %d, physical addr %p)\n",
child_dprc_id, dflt_mc_io->mmio_regs);
int err;
struct dpbp_attr dpbp_attr;
struct dpbp_cfg dpbp_cfg;
+ uint16_t major_ver, minor_ver;
dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
sizeof(struct fsl_dpbp_obj), 1);
dpbp_cfg.options = 512;
- err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg,
- &dflt_dpbp->dpbp_handle);
+ err = dpbp_create(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ &dpbp_cfg,
+ &dflt_dpbp->dpbp_id);
if (err < 0) {
err = -ENODEV;
goto err_create;
}
+ err = dpbp_get_api_version(dflt_mc_io, 0,
+ &major_ver,
+ &minor_ver);
+ if (err < 0) {
+ printf("dpbp_get_api_version() failed: %d\n", err);
+ goto err_get_api_ver;
+ }
+
+ if (major_ver < DPBP_VER_MAJOR || (major_ver == DPBP_VER_MAJOR &&
+ minor_ver < DPBP_VER_MINOR)) {
+ printf("DPBP version mismatch found %u.%u,",
+ major_ver, minor_ver);
+ printf("supported version is %u.%u\n",
+ DPBP_VER_MAJOR, DPBP_VER_MINOR);
+ }
+
+ err = dpbp_open(dflt_mc_io,
+ MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_id,
+ &dflt_dpbp->dpbp_handle);
+ if (err) {
+ printf("dpbp_open() failed\n");
+ goto err_open;
+ }
+
memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpbp->dpbp_handle,
goto err_get_attr;
}
- if ((dpbp_attr.version.major != DPBP_VER_MAJOR) ||
- (dpbp_attr.version.minor != DPBP_VER_MINOR)) {
- printf("DPBP version mismatch found %u.%u,",
- dpbp_attr.version.major, dpbp_attr.version.minor);
- printf("supported version is %u.%u\n",
- DPBP_VER_MAJOR, DPBP_VER_MINOR);
+ if (dflt_dpbp->dpbp_id != dpbp_attr.id) {
+ printf("dpbp object id and attribute id are not same\n");
+ goto err_attr_not_same;
}
- dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
#ifdef DEBUG
- printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+ printf("Init: DPBP id=0x%x\n", dflt_dpbp->dpbp_attr.id);
#endif
err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
return 0;
-err_close:
- free(dflt_dpbp);
err_get_attr:
+err_attr_not_same:
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
- dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+ dpbp_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_id);
+err_get_api_ver:
+err_close:
+err_open:
err_create:
+ free(dflt_dpbp);
err_calloc:
return err;
}
{
int err;
- err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id,
- &dflt_dpbp->dpbp_handle);
- if (err < 0) {
- printf("dpbp_open() failed: %d\n", err);
- goto err;
- }
-
- err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpbp->dpbp_handle);
+ err = dpbp_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_id);
if (err < 0) {
printf("dpbp_destroy() failed: %d\n", err);
goto err;
static int dpni_init(void)
{
int err;
- struct dpni_attr dpni_attr;
- uint8_t ext_cfg_buf[256] = {0};
- struct dpni_extended_cfg dpni_extended_cfg;
+ uint8_t cfg_buf[256] = {0};
struct dpni_cfg dpni_cfg;
+ uint16_t major_ver, minor_ver;
dflt_dpni = (struct fsl_dpni_obj *)calloc(
sizeof(struct fsl_dpni_obj), 1);
goto err_calloc;
}
- memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
- err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]);
+ memset(&dpni_cfg, 0, sizeof(dpni_cfg));
+ err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]);
if (err < 0) {
err = -ENODEV;
- printf("dpni_prepare_extended_cfg() failed: %d\n", err);
- goto err_prepare_extended_cfg;
+ printf("dpni_prepare_cfg() failed: %d\n", err);
+ goto err_prepare_cfg;
}
- memset(&dpni_cfg, 0, sizeof(dpni_cfg));
- dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
- DPNI_OPT_MULTICAST_FILTER;
-
- dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0];
- err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg,
- &dflt_dpni->dpni_handle);
-
+ err = dpni_create(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ &dpni_cfg,
+ &dflt_dpni->dpni_id);
if (err < 0) {
err = -ENODEV;
- printf("dpni_create() failed: %d\n", err);
+ printf("dpni create() failed: %d\n", err);
goto err_create;
}
- memset(&dpni_attr, 0, sizeof(struct dpni_attr));
- err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- &dpni_attr);
+ err = dpni_get_api_version(dflt_mc_io, 0,
+ &major_ver,
+ &minor_ver);
if (err < 0) {
- printf("dpni_get_attributes() failed: %d\n", err);
- goto err_get_attr;
+ printf("dpni_get_api_version() failed: %d\n", err);
+ goto err_get_version;
}
- if ((dpni_attr.version.major != DPNI_VER_MAJOR) ||
- (dpni_attr.version.minor != DPNI_VER_MINOR)) {
+ if (major_ver < DPNI_VER_MAJOR || (major_ver == DPNI_VER_MAJOR &&
+ minor_ver < DPNI_VER_MINOR)) {
printf("DPNI version mismatch found %u.%u,",
- dpni_attr.version.major, dpni_attr.version.minor);
+ major_ver, minor_ver);
printf("supported version is %u.%u\n",
DPNI_VER_MAJOR, DPNI_VER_MINOR);
}
- dflt_dpni->dpni_id = dpni_attr.id;
+ err = dpni_open(dflt_mc_io,
+ MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_id,
+ &dflt_dpni->dpni_handle);
+ if (err) {
+ printf("dpni_open() failed\n");
+ goto err_open;
+ }
+
#ifdef DEBUG
printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
#endif
-
err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_close() failed: %d\n", err);
return 0;
err_close:
-err_get_attr:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
- dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_open:
+err_get_version:
+ dpni_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_id);
err_create:
-err_prepare_extended_cfg:
+err_prepare_cfg:
free(dflt_dpni);
err_calloc:
return err;
{
int err;
- err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
- &dflt_dpni->dpni_handle);
- if (err < 0) {
- printf("dpni_open() failed: %d\n", err);
- goto err;
- }
-
- err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle);
+ err = dpni_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_id);
if (err < 0) {
printf("dpni_destroy() failed: %d\n", err);
goto err;
*/
if (bd && mc_boot_status && !is_dpl_apply_status) {
printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
- return 0;
+ goto mc_obj_cleanup;
}
if (bd && mc_boot_status && is_dpl_apply_status)
return 0;
+mc_obj_cleanup:
err = dpbp_exit();
if (err < 0) {
printf("dpbp_exit() failed: %d\n", err);
#endif
sub_cmd = argv[2][0];
+
switch (sub_cmd) {
case 'm':
if (argc < 5)
/*
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#endif
#ifdef DEBUG
-static void ldpaa_eth_get_dpni_counter(void)
-{
- int err = 0;
- u64 value;
-
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_ING_FRAME,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_ING_FRAME failed\n");
- return;
- }
- printf("DPNI_CNT_ING_FRAME=%lld\n", value);
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_ING_BYTE,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_ING_BYTE failed\n");
- return;
- }
- printf("DPNI_CNT_ING_BYTE=%lld\n", value);
-
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_ING_FRAME_DROP ,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DROP failed\n");
- return;
- }
- printf("DPNI_CNT_ING_FRAME_DROP =%lld\n", value);
-
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_ING_FRAME_DISCARD,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DISCARD failed\n");
- return;
- }
- printf("DPNI_CNT_ING_FRAME_DISCARD=%lld\n", value);
-
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_EGR_FRAME,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_EGR_FRAME failed\n");
- return;
- }
- printf("DPNI_CNT_EGR_FRAME=%lld\n", value);
+#define DPNI_STATS_PER_PAGE 6
+
+static const char *dpni_statistics[][DPNI_STATS_PER_PAGE] = {
+ {
+ "DPNI_CNT_ING_ALL_FRAMES",
+ "DPNI_CNT_ING_ALL_BYTES",
+ "DPNI_CNT_ING_MCAST_FRAMES",
+ "DPNI_CNT_ING_MCAST_BYTES",
+ "DPNI_CNT_ING_BCAST_FRAMES",
+ "DPNI_CNT_ING_BCAST_BYTES",
+ }, {
+ "DPNI_CNT_EGR_ALL_FRAMES",
+ "DPNI_CNT_EGR_ALL_BYTES",
+ "DPNI_CNT_EGR_MCAST_FRAMES",
+ "DPNI_CNT_EGR_MCAST_BYTES",
+ "DPNI_CNT_EGR_BCAST_FRAMES",
+ "DPNI_CNT_EGR_BCAST_BYTES",
+ }, {
+ "DPNI_CNT_ING_FILTERED_FRAMES",
+ "DPNI_CNT_ING_DISCARDED_FRAMES",
+ "DPNI_CNT_ING_NOBUFFER_DISCARDS",
+ "DPNI_CNT_EGR_DISCARDED_FRAMES",
+ "DPNI_CNT_EGR_CNF_FRAMES",
+ ""
+ },
+};
+
+static void print_dpni_stats(const char *strings[],
+ struct dpni_statistics dpni_stats)
+{
+ uint64_t *stat;
+ int i;
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_EGR_BYTE ,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_EGR_BYTE failed\n");
- return;
+ stat = (uint64_t *)&dpni_stats;
+ for (i = 0; i < DPNI_STATS_PER_PAGE; i++) {
+ if (strcmp(strings[i], "\0") == 0)
+ break;
+ printf("%s= %llu\n", strings[i], *stat);
+ stat++;
}
- printf("DPNI_CNT_EGR_BYTE =%lld\n", value);
+}
- err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- DPNI_CNT_EGR_FRAME_DISCARD ,
- &value);
- if (err < 0) {
- printf("dpni_get_counter: DPNI_CNT_EGR_FRAME_DISCARD failed\n");
- return;
+static void ldpaa_eth_get_dpni_counter(void)
+{
+ int err = 0;
+ unsigned int page = 0;
+ struct dpni_statistics dpni_stats;
+
+ printf("DPNI counters ..\n");
+ for (page = 0; page < 3; page++) {
+ err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, page,
+ &dpni_stats);
+ if (err < 0) {
+ printf("dpni_get_statistics: failed:");
+ printf("%d for page[%d]\n", err, page);
+ return;
+ }
+ print_dpni_stats(dpni_statistics[page], dpni_stats);
}
- printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value);
}
static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
return;
}
+ printf("\nDPMAC counters ..\n");
printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
- struct dpni_queue_attr rx_queue_attr;
struct dpmac_link_state dpmac_link_state = { 0 };
#ifdef DEBUG
struct dpni_link_state link_state;
int err = 0;
struct mii_dev *bus;
phy_interface_t enet_if;
+ struct dpni_queue d_queue;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
}
#ifdef DEBUG
+ printf("DPMAC link status: %d - ", dpmac_link_state.up);
+ dpmac_link_state.up == 0 ? printf("down\n") :
+ dpmac_link_state.up == 1 ? printf("up\n") : printf("error state\n");
+
err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, &link_state);
if (err < 0) {
return err;
}
- printf("link status: %d - ", link_state.up);
+ printf("DPNI link status: %d - ", link_state.up);
link_state.up == 0 ? printf("down\n") :
link_state.up == 1 ? printf("up\n") : printf("error state\n");
#endif
- /* TODO: support multiple Rx flows */
- err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr);
+ memset(&d_queue, 0, sizeof(struct dpni_queue));
+ err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, DPNI_QUEUE_RX,
+ 0, 0, &d_queue);
if (err) {
- printf("dpni_get_rx_flow() failed\n");
- goto err_rx_flow;
+ printf("dpni_get_queue failed\n");
+ goto err_get_queue;
}
- priv->rx_dflt_fqid = rx_queue_attr.fqid;
+ priv->rx_dflt_fqid = d_queue.fqid;
err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle,
&priv->tx_qdid);
return priv->phydev->link;
err_qdid:
-err_rx_flow:
+err_get_queue:
dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_bind:
ldpaa_dpbp_free();
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
err_dpamc_bind:
- dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ dpmac_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ dpmac_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS, priv->dpmac_id);
err_dpmac_setup:
return err;
}
if (err < 0)
printf("dprc_disconnect() failed dpmac_endpoint\n");
- err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ err = dpmac_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ if (err < 0)
+ printf("dpmac_close() failed\n");
+
+ err = dpmac_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS,
+ priv->dpmac_id);
if (err < 0)
printf("dpmac_destroy() failed\n");
}
#endif
+ /* Free DPBP handle and reset. */
ldpaa_dpbp_free();
+
dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ if (err < 0)
+ printf("dpni_reset() failed\n");
+
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ if (err < 0)
+ printf("dpni_close() failed\n");
}
static void ldpaa_dpbp_drain_cnt(int count)
}
err = ldpaa_dpbp_seed(dflt_dpbp->dpbp_attr.bpid);
+
if (err) {
printf("Buffer seeding failed for DPBP %d (bpid=%d)\n",
dflt_dpbp->dpbp_attr.id, dflt_dpbp->dpbp_attr.bpid);
static int ldpaa_dpmac_version_check(struct fsl_mc_io *mc_io,
struct ldpaa_eth_priv *priv)
{
- struct dpmac_attr attr;
int error;
-
- memset(&attr, 0, sizeof(struct dpmac_attr));
- error = dpmac_get_attributes(mc_io, MC_CMD_NO_FLAGS,
- priv->dpmac_handle,
- &attr);
- if (error == 0) {
- if ((attr.version.major != DPMAC_VER_MAJOR) ||
- (attr.version.minor != DPMAC_VER_MINOR)) {
- printf("DPMAC version mismatch found %u.%u,",
- attr.version.major, attr.version.minor);
- printf("supported version is %u.%u\n",
- DPMAC_VER_MAJOR, DPMAC_VER_MINOR);
- }
+ uint16_t major_ver, minor_ver;
+
+ error = dpmac_get_api_version(dflt_mc_io, 0,
+ &major_ver,
+ &minor_ver);
+ if ((major_ver < DPMAC_VER_MAJOR) ||
+ (major_ver == DPMAC_VER_MAJOR && minor_ver < DPMAC_VER_MINOR)) {
+ printf("DPMAC version mismatch found %u.%u,",
+ major_ver, minor_ver);
+ printf("supported version is %u.%u\n",
+ DPMAC_VER_MAJOR, DPMAC_VER_MINOR);
+ return error;
}
return error;
struct dpmac_cfg dpmac_cfg;
dpmac_cfg.mac_id = priv->dpmac_id;
- err = dpmac_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpmac_cfg,
- &priv->dpmac_handle);
+
+ err = dpmac_create(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS, &dpmac_cfg,
+ &priv->dpmac_id);
if (err)
printf("dpmac_create() failed\n");
err = ldpaa_dpmac_version_check(dflt_mc_io, priv);
- if (err < 0)
+ if (err < 0) {
printf("ldpaa_dpmac_version_check() failed: %d\n", err);
+ goto err_version_check;
+ }
+
+ err = dpmac_open(dflt_mc_io,
+ MC_CMD_NO_FLAGS,
+ priv->dpmac_id,
+ &priv->dpmac_handle);
+ if (err < 0) {
+ printf("dpmac_open() failed: %d\n", err);
+ goto err_open;
+ }
+
+ return err;
+
+err_open:
+err_version_check:
+ dpmac_destroy(dflt_mc_io,
+ dflt_dprc_handle,
+ MC_CMD_NO_FLAGS, priv->dpmac_id);
return err;
}
printf("dpni_open() failed\n");
goto err_open;
}
-
err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle,
&dflt_dpni->dpni_attrs);
dflt_dpni->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE;
/* HW erratum mandates data alignment in multiples of 256 */
dflt_dpni->buf_layout.data_align = LDPAA_ETH_BUF_ALIGN;
+
/* ...rx, ... */
- err = dpni_set_rx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- &dflt_dpni->buf_layout);
+ err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout, DPNI_QUEUE_RX);
if (err) {
- printf("dpni_set_rx_buffer_layout() failed");
+ printf("dpni_set_buffer_layout() failed");
goto err_buf_layout;
}
/* remove Rx-only options */
dflt_dpni->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
DPNI_BUF_LAYOUT_OPT_PARSER_RESULT);
- err = dpni_set_tx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- &dflt_dpni->buf_layout);
+ err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout, DPNI_QUEUE_TX);
if (err) {
- printf("dpni_set_tx_buffer_layout() failed");
+ printf("dpni_set_buffer_layout() failed");
goto err_buf_layout;
}
/* ... tx-confirm. */
dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
- err = dpni_set_tx_conf_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- &dflt_dpni->buf_layout);
+ err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout,
+ DPNI_QUEUE_TX_CONFIRM);
if (err) {
- printf("dpni_set_tx_conf_buffer_layout() failed");
+ printf("dpni_set_buffer_layout() failed");
goto err_buf_layout;
}
static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
{
struct dpni_pools_cfg pools_params;
- struct dpni_tx_flow_cfg dflt_tx_flow;
- struct dpni_tx_conf_cfg tx_conf_cfg;
+ struct dpni_queue tx_queue;
int err = 0;
memset(&pools_params, 0, sizeof(pools_params));
return err;
}
- priv->tx_flow_id = DPNI_NEW_FLOW_ID;
- memset(&dflt_tx_flow, 0, sizeof(dflt_tx_flow));
+ memset(&tx_queue, 0, sizeof(struct dpni_queue));
+
+ err = dpni_set_queue(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_QUEUE_TX, 0, 0, &tx_queue);
- dflt_tx_flow.use_common_tx_conf_queue = 0;
- err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle, &priv->tx_flow_id,
- &dflt_tx_flow);
if (err) {
- printf("dpni_set_tx_flow() failed\n");
+ printf("dpni_set_queue() failed\n");
return err;
}
- memset(&tx_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg));
- tx_conf_cfg.errors_only = true;
- /*Set tx-conf and error configuration*/
- err = dpni_set_tx_conf(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle,
- priv->tx_flow_id, &tx_conf_cfg);
+ err = dpni_set_tx_confirmation_mode(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CONF_DISABLE);
if (err) {
- printf("dpni_set_tx_conf() failed\n");
+ printf("dpni_set_tx_confirmation_mode() failed\n");
return err;
}
struct ldpaa_eth_priv *priv = NULL;
int err = 0;
-
/* Net device */
net_dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!net_dev) {
/*
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
struct ldpaa_eth_priv {
struct eth_device *net_dev;
- int dpmac_id;
+ uint32_t dpmac_id;
uint16_t dpmac_handle;
uint16_t tx_data_offset;
#include <config.h>
#include <common.h>
#include <linux/bitops.h>
+#include <dm.h>
#include <phy.h>
+/* This function is provided to cope with the possible failures of this phy
+ * during aneg process. When aneg fails, the PHY reports that aneg is done
+ * but the value found in MII_LPA is wrong:
+ * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
+ * the link partner (LP) supports aneg but the LP never acked our base
+ * code word, it is likely that we never sent it to begin with.
+ * - Late failures: MII_LPA is filled with a value which seems to make sense
+ * but it actually is not what the LP is advertising. It seems that we
+ * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
+ * If this particular bit is not set when aneg is reported being done,
+ * it means MII_LPA is likely to be wrong.
+ *
+ * In both case, forcing a restart of the aneg process solve the problem.
+ * When this failure happens, the first retry is usually successful but,
+ * in some cases, it may take up to 6 retries to get a decent result
+ */
+int meson_gxl_startup(struct phy_device *phydev)
+{
+ unsigned int retries = 10;
+ int ret, wol, lpa, exp;
+
+restart_aneg:
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ /* Need to access WOL bank, make sure the access is open */
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ if (ret)
+ return ret;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ if (ret)
+ return ret;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ if (ret)
+ return ret;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ if (ret)
+ return ret;
+
+ /* Request LPI_STATUS WOL register */
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80);
+ if (ret)
+ return ret;
+
+ /* Read LPI_STATUS value */
+ wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
+ if (wol < 0)
+ return wol;
+
+ lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
+ if (exp < 0)
+ return exp;
+
+ if (!(wol & BIT(12)) ||
+ ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
+
+ /* Looks like aneg failed after all */
+ if (!retries) {
+ printf("%s LPA corruption max attempts\n",
+ phydev->dev->name);
+ return -ETIMEDOUT;
+ }
+
+ printf("%s LPA corruption - aneg restart\n",
+ phydev->dev->name);
+
+ ret = genphy_restart_aneg(phydev);
+ if (ret)
+ return ret;
+
+ --retries;
+
+ goto restart_aneg;
+ }
+ }
+
+ return genphy_parse_link(phydev);
+}
+
static int meson_gxl_phy_config(struct phy_device *phydev)
{
/* Enable Analog and DSP register Bank access by */
.mask = 0xfffffff0,
.features = PHY_BASIC_FEATURES,
.config = &meson_gxl_phy_config,
- .startup = &genphy_startup,
+ .startup = &meson_gxl_startup,
.shutdown = &genphy_shutdown,
};
if (ret < 0)
goto err_mdio_alloc;
- gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
- ð->reset_gpio, GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
+ GPIOD_IS_OUT);
mdiodev = mdio_alloc();
if (!mdiodev) {
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
- dm_gpio_free(dev, ð->reset_gpio);
+ if (dm_gpio_is_valid(ð->reset_gpio))
+ dm_gpio_free(dev, ð->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;
static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-r8a7795" },
{ .compatible = "renesas,etheravb-r8a7796" },
+ { .compatible = "renesas,etheravb-r8a77970" },
+ { .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
+#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
+#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
+
/* DMA macros */
/* Bitmasks of XAXIDMA_CR_OFFSET register */
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
phy_interface_t interface;
struct phy_device *phydev;
struct mii_dev *bus;
+ u8 eth_hasnobuf;
};
/* BD descriptors */
u32 timeout = 200;
/* Wait till MDIO interface is ready to accept a new transaction. */
- while (timeout && (!(in_be32(®s->mdio_mcr)
+ while (timeout && (!(readl(®s->mdio_mcr)
& XAE_MDIO_MCR_READY_MASK))) {
timeout--;
udelay(1);
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_READ_MASK;
- out_be32(®s->mdio_mcr, mdioctrlreg);
+ writel(mdioctrlreg, ®s->mdio_mcr);
if (mdio_wait(regs))
return 1;
/* Read data */
- *val = in_be32(®s->mdio_mrd);
+ *val = readl(®s->mdio_mrd);
return 0;
}
XAE_MDIO_MCR_OP_WRITE_MASK;
/* Write data */
- out_be32(®s->mdio_mwd, data);
+ writel(data, ®s->mdio_mwd);
- out_be32(®s->mdio_mcr, mdioctrlreg);
+ writel(mdioctrlreg, ®s->mdio_mcr);
if (mdio_wait(regs))
return 1;
SUPPORTED_1000baseT_Full;
/* Set default MDIO divisor */
- out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+ writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
if (priv->phyaddr == -1) {
/* Detect the PHY address */
}
/* Setup the emac for the phy speed */
- emmc_reg = in_be32(®s->emmc);
+ emmc_reg = readl(®s->emmc);
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
emmc_reg |= speed;
/* Write new speed setting out to Axi Ethernet */
- out_be32(®s->emmc, emmc_reg);
+ writel(emmc_reg, ®s->emmc);
/*
* Setting the operating speed of the MAC needs a delay. There
u32 temp;
/* Stop the hardware */
- temp = in_be32(&priv->dmatx->control);
+ temp = readl(&priv->dmatx->control);
temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
- out_be32(&priv->dmatx->control, temp);
+ writel(temp, &priv->dmatx->control);
- temp = in_be32(&priv->dmarx->control);
+ temp = readl(&priv->dmarx->control);
temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
- out_be32(&priv->dmarx->control, temp);
+ writel(temp, &priv->dmarx->control);
debug("axiemac: Halted\n");
}
static int axi_ethernet_init(struct axidma_priv *priv)
{
struct axi_regs *regs = priv->iobase;
- u32 timeout = 200;
+ int err;
/*
* Check the status of the MgtRdy bit in the interrupt status
* for the Sgmii and 1000BaseX PHY interfaces. No other register reads
* will be valid until this bit is valid.
* The bit is always a 1 for all other PHY interfaces.
+ * Interrupt status and enable registers are not available in non
+ * processor mode and hence bypass in this mode
*/
- while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
- timeout--;
- udelay(1);
- }
- if (!timeout) {
- printf("%s: Timeout\n", __func__);
- return 1;
- }
+ if (!priv->eth_hasnobuf) {
+ err = wait_for_bit(__func__, (const u32 *)®s->is,
+ XAE_INT_MGTRDY_MASK, true, 200, false);
+ if (err) {
+ printf("%s: Timeout\n", __func__);
+ return 1;
+ }
- /* Stop the device and reset HW */
- /* Disable interrupts */
- out_be32(®s->ie, 0);
+ /*
+ * Stop the device and reset HW
+ * Disable interrupts
+ */
+ writel(0, ®s->ie);
+ }
/* Disable the receiver */
- out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
+ writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
/*
* Stopping the receiver in mid-packet causes a dropped packet
* indication from HW. Clear it.
*/
- /* Set the interrupt status register to clear the interrupt */
- out_be32(®s->is, XAE_INT_RXRJECT_MASK);
+ if (!priv->eth_hasnobuf) {
+ /* Set the interrupt status register to clear the interrupt */
+ writel(XAE_INT_RXRJECT_MASK, ®s->is);
+ }
/* Setup HW */
/* Set default MDIO divisor */
- out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+ writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
debug("axiemac: InitHw done\n");
return 0;
/* Set the MAC address */
int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
- out_be32(®s->uaw0, val);
+ writel(val, ®s->uaw0);
val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
- val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
- out_be32(®s->uaw1, val);
+ val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
+ writel(val, ®s->uaw1);
return 0;
}
u32 timeout = 500;
/* Reset the engine so the hardware starts from a known state */
- out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
- out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
+ writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
+ writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
/* At the initialization time, hardware should finish reset quickly */
while (timeout--) {
/* Check transmit/receive channel */
/* Reset is done when the reset bit is low */
- if (!((in_be32(&priv->dmatx->control) |
- in_be32(&priv->dmarx->control))
+ if (!((readl(&priv->dmatx->control) |
+ readl(&priv->dmarx->control))
& XAXIDMA_CR_RESET_MASK)) {
break;
}
return -1;
/* Disable all RX interrupts before RxBD space setup */
- temp = in_be32(&priv->dmarx->control);
+ temp = readl(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
- out_be32(&priv->dmarx->control, temp);
+ writel(temp, &priv->dmarx->control);
/* Start DMA RX channel. Now it's ready to receive data.*/
- out_be32(&priv->dmarx->current, (u32)&rx_bd);
+ writel((u32)&rx_bd, &priv->dmarx->current);
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Start the hardware */
- temp = in_be32(&priv->dmarx->control);
+ temp = readl(&priv->dmarx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
- out_be32(&priv->dmarx->control, temp);
+ writel(temp, &priv->dmarx->control);
/* Rx BD is ready - start */
- out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+ writel((u32)&rx_bd, &priv->dmarx->tail);
/* Enable TX */
- out_be32(®s->tc, XAE_TC_TX_MASK);
+ writel(XAE_TC_TX_MASK, ®s->tc);
/* Enable RX */
- out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
+ writel(XAE_RCW1_RX_MASK, ®s->rcw1);
/* PHY setup */
if (!setup_phy(dev)) {
/* Flush the last BD so DMA core could see the updates */
flush_cache((u32)&tx_bd, sizeof(tx_bd));
- if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
+ if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
- out_be32(&priv->dmatx->current, (u32)&tx_bd);
+ writel((u32)&tx_bd, &priv->dmatx->current);
/* Start the hardware */
- temp = in_be32(&priv->dmatx->control);
+ temp = readl(&priv->dmatx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
- out_be32(&priv->dmatx->control, temp);
+ writel(temp, &priv->dmatx->control);
}
/* Start transfer */
- out_be32(&priv->dmatx->tail, (u32)&tx_bd);
+ writel((u32)&tx_bd, &priv->dmatx->tail);
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
timeout = 200;
- while (timeout && (!(in_be32(&priv->dmatx->status) &
+ while (timeout && (!(readl(&priv->dmatx->status) &
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
timeout--;
udelay(1);
u32 status;
/* Read pending interrupts */
- status = in_be32(&priv->dmarx->status);
+ status = readl(&priv->dmarx->status);
/* Acknowledge pending interrupts */
- out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
+ writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
/*
* If Reception done interrupt is asserted, call RX call back function
debug("axiemac: RX data ready\n");
/* Disable IRQ for a moment till packet is handled */
- temp = in_be32(&priv->dmarx->control);
+ temp = readl(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
- out_be32(&priv->dmarx->control, temp);
+ writel(temp, &priv->dmarx->control);
+ if (!priv->eth_hasnobuf)
+ length = rx_bd.app4 & 0xFFFF; /* max length mask */
+ else
+ length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
- length = rx_bd.app4 & 0xFFFF; /* max length mask */
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
- out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+ writel((u32)&rx_bd, &priv->dmarx->tail);
debug("axiemac: RX completed, framelength = %d\n", length);
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
- priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
- offset, "reg", 0);
+ priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+ offset, "reg");
if (!priv->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
+ priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+ "xlnx,eth-hasnobuf");
+
printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
int phy_of_handle;
struct mii_dev *bus;
struct clk clk;
+ bool int_pcs;
};
static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
nwconfig = ZYNQ_GEM_NWCFG_INIT;
- if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+ /*
+ * Set SGMII enable PCS selection only if internal PCS/PMA
+ * core is used and interface is SGMII.
+ */
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+ priv->int_pcs) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
#ifdef CONFIG_ARM64
}
priv->interface = pdata->phy_interface;
+ priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
+ "is-internal-pcspma");
+
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_ROCKCHIP_RK3128
+ bool "Rockchip rk3128 pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3128 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_ROCKCHIP_RK3188
bool "Rockchip rk3188 pin control driver"
depends on DM
static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
+/* FIXME Before reloaction, BSS is overlapped with DT area */
+static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = {
.flags = ZERO_OFFSET_VALID,
};
{ .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
{ .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
- { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6ul_pinctrl_soc_info },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
{ /* sentinel */ }
};
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A77970
+ bool "Renesas RCar Gen3 R8A77970 pin control driver"
+ def_bool y if R8A77970
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A77995
+ bool "Renesas RCar Gen3 R8A77995 pin control driver"
+ def_bool y if R8A77995
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
endif
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
--- /dev/null
+/*
+ * R8A77970 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
+ SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
+#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
+#define GPSR0_17 F_(DU_DB7, IP2_7_4)
+#define GPSR0_16 F_(DU_DB6, IP2_3_0)
+#define GPSR0_15 F_(DU_DB5, IP1_31_28)
+#define GPSR0_14 F_(DU_DB4, IP1_27_24)
+#define GPSR0_13 F_(DU_DB3, IP1_23_20)
+#define GPSR0_12 F_(DU_DB2, IP1_19_16)
+#define GPSR0_11 F_(DU_DG7, IP1_15_12)
+#define GPSR0_10 F_(DU_DG6, IP1_11_8)
+#define GPSR0_9 F_(DU_DG5, IP1_7_4)
+#define GPSR0_8 F_(DU_DG4, IP1_3_0)
+#define GPSR0_7 F_(DU_DG3, IP0_31_28)
+#define GPSR0_6 F_(DU_DG2, IP0_27_24)
+#define GPSR0_5 F_(DU_DR7, IP0_23_20)
+#define GPSR0_4 F_(DU_DR6, IP0_19_16)
+#define GPSR0_3 F_(DU_DR5, IP0_15_12)
+#define GPSR0_2 F_(DU_DR4, IP0_11_8)
+#define GPSR0_1 F_(DU_DR3, IP0_7_4)
+#define GPSR0_0 F_(DU_DR2, IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
+#define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
+#define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
+#define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
+#define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
+#define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
+#define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
+#define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
+#define GPSR1_19 FM(AVB0_AVTP_MATCH)
+#define GPSR1_18 FM(AVB0_LINK)
+#define GPSR1_17 FM(AVB0_PHY_INT)
+#define GPSR1_16 FM(AVB0_MAGIC)
+#define GPSR1_15 FM(AVB0_MDC)
+#define GPSR1_14 FM(AVB0_MDIO)
+#define GPSR1_13 FM(AVB0_TXCREFCLK)
+#define GPSR1_12 FM(AVB0_TD3)
+#define GPSR1_11 FM(AVB0_TD2)
+#define GPSR1_10 FM(AVB0_TD1)
+#define GPSR1_9 FM(AVB0_TD0)
+#define GPSR1_8 FM(AVB0_TXC)
+#define GPSR1_7 FM(AVB0_TX_CTL)
+#define GPSR1_6 FM(AVB0_RD3)
+#define GPSR1_5 FM(AVB0_RD2)
+#define GPSR1_4 FM(AVB0_RD1)
+#define GPSR1_3 FM(AVB0_RD0)
+#define GPSR1_2 FM(AVB0_RXC)
+#define GPSR1_1 FM(AVB0_RX_CTL)
+#define GPSR1_0 F_(IRQ0, IP2_27_24)
+
+/* GPSR2 */
+#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
+#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
+#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
+#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
+#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
+#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
+#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
+#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
+#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
+#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
+#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
+#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
+#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
+#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
+#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
+#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
+#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
+
+/* GPSR3 */
+#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
+#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
+#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
+#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
+#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
+#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
+#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
+#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
+#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
+#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
+#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
+#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
+#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
+#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
+#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
+#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
+#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
+
+/* GPSR4 */
+#define GPSR4_5 F_(SDA2, IP7_27_24)
+#define GPSR4_4 F_(SCL2, IP7_23_20)
+#define GPSR4_3 F_(SDA1, IP7_19_16)
+#define GPSR4_2 F_(SCL1, IP7_15_12)
+#define GPSR4_1 F_(SDA0, IP7_11_8)
+#define GPSR4_0 F_(SCL0, IP7_7_4)
+
+/* GPSR5 */
+#define GPSR5_14 FM(RPC_INT_N)
+#define GPSR5_13 FM(RPC_WP_N)
+#define GPSR5_12 FM(RPC_RESET_N)
+#define GPSR5_11 FM(QSPI1_SSL)
+#define GPSR5_10 FM(QSPI1_IO3)
+#define GPSR5_9 FM(QSPI1_IO2)
+#define GPSR5_8 FM(QSPI1_MISO_IO1)
+#define GPSR5_7 FM(QSPI1_MOSI_IO0)
+#define GPSR5_6 FM(QSPI1_SPCLK)
+#define GPSR5_5 FM(QSPI0_SSL)
+#define GPSR5_4 FM(QSPI0_IO3)
+#define GPSR5_3 FM(QSPI0_IO2)
+#define GPSR5_2 FM(QSPI0_MISO_IO1)
+#define GPSR5_1 FM(QSPI0_MOSI_IO0)
+#define GPSR5_0 FM(QSPI0_SPCLK)
+
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C */ /* D */ /* E */ /* F */
+#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N_A26) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR1_27 \
+ GPSR1_26 \
+ GPSR1_25 \
+ GPSR1_24 \
+ GPSR1_23 \
+ GPSR1_22 \
+GPSR0_21 GPSR1_21 \
+GPSR0_20 GPSR1_20 \
+GPSR0_19 GPSR1_19 \
+GPSR0_18 GPSR1_18 \
+GPSR0_17 GPSR1_17 \
+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 \
+FM(IP8_7_4) IP8_7_4 \
+FM(IP8_11_8) IP8_11_8 \
+FM(IP8_15_12) IP8_15_12 \
+FM(IP8_19_16) IP8_19_16 \
+FM(IP8_23_20) IP8_23_20 \
+FM(IP8_27_24) IP8_27_24 \
+FM(IP8_31_28) IP8_31_28
+
+/*
+ Set Value = H'0 Set Value = H'1
+Register Function Pin Function Pin
+------------------------------------------------------------
+sel_i2c3 SDA3_A VI0_DATA2 SDA3_B VI1_DATA10
+ SCL3_A VI0_DATA3 SCL3_B VI1_DATA9
+sel_hscif0 HSCIF0_A SCIF_CLK HSCIF0_B SCIF_CLK
+sel_scif1 SCIF1_A RX1 SCIF1_B TX1
+ SCIF1_A TX1 SCIF1_B RX1
+sel_canfd0 CANFD0_A CANFD0_TX CANFD0_B CANFD0_TX
+ CANFD0_A CANFD0_RX CANFD0_B CANFD0_RX
+ CANFD0_A CANFD_CLK CANFD0_B CANFD_CLK
+sel_pwm4 PWM4_A PWM4 PWM4_B PWM4
+sel_pwm3 PWM3_A PWM3 PWM3_B PWM3
+sel_pwm2 PWM2_A PWM2 PWM2_B PWM2
+sel_pwm1 PWM1_A PWM1 PWM1_B PWM1
+sel_pwm0 PWM0_A PWM0 PWM0_B PWM0
+sel_rfso RFSO_A FSO_CFE_0_N RFSO_B FSO_CFE_0_N
+ RFSO_A FSO_CFE_1_N RFSO_B FSO_CFE_1_N
+ RFSO_A FSO_TOE_N RFSO_B FSO_TOE_N
+sel_rsp RSP_A SPEEDIN RSP_B SPEEDIN
+sel_tmu TMU_A TCLK1 TMU_B TCLK1
+ TMU_A TCLK2 TMU_B TCLK2
+*/
+/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
+#define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
+#define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
+#define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
+#define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
+#define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
+#define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
+#define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
+#define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
+#define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
+#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_9 \
+MOD_SEL0_8 \
+MOD_SEL0_7 \
+MOD_SEL0_6 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_3 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(AVB0_RX_CTL),
+ PINMUX_SINGLE(AVB0_RXC),
+ PINMUX_SINGLE(AVB0_RD0),
+ PINMUX_SINGLE(AVB0_RD1),
+ PINMUX_SINGLE(AVB0_RD2),
+ PINMUX_SINGLE(AVB0_RD3),
+ PINMUX_SINGLE(AVB0_TX_CTL),
+ PINMUX_SINGLE(AVB0_TXC),
+ PINMUX_SINGLE(AVB0_TD0),
+ PINMUX_SINGLE(AVB0_TD1),
+ PINMUX_SINGLE(AVB0_TD2),
+ PINMUX_SINGLE(AVB0_TD3),
+ PINMUX_SINGLE(AVB0_TXCREFCLK),
+ PINMUX_SINGLE(AVB0_MDIO),
+ PINMUX_SINGLE(AVB0_MDC),
+ PINMUX_SINGLE(AVB0_MAGIC),
+ PINMUX_SINGLE(AVB0_PHY_INT),
+ PINMUX_SINGLE(AVB0_LINK),
+ PINMUX_SINGLE(AVB0_AVTP_MATCH),
+
+ PINMUX_SINGLE(QSPI0_SPCLK),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(RPC_WP_N),
+ PINMUX_SINGLE(RPC_INT_N),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
+ PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
+ PINMUX_IPSR_GPSR(IP0_3_0, A0),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
+ PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
+ PINMUX_IPSR_GPSR(IP0_7_4, A1),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
+ PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
+ PINMUX_IPSR_GPSR(IP0_11_8, A2),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
+ PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
+ PINMUX_IPSR_GPSR(IP0_15_12, A3),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
+ PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
+ PINMUX_IPSR_GPSR(IP0_19_16, A4),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
+ PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
+ PINMUX_IPSR_GPSR(IP0_23_20, A5),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
+ PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
+ PINMUX_IPSR_GPSR(IP0_27_24, A6),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
+ PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
+ PINMUX_IPSR_GPSR(IP0_31_28, A7),
+ PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
+ PINMUX_IPSR_GPSR(IP1_3_0, A8),
+ PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
+ PINMUX_IPSR_GPSR(IP1_7_4, A9),
+ PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
+ PINMUX_IPSR_GPSR(IP1_11_8, A10),
+ PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
+ PINMUX_IPSR_GPSR(IP1_15_12, A11),
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
+ PINMUX_IPSR_GPSR(IP1_19_16, A12),
+ PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
+ PINMUX_IPSR_GPSR(IP1_23_20, A13),
+ PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
+ PINMUX_IPSR_GPSR(IP1_27_24, A14),
+ PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
+ PINMUX_IPSR_GPSR(IP1_31_28, A15),
+ PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2_3_0, A16),
+ PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2_7_4, A17),
+ PINMUX_IPSR_GPSR(IP2_7_4, STPWT_EXTFXR),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
+ PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP2_11_8, A18),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
+ PINMUX_IPSR_GPSR(IP2_15_12, A19),
+ PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
+ PINMUX_IPSR_GPSR(IP2_19_16, A20),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
+ PINMUX_IPSR_GPSR(IP2_23_20, A21),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
+ PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP3_3_0, RX3),
+ PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP3_7_4, TX3),
+ PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
+ PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
+ PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
+ PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_1),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
+ PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP3_23_20, SDA3_A),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
+ PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
+ PINMUX_IPSR_GPSR(IP3_27_24, SCL3_A),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
+ PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
+ PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
+ PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
+ PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
+ PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
+ PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
+ PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
+ PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
+ PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
+ PINMUX_IPSR_GPSR(IP4_15_12, A22),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
+ PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
+ PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
+ PINMUX_IPSR_GPSR(IP4_19_16, A23),
+ PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
+ PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
+ PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
+ PINMUX_IPSR_GPSR(IP4_23_20, A24),
+ PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
+ PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
+ PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
+ PINMUX_IPSR_GPSR(IP4_27_24, A25),
+ PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
+ PINMUX_IPSR_GPSR(IP4_31_28, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP5_7_4, D0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP5_11_8, D1),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP5_15_12, D2),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP5_19_16, D3),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP5_23_20, D4),
+ PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
+ PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_27_24, D5),
+ PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
+ PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_31_28, D6),
+ PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
+ PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP6_3_0, D7),
+ PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
+ PINMUX_IPSR_GPSR(IP6_7_4, D8),
+ PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP6_11_8, RX4),
+ PINMUX_IPSR_GPSR(IP6_11_8, D9),
+ PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP6_15_12, TX4),
+ PINMUX_IPSR_GPSR(IP6_15_12, D10),
+ PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
+ PINMUX_IPSR_GPSR(IP6_19_16, D11),
+ PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
+ PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
+ PINMUX_IPSR_GPSR(IP6_23_20, D12),
+ PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
+ PINMUX_IPSR_GPSR(IP6_23_20, SCL3_B),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
+ PINMUX_IPSR_GPSR(IP6_27_24, D13),
+ PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
+ PINMUX_IPSR_GPSR(IP6_27_24, SDA3_B),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
+ PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
+ PINMUX_IPSR_GPSR(IP6_31_28, D14),
+ PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
+ PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
+ PINMUX_IPSR_GPSR(IP7_3_0, D15),
+ PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
+ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
+ PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
+ PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
+ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
+ PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
+ PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
+ PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
+ PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
+ PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
+ PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
+ PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
+ PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
+ PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
+ PINMUX_IPSR_GPSR(IP7_23_20, RX0),
+ PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
+ PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
+ PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP7_27_24, TX0),
+ PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
+
+ /* IPSR8 */
+ PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
+ PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
+ PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
+ PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
+
+ PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
+
+ PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
+ PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb0_rx_ctrl_pins[] = {
+ /* AVB0_RX_CTL */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int avb0_rx_ctrl_mux[] = {
+ AVB0_RX_CTL_MARK,
+};
+static const unsigned int avb0_rxc_pins[] = {
+ /* AVB0_RXC */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int avb0_rxc_mux[] = {
+ AVB0_RXC_MARK,
+};
+static const unsigned int avb0_rd0_pins[] = {
+ /* AVB0_RD[0] */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int avb0_rd0_mux[] = {
+ AVB0_RD0_MARK,
+};
+static const unsigned int avb0_rd1_pins[] = {
+ /* AVB0_RD[1] */
+ RCAR_GP_PIN(1, 4),
+};
+static const unsigned int avb0_rd1_mux[] = {
+ AVB0_RD1_MARK,
+};
+static const unsigned int avb0_rd2_pins[] = {
+ /* AVB0_RD[2] */
+ RCAR_GP_PIN(1, 5),
+};
+static const unsigned int avb0_rd2_mux[] = {
+ AVB0_RD2_MARK,
+};
+static const unsigned int avb0_rd3_pins[] = {
+ /* AVB0_RD[3] */
+ RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb0_rd3_mux[] = {
+ AVB0_RD3_MARK,
+};
+static const unsigned int avb0_rd4_pins[] = {
+ /* AVB0_RD[3:0] */
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb0_rd4_mux[] = {
+ AVB0_RD0_MARK, AVB0_RD1_MARK,
+ AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_tx_ctrl_pins[] = {
+ /* AVB0_TX_CTL */
+ RCAR_GP_PIN(1, 7),
+};
+static const unsigned int avb0_tx_ctrl_mux[] = {
+ AVB0_TX_CTL_MARK,
+};
+static const unsigned int avb0_txc_pins[] = {
+ /* AVB0_TXC */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int avb0_txc_mux[] = {
+ AVB0_TXC_MARK,
+};
+static const unsigned int avb0_td0_pins[] = {
+ /* AVB0_TD[0] */
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int avb0_td0_mux[] = {
+ AVB0_TD0_MARK,
+};
+static const unsigned int avb0_td1_pins[] = {
+ /* AVB0_TD[1] */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int avb0_td1_mux[] = {
+ AVB0_TD1_MARK,
+};
+static const unsigned int avb0_td2_pins[] = {
+ /* AVB0_TD[2] */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int avb0_td2_mux[] = {
+ AVB0_TD2_MARK,
+};
+static const unsigned int avb0_td3_pins[] = {
+ /* AVB0_TD[3] */
+ RCAR_GP_PIN(1, 12),
+};
+static const unsigned int avb0_td3_mux[] = {
+ AVB0_TD3_MARK,
+};
+static const unsigned int avb0_td4_pins[] = {
+ /* AVB0_TD[3:0] */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int avb0_td4_mux[] = {
+ AVB0_TD0_MARK, AVB0_TD1_MARK,
+ AVB0_TD2_MARK, AVB0_TD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDIO */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_mdc_pins[] = {
+ /* AVB0_MDC */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int avb0_mdc_mux[] = {
+ AVB0_MDC_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd_clk_a_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int canfd_clk_a_mux[] = {
+ CANFD_CLK_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+static const unsigned int canfd_clk_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd_clk_b_mux[] = {
+ CANFD_CLK_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:0] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ /* G[7:0] */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ /* B[7:0] */
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+ RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK,
+ DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK,
+ DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK,
+ DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT0 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_clk_out_1_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(0, 18), /* @@ */
+};
+static const unsigned int du_clk_out_1_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* EXDISP/EXODDF/EXCDE */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int scif_clk_a_mux[] = {
+ SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+static const unsigned int i2c3_pins[] = {
+ /* SDA3_A, SCL3_A */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_A_MARK, SCL3_A_MARK,
+};
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(0, 11),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(4, 0),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int pwm0_a_mux[] = {
+ PWM0_A_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_a_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_a_mux[] = {
+ PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_a_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_a_mux[] = {
+ PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_TANS_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_TANS_MARK, CTS4_N_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int mmc_cd_mux[] = {
+ MMC_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int mmc_wp_mux[] = {
+ MMC_WP_MARK,
+};
+
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int vin0_data8_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+};
+static const unsigned int vin0_data10_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data10_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+};
+static const unsigned int vin0_data12_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int vin0_data12_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ /* VSYNC_N, HSYNC_N */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int vin1_data8_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+};
+static const unsigned int vin1_data10_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int vin1_data10_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+};
+static const unsigned int vin1_data12_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int vin1_data12_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+ VI1_DATA10_MARK, VI1_DATA11_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ /* VSYNC_N, HSYNC_N */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_rx_ctrl),
+ SH_PFC_PIN_GROUP(avb0_rxc),
+ SH_PFC_PIN_GROUP(avb0_rd0),
+ SH_PFC_PIN_GROUP(avb0_rd1),
+ SH_PFC_PIN_GROUP(avb0_rd2),
+ SH_PFC_PIN_GROUP(avb0_rd3),
+ SH_PFC_PIN_GROUP(avb0_rd4),
+ SH_PFC_PIN_GROUP(avb0_tx_ctrl),
+ SH_PFC_PIN_GROUP(avb0_txc),
+ SH_PFC_PIN_GROUP(avb0_td0),
+ SH_PFC_PIN_GROUP(avb0_td1),
+ SH_PFC_PIN_GROUP(avb0_td2),
+ SH_PFC_PIN_GROUP(avb0_td3),
+ SH_PFC_PIN_GROUP(avb0_td4),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_mdc),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd_clk_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd_clk_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(vin0_data8),
+ SH_PFC_PIN_GROUP(vin0_data10),
+ SH_PFC_PIN_GROUP(vin0_data12),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ SH_PFC_PIN_GROUP(vin1_data8),
+ SH_PFC_PIN_GROUP(vin1_data10),
+ SH_PFC_PIN_GROUP(vin1_data12),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+};
+
+static const char * const avb0_groups[] = {
+ "avb0_rx_ctrl",
+ "avb0_rxc",
+ "avb0_rd1",
+ "avb0_rd4",
+ "avb0_tx_ctrl",
+ "avb0_txc",
+ "avb0_td1",
+ "avb0_td4",
+ "avb0_txcrefclk",
+ "avb0_mdio",
+ "avb0_mdc",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_link",
+ "avb0_avtp_match",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data_a",
+ "canfd_clk_a",
+ "canfd0_data_b",
+ "canfd_clk_b",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_clk_out_0",
+ "du_clk_out_1",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk_a",
+ "scif_clk_b",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0_a",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1_a",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2_a",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3_a",
+ "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4_a",
+ "pwm4_b",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+// "scif0_clk",
+// "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+};
+
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data8",
+ "vin0_data10",
+ "vin0_data12",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data8",
+ "vin1_data10",
+ "vin1_data12",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+#define POCCTRL0 0x380
+#define POCCTRL1 0x384
+#define PIN2POCCTRL0_SHIFT(a) ({ \
+ int _gp = (a) >> 5; \
+ int _bit = (a) & 0x1f; \
+ ((_gp == 3) && (_bit < 17)) ? _bit + 7 : -1; \
+})
+
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_21_FN, GPSR0_21,
+ GP_0_20_FN, GPSR0_20,
+ GP_0_19_FN, GPSR0_19,
+ GP_0_18_FN, GPSR0_18,
+ GP_0_17_FN, GPSR0_17,
+ GP_0_16_FN, GPSR0_16,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_16_FN, GPSR3_16,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) {
+ /* RESERVED 31..12 */
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MOD_SEL0_11
+ MOD_SEL0_10
+ MOD_SEL0_9
+ MOD_SEL0_8
+ MOD_SEL0_7
+ MOD_SEL0_6
+ MOD_SEL0_5
+ MOD_SEL0_4
+ MOD_SEL0_3
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 }
+ },
+ { },
+};
+
+static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = 0xe6060384;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+ bit = (pin & 0x1f) + 7;
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations pinmux_ops = {
+ .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a77970_pinmux_info = {
+ .name = "r8a77970_pfc",
+ .ops = &pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
--- /dev/null
+/*
+ * R8A77995 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_9(0, fn, sfx), \
+ PORT_GP_32(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_21(5, fn, sfx), \
+ PORT_GP_14(6, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
+#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
+#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
+#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
+#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
+#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
+#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
+#define GPSR0_1 FM(USB0_OVC)
+#define GPSR0_0 FM(USB0_PWEN)
+
+/* GPSR1 */
+#define GPSR1_31 F_(QPOLB, IP4_27_24)
+#define GPSR1_30 F_(QPOLA, IP4_23_20)
+#define GPSR1_29 F_(DU_CDE, IP4_19_16)
+#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
+#define GPSR1_27 F_(DU_DISP, IP4_11_8)
+#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
+#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
+#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
+#define GPSR1_23 F_(DU_DR7, IP3_27_24)
+#define GPSR1_22 F_(DU_DR6, IP3_23_20)
+#define GPSR1_21 F_(DU_DR5, IP3_19_16)
+#define GPSR1_20 F_(DU_DR4, IP3_15_12)
+#define GPSR1_19 F_(DU_DR3, IP3_11_8)
+#define GPSR1_18 F_(DU_DR2, IP3_7_4)
+#define GPSR1_17 F_(DU_DR1, IP3_3_0)
+#define GPSR1_16 F_(DU_DR0, IP2_31_28)
+#define GPSR1_15 F_(DU_DG7, IP2_27_24)
+#define GPSR1_14 F_(DU_DG6, IP2_23_20)
+#define GPSR1_13 F_(DU_DG5, IP2_19_16)
+#define GPSR1_12 F_(DU_DG4, IP2_15_12)
+#define GPSR1_11 F_(DU_DG3, IP2_11_8)
+#define GPSR1_10 F_(DU_DG2, IP2_7_4)
+#define GPSR1_9 F_(DU_DG1, IP2_3_0)
+#define GPSR1_8 F_(DU_DG0, IP1_31_28)
+#define GPSR1_7 F_(DU_DB7, IP1_27_24)
+#define GPSR1_6 F_(DU_DB6, IP1_23_20)
+#define GPSR1_5 F_(DU_DB5, IP1_19_16)
+#define GPSR1_4 F_(DU_DB4, IP1_15_12)
+#define GPSR1_3 F_(DU_DB3, IP1_11_8)
+#define GPSR1_2 F_(DU_DB2, IP1_7_4)
+#define GPSR1_1 F_(DU_DB1, IP1_3_0)
+#define GPSR1_0 F_(DU_DB0, IP0_31_28)
+
+/* GPSR2 */
+#define GPSR2_31 F_(NFCE_N, IP8_19_16)
+#define GPSR2_30 F_(NFCLE, IP8_15_12)
+#define GPSR2_29 F_(NFALE, IP8_11_8)
+#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
+#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
+#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
+#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
+#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
+#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
+#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
+#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
+#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
+#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
+#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
+#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
+#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
+#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
+#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
+#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
+#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
+#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
+#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
+#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
+#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
+#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
+#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
+#define GPSR2_5 FM(VI4_DATA4)
+#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
+#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
+#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
+#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
+#define GPSR2_0 FM(VI4_CLK)
+
+/* GPSR3 */
+#define GPSR3_9 F_(NFDATA7, IP9_31_28)
+#define GPSR3_8 F_(NFDATA6, IP9_27_24)
+#define GPSR3_7 F_(NFDATA5, IP9_23_20)
+#define GPSR3_6 F_(NFDATA4, IP9_19_16)
+#define GPSR3_5 F_(NFDATA3, IP9_15_12)
+#define GPSR3_4 F_(NFDATA2, IP9_11_8)
+#define GPSR3_3 F_(NFDATA1, IP9_7_4)
+#define GPSR3_2 F_(NFDATA0, IP9_3_0)
+#define GPSR3_1 F_(NFWE_N, IP8_31_28)
+#define GPSR3_0 F_(NFRE_N, IP8_27_24)
+
+/* GPSR4 */
+#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
+#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
+#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
+#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
+#define GPSR4_27 FM(TX2)
+#define GPSR4_26 FM(RX2)
+#define GPSR4_25 F_(SCK2, IP12_11_8)
+#define GPSR4_24 F_(TX1_A, IP12_7_4)
+#define GPSR4_23 F_(RX1_A, IP12_3_0)
+#define GPSR4_22 F_(SCK1_A, IP11_31_28)
+#define GPSR4_21 F_(TX0_A, IP11_27_24)
+#define GPSR4_20 F_(RX0_A, IP11_23_20)
+#define GPSR4_19 F_(SCK0_A, IP11_19_16)
+#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
+#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
+#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
+#define GPSR4_15 FM(MSIOF0_RXD)
+#define GPSR4_14 FM(MSIOF0_TXD)
+#define GPSR4_13 FM(MSIOF0_SYNC)
+#define GPSR4_12 FM(MSIOF0_SCK)
+#define GPSR4_11 F_(SDA1, IP11_3_0)
+#define GPSR4_10 F_(SCL1, IP10_31_28)
+#define GPSR4_9 FM(SDA0)
+#define GPSR4_8 FM(SCL0)
+#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
+#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
+#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
+#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
+#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
+#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
+#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
+#define GPSR4_0 F_(NFRB_N, IP8_23_20)
+
+/* GPSR5 */
+#define GPSR5_20 FM(AVB0_LINK)
+#define GPSR5_19 FM(AVB0_PHY_INT)
+#define GPSR5_18 FM(AVB0_MAGIC)
+#define GPSR5_17 FM(AVB0_MDC)
+#define GPSR5_16 FM(AVB0_MDIO)
+#define GPSR5_15 FM(AVB0_TXCREFCLK)
+#define GPSR5_14 FM(AVB0_TD3)
+#define GPSR5_13 FM(AVB0_TD2)
+#define GPSR5_12 FM(AVB0_TD1)
+#define GPSR5_11 FM(AVB0_TD0)
+#define GPSR5_10 FM(AVB0_TXC)
+#define GPSR5_9 FM(AVB0_TX_CTL)
+#define GPSR5_8 FM(AVB0_RD3)
+#define GPSR5_7 FM(AVB0_RD2)
+#define GPSR5_6 FM(AVB0_RD1)
+#define GPSR5_5 FM(AVB0_RD0)
+#define GPSR5_4 FM(AVB0_RXC)
+#define GPSR5_3 FM(AVB0_RX_CTL)
+#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
+#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
+#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
+
+/* GPSR6 */
+#define GPSR6_13 FM(RPC_INT_N)
+#define GPSR6_12 FM(RPC_RESET_N)
+#define GPSR6_11 FM(QSPI1_SSL)
+#define GPSR6_10 FM(QSPI1_IO3)
+#define GPSR6_9 FM(QSPI1_IO2)
+#define GPSR6_8 FM(QSPI1_MISO_IO1)
+#define GPSR6_7 FM(QSPI1_MOSI_IO0)
+#define GPSR6_6 FM(QSPI1_SPCLK)
+#define GPSR6_5 FM(QSPI0_SSL)
+#define GPSR6_4 FM(QSPI0_IO3)
+#define GPSR6_3 FM(QSPI0_IO2)
+#define GPSR6_2 FM(QSPI0_MISO_IO1)
+#define GPSR6_1 FM(QSPI0_MOSI_IO0)
+#define GPSR6_0 FM(QSPI0_SPCLK)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR1_31 GPSR2_31 GPSR4_31 \
+ GPSR1_30 GPSR2_30 GPSR4_30 \
+ GPSR1_29 GPSR2_29 GPSR4_29 \
+ GPSR1_28 GPSR2_28 GPSR4_28 \
+ GPSR1_27 GPSR2_27 GPSR4_27 \
+ GPSR1_26 GPSR2_26 GPSR4_26 \
+ GPSR1_25 GPSR2_25 GPSR4_25 \
+ GPSR1_24 GPSR2_24 GPSR4_24 \
+ GPSR1_23 GPSR2_23 GPSR4_23 \
+ GPSR1_22 GPSR2_22 GPSR4_22 \
+ GPSR1_21 GPSR2_21 GPSR4_21 \
+ GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
+ GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
+ GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
+ GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
+ GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
+ GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
+ GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
+ GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
+ GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
+ GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
+ GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
+ GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
+FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
+FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
+FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
+FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
+\
+FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
+FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
+FM(IP12_11_8) IP12_11_8 \
+FM(IP12_15_12) IP12_15_12 \
+FM(IP12_19_16) IP12_19_16 \
+FM(IP12_23_20) IP12_23_20 \
+FM(IP12_27_24) IP12_27_24 \
+FM(IP12_31_28) IP12_31_28 \
+
+/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
+#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
+#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
+#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
+#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
+#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
+#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
+#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
+#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
+#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
+#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
+#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
+#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
+#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
+#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
+#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
+#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
+#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
+#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
+#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
+#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
+#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
+
+#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
+#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
+#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
+#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
+#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
+#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
+
+
+#define PINMUX_MOD_SELS \
+\
+ MOD_SEL1_31 \
+MOD_SEL0_30 MOD_SEL1_30 \
+MOD_SEL0_29 MOD_SEL1_29 \
+MOD_SEL0_28 MOD_SEL1_28 \
+MOD_SEL0_27 MOD_SEL1_27 \
+MOD_SEL0_26 MOD_SEL1_26 \
+MOD_SEL0_25 \
+MOD_SEL0_24_23 \
+MOD_SEL0_22_21 \
+MOD_SEL0_20_19 \
+MOD_SEL0_18_17 \
+MOD_SEL0_15 \
+MOD_SEL0_14 \
+MOD_SEL0_13 \
+MOD_SEL0_12 \
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_3 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+ PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+ PINMUX_DATA(fn##_MARK, FN_##msel)
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(USB0_OVC),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(VI4_DATA4),
+ PINMUX_SINGLE(VI4_CLK),
+ PINMUX_SINGLE(TX2),
+ PINMUX_SINGLE(RX2),
+ PINMUX_SINGLE(AVB0_LINK),
+ PINMUX_SINGLE(AVB0_PHY_INT),
+ PINMUX_SINGLE(AVB0_MAGIC),
+ PINMUX_SINGLE(AVB0_MDC),
+ PINMUX_SINGLE(AVB0_MDIO),
+ PINMUX_SINGLE(AVB0_TXCREFCLK),
+ PINMUX_SINGLE(AVB0_TD3),
+ PINMUX_SINGLE(AVB0_TD2),
+ PINMUX_SINGLE(AVB0_TD1),
+ PINMUX_SINGLE(AVB0_TD0),
+ PINMUX_SINGLE(AVB0_TXC),
+ PINMUX_SINGLE(AVB0_TX_CTL),
+ PINMUX_SINGLE(AVB0_RD3),
+ PINMUX_SINGLE(AVB0_RD2),
+ PINMUX_SINGLE(AVB0_RD1),
+ PINMUX_SINGLE(AVB0_RD0),
+ PINMUX_SINGLE(AVB0_RXC),
+ PINMUX_SINGLE(AVB0_RX_CTL),
+ PINMUX_SINGLE(RPC_INT_N),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_SPCLK),
+
+ /* IPSR0 */
+ PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
+ PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
+ PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
+ PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
+ PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
+ PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
+ PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
+ PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
+ PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
+ PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
+ PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
+ PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
+ PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
+ PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
+ PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
+ PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
+ PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
+ PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
+ PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
+ PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
+ PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
+ PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
+ PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
+ PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
+ PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
+ PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
+ PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
+ PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
+ PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
+ PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
+ PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
+ PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
+ PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
+ PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
+ PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
+ PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
+ PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
+ PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
+ PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
+ PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
+ PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
+ PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
+ PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
+ PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP3_19_16, NMI),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
+ PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
+ PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
+ PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
+ PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
+ PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
+ PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
+ PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
+ PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
+ PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
+ PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
+ PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
+ PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
+ PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
+ PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
+ PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
+ PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
+ PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
+ PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
+ PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
+ PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
+ PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
+ PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
+ PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
+ PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
+ PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
+ PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
+ PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
+ PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
+ PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
+ PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
+ PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
+ PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
+ PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
+ PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
+ PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
+ PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
+ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
+ PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
+ PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
+ PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
+ PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
+ PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
+ PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
+
+ PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
+ PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
+ PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
+
+ PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
+ PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
+ PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
+ PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
+ PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
+ PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
+ PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
+ PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
+ PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
+
+ PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
+ PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
+ PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
+ PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
+ PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
+ PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
+
+ PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
+ PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
+ PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
+
+ PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
+ PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
+ PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
+ PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
+ PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
+ PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
+
+ PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
+ PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
+
+ PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
+ PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
+
+ PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
+ PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
+
+ /* IPSR11 */
+ PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
+ PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
+
+ PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
+ PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
+ PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
+ PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
+ PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
+ PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
+ PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
+ PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
+
+ /* IPSR12 */
+ PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
+ PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
+
+ PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
+
+ PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
+ PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
+
+ PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
+ PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
+
+ PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
+ PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
+
+ PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
+ PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
+
+ PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
+ PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
+
+ PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
+ PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
+
+ PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int i2c0_mux[] = {
+ SCL0_MARK, SDA0_MARK,
+};
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int i2c1_mux[] = {
+ SCL1_MARK, SDA1_MARK,
+};
+static const unsigned int i2c2_a_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+};
+static const unsigned int i2c2_a_mux[] = {
+ SCL2_A_MARK, SDA2_A_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
+};
+static const unsigned int i2c2_b_mux[] = {
+ SCL2_B_MARK, SDA2_B_MARK,
+};
+static const unsigned int i2c3_a_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int i2c3_a_mux[] = {
+ SCL3_A_MARK, SDA3_A_MARK,
+};
+static const unsigned int i2c3_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int i2c3_b_mux[] = {
+ SCL3_B_MARK, SDA3_B_MARK,
+};
+
+/* - MMC ------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scif0_data_a_mux[] = {
+ RX0_A_MARK, TX0_A_MARK,
+};
+static const unsigned int scif0_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int scif0_clk_a_mux[] = {
+ SCK0_A_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif0_clk_b_mux[] = {
+ SCK0_B_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int scif1_clk_a_mux[] = {
+ SCK1_A_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 25),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCK1_B_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 25),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
+};
+static const unsigned int scif3_data_a_mux[] = {
+ RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int scif3_clk_a_mux[] = {
+ SCK3_A_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 29),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCK3_B_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scif4_data_a_mux[] = {
+ RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int scif4_clk_a_mux[] = {
+ SCK4_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scif4_clk_b_mux[] = {
+ SCK4_B_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif5_data_a_mux[] = {
+ RX5_A_MARK, TX5_A_MARK,
+};
+static const unsigned int scif5_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int scif5_clk_a_mux[] = {
+ SCK5_A_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif5_clk_b_mux[] = {
+ SCK5_B_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(2, 27),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2_a),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3_a),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_a),
+ SH_PFC_PIN_GROUP(scif0_clk_a),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_clk_b),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk_a),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif3_data_a),
+ SH_PFC_PIN_GROUP(scif3_clk_a),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data_a),
+ SH_PFC_PIN_GROUP(scif4_clk_a),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif5_data_a),
+ SH_PFC_PIN_GROUP(scif5_clk_a),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif_clk),
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_a",
+ "i2c2_b",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_a",
+ "i2c3_b",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data_a",
+ "scif0_clk_a",
+ "scif0_data_b",
+ "scif0_clk_b",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk_a",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_ctrl",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data_a",
+ "scif3_clk_a",
+ "scif3_data_b",
+ "scif3_clk_b",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data_a",
+ "scif4_clk_a",
+ "scif4_data_b",
+ "scif4_clk_b",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data_a",
+ "scif5_clk_a",
+ "scif5_data_b",
+ "scif5_clk_b",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scif_clk),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ GP_1_31_FN, GPSR1_31,
+ GP_1_30_FN, GPSR1_30,
+ GP_1_29_FN, GPSR1_29,
+ GP_1_28_FN, GPSR1_28,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ GP_2_31_FN, GPSR2_31,
+ GP_2_30_FN, GPSR2_30,
+ GP_2_29_FN, GPSR2_29,
+ GP_2_28_FN, GPSR2_28,
+ GP_2_27_FN, GPSR2_27,
+ GP_2_26_FN, GPSR2_26,
+ GP_2_25_FN, GPSR2_25,
+ GP_2_24_FN, GPSR2_24,
+ GP_2_23_FN, GPSR2_23,
+ GP_2_22_FN, GPSR2_22,
+ GP_2_21_FN, GPSR2_21,
+ GP_2_20_FN, GPSR2_20,
+ GP_2_19_FN, GPSR2_19,
+ GP_2_18_FN, GPSR2_18,
+ GP_2_17_FN, GPSR2_17,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ GP_4_31_FN, GPSR4_31,
+ GP_4_30_FN, GPSR4_30,
+ GP_4_29_FN, GPSR4_29,
+ GP_4_28_FN, GPSR4_28,
+ GP_4_27_FN, GPSR4_27,
+ GP_4_26_FN, GPSR4_26,
+ GP_4_25_FN, GPSR4_25,
+ GP_4_24_FN, GPSR4_24,
+ GP_4_23_FN, GPSR4_23,
+ GP_4_22_FN, GPSR4_22,
+ GP_4_21_FN, GPSR4_21,
+ GP_4_20_FN, GPSR4_20,
+ GP_4_19_FN, GPSR4_19,
+ GP_4_18_FN, GPSR4_18,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_20_FN, GPSR5_20,
+ GP_5_19_FN, GPSR5_19,
+ GP_5_18_FN, GPSR5_18,
+ GP_5_17_FN, GPSR5_17,
+ GP_5_16_FN, GPSR5_16,
+ GP_5_15_FN, GPSR5_15,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_13_FN, GPSR6_13,
+ GP_6_12_FN, GPSR6_12,
+ GP_6_11_FN, GPSR6_11,
+ GP_6_10_FN, GPSR6_10,
+ GP_6_9_FN, GPSR6_9,
+ GP_6_8_FN, GPSR6_8,
+ GP_6_7_FN, GPSR6_7,
+ GP_6_6_FN, GPSR6_6,
+ GP_6_5_FN, GPSR6_5,
+ GP_6_4_FN, GPSR6_4,
+ GP_6_3_FN, GPSR6_3,
+ GP_6_2_FN, GPSR6_2,
+ GP_6_1_FN, GPSR6_1,
+ GP_6_0_FN, GPSR6_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ IP9_31_28
+ IP9_27_24
+ IP9_23_20
+ IP9_19_16
+ IP9_15_12
+ IP9_11_8
+ IP9_7_4
+ IP9_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ IP10_31_28
+ IP10_27_24
+ IP10_23_20
+ IP10_19_16
+ IP10_15_12
+ IP10_11_8
+ IP10_7_4
+ IP10_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ IP11_31_28
+ IP11_27_24
+ IP11_23_20
+ IP11_19_16
+ IP11_15_12
+ IP11_11_8
+ IP11_7_4
+ IP11_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ IP12_31_28
+ IP12_27_24
+ IP12_23_20
+ IP12_19_16
+ IP12_15_12
+ IP12_11_8
+ IP12_7_4
+ IP12_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IP13_7_4
+ IP13_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+ 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
+ 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
+ /* RESERVED 31 */
+ 0, 0,
+ MOD_SEL0_30
+ MOD_SEL0_29
+ MOD_SEL0_28
+ MOD_SEL0_27
+ MOD_SEL0_26
+ MOD_SEL0_25
+ MOD_SEL0_24_23
+ MOD_SEL0_22_21
+ MOD_SEL0_20_19
+ MOD_SEL0_18_17
+ /* RESERVED 16 */
+ 0, 0,
+ MOD_SEL0_15
+ MOD_SEL0_14
+ MOD_SEL0_13
+ MOD_SEL0_12
+ MOD_SEL0_11
+ MOD_SEL0_10
+ /* RESERVED 9, 8, 7, 6 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL0_5
+ MOD_SEL0_4
+ MOD_SEL0_3
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
+ 1, 1, 1, 1, 1, 1, 2, 4, 4,
+ 4, 4, 4, 4) {
+ MOD_SEL1_31
+ MOD_SEL1_30
+ MOD_SEL1_29
+ MOD_SEL1_28
+ MOD_SEL1_27
+ MOD_SEL1_26
+ /* RESERVED 25, 24 */
+ 0, 0, 0, 0,
+ /* RESERVED 23, 22, 21, 20 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 19, 18, 17, 16 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 15, 14, 13, 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 11, 10, 9, 8 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 7, 6, 5, 4 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 3, 2, 1, 0 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ { },
+};
+
+static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = 0xe6060380;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
+ bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
+ .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a77995_pinmux_info = {
+ .name = "r8a77995_pfc",
+ .ops = &r8a77995_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
enum sh_pfc_model {
SH_PFC_R8A7795 = 0,
SH_PFC_R8A7796,
+ SH_PFC_R8A77970,
+ SH_PFC_R8A77995,
};
struct sh_pfc_pin_config {
return priv->pfc.info->functions[selector].name;
}
+int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = &priv->pmx;
+ struct sh_pfc *pfc = &priv->pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin = NULL;
+ int i, idx;
+
+ for (i = 1; i < pfc->info->nr_pins; i++) {
+ if (priv->pfc.info->pins[i].pin != pin_selector)
+ continue;
+
+ pin = &priv->pfc.info->pins[i];
+ break;
+ }
+
+ if (!pin)
+ return -EINVAL;
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = &pmx->configs[idx];
+
+ if (cfg->type != PINMUX_TYPE_NONE)
+ return -EBUSY;
+
+ return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
+}
+
+static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
+ unsigned func_selector)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = &priv->pmx;
+ struct sh_pfc *pfc = &priv->pfc;
+ const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
+ int idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+
+ if (cfg->type != PINMUX_TYPE_NONE)
+ return -EBUSY;
+
+ return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+}
+
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
unsigned func_selector)
{
return 0;
}
+static int sh_pfc_pinconf_pin_set(struct udevice *dev,
+ unsigned int pin_selector,
+ unsigned int param, unsigned int arg)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = &priv->pmx;
+ struct sh_pfc *pfc = &priv->pfc;
+ const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
+
+ sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
+
+ return 0;
+}
static int sh_pfc_pinconf_group_set(struct udevice *dev,
unsigned int group_selector,
#if CONFIG_IS_ENABLED(PINCONF)
.pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
.pinconf_params = sh_pfc_pinconf_params,
+ .pinconf_set = sh_pfc_pinconf_pin_set,
.pinconf_group_set = sh_pfc_pinconf_group_set,
#endif
+ .pinmux_set = sh_pfc_pinctrl_pin_set,
.pinmux_group_set = sh_pfc_pinctrl_group_set,
.set_state = pinctrl_generic_set_state,
};
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77970
+ if (model == SH_PFC_R8A77970)
+ priv->pfc.info = &r8a77970_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77995
+ if (model == SH_PFC_R8A77995)
+ priv->pfc.info = &r8a77995_pinmux_info;
+#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
.compatible = "renesas,pfc-r8a7796",
.data = SH_PFC_R8A7796,
},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77970
+ {
+ .compatible = "renesas,pfc-r8a77970",
+ .data = SH_PFC_R8A77970,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77995
+ {
+ .compatible = "renesas,pfc-r8a77995",
+ .data = SH_PFC_R8A77995,
+ },
#endif
{ },
};
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin);
+int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
+#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_4(bank, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
+#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
+
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
+#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_18(bank, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
+#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
+
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
#
-# Copyright (c) 2015 Google, Inc
-# Written by Simon Glass <sjg@chromium.org>
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
--- /dev/null
+/*
+ * Pinctrl driver for Rockchip 3128 SoCs
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3128_pinctrl_priv {
+ struct rk3128_grf *grf;
+};
+
+static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A1_MASK | GPIO0A0_MASK,
+ GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
+ GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
+
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A3_MASK | GPIO0A2_MASK,
+ GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
+ GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2c_iomux2,
+ GPIO2C5_MASK | GPIO2C4_MASK,
+ GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
+ GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A7_MASK | GPIO0A6_MASK,
+ GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
+ GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
+
+ break;
+ }
+}
+
+static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
+ GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
+ GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
+ GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
+ GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
+ GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
+ GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
+ GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
+ GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A5_MASK | GPIO2A7_MASK,
+ GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
+ GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,
+ GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
+ GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
+ GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
+ GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
+ GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
+ GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
+ break;
+ }
+}
+
+static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ pinctrl_rk3128_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3128_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3128_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 14:
+ return PERIPH_ID_SDCARD;
+ case 16:
+ return PERIPH_ID_EMMC;
+ case 20:
+ return PERIPH_ID_UART0;
+ case 21:
+ return PERIPH_ID_UART1;
+ case 22:
+ return PERIPH_ID_UART2;
+ case 23:
+ return PERIPH_ID_SPI0;
+ case 24:
+ return PERIPH_ID_I2C0;
+ case 25:
+ return PERIPH_ID_I2C1;
+ case 26:
+ return PERIPH_ID_I2C2;
+ case 27:
+ return PERIPH_ID_I2C3;
+ case 30:
+ return PERIPH_ID_PWM0;
+ }
+ return -ENOENT;
+}
+
+static int rk3128_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3128_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk3128_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3128_pinctrl_ops = {
+ .set_state_simple = rk3128_pinctrl_set_state_simple,
+ .request = rk3128_pinctrl_request,
+ .get_periph_id = rk3128_pinctrl_get_periph_id,
+};
+
+static int rk3128_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ return 0;
+}
+
+static const struct udevice_id rk3128_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3128-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3128) = {
+ .name = "pinctrl_rk3128",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3128_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),
+ .ops = &rk3128_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk3128_pinctrl_probe,
+};
PMUGRF_GPIO1C0_SEL_MASK,
PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
break;
+ case PERIPH_ID_I2C8:
+ rk_clrsetreg(&pmugrf->gpio1c_iomux,
+ PMUGRF_GPIO1C4_SEL_MASK,
+ PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
+ rk_clrsetreg(&pmugrf->gpio1c_iomux,
+ PMUGRF_GPIO1C5_SEL_MASK,
+ PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
+ break;
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
default:
debug("i2c id = %d iomux error!\n", i2c_id);
break;
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
break;
case PERIPH_ID_SPI0:
return PERIPH_ID_I2C4;
case 38:
return PERIPH_ID_I2C5;
+ case 37:
+ return PERIPH_ID_I2C6;
+ case 36:
+ return PERIPH_ID_I2C7;
+ case 58:
+ return PERIPH_ID_I2C8;
case 65:
return PERIPH_ID_SDMMC1;
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
via an I2C interface.
+
+config DM_PMIC_TPS65910
+ bool "Enable driver for Texas Instruments TPS65910 PMIC"
+ depends on DM_PMIC
+ ---help---
+ The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
+ DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
+ pmic children.
obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
struct driver *drv;
struct udevice *child;
const char *node_name;
+ const char *reg_name;
int bind_count = 0;
ofnode node;
int prefix_len;
debug(" - compatible prefix: '%s'\n", info->prefix);
prefix_len = strlen(info->prefix);
- if (strncmp(info->prefix, node_name, prefix_len))
- continue;
+ if (strncmp(info->prefix, node_name, prefix_len)) {
+ reg_name = ofnode_read_string(node,
+ "regulator-name");
+ if (!reg_name)
+ continue;
+ if (strncmp(info->prefix, reg_name, prefix_len))
+ continue;
+ }
drv = lists_driver_lookup_name(info->driver);
if (!drv) {
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65910_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER },
+ { .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER },
+ { .prefix = "boost_", .driver = TPS65910_BOOST_DRIVER },
+ { },
+};
+
+static int pmic_tps65910_reg_count(struct udevice *dev)
+{
+ return TPS65910_NUM_REGS;
+}
+
+static int pmic_tps65910_write(struct udevice *dev, uint reg, const u8 *buffer,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buffer, len);
+ if (ret)
+ error("%s write error on register %02x\n", dev->name, reg);
+
+ return ret;
+}
+
+static int pmic_tps65910_read(struct udevice *dev, uint reg, u8 *buffer,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buffer, len);
+ if (ret)
+ error("%s read error on register %02x\n", dev->name, reg);
+
+ return ret;
+}
+
+static int pmic_tps65910_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s regulators subnode not found\n", dev->name);
+ return -EINVAL;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s has no children (regulators)\n", dev->name);
+
+ return 0;
+}
+
+static int pmic_tps65910_probe(struct udevice *dev)
+{
+ /* use I2C control interface instead of I2C smartreflex interface to
+ * access smartrefelex registers VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG
+ * and VDD2_SR_REG
+ */
+ return pmic_clrsetbits(dev, TPS65910_REG_DEVICE_CTRL, 0,
+ TPS65910_I2C_SEL_MASK);
+}
+
+static struct dm_pmic_ops pmic_tps65910_ops = {
+ .reg_count = pmic_tps65910_reg_count,
+ .read = pmic_tps65910_read,
+ .write = pmic_tps65910_write,
+};
+
+static const struct udevice_id pmic_tps65910_match[] = {
+ { .compatible = "ti,tps65910" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pmic_tps65910) = {
+ .name = "pmic_tps65910",
+ .id = UCLASS_PMIC,
+ .of_match = pmic_tps65910_match,
+ .bind = pmic_tps65910_bind,
+ .probe = pmic_tps65910_probe,
+ .ops = &pmic_tps65910_ops,
+};
LP87565 series of PMICs have 4 single phase BUCKs that can also
be configured in multi phase modes. The driver implements
get/set api for value and enable.
+
+config DM_REGULATOR_TPS65910
+ bool "Enable driver for TPS65910 PMIC regulators"
+ depends on DM_PMIC_TPS65910
+ ---help---
+ The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all
+ regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
+ the get/set api for value and enable.
obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
+obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65910_pmic.h>
+
+#define VOUT_CHOICE_COUNT 4
+
+/*
+ * struct regulator_props - Properties of a LDO and VIO SMPS regulator
+ *
+ * All of these regulators allow setting one out of four output voltages.
+ * These output voltages are only achievable when supplying the regulator
+ * with a minimum input voltage.
+ *
+ * @vin_min[]: minimum supply input voltage in uV required to achieve the
+ * corresponding vout[] voltage
+ * @vout[]: regulator output voltage in uV
+ * @reg: I2C register used to set regulator voltage
+ */
+struct regulator_props {
+ int vin_min[VOUT_CHOICE_COUNT];
+ int vout[VOUT_CHOICE_COUNT];
+ int reg;
+};
+
+static const struct regulator_props ldo_props_vdig1 = {
+ .vin_min = { 1700000, 2100000, 2700000, 3200000 },
+ .vout = { 1200000, 1500000, 1800000, 2700000 },
+ .reg = TPS65910_REG_VDIG1
+};
+
+static const struct regulator_props ldo_props_vdig2 = {
+ .vin_min = { 1700000, 1700000, 1700000, 2700000 },
+ .vout = { 1000000, 1100000, 1200000, 1800000 },
+ .reg = TPS65910_REG_VDIG2
+};
+
+static const struct regulator_props ldo_props_vpll = {
+ .vin_min = { 2700000, 2700000, 2700000, 3000000 },
+ .vout = { 1000000, 1100000, 1800000, 2500000 },
+ .reg = TPS65910_REG_VPLL
+};
+
+static const struct regulator_props ldo_props_vdac = {
+ .vin_min = { 2700000, 3000000, 3200000, 3200000 },
+ .vout = { 1800000, 2600000, 2800000, 2850000 },
+ .reg = TPS65910_REG_VDAC
+};
+
+static const struct regulator_props ldo_props_vaux1 = {
+ .vin_min = { 2700000, 3200000, 3200000, 3200000 },
+ .vout = { 1800000, 2500000, 2800000, 2850000 },
+ .reg = TPS65910_REG_VAUX1
+};
+
+static const struct regulator_props ldo_props_vaux2 = {
+ .vin_min = { 2700000, 3200000, 3200000, 3600000 },
+ .vout = { 1800000, 2800000, 2900000, 3300000 },
+ .reg = TPS65910_REG_VAUX2
+};
+
+static const struct regulator_props ldo_props_vaux33 = {
+ .vin_min = { 2700000, 2700000, 3200000, 3600000 },
+ .vout = { 1800000, 2000000, 2800000, 3300000 },
+ .reg = TPS65910_REG_VAUX33
+};
+
+static const struct regulator_props ldo_props_vmmc = {
+ .vin_min = { 2700000, 3200000, 3200000, 3600000 },
+ .vout = { 1800000, 2800000, 3000000, 3300000 },
+ .reg = TPS65910_REG_VMMC
+};
+
+static const struct regulator_props smps_props_vio = {
+ .vin_min = { 3200000, 3200000, 4000000, 4400000 },
+ .vout = { 1500000, 1800000, 2500000, 3300000 },
+ .reg = TPS65910_REG_VIO
+};
+
+/* lookup table of control registers indexed by regulator unit number */
+static const int ctrl_regs[] = {
+ TPS65910_REG_VRTC,
+ TPS65910_REG_VIO,
+ TPS65910_REG_VDD1,
+ TPS65910_REG_VDD2,
+ TPS65910_REG_VDD3,
+ TPS65910_REG_VDIG1,
+ TPS65910_REG_VDIG2,
+ TPS65910_REG_VPLL,
+ TPS65910_REG_VDAC,
+ TPS65910_REG_VAUX1,
+ TPS65910_REG_VAUX2,
+ TPS65910_REG_VAUX33,
+ TPS65910_REG_VMMC
+};
+
+/* supply names as used in DT */
+static const char * const supply_names[] = {
+ "vccio-supply",
+ "vcc1-supply",
+ "vcc2-supply",
+ "vcc3-supply",
+ "vcc4-supply",
+ "vcc5-supply",
+ "vcc6-supply",
+ "vcc7-supply"
+};
+
+/* lookup table of regulator supplies indexed by regulator unit number */
+static const int regulator_supplies[] = {
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_SUPPLY_VCCIO,
+ TPS65910_SUPPLY_VCC1,
+ TPS65910_SUPPLY_VCC2,
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC3,
+ TPS65910_SUPPLY_VCC3
+};
+
+static int get_ctrl_reg_from_unit_addr(const uint unit_addr)
+{
+ if (unit_addr < ARRAY_SIZE(ctrl_regs))
+ return ctrl_regs[unit_addr];
+ return -ENXIO;
+}
+
+static int tps65910_regulator_get_value(struct udevice *dev,
+ const struct regulator_props *rgp)
+{
+ int sel, val, vout;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin = pdata->supply;
+
+ val = pmic_reg_read(dev->parent, rgp->reg);
+ if (val < 0)
+ return val;
+ sel = (val & TPS65910_SEL_MASK) >> 2;
+ vout = (vin >= *(rgp->vin_min + sel)) ? *(rgp->vout + sel) : 0;
+ vout = ((val & TPS65910_SUPPLY_STATE_MASK) == 1) ? vout : 0;
+
+ return vout;
+}
+
+static int tps65910_ldo_get_value(struct udevice *dev)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin;
+
+ if (!pdata)
+ return 0;
+ vin = pdata->supply;
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VRTC:
+ /* VRTC is fixed and can't be turned off */
+ return (vin >= 2500000) ? 1830000 : 0;
+ case TPS65910_UNIT_VDIG1:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdig1);
+ case TPS65910_UNIT_VDIG2:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdig2);
+ case TPS65910_UNIT_VPLL:
+ return tps65910_regulator_get_value(dev, &ldo_props_vpll);
+ case TPS65910_UNIT_VDAC:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdac);
+ case TPS65910_UNIT_VAUX1:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux1);
+ case TPS65910_UNIT_VAUX2:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux2);
+ case TPS65910_UNIT_VAUX33:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux33);
+ case TPS65910_UNIT_VMMC:
+ return tps65910_regulator_get_value(dev, &ldo_props_vmmc);
+ default:
+ return 0;
+ }
+}
+
+static int tps65910_regulator_set_value(struct udevice *dev,
+ const struct regulator_props *ldo,
+ int uV)
+{
+ int val;
+ int sel = 0;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ do {
+ /* we only allow exact voltage matches */
+ if (uV == *(ldo->vout + sel))
+ break;
+ } while (++sel < VOUT_CHOICE_COUNT);
+ if (sel == VOUT_CHOICE_COUNT)
+ return -EINVAL;
+ if (pdata->supply < *(ldo->vin_min + sel))
+ return -EINVAL;
+
+ val = pmic_reg_read(dev->parent, ldo->reg);
+ if (val < 0)
+ return val;
+ val &= ~TPS65910_SEL_MASK;
+ val |= sel << 2;
+ return pmic_reg_write(dev->parent, ldo->reg, val);
+}
+
+static int tps65910_ldo_set_value(struct udevice *dev, int uV)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin = pdata->supply;
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VRTC:
+ /* VRTC is fixed to 1.83V and can't be turned off */
+ if (vin < 2500000)
+ return -EINVAL;
+ return 0;
+ case TPS65910_UNIT_VDIG1:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdig1, uV);
+ case TPS65910_UNIT_VDIG2:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdig2, uV);
+ case TPS65910_UNIT_VPLL:
+ return tps65910_regulator_set_value(dev, &ldo_props_vpll, uV);
+ case TPS65910_UNIT_VDAC:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdac, uV);
+ case TPS65910_UNIT_VAUX1:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux1, uV);
+ case TPS65910_UNIT_VAUX2:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux2, uV);
+ case TPS65910_UNIT_VAUX33:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux33, uV);
+ case TPS65910_UNIT_VMMC:
+ return tps65910_regulator_set_value(dev, &ldo_props_vmmc, uV);
+ default:
+ return 0;
+ }
+}
+
+static int tps65910_get_enable(struct udevice *dev)
+{
+ int reg, val;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ reg = get_ctrl_reg_from_unit_addr(pdata->unit);
+ if (reg < 0)
+ return reg;
+
+ val = pmic_reg_read(dev->parent, reg);
+ if (val < 0)
+ return val;
+
+ /* bits 1:0 of regulator control register define state */
+ return ((val & TPS65910_SUPPLY_STATE_MASK) == 1);
+}
+
+static int tps65910_set_enable(struct udevice *dev, bool enable)
+{
+ int reg;
+ uint clr, set;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ reg = get_ctrl_reg_from_unit_addr(pdata->unit);
+ if (reg < 0)
+ return reg;
+
+ if (enable) {
+ clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_ON;
+ set = TPS65910_SUPPLY_STATE_MASK & TPS65910_SUPPLY_STATE_ON;
+ } else {
+ clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_OFF;
+ set = TPS65910_SUPPLY_STATE_MASK & TPS65910_SUPPLY_STATE_OFF;
+ }
+ return pmic_clrsetbits(dev->parent, reg, clr, set);
+}
+
+static int buck_get_vdd1_vdd2_value(struct udevice *dev, int reg_vdd)
+{
+ int gain;
+ int val = pmic_reg_read(dev, reg_vdd);
+
+ if (val < 0)
+ return val;
+ gain = (val & TPS65910_GAIN_SEL_MASK) >> 6;
+ gain = (gain == 0) ? 1 : gain;
+ val = pmic_reg_read(dev, reg_vdd + 1);
+ if (val < 0)
+ return val;
+ if (val & TPS65910_VDD_SR_MASK)
+ /* use smart reflex value instead */
+ val = pmic_reg_read(dev, reg_vdd + 2);
+ if (val < 0)
+ return val;
+ return (562500 + (val & TPS65910_VDD_SEL_MASK) * 12500) * gain;
+}
+
+static int tps65910_buck_get_value(struct udevice *dev)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VIO:
+ return tps65910_regulator_get_value(dev, &smps_props_vio);
+ case TPS65910_UNIT_VDD1:
+ return buck_get_vdd1_vdd2_value(dev->parent, TPS65910_REG_VDD1);
+ case TPS65910_UNIT_VDD2:
+ return buck_get_vdd1_vdd2_value(dev->parent, TPS65910_REG_VDD2);
+ default:
+ return 0;
+ }
+}
+
+static int buck_set_vdd1_vdd2_value(struct udevice *dev, int uV)
+{
+ int ret, reg_vdd, gain;
+ int val;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VDD1:
+ reg_vdd = TPS65910_REG_VDD1;
+ break;
+ case TPS65910_UNIT_VDD2:
+ reg_vdd = TPS65910_REG_VDD2;
+ break;
+ default:
+ return -EINVAL;
+ }
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ /* check setpoint is within limits */
+ if (uV < uc_pdata->min_uV) {
+ error("voltage %duV for %s too low\n", uV, dev->name);
+ return -EINVAL;
+ }
+ if (uV > uc_pdata->max_uV) {
+ error("voltage %duV for %s too high\n", uV, dev->name);
+ return -EINVAL;
+ }
+
+ val = pmic_reg_read(dev->parent, reg_vdd);
+ if (val < 0)
+ return val;
+ gain = (val & TPS65910_GAIN_SEL_MASK) >> 6;
+ gain = (gain == 0) ? 1 : gain;
+ val = ((uV / gain) - 562500) / 12500;
+ if (val < TPS65910_VDD_SEL_MIN || val > TPS65910_VDD_SEL_MAX)
+ /*
+ * Neither do we change the gain, nor do we allow shutdown or
+ * any approximate value (for now)
+ */
+ return -EPERM;
+ val &= TPS65910_VDD_SEL_MASK;
+ ret = pmic_reg_write(dev->parent, reg_vdd + 1, val);
+ if (ret)
+ return ret;
+ return 0;
+}
+
+static int tps65910_buck_set_value(struct udevice *dev, int uV)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ if (pdata->unit == TPS65910_UNIT_VIO)
+ return tps65910_regulator_set_value(dev, &smps_props_vio, uV);
+
+ return buck_set_vdd1_vdd2_value(dev, uV);
+}
+
+static int tps65910_boost_get_value(struct udevice *dev)
+{
+ int vout;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ vout = (pdata->supply >= 3000000) ? 5000000 : 0;
+ return vout;
+}
+
+static int tps65910_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct udevice *supply;
+ int ret;
+ const char *supply_name;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->unit = dev_get_driver_data(dev);
+ if (pdata->unit > TPS65910_UNIT_VMMC)
+ return -EINVAL;
+ supply_name = supply_names[regulator_supplies[pdata->unit]];
+
+ debug("Looking up supply power %s\n", supply_name);
+ ret = device_get_supply_regulator(dev->parent, supply_name, &supply);
+ if (ret) {
+ debug(" missing supply power %s\n", supply_name);
+ return ret;
+ }
+ pdata->supply = regulator_get_value(supply);
+ if (pdata->supply < 0) {
+ debug(" invalid supply voltage for regulator %s\n",
+ supply->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops tps65910_boost_ops = {
+ .get_value = tps65910_boost_get_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_boost) = {
+ .name = TPS65910_BOOST_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_boost_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
+
+static const struct dm_regulator_ops tps65910_buck_ops = {
+ .get_value = tps65910_buck_get_value,
+ .set_value = tps65910_buck_set_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_buck) = {
+ .name = TPS65910_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_buck_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
+
+static const struct dm_regulator_ops tps65910_ldo_ops = {
+ .get_value = tps65910_ldo_get_value,
+ .set_value = tps65910_ldo_set_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_ldo) = {
+ .name = TPS65910_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_ldo_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
return (struct pwm_regs *)PWM1_BASE_ADDR;
case 1:
return (struct pwm_regs *)PWM2_BASE_ADDR;
+#ifdef CONFIG_MX6
case 2:
return (struct pwm_regs *)PWM3_BASE_ADDR;
case 3:
return (struct pwm_regs *)PWM4_BASE_ADDR;
+#endif
#ifdef CONFIG_MX6SX
case 4:
return (struct pwm_regs *)PWM5_BASE_ADDR;
#
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct dram_info {
+ struct ram_info info;
+ struct rk3128_grf *grf;
+};
+
+static int rk3128_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->grf->os_reg[1]);
+
+ return 0;
+}
+
+static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3128_dmc_ops = {
+ .get_info = rk3128_dmc_get_info,
+};
+
+static const struct udevice_id rk3128_dmc_ids[] = {
+ { .compatible = "rockchip,rk3128-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3128) = {
+ .name = "rockchip_rk3128_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3128_dmc_ids,
+ .ops = &rk3128_dmc_ops,
+ .probe = rk3128_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+};
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
compatible Real Time Clock devices.
+config RTC_S35392A
+ bool "Enable S35392A driver"
+ select BITREVERSE
+ help
+ Enable s35392a driver which provides rtc get and set function.
+
endmenu
obj-$(CONFIG_RTC_RV3029) += rv3029.o
obj-$(CONFIG_RTC_RX8025) += rx8025.o
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
+obj-$(CONFIG_RTC_S35392A) += s35392a.o
obj-$(CONFIG_SANDBOX) += sandbox_rtc.o
obj-$(CONFIG_RTC_X1205) += x1205.o
--- /dev/null
+/*
+ * SII Semiconductor Corporation S35392A RTC driver.
+ *
+ * Copyright (c) 2017, General Electric Company
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <command.h>
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <linux/bitrev.h>
+#include <rtc.h>
+
+#define S35390A_CMD_STATUS1 0x30
+#define S35390A_CMD_STATUS2 0x31
+#define S35390A_CMD_TIME1 0x32
+#define S35390A_CMD_TIME2 0x33
+#define S35390A_CMD_INT2_REG1 0x35
+
+#define S35390A_BYTE_YEAR 0
+#define S35390A_BYTE_MONTH 1
+#define S35390A_BYTE_DAY 2
+#define S35390A_BYTE_WDAY 3
+#define S35390A_BYTE_HOURS 4
+#define S35390A_BYTE_MINS 5
+#define S35390A_BYTE_SECS 6
+
+/* flags for STATUS1 */
+#define S35390A_FLAG_POC 0x01
+#define S35390A_FLAG_BLD 0x02
+#define S35390A_FLAG_INT2 0x04
+#define S35390A_FLAG_24H 0x40
+#define S35390A_FLAG_RESET 0x80
+
+/*
+ * If either BLD or POC is set, then the chip has lost power long enough for
+ * the time value to become invalid.
+ */
+#define S35390A_LOW_VOLTAGE (S35390A_FLAG_POC | S35390A_FLAG_BLD)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt, args...) printf(fmt, ##args)
+#else
+#define DEBUGR(fmt, args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#ifdef CONFIG_DM_RTC
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+ u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+struct ludevice dev;
+
+#endif
+
+#define msleep(a) udelay(a * 1000)
+
+int lowvoltage;
+
+static int s35392a_rtc_reset(DEV_TYPE *dev);
+
+static int s35392a_rtc_read(DEV_TYPE *dev, u8 reg, u8 *buf, int len)
+{
+ int ret;
+
+#ifdef CONFIG_DM_RTC
+ /* TODO: we need to tweak the chip address to reg */
+ ret = dm_i2c_read(dev, 0, buf, len);
+#else
+ (void)dev;
+ ret = i2c_read(reg, 0, -1, buf, len);
+#endif
+
+ return ret;
+}
+
+static int s35392a_rtc_write(DEV_TYPE *dev, u8 reg, u8 *buf, int len)
+{
+ int ret;
+
+#ifdef CONFIG_DM_RTC
+ /* TODO: we need to tweak the chip address to reg */
+ ret = dm_i2c_write(dev, 0, buf, 1);
+#else
+ (void)dev;
+ ret = i2c_write(reg, 0, 0, buf, len);
+#endif
+
+ return ret;
+}
+
+static int s35392a_rtc_read8(DEV_TYPE *dev, unsigned int reg)
+{
+ u8 val;
+ int ret;
+
+ ret = s35392a_rtc_read(dev, reg, &val, sizeof(val));
+ return ret < 0 ? ret : val;
+}
+
+static int s35392a_rtc_write8(DEV_TYPE *dev, unsigned int reg, int val)
+{
+ int ret;
+ u8 lval = val;
+
+ ret = s35392a_rtc_write(dev, reg, &lval, sizeof(lval));
+ return ret < 0 ? ret : 0;
+}
+
+static int validate_time(const struct rtc_time *tm)
+{
+ if ((tm->tm_year < 2000) || (tm->tm_year > 2099))
+ return -EINVAL;
+
+ if ((tm->tm_mon < 1) || (tm->tm_mon > 12))
+ return -EINVAL;
+
+ if ((tm->tm_mday < 1) || (tm->tm_mday > 31))
+ return -EINVAL;
+
+ if ((tm->tm_wday < 0) || (tm->tm_wday > 6))
+ return -EINVAL;
+
+ if ((tm->tm_hour < 0) || (tm->tm_hour > 23))
+ return -EINVAL;
+
+ if ((tm->tm_min < 0) || (tm->tm_min > 59))
+ return -EINVAL;
+
+ if ((tm->tm_sec < 0) || (tm->tm_sec > 59))
+ return -EINVAL;
+
+ return 0;
+}
+
+void s35392a_rtc_init(DEV_TYPE *dev)
+{
+ int status;
+
+ status = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
+ if (status < 0)
+ goto error;
+
+ DEBUGR("init: S35390A_CMD_STATUS1: 0x%x\n", status);
+
+ lowvoltage = status & S35390A_LOW_VOLTAGE ? 1 : 0;
+
+ if (status & S35390A_FLAG_POC)
+ /*
+ * Do not communicate for 0.5 seconds since the power-on
+ * detection circuit is in operation.
+ */
+ msleep(500);
+
+ else if (!lowvoltage)
+ /*
+ * If both POC and BLD are unset everything is fine.
+ */
+ return;
+
+ if (lowvoltage)
+ printf("RTC low voltage detected\n");
+
+ if (!s35392a_rtc_reset(dev))
+ return;
+
+error:
+ printf("Error RTC init.\n");
+}
+
+/* Get the current time from the RTC */
+static int s35392a_rtc_get(DEV_TYPE *dev, struct rtc_time *tm)
+{
+ u8 date[7];
+ int ret, i;
+
+ if (lowvoltage) {
+ DEBUGR("RTC low voltage detected\n");
+ return -EINVAL;
+ }
+
+ ret = s35392a_rtc_read(dev, S35390A_CMD_TIME1, date, sizeof(date));
+ if (ret < 0) {
+ DEBUGR("Error reading date from RTC\n");
+ return -EIO;
+ }
+
+ /* This chip returns the bits of each byte in reverse order */
+ for (i = 0; i < 7; ++i)
+ date[i] = bitrev8(date[i]);
+
+ tm->tm_sec = bcd2bin(date[S35390A_BYTE_SECS]);
+ tm->tm_min = bcd2bin(date[S35390A_BYTE_MINS]);
+ tm->tm_hour = bcd2bin(date[S35390A_BYTE_HOURS] & ~S35390A_FLAG_24H);
+ tm->tm_wday = bcd2bin(date[S35390A_BYTE_WDAY]);
+ tm->tm_mday = bcd2bin(date[S35390A_BYTE_DAY]);
+ tm->tm_mon = bcd2bin(date[S35390A_BYTE_MONTH]);
+ tm->tm_year = bcd2bin(date[S35390A_BYTE_YEAR]) + 2000;
+
+ DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+/* Set the RTC */
+static int s35392a_rtc_set(DEV_TYPE *dev, const struct rtc_time *tm)
+{
+ int i, ret;
+ int status;
+ u8 date[7];
+
+ DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ ret = validate_time(tm);
+ if (ret < 0)
+ return -EINVAL;
+
+ /* We support only 24h mode */
+ ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
+ if (ret < 0)
+ return -EIO;
+ status = ret;
+
+ ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1,
+ status | S35390A_FLAG_24H);
+ if (ret < 0)
+ return -EIO;
+
+ date[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 2000);
+ date[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon);
+ date[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
+ date[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
+ date[S35390A_BYTE_HOURS] = bin2bcd(tm->tm_hour);
+ date[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
+ date[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
+
+ /* This chip expects the bits of each byte to be in reverse order */
+ for (i = 0; i < 7; ++i)
+ date[i] = bitrev8(date[i]);
+
+ ret = s35392a_rtc_write(dev, S35390A_CMD_TIME1, date, sizeof(date));
+ if (ret < 0) {
+ DEBUGR("Error writing date to RTC\n");
+ return -EIO;
+ }
+
+ /* Now we have time. Reset the low voltage status */
+ lowvoltage = 0;
+
+ return 0;
+}
+
+/* Reset the RTC. */
+static int s35392a_rtc_reset(DEV_TYPE *dev)
+{
+ int buf;
+ int ret;
+ unsigned int initcount = 0;
+
+ buf = S35390A_FLAG_RESET;
+
+initialize:
+ ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1, buf);
+ if (ret < 0)
+ return -EIO;
+
+ ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1);
+ if (ret < 0)
+ return -EIO;
+ buf = ret;
+
+ if (!lowvoltage)
+ lowvoltage = buf & S35390A_LOW_VOLTAGE ? 1 : 0;
+
+ if (buf & S35390A_LOW_VOLTAGE) {
+ /* Try up to five times to reset the chip */
+ if (initcount < 5) {
+ ++initcount;
+ goto initialize;
+ } else {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_RTC
+
+int rtc_get(struct rtc_time *tm)
+{
+ return s35392a_rtc_get(&dev, tm);
+}
+
+int rtc_set(struct rtc_time *tm)
+{
+ return s35392a_rtc_set(&dev, tm);
+}
+
+void rtc_reset(void)
+{
+ s35392a_rtc_reset(&dev);
+}
+
+void rtc_init(void)
+{
+ s35392a_rtc_init(&dev);
+}
+
+#else
+
+static int s35392a_probe(struct udevice *dev)
+{
+ s35392a_rtc_init(dev);
+ return 0;
+}
+
+static const struct rtc_ops s35392a_rtc_ops = {
+ .get = s35392a_rtc_get,
+ .set = s35392a_rtc_set,
+ .read8 = s35392a_rtc_read8,
+ .write8 = s35392a_rtc_write8,
+ .reset = s35392a_rtc_reset,
+};
+
+static const struct udevice_id s35392a_rtc_ids[] = {
+ { .compatible = "sii,s35392a-rtc" },
+ { }
+};
+
+U_BOOT_DRIVER(s35392a_rtc) = {
+ .name = "s35392a_rtc",
+ .id = UCLASS_RTC,
+ .probe = s35392a_probe,
+ .of_match = s35392a_rtc_ids,
+ .ops = &s35392a_rtc_ops,
+};
+
+#endif
enable its onboard serial ports, say Y to this option.
If unsure, say N.
+config ZYNQ_SERIAL
+ bool "Cadence (Xilinx Zynq) UART support"
+ depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ help
+ This driver supports the Cadence UART. It is found e.g. in Xilinx
+ Zynq/ZynqMP.
+
config MPC8XX_CONS
bool "Console driver for MPC8XX"
depends on 8xx
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
- defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \
- defined(CONFIG_R8A7796)
+ defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3)
# if defined(CONFIG_SCIF_A)
# define SCIF_ORER 0x0200
# else
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
-config NDS_AE3XX_SPI
- bool "Andestech AE3XX SPI driver"
+config ATCSPI200_SPI
+ bool "Andestech ATCSPI200 SPI driver"
help
- Enable the Andestech AE3XX SPI driver. This driver can be
- used to access the SPI flash on platforms embedding this
- Andestech IP core.
+ Enable the Andestech ATCSPI200 SPI driver. This driver can be
+ used to access the SPI flash on AE3XX and AE250 platforms embedding
+ this Andestech IP core.
config TI_QSPI
bool "TI QSPI driver"
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
-obj-$(CONFIG_NDS_AE3XX_SPI) += nds_ae3xx_spi.o
+obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
/*
- * NDS SPI controller driver.
+ * Andestech ATCSPI200 SPI controller driver.
*
* Copyright 2017 Andes Technology, Inc.
* Author: Rick Chen (rick@andestech.com)
#define SPI1_BASE 0xf0f00000
#define NSPI_MAX_CS_NUM 1
-struct ae3xx_spi_regs {
+struct atcspi200_spi_regs {
u32 rev;
u32 reserve1[3];
u32 format; /* 0x10 */
#ifndef CONFIG_DM_SPI
struct spi_slave slave;
#endif
- volatile struct ae3xx_spi_regs *regs;
+ volatile struct atcspi200_spi_regs *regs;
int to;
unsigned int freq;
ulong clock;
unsigned int max_transfer_length;
};
-static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns)
+static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
{
u32 tm;
u8 div;
}
-static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns)
+static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
{
unsigned int format=0;
ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
ns->cmd_len = 0;
format = ns->mode|DATA_LENGTH(8);
ns->regs->format = format;
- __ae3xx_spi_set_speed(ns);
+ __atcspi200_spi_set_speed(ns);
return 0;
}
-static int __ae3xx_spi_release_bus(struct nds_spi_slave *ns)
+static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
{
/* do nothing */
return 0;
}
-static int __ae3xx_spi_start(struct nds_spi_slave *ns)
+static int __atcspi200_spi_start(struct nds_spi_slave *ns)
{
int i,olen=0;
int tc = ns->regs->tctrl;
return 0;
}
-static int __ae3xx_spi_stop(struct nds_spi_slave *ns)
+static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
{
ns->regs->timing = ns->mtiming;
while ((ns->regs->status & SPIBSY)&&(ns->to--))
}
-static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
+static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
unsigned int bitlen, const void *data_out, void *data_in,
unsigned long flags)
{
memcpy(cmd_buf, data_out, cmd_len);
data_out = 0;
data_len = 0;
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
break;
}
debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n",
num_bytes = (tran_len) % CHUNK_SIZE;
if(num_bytes == 0)
num_bytes = CHUNK_SIZE;
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
while (num_blks) {
event = in_le32(&ns->regs->status);
ns->cmd_buf[3] += ((tran_len)&0xff);
ns->data_len = data_len;
}
- ret = __ae3xx_spi_stop(ns);
+ ret = __atcspi200_spi_stop(ns);
}
- ret = __ae3xx_spi_stop(ns);
+ ret = __atcspi200_spi_stop(ns);
return ret;
}
switch (bus) {
case SPI0_BUS:
- ns->regs = (struct ae3xx_spi_regs *)SPI0_BASE;
+ ns->regs = (struct atcspi200_spi_regs *)SPI0_BASE;
break;
case SPI1_BUS:
- ns->regs = (struct ae3xx_spi_regs *)SPI1_BASE;
+ ns->regs = (struct atcspi200_spi_regs *)SPI1_BASE;
break;
default:
int spi_claim_bus(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __ae3xx_spi_claim_bus(ns);
+ return __atcspi200_spi_claim_bus(ns);
}
void spi_release_bus(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_release_bus(ns);
+ __atcspi200_spi_release_bus(ns);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
void *data_in, unsigned long flags)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __ae3xx_spi_xfer(ns, bitlen, data_out, data_in, flags);
+ return __atcspi200_spi_xfer(ns, bitlen, data_out, data_in, flags);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
void spi_cs_activate(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_stop(ns);
+ __atcspi200_spi_stop(ns);
}
#else
-static int ae3xx_spi_set_speed(struct udevice *bus, uint max_hz)
+static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
debug("%s speed %u\n", __func__, max_hz);
ns->freq = max_hz;
- __ae3xx_spi_set_speed(ns);
+ __atcspi200_spi_set_speed(ns);
return 0;
}
-static int ae3xx_spi_set_mode(struct udevice *bus, uint mode)
+static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
return 0;
}
-static int ae3xx_spi_claim_bus(struct udevice *dev)
+static int atcspi200_spi_claim_bus(struct udevice *dev)
{
struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
return -EINVAL;
}
- return __ae3xx_spi_claim_bus(ns);
+ return __atcspi200_spi_claim_bus(ns);
}
-static int ae3xx_spi_release_bus(struct udevice *dev)
+static int atcspi200_spi_release_bus(struct udevice *dev)
{
struct nds_spi_slave *ns = dev_get_priv(dev->parent);
- return __ae3xx_spi_release_bus(ns);
+ return __atcspi200_spi_release_bus(ns);
}
-static int ae3xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din,
unsigned long flags)
{
struct udevice *bus = dev->parent;
struct nds_spi_slave *ns = dev_get_priv(bus);
- return __ae3xx_spi_xfer(ns, bitlen, dout, din, flags);
+ return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
}
-static int ae3xx_spi_get_clk(struct udevice *bus)
+static int atcspi200_spi_get_clk(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
struct clk clk;
return 0;
}
-static int ae3xx_spi_probe(struct udevice *bus)
+static int atcspi200_spi_probe(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
ns->to = SPI_TIMEOUT;
ns->max_transfer_length = MAX_TRANSFER_LEN;
ns->mtiming = ns->regs->timing;
- ae3xx_spi_get_clk(bus);
+ atcspi200_spi_get_clk(bus);
return 0;
}
-static int ae3xx_ofdata_to_platadata(struct udevice *bus)
+static int atcspi200_ofdata_to_platadata(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
ns->regs = map_physmem(devfdt_get_addr(bus),
- sizeof(struct ae3xx_spi_regs),
+ sizeof(struct atcspi200_spi_regs),
MAP_NOCACHE);
if (!ns->regs) {
printf("%s: could not map device address\n", __func__);
return 0;
}
-static const struct dm_spi_ops ae3xx_spi_ops = {
- .claim_bus = ae3xx_spi_claim_bus,
- .release_bus = ae3xx_spi_release_bus,
- .xfer = ae3xx_spi_xfer,
- .set_speed = ae3xx_spi_set_speed,
- .set_mode = ae3xx_spi_set_mode,
+static const struct dm_spi_ops atcspi200_spi_ops = {
+ .claim_bus = atcspi200_spi_claim_bus,
+ .release_bus = atcspi200_spi_release_bus,
+ .xfer = atcspi200_spi_xfer,
+ .set_speed = atcspi200_spi_set_speed,
+ .set_mode = atcspi200_spi_set_mode,
};
-static const struct udevice_id ae3xx_spi_ids[] = {
+static const struct udevice_id atcspi200_spi_ids[] = {
{ .compatible = "andestech,atcspi200" },
{ }
};
-U_BOOT_DRIVER(ae3xx_spi) = {
- .name = "ae3xx_spi",
+U_BOOT_DRIVER(atcspi200_spi) = {
+ .name = "atcspi200_spi",
.id = UCLASS_SPI,
- .of_match = ae3xx_spi_ids,
- .ops = &ae3xx_spi_ops,
- .ofdata_to_platdata = ae3xx_ofdata_to_platadata,
+ .of_match = atcspi200_spi_ids,
+ .ops = &atcspi200_spi_ops,
+ .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
.priv_auto_alloc_size = sizeof(struct nds_spi_slave),
- .probe = ae3xx_spi_probe,
+ .probe = atcspi200_spi_probe,
};
#endif
*/
if (clk_div > 0xfffe) {
clk_div = 0xfffe;
- debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
+ debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
__func__, speed, priv->input_rate / clk_div);
}
return -EINVAL;
/* Scan peripherals connected to each SPMI channel */
- for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
+ for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf0000) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
-endif
-obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += sysreset_rk322x.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
-obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
-obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
-obj-$(CONFIG_ROCKCHIP_RV1108) += sysreset_rv1108.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- sysreset_walk_halt(SYSRESET_WARM);
+ sysreset_walk_halt(SYSRESET_COLD);
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3036.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3036_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- writel(0xeca8, &cru->cru_glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- writel(0xfdb9, &cru->cru_glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3036_sysreset = {
- .request = rk3036_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3036) = {
- .name = "rk3036_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3036_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3188.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3188_cru *cru = rockchip_get_cru();
- struct rk3188_grf *grf;
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- if (IS_ERR(grf))
- return -EPROTONOSUPPORT;
-
- /*
- * warm-reset keeps the remap value,
- * so make sure it's disabled.
- */
- rk_clrsetreg(&grf->soc_con0,
- NOC_REMAP_MASK << NOC_REMAP_SHIFT,
- 0 << NOC_REMAP_SHIFT);
-
- rk_clrreg(&cru->cru_mode_con, 0xffff);
- writel(0xeca8, &cru->cru_glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- rk_clrreg(&cru->cru_mode_con, 0xffff);
- writel(0xfdb9, &cru->cru_glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3188_sysreset = {
- .request = rk3188_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3188) = {
- .name = "rk3188_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3188_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk322x.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk322x_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- writel(0xeca8, &cru->cru_glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- writel(0xfdb9, &cru->cru_glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk322x_sysreset = {
- .request = rk322x_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk322x) = {
- .name = "rk322x_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk322x_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3288_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- rk_clrreg(&cru->cru_mode_con, 0xffff);
- writel(0xeca8, &cru->cru_glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- rk_clrreg(&cru->cru_mode_con, 0xffff);
- writel(0xfdb9, &cru->cru_glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3288_sysreset = {
- .request = rk3288_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3288) = {
- .name = "rk3288_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3288_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3328.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <linux/err.h>
-
-int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3328_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- writel(0xeca8, &cru->glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- writel(0xfdb9, &cru->glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3328_sysreset = {
- .request = rk3328_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3328) = {
- .name = "rk3328_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3328_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
-{
- struct rk3368_pll *pll;
- int i;
-
- for (i = 0; i < 6; i++) {
- pll = &cru->pll[i];
- rk_clrreg(&pll->con3, PLL_MODE_MASK);
- }
-}
-
-static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3368_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- rk3368_pll_enter_slow_mode(cru);
- rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
- PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
- writel(0xeca8, &cru->glb_srst_snd_val);
- break;
- case SYSRESET_COLD:
- rk3368_pll_enter_slow_mode(cru);
- rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
- PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
- writel(0xfdb9, &cru->glb_srst_fst_val);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3368_sysreset = {
- .request = rk3368_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3368) = {
- .name = "rk3368_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3368_sysreset,
-};
+++ /dev/null
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rk3399_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
- switch (type) {
- case SYSRESET_WARM:
- writel(0xeca8, &cru->glb_srst_snd_value);
- break;
- case SYSRESET_COLD:
- writel(0xfdb9, &cru->glb_srst_fst_value);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rk3399_sysreset = {
- .request = rk3399_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rk3399) = {
- .name = "rk3399_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rk3399_sysreset,
-};
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3328.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct sysreset_reg *offset = dev_get_priv(dev);
+ unsigned long cru_base = (unsigned long)rockchip_get_cru();
+
+ if (IS_ERR_VALUE(cru_base))
+ return (int)cru_base;
+
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rockchip_sysreset = {
+ .request = rockchip_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rockchip) = {
+ .name = "rockchip_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rockchip_sysreset,
+};
+++ /dev/null
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <sysreset.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rv1108.h>
-#include <asm/arch/hardware.h>
-#include <linux/err.h>
-
-int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
- struct rv1108_cru *cru = rockchip_get_cru();
-
- if (IS_ERR(cru))
- return PTR_ERR(cru);
-
- switch (type) {
- case SYSRESET_WARM:
- writel(0xeca8, &cru->glb_srst_snd_val);
- break;
- case SYSRESET_COLD:
- writel(0xfdb9, &cru->glb_srst_fst_val);
- break;
- default:
- return -EPROTONOSUPPORT;
- }
-
- return -EINPROGRESS;
-}
-
-static struct sysreset_ops rv1108_sysreset = {
- .request = rv1108_sysreset_request,
-};
-
-U_BOOT_DRIVER(sysreset_rv1108) = {
- .name = "rv1108_sysreset",
- .id = UCLASS_SYSRESET,
- .ops = &rv1108_sysreset,
-};
help
Select this to enable a timer for AG01P devices.
-config AE3XX_TIMER
- bool "AE3XX timer support"
- depends on TIMER && NDS32
+config ATCPIT100_TIMER
+ bool "ATCPIT100 timer support"
+ depends on TIMER
help
- Select this to enable a timer for AE3XX devices.
+ Select this to enable a ATCPIT100 timer which will be embeded
+ in AE3XX, AE250 boards.
config ROCKCHIP_TIMER
bool "Rockchip timer support"
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
-obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
DECLARE_GLOBAL_DATA_PTR;
-#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
+#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
/*
* Definition of register offsets
u32 int_mask; /* 0x38 */
};
-struct atftmr_timer_platdata {
- unsigned long *regs;
+struct atcpit_timer_platdata {
+ u32 *regs;
};
-static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
u32 val;
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
*count = timer_conv_64(val);
return 0;
}
-static int atctmr_timer_probe(struct udevice *dev)
+static int atcpit_timer_probe(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
REG32_TMR(CH_REL(1)) = 0xffffffff;
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
return 0;
}
-static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
+static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
return 0;
}
-static const struct timer_ops ag101p_timer_ops = {
- .get_count = atftmr_timer_get_count,
+static const struct timer_ops atcpit_timer_ops = {
+ .get_count = atcpit_timer_get_count,
};
-static const struct udevice_id ag101p_timer_ids[] = {
+static const struct udevice_id atcpit_timer_ids[] = {
{ .compatible = "andestech,atcpit100" },
{}
};
-U_BOOT_DRIVER(altera_timer) = {
- .name = "ae3xx_timer",
+U_BOOT_DRIVER(atcpit100_timer) = {
+ .name = "atcpit100_timer",
.id = UCLASS_TIMER,
- .of_match = ag101p_timer_ids,
- .ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
- .probe = atctmr_timer_probe,
- .ops = &ag101p_timer_ops,
+ .of_match = atcpit_timer_ids,
+ .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
+ .probe = atcpit_timer_probe,
+ .ops = &atcpit_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
};
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
+#ifdef CONFIG_ARM64
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+
switch (soc) {
#ifdef CONFIG_ARM64
case SVR_LS2080A:
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
- case SVR_LS1043A:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
#ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020:
#include <spl.h>
#include <image.h>
#include <imximage.h>
+#include <watchdog.h>
#define HID_REPORT_ID_MASK 0x000000ff
puts("\rCTRL+C - Operation aborted.\n");
return 1;
}
+
+ WATCHDOG_RESET();
usb_gadget_handle_interrupts(controller_index);
}
return;
}
+ WATCHDOG_RESET();
usb_gadget_handle_interrupts(controller_index);
sdp_handle_in_ep();
#define FSG_NUM_BUFFERS 2
/* Default size of buffer length. */
-#define FSG_BUFLEN ((u32)16384)
+#define FSG_BUFLEN ((u32)131072)
/* Maximal number of LUNs supported in mass storage function */
#define FSG_MAX_LUNS 8
help
Enables support for the on-chip xHCI controller on Rockchip SoCs.
+config USB_XHCI_RCAR
+ bool "Renesas RCar USB 3.0 support"
+ default y
+ depends on ARCH_RMOBILE
+ help
+ Choose this option to add support for USB 3.0 driver on Renesas
+ RCar Gen3 SoCs.
+
config USB_XHCI_STI
bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
depends on ARCH_STI
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
# designware
uint32_t cmd, reg;
int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
- if (!ctrl || !ctrl->hcor)
- return -EINVAL;
-
cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
/* If not run, directly return */
if (!(cmd & CMD_RUN))
* dangerous operation, it's responsibility of the calling
* code to make sure enough space is reserved.
*/
- invalidate_dcache_range((unsigned long)buffer,
- ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
+ if (buffer != NULL && length > 0)
+ invalidate_dcache_range((unsigned long)buffer,
+ ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
/* Check that the TD processing happened */
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
if (rc)
return rc;
+ if (!ctrl->hccr || !ctrl->hcor)
+ return -1;
if (init == USB_INIT_DEVICE)
goto done;
{
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct ehci_ctrl *ctrl = dev_get_priv(dev);
- int ret;
+ int ret = -1;
debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
dev->name, ctrl, hccr, hcor, init);
+ if (!ctrl || !hccr || !hcor)
+ goto err;
+
priv->desc_before_addr = true;
ehci_setup_ops(ctrl, ops);
} __attribute__ ((packed));
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define ehci_readl(x) cpu_to_be32(readl(x))
-#define ehci_writel(a, b) writel(cpu_to_be32(b), a)
+#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
+#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
#else
-#define ehci_readl(x) cpu_to_le32(readl(x))
-#define ehci_writel(a, b) writel(cpu_to_le32(b), a)
+#define ehci_readl(x) readl(x)
+#define ehci_writel(a, b) writel(b, a)
#endif
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
#include <console.h>
#include <usb.h>
#include <asm/io.h>
+#include <linux/iopoll.h>
#include "r8a66597.h"
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
+#if !defined(CONFIG_RZA_USB)
r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
i = 0;
return -1;
}
} while ((tmp & SCKE) != SCKE);
+#else
+ /*
+ * RZ/A Only:
+ * Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
+ * and USB1, so we must always set the USB0 register
+ */
+#if (CONFIG_R8A66597_XTAL == 1)
+ setbits(le16, R8A66597_BASE0, XTAL);
+#endif
+ mdelay(1);
+ setbits(le16, R8A66597_BASE0, UPLLE);
+ mdelay(1);
+ r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
+#endif /* CONFIG_RZA_USB */
#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
+#if !defined(CONFIG_RZA_USB)
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#endif
+#else
+ r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
+
+ clrbits(le16, R8A66597_BASE0, UPLLE);
+ mdelay(1);
+ r8a66597_bclr(r8a66597, USBE, SYSCFG0);
+ mdelay(1);
+
+#endif
}
static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
+#if !defined(CONFIG_RZA_USB)
r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
+#endif
}
static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
if (ret < 0)
return ret;
+#if !defined(CONFIG_RZA_USB)
r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG);
+#endif
r8a66597_bset(r8a66597, USBE, SYSCFG0);
r8a66597_bset(r8a66597, INTL, SOFCFG);
unsigned long setup_addr = USBREQ;
u16 intsts1;
int timeout = 3000;
+#if defined(CONFIG_RZA_USB)
+ u16 dcpctr;
+#endif
u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
r8a66597_write(r8a66597, make_devsel(devsel) |
(8 << dev->maxpacketsize), DCPMAXP);
r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
+#if defined(CONFIG_RZA_USB)
+ dcpctr = r8a66597_read(r8a66597, DCPCTR);
+ if ((dcpctr & PID) == PID_BUF) {
+ if (readw_poll_timeout(r8a66597->reg + DCPCTR, dcpctr,
+ dcpctr & BSTS, 1000) < 0) {
+ printf("DCPCTR BSTS timeout!\n");
+ return -ETIMEDOUT;
+ }
+ }
+#endif
+
for (i = 0; i < 4; i++) {
r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);
setup_addr += 2;
#define DEVADD8 0xE0
#define DEVADD9 0xE2
#define DEVADDA 0xE4
+#define SUSPMODE0 0x102 /* RZ/A only */
/* System Configuration Control Register */
+#if !defined(CONFIG_RZA_USB)
#define XTAL 0xC000 /* b15-14: Crystal selection */
#define XTAL48 0x8000 /* 48MHz */
#define XTAL24 0x4000 /* 24MHz */
#define SCKE 0x0400 /* b10: USB clock enable */
#define PCSDIS 0x0200 /* b9: not CS wakeup */
#define LPSME 0x0100 /* b8: Low power sleep mode */
+#endif
#define HSE 0x0080 /* b7: Hi-speed enable */
#define DCFM 0x0040 /* b6: Controller function select */
#define DRPD 0x0020 /* b5: D+/- pull down control */
#define DPRPU 0x0010 /* b4: D+ pull up control */
+#if defined(CONFIG_RZA_USB)
+#define XTAL 0x0004 /* b2: Crystal selection */
+#define XTAL12 0x0004 /* 12MHz */
+#define XTAL48 0x0000 /* 48MHz */
+#define UPLLE 0x0002 /* b1: internal PLL control */
+#endif
#define USBE 0x0001 /* b0: USB module operation enable */
/* System Configuration Status Register */
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
#define MBW 0x0800
#else
+#if !defined(CONFIG_RZA_USB)
#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
+#else
+#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
+#endif
#endif
#define MBW_8 0x0000 /* 8bit */
#define MBW_16 0x0400 /* 16bit */
+#define MBW_32 0x0800 /* 32bit */
#define BIGEND 0x0100 /* b8: Big endian mode */
#define BYTE_LITTLE 0x0000 /* little dendian */
#define BYTE_BIG 0x0100 /* big endifan */
#define USBSPD 0x00C0
#define RTPORT 0x0001
+/* Suspend Mode Register */
+#define SUSPM 0x4000 /* b14: Suspend */
+
#define R8A66597_MAX_NUM_PIPE 10
#define R8A66597_BUF_BSIZE 8
#define R8A66597_MAX_DEVICE 10
int len)
{
int i;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
+#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long fifoaddr = r8a66597->reg + offset;
unsigned long count;
unsigned long *p = buf;
{
int i;
unsigned long fifoaddr = r8a66597->reg + offset;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
+#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long count;
unsigned char *pb;
unsigned long *p = buf;
--- /dev/null
+/*
+ * Renesas RCar xHCI controller firmware version 3
+ *
+ * Copyright (c) 2014, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in binary form, without modification, are permitted
+ * provided that the following conditions are met:
+ *
+ * 1. Redistribution in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 2. The name of Renesas Electronics Corporation may not be used to endorse or
+ * promote products derived from this software without specific prior written
+ * permission.
+ * 3. Reverse engineering, decompilation, or disassembly of this software is
+ * not permitted.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS ELECTRONICS CORPORATION DISCLAIMS
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL RENESAS ELECTRONICS
+ * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is generated from the firmware blob r8a779x_usb3_v3.dlmem
+ * with associated license file LICENCE.r8a779x_usb3, both taken from
+ * linux-firmware.git [1] as of:
+ *
+ * commit 7c3dfc0bb21bf717dc19a6b677a866aef8b70c35
+ * Author: Yoshihiro Shimoda
+ * Date: Wed Aug 10 19:56:39 2016 +0900
+ *
+ * usb: host: xhci-rcar: update firmware for R-Car H3 and M3-W
+ *
+ * To generate the content of the array below, use ie. the following command:
+ * $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \
+ * sed "s@\(.\{47\}\) @\1\n@g"
+ *
+ * [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
+ */
+
+#ifndef __FIRMWARE_R8A779X_USB3_V3__
+#define __FIRMWARE_R8A779X_USB3_V3__
+
+static const u32 firmware_r8a779x_usb3_v3[] = {
+ 0xf4c455aa, 0x00d20014, 0x00000000, 0x23dc00e8,
+ 0x00000000, 0x1a5c2007, 0x0001ff63, 0x001eff80,
+ 0x0001ff23, 0x007f1a44, 0xff631a5c, 0xff800001,
+ 0xff2301e2, 0x1a440001, 0x0780007f, 0x06250061,
+ 0x00021e74, 0x40002e05, 0x40002e05, 0x8000f625,
+ 0xdc90062a, 0x556f0000, 0xdd14062a, 0x17040000,
+ 0x5573d612, 0x15ea062a, 0x57650000, 0x16c285d5,
+ 0x060200f0, 0x1deaffe0, 0xe4251724, 0x05d9128d,
+ 0x10001620, 0xe4251764, 0xd6151724, 0x1db1129f,
+ 0x8625ef25, 0x0088063f, 0x32010002, 0x3200007d,
+ 0x0392ffbe, 0x05e251e0, 0xffbe3200, 0x51e003e4,
+ 0x520005ba, 0xef2515f5, 0x063f8625, 0x000200ae,
+ 0x007d3200, 0xd6151724, 0x05b9129d, 0x0d8cffbe,
+ 0xd61417c4, 0xd6179e24, 0x000037d3, 0x4ad0ffbe,
+ 0x06405201, 0x26e6007f, 0x0f9a0631, 0x063f0000,
+ 0x00000e64, 0x0782007f, 0x8f250061, 0xee248019,
+ 0x30030000, 0x00f4063f, 0x00710002, 0x80158725,
+ 0x00d00626, 0x3a010002, 0x0108063f, 0x00700002,
+ 0x0505f01d, 0x7e3d0501, 0x7d030008, 0x80001640,
+ 0x150d1511, 0xf6241509, 0x0509fd00, 0x1503121f,
+ 0x801d7725, 0x00013723, 0x1764121e, 0x063f5c11,
+ 0x0002013e, 0x0642006e, 0x0780007f, 0xe8060061,
+ 0x0d0cffbe, 0x0001577d, 0x007f0640, 0x0d0a07be,
+ 0x17201624, 0x9c00062a, 0x118a03ff, 0x17210764,
+ 0xffec0602, 0xf6240d89, 0x35011720, 0x12820503,
+ 0x1505125d, 0x1724007f, 0x11461721, 0xf6241db2,
+ 0x55021720, 0x12c2100a, 0x3f6211c4, 0x160a172d,
+ 0x15030001, 0x17295724, 0x05bb51e2, 0x17250764,
+ 0x17251724, 0xeeee062a, 0x12c2eeee, 0x576211c4,
+ 0x007f172d, 0x00610780, 0xe8060086, 0x17e0ffbe,
+ 0x5c591724, 0x1281580a, 0xe9e00db1, 0x17240d92,
+ 0x129dd605, 0x172405d9, 0x129dd605, 0x500bfdd1,
+ 0x007f0640, 0x3bd60631, 0x063f0000, 0x00000e64,
+ 0x0780007f, 0x06250061, 0x00021e74, 0x40002e05,
+ 0x40002e05, 0x0dd00744, 0x17441201, 0xef840dd1,
+ 0xea610dd1, 0x0dc205e1, 0x0dd1ea63, 0x15b50df2,
+ 0x0046ff80, 0x1de251e0, 0x14b6ff80, 0xff800df5,
+ 0x0dc50116, 0x023aff80, 0xff8005b5, 0xff800360,
+ 0x05c514be, 0xffbe3201, 0x3f841702, 0x39fd0dd1,
+ 0x0622ddf2, 0xaaaa1100, 0x32013902, 0x16d8ffbe,
+ 0x0640d5f5, 0x0780007f, 0xffbe0061, 0x51e00398,
+ 0x320105ca, 0x00eeffbe, 0x1c3affbe, 0x0386ffbe,
+ 0x05ca51e0, 0xffbe3201, 0xff8000dc, 0xff800438,
+ 0x321f04a2, 0xfebcffbf, 0x036affbe, 0x05ca51e0,
+ 0xffbe3201, 0x172400c0, 0x1282d60d, 0xffbe15e9,
+ 0xf62442ce, 0x1500d600, 0xf1ff5620, 0x1501114a,
+ 0xd6051724, 0x05d9128d, 0xd6019e24, 0x000087d3,
+ 0xd6b91724, 0x08f01764, 0x032affbe, 0x05ca51e0,
+ 0xffbe3201, 0xef250080, 0x063f8625, 0x000202fc,
+ 0x007d3201, 0x030effbe, 0x05ca51e0, 0xffbe3201,
+ 0xff800064, 0x062604d6, 0x000224ac, 0x1de8ffbe,
+ 0x15f251e0, 0x02eeffbe, 0x05ca51e0, 0xffbe3201,
+ 0xef250044, 0x063f8625, 0x00020338, 0x007d3200,
+ 0x016087e0, 0xffbe3201, 0x52011578, 0x0dd05744,
+ 0x007f0640, 0x30e10780, 0xd6051724, 0x128dd200,
+ 0x172415a9, 0x1282d60d, 0x172405d1, 0x1285d605,
+ 0x9e240da1, 0x17d3d600, 0xffbe0000, 0xff80440a,
+ 0x6dd500e2, 0x481affbe, 0xd7e91724, 0x15d11284,
+ 0xd60d1724, 0x15911282, 0x1e26ffbe, 0xd6011724,
+ 0x05b91298, 0xd602bfc4, 0xd6051724, 0x05d9129b,
+ 0x04001640, 0xd6051764, 0xd7e91724, 0x05a91284,
+ 0x1724d201, 0x128dd605, 0x17240d91, 0x1282d60d,
+ 0xd1e005d9, 0xffbe05ba, 0xef251eda, 0x063f82b1,
+ 0x000203de, 0x1724007d, 0x1282d60d, 0xd1e035a9,
+ 0x172435ea, 0x1281d6b9, 0x178425f9, 0x11e008f3,
+ 0xea0125ba, 0x80001625, 0x00c4de02, 0x301d15d5,
+ 0xffbe0086, 0x51e0d8a6, 0x372a0de2, 0xe73b0001,
+ 0x063f0001, 0x00020422, 0x51e0007c, 0x87c405ca,
+ 0x0da5d6b8, 0x1724ea41, 0x52025c59, 0x05a91281,
+ 0xe9ea5201, 0x1201e5d7, 0x08f91744, 0xd60c8fc4,
+ 0x05dad1e0, 0x205affbe, 0x03caff80, 0x30ff0640,
+ 0x00610780, 0x8625ef25, 0x046a063f, 0x32010002,
+ 0xffbe007d, 0xffbe1572, 0x064015de, 0x0780007f,
+ 0x17a40061, 0x12610dd1, 0x178415ba, 0x11e0e459,
+ 0xffbe0df2, 0xef2542f2, 0x063f806d, 0x0002049a,
+ 0x9e24007d, 0x1fd3d60f, 0x07440000, 0x17240dd1,
+ 0x1285d605, 0x27c405e9, 0xff80d6b2, 0x45d50092,
+ 0x82b9ef25, 0x04c4063f, 0x007d0002, 0x05c251e0,
+ 0x181effbe, 0x17243da5, 0x1282e421, 0x32000dd9,
+ 0x13deffbe, 0x82c1ef25, 0x04e8063f, 0x007d0002,
+ 0x0dd00744, 0x17242da5, 0x1288e421, 0xffbe05b9,
+ 0x17242250, 0x1289e425, 0xffbe05b9, 0x1724224c,
+ 0x128ae425, 0xffbe05b9, 0xffbe24d6, 0x51e000f8,
+ 0x320105ca, 0xfe4effbd, 0xe4211724, 0x0dd91281,
+ 0x0dd117a4, 0x05da1261, 0xd60f9e24, 0x00001fd3,
+ 0xd60c9fc4, 0x0026ff80, 0x007f0640, 0x00610780,
+ 0x8625ef25, 0x0556063f, 0x32000002, 0xffbe007d,
+ 0xffbe1562, 0x0640166e, 0x0782007f, 0xef250061,
+ 0x063f8019, 0x00020574, 0x007d3003, 0x8625ef25,
+ 0x0582063f, 0x32000002, 0xffbe007d, 0xffbe168c,
+ 0x372316b4, 0xef250001, 0x063f801d, 0x0002059a,
+ 0xffbe007d, 0x06421724, 0x0780007f, 0x172400e1,
+ 0x1281e421, 0x17240d81, 0x1284e439, 0xff8005c1,
+ 0x45c50090, 0x82b9ef25, 0x05c8063f, 0x007d0002,
+ 0x05c251e0, 0x188affbe, 0xef253d95, 0x063f82d5,
+ 0x000205e0, 0x007d3200, 0x8311ef25, 0x05ec063f,
+ 0x007d0002, 0x08f717a4, 0x05ba11e0, 0x0450ff80,
+ 0x02bcff80, 0x08f71784, 0x25821262, 0x08f717a4,
+ 0x1dca11e0, 0x456cffbe, 0xffbee00a, 0xef25313e,
+ 0x063f82e1, 0x00020622, 0xef25007d, 0x063f82f1,
+ 0x0002062e, 0xffbe007d, 0xe1e0327a, 0xffbe05f2,
+ 0x51e04542, 0xffbe05ba, 0x06402cf4, 0x078200ff,
+ 0xef250061, 0x063f8019, 0x00020658, 0x007d3003,
+ 0x8625ef25, 0x0666063f, 0x32010002, 0x1724007d,
+ 0x1281ea01, 0x07c405b1, 0xffbeea00, 0xf62416da,
+ 0x1558d600, 0x00105640, 0x1559110a, 0x171affbe,
+ 0x00013723, 0x801def25, 0x0698063f, 0x007d0002,
+ 0x85adef25, 0x06a4063f, 0x007d0002, 0x8019ef25,
+ 0x06b2063f, 0x30030002, 0xffbe007d, 0x3723174e,
+ 0xef250001, 0x063f801d, 0x000206c6, 0x0642007d,
+ 0x0780007f, 0x121f0061, 0x5c00f624, 0x15091507,
+ 0x150d150b, 0xfd00f624, 0x15031505, 0xe900f624,
+ 0x15071505, 0xd600f624, 0x15061505, 0x0d911282,
+ 0x1764121f, 0x0000d605, 0x00000000, 0x00000000,
+ 0x8001ef25, 0x0714063f, 0x007d0002, 0x8015ef25,
+ 0x01ec0626, 0x3a020002, 0x0728063f, 0x007d0002,
+ 0x8021ef25, 0x0734063f, 0x007d0002, 0x007f0640,
+ 0x00210780, 0xfbccffbd, 0x07d01620, 0x0fb8f624,
+ 0x56801480, 0x5481ffff, 0x14835482, 0x001c1620,
+ 0x0818f624, 0x520413b0, 0x120353b1, 0x13b313b2,
+ 0x5bb45a01, 0x5c8153b5, 0x00c85620, 0x5e205482,
+ 0x5c830190, 0x00645e20, 0x54855c84, 0x04870486,
+ 0x00fa5620, 0x5e205488, 0x5c89012c, 0x5e20548a,
+ 0x5c8b0014, 0x03c05620, 0x5205548c, 0x539b539a,
+ 0x639c6206, 0x6b9d6a09, 0x539f5b9e, 0x63a153a0,
+ 0x5ba25a0a, 0x00105e20, 0x5a025ba3, 0x5ba55ba4,
+ 0x13a713a6, 0x5ba913a8, 0x13ab5baa, 0x13ad13ac,
+ 0x5baf53ae, 0x003f0640, 0x00610780, 0xe000f624,
+ 0x96201544, 0x9e24f0ff, 0x1152fb75, 0x03001682,
+ 0xafd31545, 0xffbe0000, 0x27c41806, 0xef25d6b2,
+ 0x063f834d, 0x00020812, 0xffbe007d, 0x064018a0,
+ 0x0782007f, 0xef250061, 0x063f8019, 0x0002082c,
+ 0x007d3003, 0x08f317a4, 0x1d8a1261, 0xd6051724,
+ 0x15c9129c, 0x08001640, 0xd6051764, 0x00001200,
+ 0x00000000, 0x00000000, 0x12671241, 0x1724fd96,
+ 0x129cd605, 0x074405b1, 0xffbe08f3, 0x51e02500,
+ 0xffbe1dc2, 0x37232554, 0xef250001, 0x063f801d,
+ 0x0002087e, 0x1724007d, 0x5640d605, 0x114a0300,
+ 0xffbe15c2, 0x17241a1e, 0x1282fd05, 0x17240de1,
+ 0x1285d605, 0x0d95fd91, 0x00013723, 0x801def25,
+ 0x08b0063f, 0x007d0002, 0x007f0642, 0x00610782,
+ 0x8019ef25, 0x08c6063f, 0x30030002, 0xffbe007d,
+ 0x51e02650, 0xffbe05da, 0xffbe26d6, 0x37232710,
+ 0xef250001, 0x063f801d, 0x000208e6, 0x0642007d,
+ 0x0780007f, 0xffbe0021, 0x51e02906, 0xffbe05b2,
+ 0x06402acc, 0x0780003f, 0xef250061, 0x063f8631,
+ 0x0002090e, 0x51e0007d, 0xffbe05ba, 0x0640325c,
+ 0x0780007f, 0xd20070e1, 0x17441201, 0x16250855,
+ 0xce028000, 0xde020330, 0x17240334, 0xe802eab5,
+ 0xea9aeaca, 0x003f16c2, 0x35c2e9e2, 0x001f16dd,
+ 0x000c36e2, 0x170631c4, 0x362694b4, 0x12d894b0,
+ 0x1261129c, 0x05d21df1, 0x0da11263, 0x1da515c2,
+ 0x0001e739, 0x0974063f, 0x007c0002, 0xe73b15d5,
+ 0x063f0001, 0x00020982, 0x06aa007c, 0x0dc2ffff,
+ 0x0da5d201, 0x0009e73b, 0x0998063f, 0x007c0002,
+ 0xff8005b5, 0xea41003e, 0x003f56dd, 0xeab65744,
+ 0x1640c5d5, 0xf6240001, 0x1503ea00, 0xe802155a,
+ 0xea9aeaca, 0x003f16c2, 0xbd8ae9e2, 0x05fad261,
+ 0x8339ef25, 0x09d4063f, 0x007d0002, 0x70ff0640,
+ 0x00610780, 0x5864f006, 0x5ad81303, 0x12d85a9c,
+ 0x0dba1299, 0x80011724, 0x30005640, 0x25d2114a,
+ 0x80011724, 0x129a12ca, 0x52c25002, 0x572a51c4,
+ 0x66408001, 0x514c8000, 0x060b1d82, 0x15d1fff0,
+ 0x57eb5201, 0x5f2400c0, 0x514be435, 0x38020de2,
+ 0x000c16e2, 0x854def25, 0x47e211c4, 0x32440fc9,
+ 0x0a40063f, 0x007d0002, 0x007f0640, 0x00e10780,
+ 0x2200063c, 0xf624aaaa, 0xe86000a4, 0xea610384,
+ 0x0d8205e1, 0x0d91ea63, 0x0dd50db2, 0x4292ffbe,
+ 0xff800dd5, 0x0da50034, 0x0076ff80, 0xffbe05f5,
+ 0x05c542de, 0xffbe3202, 0x3f840ed2, 0x39fd00a5,
+ 0x391c05d2, 0xffbe3202, 0x17840eae, 0x11e000a9,
+ 0x0640ddba, 0x078000ff, 0xefa40061, 0xea6100a5,
+ 0x159205e1, 0x05e1ea63, 0x0da50d82, 0x430effbe,
+ 0xffbe0da5, 0x05f543bc, 0x4406ffbe, 0x320305c5,
+ 0x0e88ffbe, 0x00a53fa4, 0x0d8239fd, 0x33000622,
+ 0x3902aaaa, 0xffbe3204, 0x06400e5e, 0x0780007f,
+ 0xef8400e1, 0xe7a400a7, 0x101d00a7, 0xffed0602,
+ 0x00424de1, 0x00160013, 0x001c0019, 0x0022001f,
+ 0x00280025, 0x002e002b, 0x00340031, 0x003a0037,
+ 0x0040003d, 0x00490043, 0xffbe0046, 0x3da543ea,
+ 0x4488ffbe, 0xffbe35f5, 0x35c5448a, 0x0098ff80,
+ 0xff803595, 0x2de500d4, 0x0114ff80, 0xff802db5,
+ 0x2d8501a8, 0x01e0ff80, 0xff8025d5, 0x25a502fe,
+ 0x05b0ff80, 0xff801df5, 0x1dc505d4, 0x694effbe,
+ 0xffbe1d95, 0x15e56a22, 0x0604ff80, 0xff8015b5,
+ 0x1585061e, 0x6c9effbe, 0xffbe0dd5, 0x0da56cea,
+ 0x6d96ffbe, 0xffbe05f5, 0x05c56e5e, 0xffbe3204,
+ 0x3f840dba, 0x39fd00a7, 0x06220d82, 0xaaaa4400,
+ 0x32083902, 0x0d90ffbe, 0x00a73fa4, 0x0d9239fc,
+ 0x55000622, 0x3902aaaa, 0x00103620, 0x0d78ffbe,
+ 0x00ff0640, 0x00a717a4, 0x1dab1269, 0x000a0042,
+ 0x001b000c, 0x0010000e, 0x0012001b, 0x001b0014,
+ 0x07be0016, 0x07be4470, 0x07be4522, 0x07be458e,
+ 0x07be45ae, 0x07be461a, 0x07be463a, 0x32054696,
+ 0x0d4807be, 0x17a4007f, 0x126900a7, 0x00421dcb,
+ 0x001d000a, 0x0010000c, 0x0016000e, 0x00140012,
+ 0x0018001d, 0x46fc07be, 0x47d607be, 0x494407be,
+ 0x487207be, 0x4a3607be, 0x4a8a07be, 0x497a07be,
+ 0x4b7407be, 0x07be3206, 0x007f0d02, 0x00a717a4,
+ 0xffe70602, 0x004245d1, 0x00460019, 0x001d001b,
+ 0x0021001f, 0x00250023, 0x00290027, 0x002d002b,
+ 0x0031002f, 0x00350033, 0x00370046, 0x003b0039,
+ 0x0046003d, 0x0046003f, 0x07be0041, 0x07be4b80,
+ 0x07be4c5e, 0x07be4d0c, 0x07be4d72, 0x07be4dd2,
+ 0x07be4e8c, 0x07be4f12, 0x07be504c, 0x07be50f6,
+ 0x07be512c, 0x07be51c6, 0x07be5212, 0x07be5320,
+ 0x07be5462, 0x07be54d0, 0x07be55fa, 0x07be562e,
+ 0x07be5698, 0x07be56d0, 0x07be582c, 0x3207599c,
+ 0x0c6807be, 0x17a4007f, 0x126900a7, 0x00421d8b,
+ 0x0019000a, 0x000e000c, 0x00100019, 0x00120019,
+ 0x00140019, 0x5a3e07be, 0x5abc07be, 0x5b5407be,
+ 0x5bba07be, 0x5c2207be, 0x5d3c07be, 0x07be3208,
+ 0x007f0c2a, 0x00a717a4, 0x0d811261, 0x12631582,
+ 0x0dd205f1, 0x05e21264, 0x07be05f5, 0x07805d24,
+ 0x07be0010, 0x32095f2c, 0x0c0007be, 0x0786007f,
+ 0x378470e1, 0x16240811, 0xe8068284, 0xe9c2eac5,
+ 0xe4391724, 0xd200e200, 0x07a4de24, 0x05e91283,
+ 0x07b337a4, 0x6cb6ffbe, 0xffbe65e5, 0x171da9f6,
+ 0x12d90001, 0x1264129d, 0xf7dd0d9a, 0x05e20006,
+ 0x0007e79d, 0xe2d8d201, 0x17bbe29f, 0x3784000d,
+ 0xcf250811, 0x063f83cd, 0x00020dbc, 0x129f12de,
+ 0x00793802, 0xf6241201, 0x139c00ac, 0xd1e0039d,
+ 0xe1e02582, 0x171d0dda, 0xf6240015, 0x12ddeb54,
+ 0x12c3129e, 0x121ff1c2, 0x15031501, 0x120115a5,
+ 0x00acf624, 0x571d139c, 0x56ca000b, 0x5241001f,
+ 0x00c017ea, 0x139d125f, 0x07b4f624, 0x05030501,
+ 0x0e5497c4, 0x0e540fc4, 0x000d3f3b, 0x0e5407c4,
+ 0x17441203, 0x300700a7, 0x3acb3298, 0x3ac63a9b,
+ 0x08e0ffbe, 0x00ac3624, 0x00401620, 0x1501f003,
+ 0x17250503, 0x3e24839d, 0x400a0e54, 0x1505480b,
+ 0x05ccffbe, 0x70ff0646, 0x00210780, 0x00a717a4,
+ 0x0d911261, 0x126415f2, 0x15f22591, 0x1d811266,
+ 0x1d950de2, 0x003aff80, 0xfd191724, 0x129512c5,
+ 0x16c21242, 0x17440003, 0x15851714, 0x0132ff80,
+ 0xffbe0dd5, 0x0da55f18, 0x01a6ff80, 0xffbe05f5,
+ 0x05c560f8, 0xffbe320a, 0x06400ab2, 0x0780003f,
+ 0x5f2400e1, 0xee2407b1, 0x662407a4, 0x100b8000,
+ 0x50021298, 0x51cc52c2, 0x0da211e0, 0xffdf0602,
+ 0x172a05f1, 0x56400001, 0x51428000, 0x320b05ba,
+ 0x56405dc5, 0x51423000, 0x36c255e2, 0x100b00ff,
+ 0xe72512cb, 0x129b841d, 0x063f3802, 0x00020efa,
+ 0x5744007c, 0x008a0810, 0x060d680a, 0x05baff01,
+ 0x45b53205, 0x100d6ac5, 0x172211c4, 0x16c28299,
+ 0x12610007, 0x12633df2, 0x100a35ea, 0x66c21285,
+ 0x16ca0003, 0x5a01001f, 0x00c05fe2, 0x17196764,
+ 0x100c62c2, 0x172211c4, 0x5f64ea49, 0x114b171d,
+ 0x17241dea, 0x12c5fd19, 0x12421295, 0x000376c2,
+ 0xfd191724, 0x129512c5, 0x000316c2, 0xfd9a11ee,
+ 0x172d69c4, 0x16c28299, 0x12610007, 0x126315b2,
+ 0x61c40daa, 0xea49172c, 0x05d25942, 0x17441206,
+ 0x15c500a7, 0x00133620, 0x000f3fbd, 0x6b0effbe,
+ 0xef250dd5, 0x063f8625, 0x00020fa8, 0x007d3201,
+ 0xf6241201, 0x138400a4, 0x06401383, 0x172400ff,
+ 0x5e24e421, 0x128107a4, 0x172405d9, 0x1283e439,
+ 0x37ab05d9, 0x07be000f, 0x17846a64, 0x12c50811,
+ 0x172211c4, 0x16c28299, 0x12630007, 0xf62405f2,
+ 0x038300a4, 0x13841201, 0x172425a5, 0x57241719,
+ 0x12c2171d, 0x172211c4, 0x5142ea49, 0xfd191724,
+ 0x129512c5, 0x05f251e0, 0x16c21242, 0x17440003,
+ 0x0dd51714, 0x17155784, 0x000316c2, 0x05fa11ea,
+ 0x000f3fab, 0x00133620, 0x6a7207be, 0x0788007f,
+ 0x67240021, 0x62d2eab1, 0x160c629a, 0x1261ffff,
+ 0x126315b3, 0x12691592, 0x126b0df2, 0x126d0dd2,
+ 0x06020db2, 0x0d82ffef, 0xffed1602, 0x05c31261,
+ 0x12611259, 0x57844d9b, 0x5e240811, 0x100a8284,
+ 0x11cb12c5, 0x05b26261, 0x0dba6262, 0x51c452c2,
+ 0x8085572a, 0x05d9528e, 0x07635200, 0x05f50001,
+ 0xeb6d5724, 0x00015763, 0xeb715724, 0x5503f003,
+ 0x1b005640, 0x05075505, 0x56ca530d, 0x568a0003,
+ 0x538d0080, 0x57225b0e, 0x5ecb0001, 0x6eca00e0,
+ 0x590d001f, 0x52d45b8e, 0x538f5299, 0xffff560c,
+ 0x05e35261, 0x05c25269, 0xffef060a, 0x3f8205ea,
+ 0x3ec7000d, 0x05d5000f, 0xeab13f24, 0x3a9c3acc,
+ 0xffbe3003, 0x12050436, 0x00a71744, 0x003f0648,
+ 0x00a717a4, 0x0d811261, 0x12631582, 0x0dd205f1,
+ 0x05e21264, 0x07be05f5, 0x07be5eac, 0x07be5fc4,
+ 0x320b6022, 0x082407be, 0x17a4007f, 0x126900a7,
+ 0x00421dab, 0x000c000a, 0x000e001b, 0x001b0010,
+ 0x00140012, 0x0016001b, 0x603607be, 0x613a07be,
+ 0x61a607be, 0x61c607be, 0x623207be, 0x625207be,
+ 0x62d007be, 0x07be320c, 0x007f07e2, 0x00a717a4,
+ 0x05d11261, 0x12620db2, 0x05d505c2, 0x643807be,
+ 0x655407be, 0x07be320d, 0x007f07c2, 0x00a717a4,
+ 0x05d11261, 0x126205e2, 0x05f505e2, 0x654007be,
+ 0x65fe07be, 0x666607be, 0x07be320e, 0x0780079e,
+ 0x008610e1, 0xeac5e806, 0x077de9c4, 0x077d8289,
+ 0x077d828d, 0x077d8291, 0x077d8295, 0x077d8299,
+ 0x077d829d, 0xe00682a1, 0xd8070087, 0x6b06ffbe,
+ 0x8285171d, 0x301c381b, 0x129d12d9, 0x05ca1264,
+ 0x6c54ffbe, 0xffbe05b5, 0x06406c86, 0x078010ff,
+ 0xd80770e1, 0xd008009b, 0xc809009a, 0x009ce006,
+ 0xeac5e81c, 0x82841624, 0x301de9c2, 0x46203a00,
+ 0xffbe0020, 0x301c062a, 0x401a381b, 0xffbe4819,
+ 0x301c6cba, 0x0001171d, 0x401a381b, 0x12d94819,
+ 0x1264129d, 0xffbe158a, 0xf7dd6e9e, 0x48190006,
+ 0x381b401a, 0x05ca301c, 0x6f1affbe, 0xffbe05e5,
+ 0x05b56f4e, 0x6f54ffbe, 0x70ff0640, 0x10e10780,
+ 0xe8060086, 0xe9c4eac5, 0x0087e006, 0xffbed807,
+ 0x171d7016, 0xee3d8285, 0x301c8284, 0x12d9381b,
+ 0x1264129d, 0xffbe0dea, 0xf7dd7012, 0x381b0006,
+ 0x05ca301c, 0x7064ffbe, 0xffbe05e5, 0x05b570c6,
+ 0x70f8ffbe, 0x10ff0640, 0x00610780, 0xe8060086,
+ 0x1624eac4, 0xe9c205a4, 0x00051728, 0x008b5807,
+ 0x30025002, 0x529852d0, 0x00013e0a, 0x32900087,
+ 0x2da25a61, 0x1dc25a63, 0x35aa5a64, 0x129d12da,
+ 0x05e21261, 0x0d821263, 0x0da21265, 0x30080dd5,
+ 0x8512ffbe, 0x300825f5, 0x85f4ffbe, 0x300825b5,
+ 0x86d6ffbe, 0x30081df5, 0x879cffbe, 0x12da1db5,
+ 0x1261129d, 0x126505b2, 0xffbe05ca, 0x15a58858,
+ 0x8862ffbe, 0x12da0df5, 0x1261129d, 0x126505b2,
+ 0xffbe05ca, 0x05e58860, 0x8886ffbe, 0xffbe05b5,
+ 0x577d88ac, 0x06400001, 0x0780007f, 0x00860061,
+ 0xeac4e806, 0x05a41624, 0xefc7e9c2, 0x30070004,
+ 0xffbe05ca, 0x05b588c4, 0x8976ffbe, 0x0005577d,
+ 0x007f0640, 0xffe1078a, 0x00bc3620, 0x8cbcffbe,
+ 0xffbea00a, 0x57638cbe, 0xffbe0002, 0x57638cb6,
+ 0xffbe0004, 0x57638cb4, 0x36200006, 0xffbe00bc,
+ 0x57638cae, 0x36200008, 0xffbe00bc, 0x57638caa,
+ 0xffbe000a, 0x57638cdc, 0xffbe000c, 0x57638cd4,
+ 0xffbe000e, 0x57638cd2, 0x36200010, 0xffbe00bc,
+ 0x57638ccc, 0xaa000012, 0xb200ba00, 0xe815ca00,
+ 0x1624eac3, 0xe9c204a4, 0xd860f01d, 0xe063c067,
+ 0x0220dff4, 0xffbe3018, 0xf01d8c42, 0xe7ea1061,
+ 0x57e30220, 0x5fe30003, 0x17ea0005, 0x50650220,
+ 0x57ebe1db, 0x11dc0220, 0x5fe351c2, 0x10640007,
+ 0x022017eb, 0x11cad862, 0x000957e3, 0xdfeae066,
+ 0x30180220, 0xffbed9c2, 0xe7ea8c16, 0xf01d0220,
+ 0xd060e1db, 0x000b17e3, 0xd8633018, 0x0220d7e2,
+ 0x8c04ffbe, 0x1061f01d, 0x0220dfea, 0x000d57e3,
+ 0x000f5fe3, 0x022017ea, 0xd9da5065, 0x022057eb,
+ 0x51c211db, 0x00115fe3, 0x17eb1064, 0xd0620220,
+ 0x57e311ca, 0xd8660013, 0x0220d7ea, 0xd1c23018,
+ 0x8c0affbe, 0x0220dfea, 0xb9fcd9da, 0xb81c05a9,
+ 0x05a9b1fb, 0xee1db01b, 0xca410040, 0xca640099,
+ 0x10159dc1, 0x500212c2, 0xbf6a51c4, 0x11c403bd,
+ 0x03ddb762, 0x0095aa41, 0x85f1aa68, 0xffff064a,
+ 0x00210780, 0x00041706, 0x12da0087, 0x16c2129d,
+ 0x3a610003, 0x2dc255b1, 0x3dd13a63, 0x3a6415e2,
+ 0x12614dda, 0x0de205e1, 0x05e11263, 0x45e50d82,
+ 0xa402ffbe, 0xffbe45c5, 0x4595a464, 0xa546ffbe,
+ 0xffbe3de5, 0x3db5a602, 0x05e11261, 0x12630de2,
+ 0x0d8205e1, 0xffbe35b5, 0x3595a3b8, 0xa41affbe,
+ 0xffbe2de5, 0x2db5a4d2, 0xa58effbe, 0x12612d85,
+ 0x0de205e1, 0x05e11263, 0x25850d82, 0xa35cffbe,
+ 0xffbe1de5, 0x1db5a3d0, 0xa47cffbe, 0xffbe1d85,
+ 0x15d5a538, 0x05e11261, 0x12630de2, 0x0d8205e1,
+ 0xffbe0dd5, 0x0db5a31c, 0xa3a6ffbe, 0xffbe0d85,
+ 0x05d5a428, 0xa50effbe, 0x520105a5, 0x003f0640,
+ 0x00210780, 0x0fc11784, 0x05f211e0, 0x0fb8f624,
+ 0x03883069, 0xabf4ffbe, 0xfd111724, 0x05b11284,
+ 0xfd081fc4, 0x003f0640, 0xf0e10780, 0x8625ef25,
+ 0x3201d200, 0x15e4063f, 0x007d0002, 0x5c591724,
+ 0x1281c00a, 0x0000e7e9, 0x80001625, 0x00c0ce02,
+ 0x301c1db5, 0xffbe0086, 0xe80ac6b2, 0x15b2e9e0,
+ 0xff80301d, 0x373d00a0, 0xdf390001, 0x063f0001,
+ 0x0002161e, 0x5261007b, 0xcfdd05c2, 0x05b20003,
+ 0x0d95d201, 0x1724e241, 0x12815c59, 0x000017e9,
+ 0xe587e1e2, 0x8625ef25, 0x164a063f, 0x30180002,
+ 0x501a007d, 0xf0ff0640, 0x10e10780, 0x5c591724,
+ 0x1281ea02, 0xea0105a9, 0x80001625, 0x00c0de02,
+ 0x301d15e5, 0xffbe0086, 0xe00ac642, 0x0de2e1e0,
+ 0xff80301c, 0x373c0030, 0xe73b0001, 0x063f0001,
+ 0x0002168e, 0x5261007c, 0xea410db2, 0x5c591724,
+ 0x12815202, 0x520105a9, 0xe5c7e9ea, 0x06405200,
+ 0x1a5c10ff, 0x00011726, 0x0001062a, 0x17630012,
+ 0x12cb0001, 0x114a128b, 0x00125640, 0x0dea11ea,
+ 0x17461202, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x1a440000, 0xf624007f,
+ 0x03800d24, 0x00dc1620, 0x12021381, 0x03831382,
+ 0x0d290764, 0x12011388, 0x007f1389, 0x00e10780,
+ 0x09e1ef84, 0x09e1e7a4, 0x1267101d, 0x0042259b,
+ 0x000b0008, 0x0011000e, 0x00170014, 0x001d001a,
+ 0x006eff80, 0xff8015d5, 0x15a501c2, 0xd03cffbe,
+ 0xffbe0df5, 0x0dc5d088, 0xd0f8ffbe, 0xff800d95,
+ 0x05e501f8, 0xd1f6ffbe, 0xffbe05b5, 0x3f84d2f4,
+ 0x39fd09e1, 0x06220d92, 0xaaaa6600, 0x36203902,
+ 0xffbe0020, 0x3fa401d2, 0x39fc09e1, 0x06220d92,
+ 0xaaaa7700, 0x36203902, 0xffbe0040, 0x178401ba,
+ 0x11e009e1, 0xff8005b2, 0x0640066c, 0x078000ff,
+ 0x17a40021, 0x126109e1, 0x05f205d1, 0x0d821263,
+ 0xff800d95, 0x05e5002c, 0x0056ff80, 0xffbe05b5,
+ 0xffbecdd4, 0x5784d2a8, 0x17a409e1, 0x51e209e3,
+ 0xf62405d2, 0x13a409bc, 0x064003a5, 0x0780003f,
+ 0xffbe0061, 0x1724cc88, 0x12815c59, 0xef250df1,
+ 0x063f8625, 0x000217f4, 0x007d3201, 0x8625ef25,
+ 0x1802063f, 0x300a0002, 0x0640007d, 0x0788007f,
+ 0x17240061, 0x12815c59, 0x17246de1, 0x5640c0a1,
+ 0x114a8000, 0x17240d9a, 0x129cd621, 0x962405d1,
+ 0x1fd2d623, 0x17240000, 0x5640c0a1, 0x114a8000,
+ 0x12035da2, 0xc000f624, 0x15501531, 0x55b2114a,
+ 0x8625ef25, 0x1856063f, 0x32010002, 0x1724007d,
+ 0x128efb75, 0x178415c9, 0x06025c61, 0xfdc2ffdf,
+ 0x5c611784, 0xffde0602, 0x172405ea, 0x06c2fb9d,
+ 0xf5fa000c, 0xfb759624, 0x0000afd2, 0xc0648fc4,
+ 0xd6239624, 0x00009fd2, 0x0dd11784, 0x05fa1262,
+ 0x3a013200, 0x4a024200, 0x3224ffbe, 0x17441202,
+ 0x172409e1, 0x1282c061, 0x074405c9, 0x1db509e1,
+ 0xc000f624, 0x35583d5a, 0xffbd4210, 0x1624fdf4,
+ 0xf00308fc, 0x16201501, 0x150300c0, 0x20001620,
+ 0x17251505, 0x362481ad, 0x400a09bc, 0x1507480b,
+ 0xfad6ffbd, 0x007f0648, 0x00210780, 0x09e117a4,
+ 0x05e211e0, 0x05f21264, 0x0d821265, 0xffbe0d95,
+ 0x05e5ccac, 0xccf2ffbe, 0xffbe05b5, 0xffbecd76,
+ 0x5784d14c, 0x17a409e1, 0x51e209e3, 0x12640db2,
+ 0x9e2405da, 0x07d3c049, 0xf6240000, 0x13a409bc,
+ 0x064003a5, 0x0780003f, 0xffbe0061, 0x1784cf60,
+ 0x126609e1, 0xef250dda, 0x063f824d, 0x0002195a,
+ 0xef25007d, 0x063f8251, 0x00021966, 0x0640007d,
+ 0x0780007f, 0xffbe0021, 0x1784d2a0, 0x12610a15,
+ 0x05d20de1, 0x05e11263, 0x0d950d82, 0xd30cffbe,
+ 0xffbe05e5, 0x05b5d3da, 0xd4b4ffbe, 0x003f0640,
+ 0x00210780, 0x0a0d1724, 0x00ff062b, 0x5200ffff,
+ 0x1262114b, 0x96400da2, 0x11f20030, 0x96400d92,
+ 0x11f20031, 0x0d950d82, 0xd518ffbe, 0xffbe05e5,
+ 0x05b5d5f8, 0xd60effbe, 0x003f0640, 0x00210780,
+ 0x0a0d1724, 0x5ec25200, 0x060b00ff, 0x15eaff80,
+ 0x12611298, 0x05f215b1, 0x0d811263, 0x126f0da2,
+ 0x0dc50db2, 0xd63cffbe, 0xffbe0d95, 0x05e5d64c,
+ 0xd65cffbe, 0xffbe05b5, 0x0640d662, 0x17a4003f,
+ 0x12610a0f, 0x05f21581, 0x05f11263, 0x126f0d82,
+ 0x0d950d82, 0xd65a07be, 0xd68007be, 0xd6a607be,
+ 0xd6c007be, 0x0780007f, 0x17840021, 0x52000a0d,
+ 0xff800602, 0x05e20df9, 0xff7e0602, 0x0d8205e9,
+ 0xffbe0d95, 0x05e5d6f6, 0xd706ffbe, 0xffbe05b5,
+ 0x0640d720, 0x1784003f, 0x06020a0d, 0x05baff80,
+ 0xd74607be, 0xff7f0602, 0x07be05ba, 0x07bed768,
+ 0x0780d76e, 0x17240021, 0x062b0a0d, 0xffff00ff,
+ 0x114b5200, 0x0da21262, 0x00309640, 0x0d9211f2,
+ 0x00319640, 0x0d8211f2, 0xffbe0d95, 0x05e5d822,
+ 0xd8d4ffbe, 0xffbe05b5, 0x0640d8ec, 0x1784003f,
+ 0x520109e1, 0x05ba1266, 0xd91a07be, 0x1784007f,
+ 0x520109e1, 0x05ba1266, 0xd98007be, 0x0780007f,
+ 0xee240061, 0x301dc500, 0xd9d6ffbe, 0x0009361d,
+ 0xd9e8ffbe, 0x0012361d, 0xffbe3a00, 0x361dda00,
+ 0x3a000019, 0xda2cffbe, 0x001f361d, 0xffbe3a01,
+ 0x361dd9ec, 0x3a010026, 0xda18ffbe, 0x007f0640,
+ 0x00610780, 0xc500ee24, 0xffbe301d, 0x361dda12,
+ 0xffbe0005, 0x0640da1a, 0x0780007f, 0x170400e1,
+ 0x16c2097c, 0x12610007, 0x126305b2, 0xffbe05ba,
+ 0x1724db90, 0x1285c0a1, 0x063c2dd1, 0xaaaa8800,
+ 0x0b71efa4, 0x0b700744, 0x0d91ea61, 0xea630db2,
+ 0xea650dc2, 0xea660dd2, 0x0df50de2, 0xdce8ffbe,
+ 0xffbe0dc5, 0x0d95dd3a, 0xdddcffbe, 0xffbe05e5,
+ 0x05b5de32, 0x00a6ff80, 0x0b713fa4, 0x05e239fd,
+ 0x3620391c, 0xffbd0080, 0x1784fd8e, 0x11e00b71,
+ 0x0640dd8a, 0x078000ff, 0x170400e1, 0x16c2093c,
+ 0x12610007, 0x126305b2, 0xffbe05ba, 0xffbedbb8,
+ 0x51e0eba0, 0x17243592, 0x1285c0a1, 0x063c2dd1,
+ 0xaaaacc00, 0x0c57efa4, 0x0c560744, 0x0d91ea61,
+ 0xea630db2, 0xea650dc2, 0xea660dd2, 0x0df50de2,
+ 0xe2dcffbe, 0xffbe0dc5, 0x0d95e32e, 0xe3e8ffbe,
+ 0xffbe05e5, 0x05b5e47c, 0x00feff80, 0x0c573fa4,
+ 0x05e239fd, 0x3620391c, 0xffbd0400, 0x1784fd0a,
+ 0x11e00c57, 0x0640dd8a, 0x078000ff, 0xef840061,
+ 0x101d0b73, 0x359b126b, 0x000c0042, 0x0012000f,
+ 0x00180015, 0x001e001b, 0x00240021, 0x002a0027,
+ 0xffbe002d, 0x2595dd88, 0x005cff80, 0xffbe1de5,
+ 0x1db5de12, 0xde3effbe, 0xffbe1d85, 0x15d5de94,
+ 0xde9cffbe, 0xffbe15a5, 0x0df5dea4, 0xdf38ffbe,
+ 0xffbe0dc5, 0x0d95dfaa, 0xdfe0ffbe, 0xffbe05e5,
+ 0x05b5dff6, 0xe054ffbe, 0x0b733f84, 0x0d9239fd,
+ 0x99000622, 0x3902aaaa, 0x01003620, 0xfc78ffbd,
+ 0x007f0640, 0x00610780, 0x0b73efa4, 0x0d81ea61,
+ 0xea630da2, 0x0dd20db1, 0x0de2ea65, 0xffbe0df5,
+ 0x0dc5e036, 0xe05cffbe, 0xffbe0d95, 0x05e5e098,
+ 0xe0e8ffbe, 0xffbe05b5, 0x3fa4e198, 0x39fd0b73,
+ 0x06220d92, 0xaaaabb00, 0x36203902, 0xffbd0200,
+ 0x0640fc26, 0x0780007f, 0xef840061, 0x101d0c59,
+ 0x359b126b, 0x000c0042, 0x0012000f, 0x00180015,
+ 0x001e001b, 0x00240021, 0x002a0027, 0xffbe002d,
+ 0x2595e3c8, 0x005cff80, 0xffbe1de5, 0x1db5e41c,
+ 0xe47affbe, 0xffbe1d85, 0x15d5e4e0, 0xe508ffbe,
+ 0xffbe15a5, 0x0df5e530, 0xe544ffbe, 0xffbe0dc5,
+ 0x0d95e61e, 0xe680ffbe, 0xffbe05e5, 0x05b5e696,
+ 0xe728ffbe, 0x0c593f84, 0x0d9239fd, 0xdd000622,
+ 0x3902aaaa, 0x08003620, 0xfb9cffbd, 0x007f0640,
+ 0x00610780, 0x0c59efa4, 0x0d81ea61, 0xea630dd2,
+ 0x05f20de1, 0x0de2ea65, 0xffbe0df5, 0x0dc5e70a,
+ 0xe734ffbe, 0xffbe0d95, 0x05e5e840, 0xe890ffbe,
+ 0xffbe05b5, 0x3fa4e8c4, 0x39fd0c59, 0x06220d92,
+ 0xaaaaee00, 0x36203902, 0xffbd1000, 0x0640fb4a,
+ 0x0780007f, 0x17240061, 0x1286c061, 0x16200d99,
+ 0x17640020, 0x3202c061, 0xffbe3a00, 0xefa4ef1c,
+ 0x07440cd5, 0xea610cd9, 0x0db20d91, 0x15c1ea63,
+ 0xea650db2, 0x0de20dc1, 0xffbe0df5, 0x0dc5eb38,
+ 0xeb5effbe, 0xffbe0d95, 0x05e5ebe6, 0xec4affbe,
+ 0xffbe05b5, 0x3fa4ecc8, 0x39fd0cd5, 0x06220d92,
+ 0xaaaaff00, 0x36203902, 0xffbd2000, 0x17a4fada,
+ 0x11e00cd9, 0x0640d5da, 0x0000007f, 0x000200de,
+ 0x0000102c, 0x00001064, 0x0000109e, 0x0000111c,
+ 0x0000115a, 0x00020142, 0x00020154, 0x000011a6,
+ 0x000011ee, 0x000012a6, 0x00001250, 0x000012f4,
+ 0x00001376, 0x0000ccc8, 0x0000ccfc, 0x0000cd72,
+ 0x0000cda8, 0x0000ce0a, 0x0000cecc, 0x000215d0,
+ 0x0000cfc4, 0x0000d018, 0x0000d062, 0x00021650,
+ 0x0000d12e, 0x0000d1a8, 0x0000d204, 0x0000d274,
+ 0x0000d2d0, 0x0000d334, 0x0000d3fe, 0x0000d462,
+ 0x0000d4e8, 0x0000d54a, 0x0000d5d0, 0x0000d632,
+ 0x0000d67a, 0x0000d6e2, 0x0000d73a, 0x0000d7b4,
+ 0x0000d84c, 0x0000d8c4, 0x0000d916, 0x0000d968,
+ 0x0000d9e4, 0x0000da36, 0x0000dab2, 0x0000db04,
+ 0x0000db5a, 0x0000db84, 0x0000dba4, 0x0000dbd8,
+ 0x0000dc22, 0x0000dc50, 0x0000dc90, 0x0000dcc6,
+ 0x0000dd14, 0x0000dd62, 0x0000dd86, 0x0000dda2,
+ 0x0000ddba, 0x0000ddce, 0x0000dde2, 0x0000ddf8,
+ 0x0000de12, 0x0000de28, 0x0000de3e, 0x0000de84,
+ 0x0000defe, 0x0000dfb2, 0x0000dfe6, 0x0000e01a,
+ 0x0000e050, 0x0000e086, 0x0000e0bc, 0x0000e0f2,
+ 0x0000e150, 0x0000e19c, 0x0000e1d0, 0x0000e212,
+ 0x0000e304, 0x0000e27a, 0x0000e318, 0x0000e3a4,
+ 0x0000e42a, 0x0000c608, 0x0000c6d8, 0x0000c74e,
+ 0x0000c76a, 0x0000c786, 0x0000c7d6, 0x0000c866,
+ 0x0000c930, 0x0000c960, 0x0000c98e, 0x0000c9c8,
+ 0x0000c9de, 0x0000c9fc, 0x0000ca28, 0x0000ca6c,
+ 0x0000ca90, 0x0000caa2, 0x0000cae4, 0x0000cb88,
+ 0x0000cc30, 0x0000cc52, 0x0000e578, 0x0000ea76,
+ 0x0000eae6, 0x0000eb6a, 0x0002196a, 0x00021998,
+ 0x0000eff6, 0x0000f018, 0x000219d4, 0x00021a16,
+ 0x0000f11e, 0x0000f146, 0x00021a3e, 0x00021a6e,
+ 0x0000f23e, 0x0000f268, 0x0000f29e, 0x00021a8a,
+ 0x0000f3c8, 0x0000f3e8, 0x00021ac6, 0x00021ad6,
+ 0x0000f48a, 0x00021ae6, 0x00021b28, 0x0000f57e,
+ 0x0000f60c, 0x0000f660, 0x0000f68a, 0x0000f6a2,
+ 0x0000f6b2, 0x0000f6dc, 0x00021b42, 0x00021bbe,
+ 0x0000f940, 0x0000f9b6, 0x0000fe5e, 0x0000ffbc,
+ 0x00010084, 0x000105e0, 0x000106ee, 0x00010722,
+ 0x00010762, 0x0001078a, 0x000107f8, 0x0001085c,
+ 0x0001089e, 0x000109e8, 0x00010be0, 0x00010c84,
+ 0x00010cf4, 0x00010d82, 0x00010da0, 0x00010e0e,
+ 0x00010e60, 0x00010eb4, 0x00010f18, 0x00010f66,
+ 0x00010f6e, 0x00010f76, 0x00010fb6, 0x00010fd4,
+ 0x00001ed6, 0x00002164, 0x000022bc, 0x000023ec,
+ 0x00002328, 0x00002530, 0x00000000, 0x000025d4,
+ 0x0000274c, 0x000208ea, 0x000034b4, 0x000035ca,
+ 0x000036ae, 0x0000372e, 0x0000382e, 0x0000385e,
+ 0x00003910, 0x00003960, 0x0000398e, 0x000039fc,
+ 0x00003a68, 0x00003a98, 0x00003ace, 0x00003b0e,
+ 0x00003b2e, 0x00003b60, 0x00003b6a, 0x000208fe,
+ 0x00003bb4, 0x00003cba, 0x00003d48, 0x00003dd4,
+ 0x00003e80, 0x00003f26, 0x0002091a, 0x00004030,
+ 0x0000408a, 0x00004116, 0x00004144, 0x000041e4,
+ 0x00004328, 0x00004416, 0x0000450a, 0x00004572,
+ 0x000045a8, 0x000045fc, 0x00004650, 0x0000468c,
+ 0x000046de, 0x00004790, 0x0000488c, 0x00004a8c,
+ 0x000048ac, 0x00004ab0, 0x00000000, 0x00000000,
+ 0x00000000, 0x00004c18, 0x00004ae0, 0x000022f2,
+ 0x00004e64, 0x00006e08, 0x00006c0e, 0x00007a08,
+ 0x00007a48, 0x00007aba, 0x00007ada, 0x00007af8,
+ 0x00007b82, 0x00007bd2, 0x00007c40, 0x00007cae,
+ 0x000211b6, 0x00021206, 0x00021274, 0x00008484,
+ 0x0000851c, 0x0000857a, 0x000085ca, 0x0000865e,
+ 0x00008758, 0x000087ec, 0x000088a2, 0x00008948,
+ 0x00008a54, 0x00008ac8, 0x00008b58, 0x00008bdc,
+ 0x00008bf2, 0x00008c4c, 0x00008cb4, 0x00008d5e,
+ 0x00008de6, 0x00008e6c, 0x00008f34, 0x00008f5e,
+ 0x00008ff4, 0x00009046, 0x000090da, 0x0000911c,
+ 0x00009146, 0x0000918e, 0x000091ae, 0x000091fa,
+ 0x000092e4, 0x000093a0, 0x000093e2, 0x00009424,
+ 0x00009458, 0x00009488, 0x000094ca, 0x0000950c,
+ 0x00009540, 0x00009586, 0x000096ac, 0x000097f6,
+ 0x000212c0, 0x00009bb2, 0x00009bde, 0x00009c12,
+ 0x00021362, 0x00009daa, 0x00009e20, 0x00009e7a,
+ 0x00009eb4, 0x00009f1a, 0x00009f7e, 0x00009fd6,
+ 0x0000a00a, 0x0002138c, 0x0000a0cc, 0x0000a110,
+ 0x0000a156, 0x0000a192, 0x0000a1e2, 0x0000a28e,
+ 0x0000a3ec, 0x0000a4ac, 0x0000a4d6, 0x0000a52a,
+ 0x0000a62c, 0x0000a662, 0x0000a77c, 0x0000a7be,
+ 0x0000a7e4, 0x0000a820, 0x0000a87a, 0x0000a914,
+ 0x0000a972, 0x0000aa32, 0x0000aaa2, 0x0000abf8,
+ 0x0000ad28, 0x0000ad48, 0x0000adb0, 0x0000ae52,
+ 0x0000ae8c, 0x0000af88, 0x0000b002, 0x0000b0ae,
+ 0x0000b1aa, 0x0000b2f0, 0x0000b3b0, 0x0000b442,
+ 0x0000b470, 0x0000b51a, 0x0000b550, 0x0000b578,
+ 0x0000b59a, 0x0000b5cc, 0x0000b5f6, 0x0000b648,
+ 0x0000b78e, 0x0000b7e6, 0x0000b894, 0x000214e8,
+ 0x0000bb76, 0x0000bce2, 0x0000bd04, 0x0000bd94,
+ 0x0000be98, 0x0000bfb0, 0x0000bfb2, 0x0000bff2,
+ 0x0000c060, 0x0000c0d8, 0x0000c158, 0x0000c1c6,
+ 0x0000c30e, 0x000215a8, 0x0000c388, 0x0000c4d0,
+ 0x0000c50e, 0x0000c548, 0x0000c588, 0x0000c5c8,
+ 0x000013e4, 0x00001436, 0x0000147e, 0x000014a6,
+ 0x000014de, 0x000014f2, 0x00001546, 0x000015c4,
+ 0x000015ea, 0x0000164c, 0x00001660, 0x0000168e,
+ 0x000016ca, 0x000016f0, 0x0000171e, 0x0000175e,
+ 0x00001798, 0x000017be, 0x000017e4, 0x0000183a,
+ 0x0000186a, 0x000018cc, 0x0000193a, 0x0002017e,
+ 0x00001966, 0x0000198e, 0x0000a1ca, 0x0000c2b4,
+ 0x000201bc, 0x0000cc74, 0x00011014, 0x00011076,
+ 0x000032dc, 0x000079cf
+};
+
+#endif /* __FIRMWARE_R8A779X_USB3_V3__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Renesas RCar USB HOST xHCI Controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <usb.h>
+#include <wait_bit.h>
+
+#include "xhci.h"
+#include "xhci-rcar-r8a779x_usb3_v3.h"
+
+/* Register Offset */
+#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
+#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
+
+/* Register Settings */
+/* FW Download Control & Status */
+#define RCAR_USB3_DL_CTRL_ENABLE BIT(0)
+#define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4)
+#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8)
+
+struct rcar_xhci_platdata {
+ fdt_addr_t hcd_base;
+ struct clk clk;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct rcar_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_platdata usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+static int xhci_rcar_download_fw(struct rcar_xhci *ctx, const u32 *fw_data,
+ const size_t fw_array_size)
+{
+ void __iomem *regs = (void __iomem *)ctx->hcd;
+ int i, ret;
+
+ /* Download R-Car USB3.0 firmware */
+ setbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
+
+ for (i = 0; i < fw_array_size; i++) {
+ writel(fw_data[i], regs + RCAR_USB3_FW_DATA0);
+ setbits_le32(regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SET_DATA0);
+
+ ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
+ 10, false);
+ if (ret)
+ break;
+ }
+
+ clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
+
+ ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
+ 10, false);
+
+ return ret;
+}
+
+static int xhci_rcar_probe(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rcar_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len, ret;
+
+ ret = clk_get_by_index(dev, 0, &plat->clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get USB3 clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&plat->clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable USB3 clock\n");
+ goto err_clk;
+ }
+
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ ret = xhci_rcar_download_fw(ctx, firmware_r8a779x_usb3_v3,
+ ARRAY_SIZE(firmware_r8a779x_usb3_v3));
+ if (ret) {
+ dev_err(dev, "Failed to download firmware\n");
+ goto err_fw;
+ }
+
+ ret = xhci_register(dev, ctx->hcd, hcor);
+ if (ret) {
+ dev_err(dev, "Failed to register xHCI\n");
+ goto err_fw;
+ }
+
+ return 0;
+
+err_fw:
+ clk_disable(&plat->clk);
+err_clk:
+ clk_free(&plat->clk);
+ return ret;
+}
+
+static int xhci_rcar_deregister(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+
+ clk_disable(&plat->clk);
+ clk_free(&plat->clk);
+
+ return xhci_deregister(dev);
+}
+
+static int xhci_rcar_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+
+ plat->hcd_base = devfdt_get_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_rcar_ids[] = {
+ { .compatible = "renesas,xhci-r8a7795" },
+ { .compatible = "renesas,xhci-r8a7796" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_rcar",
+ .id = UCLASS_USB,
+ .probe = xhci_rcar_probe,
+ .remove = xhci_rcar_deregister,
+ .ops = &xhci_usb_ops,
+ .of_match = xhci_rcar_ids,
+ .ofdata_to_platdata = xhci_rcar_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct rcar_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct rcar_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
int sunxi_simplefb_setup(void *blob)
{
- struct udevice *de2, *hdmi;
+ struct udevice *de2, *hdmi, *lcd;
struct video_priv *de2_priv;
struct video_uc_platdata *de2_plat;
int mux;
debug("HDMI present but not probed\n");
}
+ ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+ "sunxi_lcd", &lcd);
+ if (ret)
+ debug("LCD not present\n");
+ else if (device_active(lcd))
+ pipeline = "mixer0-lcd0";
+ else
+ debug("LCD present but not probed\n");
+
if (!pipeline) {
debug("No active display present\n");
return 0;
sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
- /*
- * Condition in original code is a bit weird. This is attempt
- * to make it more reasonable and it works. It could be that
- * bits and conditions are related and should be separated.
- */
- if (!((edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) &&
- (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH))) {
- setbits_le32(&phy->pol, 0x300);
- }
+ if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ setbits_le32(&phy->pol, 0x200);
+
+ if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ setbits_le32(&phy->pol, 0x100);
setbits_le32(&phy->ctrl, 0xf << 12);
dtb_depends += $(DTB:.dtb=.dts)
endif
+# Pass the original device tree file through fdtgrep twice. The first pass
+# removes any unwanted nodes (i.e. those which don't have the
+# 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second
+# pass removes various unused properties from the remaining nodes.
+# The output is typically a much smaller device tree file.
+ifeq ($(CONFIG_TPL_BUILD),y)
+fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl
+else
+fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl
+endif
+quiet_cmd_fdtgrep = FDTGREP $@
+ cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \
+ -n /chosen -n /config -O dtb | \
+ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
+ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS)))
+
+$(obj)/dt-spl.dtb: $(DTB) $(objtree)/tools/fdtgrep FORCE
+ $(call if_changed,fdtgrep)
+
$(obj)/dt.dtb: $(DTB) FORCE
$(call if_changed,shipped)
-targets += dt.dtb
+targets += dt.dtb dt-spl.dtb
$(DTB): $(dtb_depends)
ifeq ($(EXT_DTB),)
arch-dtbs:
$(Q)$(MAKE) $(build)=$(ARCH_PATH) dtbs
-.SECONDARY: $(obj)/dt.dtb.S
+.SECONDARY: $(obj)/dt.dtb.S $(obj)/dt-spl.dtb.S
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_OF_EMBED) := dt-spl.dtb.o
+# support "out-of-tree" build for dtb-spl
+$(obj)/dt-spl.dtb.o: $(obj)/dt-spl.dtb.S FORCE
+ $(call if_changed_dep,as_o_S)
+else
obj-$(CONFIG_OF_EMBED) := dt.dtb.o
+endif
-dtbs: $(obj)/dt.dtb
+dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb
@:
-clean-files := dt.dtb.S
+clean-files := dt.dtb.S dt-spl.dtb.S
# Let clean descend into dts directories
subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
endif
+if ARCH_ROCKCHIP
+
+config ENV_OFFSET
+ hex
+ depends on !ENV_IS_IN_UBI
+ depends on !ENV_IS_NOWHERE
+ default 0x3f8000
+ help
+ Offset from the start of the device (or partition)
+
+config ENV_SIZE
+ hex
+ default 0x8000
+ help
+ Size of the environment storage area
+
+endif
+
endmenu
.partition = "u-boot,mmc-env-partition",
.offset = "u-boot,mmc-env-offset",
};
- s64 val, defvalue;
+ s64 val = 0, defvalue;
const char *propname;
const char *str;
int err;
offset = 0;
do {
+ if (offset & 3) {
+ printf("Badly aligned ext2_dirent\n");
+ break;
+ }
+
dir = (struct ext2_dirent *)(block_buffer + offset);
direntname = (char*)(dir) + sizeof(struct ext2_dirent);
offset = 0;
do {
+ if (offset & 3) {
+ printf("Badly aligned ext2_dirent\n");
+ break;
+ }
+
previous_dir = dir;
dir = (struct ext2_dirent *)(block_buffer + offset);
direntname = (char *)(dir) + sizeof(struct ext2_dirent);
char *delayed_buf = NULL;
short status;
+ if (blocksize <= 0)
+ return -1;
+
/* Adjust len so it we can't read past the end of the file. */
if (len + pos > filesize)
len = (filesize - pos);
(blockend >> log2blksz);
}
} else {
+ int n;
if (previous_block_number != -1) {
/* spill */
status = ext4fs_devread(delayed_start,
return -1;
previous_block_number = -1;
}
- memset(buf, 0, blocksize - skipfirst);
+ /* Zero no more than `len' bytes. */
+ n = blocksize - skipfirst;
+ if (n > len)
+ n = len;
+ memset(buf, 0, n);
}
buf += blocksize - skipfirst;
}
int fat_opendir(const char *filename, struct fs_dir_stream **dirsp)
{
- fat_dir *dir = calloc(1, sizeof(*dir));
+ fat_dir *dir;
int ret;
+ dir = malloc_cache_aligned(sizeof(*dir));
if (!dir)
return -ENOMEM;
+ memset(dir, 0, sizeof(*dir));
ret = fat_itr_root(&dir->itr, &dir->fsdata);
if (ret)
lbaint_t sector, int byte_offset, int byte_len, char *buf)
{
unsigned block_len;
- int log2blksz = blk->log2blksz;
+ int log2blksz;
ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (blk ? blk->blksz : 0));
if (blk == NULL) {
printf("** Invalid Block Device Descriptor (NULL)\n");
return 0;
}
+ log2blksz = blk->log2blksz;
/* Check partition boundaries */
if ((sector + ((byte_offset + byte_len - 1) >> log2blksz))
#include <linux/mtd/mtd.h>
#include <linux/types.h>
#include <linux/time.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
static inline void translate_spare2oob(const struct yaffs_spare *spare, u8 *oob)
int ahci_reset(void __iomem *base);
/**
- * achi_init_one_dm() - set up a single AHCI port
+ * ahci_init_one_dm() - set up a single AHCI port
*
* @dev: Controller to init
*/
-int achi_init_one_dm(struct udevice *dev);
+int ahci_init_one_dm(struct udevice *dev);
/**
- * achi_start_ports_dm() - start all AHCI ports for a controller
+ * ahci_start_ports_dm() - start all AHCI ports for a controller
*
* @dev: Controller containing ports to start
*/
-int achi_start_ports_dm(struct udevice *dev);
+int ahci_start_ports_dm(struct udevice *dev);
/**
* ahci_init_dm() - init AHCI for a controller, finding all ports
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
unsigned long fb_base; /* Base address of framebuffer mem */
#endif
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#if defined(CONFIG_POST)
unsigned long post_log_word; /* Record POST activities */
unsigned long post_log_res; /* success of POST test */
unsigned long post_init_f_time; /* When post_init_f started */
struct bootstage_data *bootstage; /* Bootstage information */
struct bootstage_data *new_bootstage; /* Relocated bootstage info */
#endif
+#ifdef CONFIG_LOG
+ int log_drop_count; /* Number of dropped log messages */
+ int default_log_level; /* For devices with no filters */
+ struct list_head log_head; /* List of struct log_device */
+#endif
} gd_t;
#endif
#define GD_FLG_RECORD 0x01000 /* Record console */
#define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */
#define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done */
+#define GD_FLG_LOG_READY 0x08000 /* Log system is ready for use */
#endif /* __ASM_GENERIC_GBL_DATA_H */
--- /dev/null
+/*
+ * Symbol access for symbols set up by binman as part of the build.
+ *
+ * This allows C code to access the position of a particular part of the image
+ * assembled by binman.
+ *
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BINMAN_SYM_H
+#define __BINMAN_SYM_H
+
+#define BINMAN_SYM_MISSING (-1UL)
+
+#ifdef CONFIG_BINMAN
+
+/**
+ * binman_symname() - Internal fnuction to get a binman symbol name
+ *
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns name of the symbol for that entry and property
+ */
+#define binman_symname(_entry_name, _prop_name) \
+ _binman_ ## _entry_name ## _prop_ ## _prop_name
+
+/**
+ * binman_sym_declare() - Declare a symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare(_type, _entry_name, _prop_name) \
+ _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_extern() - Declare a extern symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_extern(_type, _entry_name, _prop_name) \
+ extern _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_declare_optional() - Declare an optional symbol
+ *
+ * If this symbol cannot be provided by binman, an error will not be generated.
+ * Instead the image will be assigned the value BINMAN_SYM_MISSING.
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name) \
+ _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), weak, unused, \
+ section(".binman_sym")))
+
+/**
+ * binman_sym() - Access a previously declared symbol
+ *
+ * This is used to get the value of a symbol. E.g.:
+ *
+ * ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns value of that property (filled in by binman)
+ */
+#define binman_sym(_type, _entry_name, _prop_name) \
+ (*(_type *)&binman_symname(_entry_name, _prop_name))
+
+#else /* !BINMAN */
+
+#define binman_sym_declare(_type, _entry_name, _prop_name)
+
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name)
+
+#define binman_sym_extern(_type, _entry_name, _prop_name)
+
+#define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING
+
+#endif /* BINMAN */
+
+#endif
#ifndef __CHARSET_H_
#define __CHARSET_H_
+#include <linux/types.h>
+
#define MAX_UTF8_PER_UTF16 3
/**
*/
uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size);
+/**
+ * utf8_to_utf16() - Convert an utf8 string to utf16
+ *
+ * Converts up to 'size' characters of the utf16 string 'src' to utf8
+ * written to the 'dest' buffer. Stops at 0x00.
+ *
+ * @dest the destination buffer to write the utf8 characters
+ * @src the source utf16 string
+ * @size maximum number of utf16 characters to convert
+ * @return the pointer to the first unwritten byte in 'dest'
+ */
+uint16_t *utf8_to_utf16(uint16_t *dest, const uint8_t *src, size_t size);
+
#endif /* __CHARSET_H_ */
#define CONFIG_SYS_SUPPORT_64BIT_DATA
#endif
-#ifdef DEBUG
-#define _DEBUG 1
-#else
-#define _DEBUG 0
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define _SPL_BUILD 1
-#else
-#define _SPL_BUILD 0
-#endif
-
-/*
- * Output a debug text when condition "cond" is met. The "cond" should be
- * computed by a preprocessor in the best case, allowing for the best
- * optimization.
- */
-#define debug_cond(cond, fmt, args...) \
- do { \
- if (cond) \
- printf(pr_fmt(fmt), ##args); \
- } while (0)
-
-/* Show a message if DEBUG is defined in a file */
-#define debug(fmt, args...) \
- debug_cond(_DEBUG, fmt, ##args)
-
-/* Show a message if not in SPL */
-#define warn_non_spl(fmt, args...) \
- debug_cond(!_SPL_BUILD, fmt, ##args)
-
-/*
- * An assertion is run-time check done in debug mode only. If DEBUG is not
- * defined then it is skipped. If DEBUG is defined and the assertion fails,
- * then it calls panic*( which may or may not reset/halt U-Boot (see
- * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
- * before release, and after release it is hoped that they don't matter. But
- * in any case these failing assertions cannot be fixed with a reset (which
- * may just do the same assertion again).
- */
-void __assert_fail(const char *assertion, const char *file, unsigned line,
- const char *function);
-#define assert(x) \
- ({ if (!(x) && _DEBUG) \
- __assert_fail(#x, __FILE__, __LINE__, __func__); })
+#include <log.h>
typedef void (interrupt_handler_t)(void *);
extern ulong monitor_flash_len;
int mac_read_from_eeprom(void);
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
+extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
int set_cpu_clk_info(void);
int mdm_init(void);
int print_cpuinfo(void);
#define BOOTEFI_NAME "bootaa64.efi"
#elif defined(CONFIG_ARM)
#define BOOTEFI_NAME "bootarm.efi"
+#elif defined(CONFIG_X86_RUN_32BIT)
+#define BOOTEFI_NAME "bootia32.efi"
+#elif defined(CONFIG_X86_RUN_64BIT)
+#define BOOTEFI_NAME "bootx64.efi"
#endif
#endif
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
-#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 4
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#endif
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#endif /* CONFIG_PCI */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#define CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif /* CONFIG_TSEC_ENET */
/* SATA */
-#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
#ifdef CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_FSL_SATA
-#define CONFIG_LIBATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_PCIE3
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_SRIO
*/
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
#endif
#endif
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_CLK_FREQ 66666666
/*
* SD (MMC) controller
*/
-#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER 1
#define CONFIG_FTSDC010_SDIO
/*
* SD (MMC) controller
*/
-#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER 1
#define CONFIG_FTSDC010_SDIO
#define CONFIG_MXC_OCOTP
/* SATA Configs */
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
/* MMC Configs */
#define CONFIG_FSL_ESDHC
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
#define DFUARGS \
- "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+ DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_NAND
#define CONFIG_OMAP_USB3PHY1_HOST
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Network */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_IMX_HDMI
/* SATA */
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
/* Ethernet */
#define CONFIG_FEC_MXC
#ifndef CONFIG_SPL_BUILD
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_DWC_AHSATA
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
/*
* SATA
*/
-#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA_MV
-#define CONFIG_LIBATA
#define CONFIG_LBA48
/* Additional FS support/configuration */
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* SPI Flash Configs */
#define CONFIG_OMAP_USB2PHY2_HOST
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
--- /dev/null
+/*
+ * include/configs/draak.h
+ * This file is Draak board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DRAAK_H
+#define __DRAAK_H
+
+#undef DEBUG
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CONFIG_CMD_CACHE
+
+#endif /* __DRAAK_H */
--- /dev/null
+/*
+ * include/configs/eagle.h
+ * This file is Eagle board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EAGLE_H
+#define __EAGLE_H
+
+#undef DEBUG
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+#endif /* __EAGLE_H */
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
-#define CONFIG_MVSATA_IDE
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#undef CONFIG_SCSI_AHCI
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#include <configs/rk3368_common.h>
-#define CONFIG_ENV_SIZE 0x2000
-
#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EVB_RK3128_H
+#define __EVB_RK3128_H
+
+#include <configs/rk3128_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
"stdout=serial\0" \
"stderr=serial\0"
-/* SATA is not supported in Quark SoC */
-#undef CONFIG_SCSI_AHCI
-
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* MMC Configs */
#include <configs/rk3368_common.h>
-#define CONFIG_ENV_SIZE 0x2000
-
#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
- #define CONFIG_LIBATA
#endif
/*
#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c
#define CONFIG_MISC_INIT_R
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
#define CONFIG_SYS_SCSI_MAX_LUN 1
# endif
# include "imx6_spl.h"
-# ifdef CONFIG_SPL_BUILD
-# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)
-# define CONFIG_SYS_FSL_USDHC_NUM 2
-# else
-# define CONFIG_SYS_FSL_USDHC_NUM 1
-# endif
-
-# define CONFIG_SYS_FSL_ESDHC_ADDR 0
-# undef CONFIG_DM_GPIO
-# undef CONFIG_DM_MMC
-# endif
#endif
#endif /* __IMX6_ENGICAM_CONFIG_H */
--- /dev/null
+/*
+ * Configuration for Khadas VIM
+ *
+ * Copyright (C) 2017 Baylibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_PHY_ADDR 8
+
+#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
+
+#include <configs/meson-gxbb-common.h>
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Configuration for LibreTech CC
+ *
+ * Copyright (C) 2017 Baylibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_PHY_ADDR 8
+
+#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
+
+#include <configs/meson-gxbb-common.h>
+
+#endif /* __CONFIG_H */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
-#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
+#include <config_distro_defaults.h>
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+#endif
+
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"kernel_addr=0x100000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0xa00000\0" \
+ "kernel_start=0x1000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
+#undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+#ifndef CONFIG_SPL_BUILD
+#undef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0)
+#endif
+
#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=no\0" \
- "loadaddr=0x80100000\0" \
- "kernel_addr=0x100000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0xa00000\0" \
- "kernel_load=0x96000000\0" \
- "kernel_size=0x2800000\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "scriptaddr=0x80000000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x96000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0x96000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV \
+ "boot_scripts=ls1012afrdm_boot.scr\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "installer=load usb 0:2 $load_addr " \
+ "/flex_installer_arm64.itb; " \
+ "bootm $load_addr#$board\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
* I2C IO expander
*/
-#define I2C_MUX_IO1_ADDR 0x24
-#define __SW_BOOT_MASK 0xFC
-#define __SW_BOOT_EMU 0x10
-#define __SW_BOOT_BANK1 0x00
-#define __SW_BOOT_BANK2 0x01
-#define __SW_REV_MASK 0x07
-#define __SW_REV_A 0xF8
-#define __SW_REV_B 0xF0
+#define I2C_MUX_IO_ADDR 0x24
+#define I2C_MUX_IO_0 0
+#define I2C_MUX_IO_1 1
+#define SW_BOOT_MASK 0x03
+#define SW_BOOT_EMU 0x02
+#define SW_BOOT_BANK1 0x00
+#define SW_BOOT_BANK2 0x01
+#define SW_REV_MASK 0xF8
+#define SW_REV_A 0xF8
+#define SW_REV_B 0xF0
+#define SW_REV_C 0xE8
+#define SW_REV_C1 0xE0
+#define SW_REV_C2 0xD8
+#define SW_REV_D 0xD0
+#define SW_REV_E 0xC8
/* MMC */
#ifdef CONFIG_MMC
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "scriptaddr=0x80000000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV \
+ "boot_scripts=ls1012ardb_boot.scr\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "installer=load mmc 0:2 $load_addr " \
+ "/flex_installer_arm64.itb; " \
+ "bootm $load_addr#$board\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#include <asm/fsl_secure_boot.h>
#define CONFIG_FSL_ESDHC
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
- "kernel_addr=0x65000000\0" \
+ "kernel_addr=0x61000000\0" \
+ "kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
+ "kernelheader_size=0x40000\0" \
"fdt_addr_r=0x90000000\0" \
"ramdisk_addr_r=0xa0000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
BOOTENV \
"boot_scripts=ls1021atwr_boot.scr\0" \
"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
+ "$kernel_addr $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"nor_bootcmd=echo Trying load from nor..;" \
"cp.b $kernel_addr $load_addr " \
- "$kernel_size && bootm $load_addr#$board\0" \
+ "$kernel_size; env exists secureboot " \
+ "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo && mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
#endif
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run qspi_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
+ "env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run sd_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run nor_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
#endif
/*
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
- "kernel_addr=0x65000000\0" \
+ "kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0xa0000000\0" \
+ "kernelheader_addr=0x60800000\0" \
"kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
"kernel_addr_sd=0x8000\0" \
"kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
"console=ttyS0,115200\0" \
"boot_os=y\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
+ "$kernel_addr $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"nor_bootcmd=echo Trying load from nor..;" \
"cp.b $kernel_addr $load_addr " \
- "$kernel_size && bootm $load_addr#$board\0" \
+ "$kernel_size; env exists secureboot " \
+ "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run qspi_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run sd_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run nor_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#endif
#endif
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#ifndef CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT2
#endif
"fdt_addr_r=0x90000000\0" \
"ramdisk_addr_r=0xa0000000\0" \
"kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
"kernel_addr_sd=0x8000\0" \
"kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
"console=ttyS0,115200\0" \
CONFIG_MTDPARTS_DEFAULT "\0" \
BOOTENV \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
- "$kernel_start $kernel_size && bootm $load_addr#$board\0" \
+ "$kernel_start $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
#endif
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TAVDS(0x6) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1a) | \
FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
+ FTIM2_NOR_TCH(0x8) | \
FTIM2_NOR_TWPH(0xe) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run qspi_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
- "&& esbc_halt; run sd_bootcmd;"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
#endif
#endif
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#endif
-
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
/* Command line configuration */
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_CACHE
/* SATA */
#ifdef CONFIG_SCSI
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
/* Initial environment variables */
+#ifdef CONFIG_SECURE_BOOT
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
+ "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
+ "sf read 0xa0e00000 0xe00000 0x100000;" \
+ "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
+ "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
+ "mcmemsize=0x70000000 \0"
+#else /* if !(CONFIG_SECURE_BOOT) */
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
"mcmemsize=0x70000000 \0"
#endif
+#endif /* CONFIG_SECURE_BOOT */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_MISC_INIT_R
+
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#endif
+#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define MC_INIT_CMD \
"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
"sf read 0x80100000 0xE00000 0x100000;" \
- "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "env exists secureboot && " \
+ "sf read 0x80700000 0x700000 0x40000 && " \
+ "sf read 0x80740000 0x740000 0x40000 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000\0"
#elif defined(CONFIG_SD_BOOT)
#define MC_INIT_CMD \
"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
"mmc read 0x80100000 0x7000 0x800;" \
- "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "env exists secureboot && " \
+ "mmc read 0x80700000 0x3800 0x10 && " \
+ "mmc read 0x80740000 0x3A00 0x10 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000\0"
#endif
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x1000000\0" \
"kernel_addr_sd=0x8000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
"kernel_start=0x580100000\0" \
"kernelheader_start=0x580800000\0" \
"scriptaddr=0x80000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernel_size_sd=0x14000\0" \
+ "kernelhdr_size_sd=0x10\0" \
MC_INIT_CMD \
BOOTENV \
"boot_scripts=ls1088ardb_boot.scr\0" \
"bootm $load_addr#ls1088ardb\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size &&" \
+ "$kernel_addr $kernel_size ; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
"bootm $load_addr#$BOARD\0" \
- "sd_bootcmd=echo Trying load from sd card..;" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
- "env exists mcinitcmd && run mcinitcmd && " \
- "sf read 0x80200000 0xd00000 0x100000;" \
- " fsl_mc apply dpl 0x80200000;" \
- "run distro_bootcmd;run qspi_bootcmd"
+ "sf read 0x80200000 0xd00000 0x100000;" \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && sf read 0x80780000 0x780000 0x100000 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc apply dpl 0x80200000;" \
+ "run distro_bootcmd;run qspi_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+
/* Try to boot an on-SD kernel first, then do normal distro boot */
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND \
- "env exists mcinitcmd && run mcinitcmd ;" \
- "&& env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x88000000 0x6800 0x800; " \
- "&& fsl_mc apply dpl 0x88000000;" \
- "run distro_bootcmd;run sd_bootcmd"
+ "env exists mcinitcmd && mmcinfo; " \
+ "mmc read 0x80200000 0x6800 0x800; " \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && mmc read 0x80780000 0x3800 0x10 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc apply dpl 0x80200000;" \
+ "run distro_bootcmd;run sd_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
#endif
/* MAC/PHY configuration */
#endif
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
* SATA
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/*
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
-#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-/* Environment in SPI NOR flash */
-#ifdef CONFIG_MVEBU_SPI_BOOT
-/* Environment in NAND flash */
-#endif
-
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SYS_MMC_ENV_DEV 0
#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
- #define CONFIG_LIBATA
#endif
/* Framebuffer and LCD */
--- /dev/null
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONSOLE_DEV "ttymxc0"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
+
+/* Eth Configs */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+/* USB Configs */
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+#define CONFIG_SYS_RTC_BUS_NUM 2
+#define CONFIG_SYS_I2C_RTC_ADDR 0x30
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_ETHPRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE 0x77800000
+
+#define PPD_CONFIG_NFS \
+ "nfsserver=192.168.252.95\0" \
+ "gatewayip=192.168.252.95\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.252.99\0" \
+ "kernsize=0x2000\0" \
+ "use_dhcp=0\0" \
+ "nfsroot=/opt/springdale/rd\0" \
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
+ "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
+ "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
+ "set getcmd dhcp; else set kern_ipconf " \
+ "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
+ "set getcmd tftp; fi\0" \
+ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
+ "${nfsserver}:${image}; bootm ${loadaddr}\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ PPD_CONFIG_NFS \
+ "bootlimit=10\0" \
+ "image=/boot/fitImage\0" \
+ "fdt_high=0xffffffff\0" \
+ "dev=mmc\0" \
+ "devnum=0\0" \
+ "rootdev=mmcblk0p\0" \
+ "quiet=quiet loglevel=0\0" \
+ "console=" CONSOLE_DEV "\0" \
+ "lvds=ldb\0" \
+ "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
+ "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
+ "console=${console} ${rtc_status}\0" \
+ "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
+ "rootwait ${bootargs}\0" \
+ "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
+ "then setenv quiet; fi\0" \
+ "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
+ "/boot/bootcause/firstboot\0" \
+ "swappartitions=setexpr partnum 3 - ${partnum}\0" \
+ "failbootcmd=" \
+ "ppd_lcd_enable; " \
+ "msg=\"Monitor failed to start. " \
+ "Try again, or contact GE Service for support.\"; " \
+ "echo $msg; " \
+ "setenv stdout vga; " \
+ "echo \"\n\n\n\n \" $msg; " \
+ "setenv stdout serial; " \
+ "mw.b 0x7000A000 0xbc; " \
+ "mw.b 0x7000A001 0x00; " \
+ "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
+ "altbootcmd=" \
+ "run doquiet; " \
+ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+ "run hasfirstboot || setenv partnum 0; " \
+ "if test ${partnum} != 0; then " \
+ "setenv bootcause REVERT; " \
+ "run swappartitions loadimage doboot; " \
+ "fi; " \
+ "run failbootcmd\0" \
+ "loadimage=" \
+ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+ "doboot=" \
+ "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+ "run setargs; " \
+ "run bootargs_emmc; " \
+ "bootm ${loadaddr}\0" \
+ "tryboot=" \
+ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+ "run loadimage || run swappartitions && run loadimage || " \
+ "setenv partnum 0 && echo MISSING IMAGE;" \
+ "run doboot; " \
+ "run failbootcmd\0" \
+ "video-mode=" \
+ "lcd:800x480-24@60,monitor=lcd\0" \
+
+#define CONFIG_MMCBOOTCOMMAND \
+ "if mmc dev ${devnum}; then " \
+ "run doquiet; " \
+ "run tryboot; " \
+ "fi; " \
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS 48 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_FSL_IIM
+
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* I2C1 */
+#define CONFIG_SYS_NUM_I2C_BUSES 9
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
+ }
+
+#define CONFIG_BCH
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+/* Backlight Control */
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66666000
+
+/* Framebuffer and LCD */
+#ifdef CONFIG_VIDEO
+ #define CONFIG_VIDEO_IPUV3
+#endif
+
+#endif /* __CONFIG_H */
/* SATA Configuration */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Ethernet Configuration */
"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
"mmcdev=2\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "finduuid=part uuid mmc 2:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
#define CONFIG_FEC_MXC
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* UART */
/* Environment */
#define CONFIG_PREBOOT "usb start"
+#if !defined(CONFIG_SPL_BUILD)
+
+#include <config_distro_defaults.h>
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV
+
+#if defined(CONFIG_NAND)
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+#endif /* CONFIG_NAND */
+
+#define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance"; " \
+ "run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance"; " \
+ "run mmcbootz\0"
+
+#define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(ZIMAGE_MMC, zimage_mmc, 0) \
+ func(UIMAGE_MMC, uimage_mmc, 0) \
+ func(NAND, nand, 0)
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
+ "mmcbootenv=" \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan && run loadbootenv; then " \
+ "run importbootenv; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi; " \
+ "fi\0" \
"loaduimage=setenv bootfile uImage; " \
"fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"loadzimage=setenv bootfile zImage; " \
"fatload mmc ${mmcdev} ${loadaddr} zImage\0" \
- "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} " CONFIG_DEFAULT_FDT_FILE "\0" \
- "mmcboot=echo Booting ${bootfile} from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr} - ${fdtaddr}\0" \
- "mmcbootz=echo Booting ${bootfile} from mmc ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+ "mmcboot=run mmcbootenv; " \
+ "if run loaduimage && run loaddtb; then " \
+ "echo Booting ${bootfile} from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi\0" \
+ "mmcbootz=run mmcbootenv; " \
+ "if run loadzimage && run loaddtb; then " \
+ "echo Booting ${bootfile} from mmc ...; " \
+ "run mmcargs; " \
+ "bootz ${loadaddr} - ${fdtaddr};" \
+ "fi\0" \
"nandboot=echo Booting uImage from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} kernel; " \
"nand read ${fdtaddr} dtb; " \
- "bootm ${loadaddr} - ${fdtaddr}\0"
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ BOOTENV
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootenv; then " \
- "run importbootenv; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi; " \
- "else " \
- "if run loadzimage && run loaddtb; then " \
- "run mmcbootz; fi; " \
- "if run loaduimage && run loaddtb; then " \
- "run mmcboot; fi; " \
- "run nandboot; " \
- "fi; " \
- "else run nandboot; fi"
+#endif /* !CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */
#define CONFIG_PREBOOT \
"setenv preboot;" \
- "nand unlock;" \
"saveenv;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"tftpboot $loadaddr zImage;" \
"bootz $loadaddr\0" \
"nandbootcommon=echo 'Booting kernel from NAND...';" \
- "nand unlock;" \
"run nandargs;" \
"run common_bootargs;" \
"run dump_bootargs;" \
#define CONSOLEDEV "ttyO2"
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* SPL */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#if defined(CONFIG_TARGET_P2020RDB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
#endif
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#ifndef __ASSEMBLY__
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
+#define CONFIG_DFU_ENV_SETTINGS \
+ "dfu_alt_info=uboot raw 0x2 0x400 mmcpart 1;" \
+ "boot part 0 1;" \
+ "/zImage ext4 0 1;" \
+ "/imx6ul-pico-hobbit.dtb ext4 0 1;" \
+ "rootfs part 0 2\0" \
+
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_addr=0x83000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
- "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+ CONFIG_DFU_ENV_SETTINGS \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
+ "partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=boot,size=16MiB;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
+ "setup_emmc=gpt write mmc 0 $partitions; reset;\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#endif /* __PICO_IMX6UL_CONFIG_H */
#include <configs/rk3399_common.h>
-/*
- * SPL @ 32kB for ~130kB
- * ENV @ 240KB for 8kB
- * FIT payload (ATF, U-Boot, FDT) @ 256kB
- */
-#undef CONFIG_ENV_OFFSET
-#define CONFIG_ENV_OFFSET (240 * 1024)
-
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 6
-#define CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
/* Environment options */
#define CONFIG_ENV_SIZE SZ_64K
#define CONFIG_ARCH_CPU_INIT
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE 0xF1010000
+#define GICC_BASE 0xF1020000
+
/* console */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* MEMORY */
+#if defined(CONFIG_R8A77970)
+#define CONFIG_SYS_TEXT_BASE 0x58280000
+#else
#define CONFIG_SYS_TEXT_BASE 0x50000000
+#endif
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000
-#if defined(CONFIG_R8A7795)
#define CONFIG_NR_DRAM_BANKS 4
-#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
-#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
-#define PHYS_SDRAM_2 0x500000000
-#define PHYS_SDRAM_2_SIZE 0x40000000u
-#define PHYS_SDRAM_3 0x600000000
-#define PHYS_SDRAM_3_SIZE 0x40000000u
-#define PHYS_SDRAM_4 0x700000000
-#define PHYS_SDRAM_4_SIZE 0x40000000u
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#elif defined(CONFIG_R8A7796)
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
-#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE)
-#define PHYS_SDRAM_2 0x0600000000
-#define PHYS_SDRAM_2_SIZE 0x80000000u
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#endif
+#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
+#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_LOAD_ADDR 0x48080000
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff
-#define CONFIG_SPL_TEXT_BASE 0x10081004
+#define CONFIG_SPL_TEXT_BASE 0x10081000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3128_COMMON_H
+#define __CONFIG_RK3128_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
+#define CONFIG_SYS_LOAD_ADDR 0x60800800
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_NR_DRAM_BANKS 2
+#define SDRAM_MAX_SIZE 0x80000000
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+#ifndef CONFIG_SPL_BUILD
+
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60500000\0" \
+ "pxefile_addr_r=0x60600000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "partitions=" PARTS_DEFAULT \
+ BOOTENV
+
+#endif
+
+#endif
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_TEXT_BASE 0x10080804
-/* tpl size 1kb - 4byte RK31 header */
-#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4)
-#elif defined(CONFIG_SPL_BUILD)
-/* spl size 32kb sram - 2kb bootrom - 1kb spl */
-#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00)
-#define CONFIG_SPL_TEXT_BASE 0x10080C00
+#define CONFIG_SPL_TEXT_BASE 0x10080800
+/* spl size 32kb sram - 2kb bootrom */
+#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
#define CONFIG_SPL_FRAMEWORK 1
-#define CONFIG_SPL_CLK 1
-#define CONFIG_SPL_PINCTRL 1
-#define CONFIG_SPL_REGMAP 1
-#define CONFIG_SPL_SYSCON 1
-#define CONFIG_SPL_RAM 1
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
#define CONFIG_ROCKCHIP_SERIAL 1
-#endif
#define CONFIG_SPL_STACK 0x10087fff
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
# define CONFIG_SPL_TEXT_BASE 0x0
#else
-# define CONFIG_SPL_TEXT_BASE 0xff704004
+# define CONFIG_SPL_TEXT_BASE 0xff704000
#endif
/* MMC/SD IP block */
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
- "name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \
- "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \
- "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
- "name=atf,size=4M,uuid=${uuid_gpt_atf};" \
+ "name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \
+ "name=trust,size=4M,uuid=${uuid_gpt_atf};" \
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
"name=rootfs,size=-,uuid="ROOT_UUID
#endif
-/*
- * Rockchip SoCs use fixed ENV 32KB@(4MB-32KB)
- */
-#define CONFIG_ENV_OFFSET (SZ_4M - SZ_32K)
-#define CONFIG_ENV_SIZE SZ_32K
-
#define CONFIG_DISPLAY_BOARDINFO_LATE
#endif /* _ROCKCHIP_COMMON_H_ */
#endif
/* Console UART */
-#ifdef CONFIG_BCM2837
+#if defined (CONFIG_BCM2837) || defined(CONFIG_TARGET_RPI_0_W)
#define CONFIG_BCM283X_MU_SERIAL
#else
#define CONFIG_PL01X_SERIAL
#include <asm/arch/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#undef DEBUG
-#define CONFIG_RCAR_BOARD_STRING "Salvator-X"
-
#include "rcar-gen3-common.h"
-/* SCIF */
-#define CONFIG_CONS_SCIF2
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
-
-/* [A] Hyper Flash */
-/* use to RPC(SPI Multi I/O Bus Controller) */
-
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define RCAR_XTAL_CLK 33333333u
-#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
-/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
-/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
-#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
-#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
-#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
+#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
-#define GICD_BASE 0xF1010000
-#define GICC_BASE 0xF1020000
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x60
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
-
-/* USB */
-#ifdef CONFIG_R8A7795
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#else
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 200000000
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
-/* Module stop status bits */
-/* MFIS, SCIF1 */
-#define CONFIG_SMSTP2_ENA 0x00002040
-/* SCIF2 */
-#define CONFIG_SMSTP3_ENA 0x00000400
-/* INTC-AP, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-
#endif /* __SALVATOR_X_H */
+++ /dev/null
-/*
- * Configuration settings for the SAMA5D2 PTC Engineering board.
- *
- * Copyright (C) 2016 Atmel
- * Wenyou Yang <wenyou.yang@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "at91-sama5_common.h"
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE 0xf801c000
-#define CONFIG_USART_ID 24
-
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-
-#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR 0x210000
-#else
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
-#endif
-
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
-#undef CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_PIO4
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-
-/* SerialFlash */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#endif
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x80000000
-/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#endif
-
-/* USB device */
-
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-
-#ifdef CONFIG_NAND_BOOT
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_OFFSET_REDUND
-#undef CONFIG_BOOTCOMMAND
-/* u-boot env in nand flash */
-#define CONFIG_ENV_OFFSET 0x200000
-#define CONFIG_ENV_OFFSET_REDUND 0x400000
-#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
- "nand read 0x22000000 0x600000 0x600000;" \
- "bootz 0x22000000 - 0x21000000"
-#endif
-
-/* SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x200000
-#define CONFIG_SPL_MAX_SIZE 0x10000
-#define CONFIG_SPL_BSS_START_ADDR 0x20000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
-#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-
-#elif CONFIG_NAND_BOOT
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_BASE
-#endif
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-
-#endif
--- /dev/null
+/*
+ * Configuration file for the SAMA5D2 PTC EK Board.
+ *
+ * Copyright (C) 2017 Microchip Technology Inc.
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ * Ludovic Desroches <ludovic.desroches@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+
+#define CONFIG_MISC_INIT_R
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* NAND Flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_DENALI_ECC_SIZE 512
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#endif
#ifdef CONFIG_ARM64
#define CONFIG_BUILD_TARGET "u-boot.itb"
+#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#endif
/* Serial & console */
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
#ifdef CONFIG_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SUNXI_AHCI
#define CONFIG_SYS_64BIT_LBA
#define SUNXI_MTDPARTS_DEFAULT
#endif
+#define PARTS_DEFAULT \
+ "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \
+ "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \
+ "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \
+ "name=system,size=-,uuid=${uuid_gpt_system};"
+
+#define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b"
+
+#ifdef CONFIG_ARM64
+#define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae"
+#else
+#define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3"
+#endif
+
#define CONSOLE_ENV_SETTINGS \
CONSOLE_STDIN_SETTINGS \
CONSOLE_STDOUT_SETTINGS
"console=ttyS0,115200\0" \
SUNXI_MTDIDS_DEFAULT \
SUNXI_MTDPARTS_DEFAULT \
+ "uuid_gpt_esp=" UUID_GPT_ESP "\0" \
+ "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
BOOTCMD_SUNXI_COMPAT \
BOOTENV
--- /dev/null
+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2017 Opal Kelly Inc.
+ *
+ * Configuration settings for the SYZYGY Hub development board
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_SYZYGY_HUB_H
+#define __CONFIG_SYZYGY_HUB_H
+
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fit_image=fit.itb\0" \
+ "bitstream_image=download.bit\0" \
+ "loadbit_addr=0x1000000\0" \
+ "load_addr=0x2000000\0" \
+ "fit_size=0x800000\0" \
+ "flash_off=0x100000\0" \
+ "nor_flash_off=0xE2100000\0" \
+ "fdt_high=0x20000000\0" \
+ "initrd_high=0x20000000\0" \
+ "loadbootenv_addr=0x2000000\0" \
+ "fdt_addr_r=0x1f00000\0" \
+ "pxefile_addr_r=0x2000000\0" \
+ "kernel_addr_r=0x2000000\0" \
+ "scriptaddr=0x3000000\0" \
+ "ramdisk_addr_r=0x3100000\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootenv_dev=mmc\0" \
+ "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+ "env import -t ${loadbootenv_addr} $filesize\0" \
+ "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
+ "setbootenv=if env run bootenv_existence_test; then " \
+ "if env run loadbootenv; then " \
+ "env run importbootenv; " \
+ "fi; " \
+ "fi; \0" \
+ "sd_loadbootenv=set bootenv_dev mmc && " \
+ "run setbootenv \0" \
+ "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \
+ "preboot=if test $modeboot = sdboot; then " \
+ "run sd_loadbootenv; " \
+ "echo Checking if uenvcmd is set ...; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi; " \
+ "fi; \0" \
+ "sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \
+ "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+ "echo Programming FPGA... && " \
+ "fpga loadb 0 ${loadbit_addr} ${filesize} && " \
+ "echo Copying FIT from SD to RAM... && " \
+ "load mmc 0 ${load_addr} ${fit_image} && " \
+ "bootm ${load_addr}\0" \
+ "jtagboot=echo TFTPing FIT to RAM... && " \
+ "tftpboot ${load_addr} ${fit_image} && " \
+ "bootm ${load_addr}\0" \
+ DFU_ALT_INFO \
+ BOOTENV
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_SYZYGY_HUB_H */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* USB */
/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA_MV
-#define CONFIG_LIBATA
#define CONFIG_LBA48
/* Additional FS support/configuration */
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Network support */
#undef DEBUG
-#define CONFIG_RCAR_BOARD_STRING "ULCB"
-
#include "rcar-gen3-common.h"
-/* M3 ULCB has 2 banks, each with 1 GiB of RAM */
-#if defined(CONFIG_R8A7796)
-#undef PHYS_SDRAM_1_SIZE
-#undef PHYS_SDRAM_2_SIZE
-#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
-#define PHYS_SDRAM_2_SIZE 0x40000000u
-#endif
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
-
-/* [A] Hyper Flash */
-/* use to RPC(SPI Multi I/O Bus Controller) */
-
/* Ethernet RAVB */
-#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define RCAR_XTAL_CLK 33333333u
-#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
-/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
-/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
-#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
-#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
-#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
+#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-/* Generic Interrupt Controller Definitions */
-#define CONFIG_GICV2
-#define GICD_BASE 0xF1010000
-#define GICC_BASE 0xF1020000
-
-/* CPLD SPI */
-#define CONFIG_CMD_SPI
-#define CONFIG_SOFT_SPI
-#define SPI_DELAY udelay(0)
-#define SPI_SDA(val) ulcb_softspi_sda(val)
-#define SPI_SCL(val) ulcb_softspi_scl(val)
-#define SPI_READ ulcb_softspi_read()
-#ifndef __ASSEMBLY__
-void ulcb_softspi_sda(int);
-void ulcb_softspi_scl(int);
-unsigned char ulcb_softspi_read(void);
-#endif
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x60
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
-
-/* USB */
-#ifdef CONFIG_R8A7795
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#else
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 200000000
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
-/* Module stop status bits */
-/* MFIS, SCIF1 */
-#define CONFIG_SMSTP2_ENA 0x00002040
-/* SCIF2 */
-#define CONFIG_SMSTP3_ENA 0x00000400
-/* INTC-AP, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-
#endif /* __ULCB_H */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* SD/MMC */
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
#define CONFIG_SYS_MEMTEST_START 0x10000000
--- /dev/null
+/*
+ * Configuation settings for the WB45N CPU Module.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC 1
+#define CONFIG_ATMEL_NAND_HW_PMECC 1
+#define CONFIG_PMECC_CAP 4
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_ETHADDR C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE 1
+
+/* System */
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET 0xa0000
+#define CONFIG_ENV_OFFSET_REDUND 0xc0000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */
+
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
+ "run _mtd; bootm"
+
+#define MTDIDS_DEFAULT "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
+ "128K(at91bs)," \
+ "512K(u-boot)," \
+ "128K(u-boot-env)," \
+ "128K(redund-env)," \
+ "2560K(kernel-a)," \
+ "2560K(kernel-b)," \
+ "38912K(rootfs-a)," \
+ "38912K(rootfs-b)," \
+ "46208K(user)," \
+ "512K(logs)"
+
+#else
+#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
+ "rw noinitrd mem=64M " \
+ "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "autoload=no\0" \
+ "autostart=no\0" \
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+ "\0"
+
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#endif /* __CONFIG_H__ */
--- /dev/null
+/*
+ * Configuation settings for the WB50N CPU Module.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_IMAGE_FORMAT_LEGACY
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_DBGU
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x310000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x21000000
+#define CONFIG_SYS_MEMTEST_END 0x22000000
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_ETHADDR C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "autostart=no\0"
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET 0xA0000
+#define CONFIG_ENV_OFFSET_REDUND 0xC0000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_BOOTCOMMAND \
+ "nand read 0x22000000 0x000e0000 0x500000; " \
+ "bootm"
+
+#define CONFIG_BOOTARGS \
+ "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
/* Serial setup */
#define CONFIG_ARM_DCC
#define CONFIG_CPU_ARMV8
-#define CONFIG_ZYNQ_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_PANIC_HANG
#define CONFIG_SYS_MAXARGS 64
/* Ethernet driver */
#endif
#ifdef CONFIG_SATA_CEVA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
#define CONFIG_SPL_FRAMEWORK
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
+# define CONFIG_SPL_SPI_LOAD
+# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
+# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
+# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
+
+# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000
+#endif
+
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000
# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH_SUPPORT
# define CONFIG_ENV_MAX_ENTRIES 10
+#endif
-# define CONFIG_SYS_SPL_MALLOC_START 0x20000000
-# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
#endif
-#endif
#define CONFIG_BOARD_EARLY_INIT_F
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CONFIG_ARM_DCC
-#define CONFIG_ZYNQ_SERIAL
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
/* Environment */
#ifndef CONFIG_ENV_IS_NOWHERE
-# ifdef CONFIG_MTD_NOR_FLASH
-/* Environment in NOR flash */
-# elif defined(CONFIG_ZYNQ_QSPI)
-/* Environment in Serial Flash */
-# endif
-
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# define CONFIG_ENV_OFFSET 0xE0000
#endif
GENERATED_GBL_DATA_SIZE)
/* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
/* FIT support */
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
-/* FDT support */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_FPGA
#endif
/* Address in RAM where the parameters must be copied by SPL. */
/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
#define CONFIG_SPL_MAX_SIZE 0x30000
-/* The highest 64k OCM address */
-#define OCM_HIGH_ADDR 0xffff0000
-
/* On the top of OCM space */
-#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
+#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000
/*
* SPL stack position - and stack goes down
--- /dev/null
+/*
+ * (C) Copyright 2013 - 2017 Xilinx.
+ *
+ * Configuration settings for the Xilinx Zynq CSE board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_CSE_H
+#define __CONFIG_ZYNQ_CSE_H
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#include <configs/zynq-common.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
+#undef CONFIG_SYS_LONGHELP
+
+#undef CONFIG_SYS_CBSIZE
+#undef CONFIG_BOOTM_VXWORKS
+#undef CONFIG_BOOTM_LINUX
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_ENV_SIZE 400
+#undef CONFIG_SYS_INIT_RAM_ADDR
+#undef CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#undef CONFIG_SPL_BSS_START_ADDR
+#undef CONFIG_SPL_BSS_MAX_SIZE
+#define CONFIG_SPL_BSS_START_ADDR 0x20000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN 0x1000
+
+#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000
+
+#endif /* __CONFIG_ZYNQ_CSE_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2 0
+#define R8A77970_CLK_ZR 1
+#define R8A77970_CLK_ZTR 2
+#define R8A77970_CLK_ZTRD2 3
+#define R8A77970_CLK_ZT 4
+#define R8A77970_CLK_ZX 5
+#define R8A77970_CLK_S1D1 6
+#define R8A77970_CLK_S1D2 7
+#define R8A77970_CLK_S1D4 8
+#define R8A77970_CLK_S2D1 9
+#define R8A77970_CLK_S2D2 10
+#define R8A77970_CLK_S2D4 11
+#define R8A77970_CLK_LB 12
+#define R8A77970_CLK_CL 13
+#define R8A77970_CLK_ZB3 14
+#define R8A77970_CLK_ZB3D2 15
+#define R8A77970_CLK_DDR 16
+#define R8A77970_CLK_CR 17
+#define R8A77970_CLK_CRD2 18
+#define R8A77970_CLK_SD0H 19
+#define R8A77970_CLK_SD0 20
+#define R8A77970_CLK_RPC 21
+#define R8A77970_CLK_RPCD2 22
+#define R8A77970_CLK_MSO 23
+#define R8A77970_CLK_CANFD 24
+#define R8A77970_CLK_CSI0 25
+#define R8A77970_CLK_FRAY 26
+#define R8A77970_CLK_CP 27
+#define R8A77970_CLK_CPEX 28
+#define R8A77970_CLK_R 29
+#define R8A77970_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2 0
+#define R8A77995_CLK_ZG 1
+#define R8A77995_CLK_ZTR 2
+#define R8A77995_CLK_ZT 3
+#define R8A77995_CLK_ZX 4
+#define R8A77995_CLK_S0D1 5
+#define R8A77995_CLK_S1D1 6
+#define R8A77995_CLK_S1D2 7
+#define R8A77995_CLK_S1D4 8
+#define R8A77995_CLK_S2D1 9
+#define R8A77995_CLK_S2D2 10
+#define R8A77995_CLK_S2D4 11
+#define R8A77995_CLK_S3D1 12
+#define R8A77995_CLK_S3D2 13
+#define R8A77995_CLK_S3D4 14
+#define R8A77995_CLK_S1D4C 15
+#define R8A77995_CLK_S3D1C 16
+#define R8A77995_CLK_S3D2C 17
+#define R8A77995_CLK_S3D4C 18
+#define R8A77995_CLK_LB 19
+#define R8A77995_CLK_CL 20
+#define R8A77995_CLK_ZB3 21
+#define R8A77995_CLK_ZB3D2 22
+#define R8A77995_CLK_CR 23
+#define R8A77995_CLK_CRD2 24
+#define R8A77995_CLK_SD0H 25
+#define R8A77995_CLK_SD0 26
+#define R8A77995_CLK_SSP2 27
+#define R8A77995_CLK_SSP1 28
+#define R8A77995_CLK_RPC 29
+#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_ZA2 31
+#define R8A77995_CLK_ZA8 32
+#define R8A77995_CLK_Z2D 33
+#define R8A77995_CLK_CANFD 34
+#define R8A77995_CLK_MSO 35
+#define R8A77995_CLK_R 36
+#define R8A77995_CLK_OSC 37
+#define R8A77995_CLK_LV0 38
+#define R8A77995_CLK_LV1 39
+#define R8A77995_CLK_CP 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_GPLL 3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU 64
+#define SCLK_SPI 65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S 82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_SARADC 91
+#define SCLK_OTGPHY0 93
+#define SCLK_LCDC 100
+#define SCLK_HDMI 109
+#define SCLK_HEVC 111
+#define SCLK_I2S_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC 151
+#define SCLK_MACREF 152
+#define SCLK_SFC 160
+
+#define DCLK_LCDC 190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_VIO0 197
+#define ACLK_VIO1 203
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_SARADC 318
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_GRF 329
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_SPI 338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_HDMI 360
+#define PCLK_CPU 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL 364
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_OTG0 449
+#define HCLK_OTG1 450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_I2S 462
+#define HCLK_LCDC 465
+#define HCLK_ROM 467
+#define HCLK_VIO_BUS 472
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C 12
+#define SRST_TOPDBG 13
+#define SRST_STRC_SYS_A 14
+#define SRST_PD_CORE_NIU 15
+
+#define SRST_TIMER2 16
+#define SRST_CPUSYS_H 17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER3 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_PERI_NIU 23
+#define SRST_I2S 24
+#define SRST_DDR_PLL 25
+#define SRST_GPU_DLL 26
+#define SRST_TIMER0 27
+#define SRST_TIMER1 28
+#define SRST_CORE_DLL 29
+#define SRST_EFUSE_P 30
+#define SRST_ACODEC_P 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_SFC 47
+
+#define SRST_PWM0 48
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_GRF 55
+#define SRST_PERIPHSYS_A 57
+#define SRST_PERIPHSYS_H 58
+#define SRST_PERIPHSYS_P 59
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA2 64
+#define SRST_MAC 66
+#define SRST_NANDC 68
+#define SRST_USBOTG0 69
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_OTGC1 74
+#define SRST_DDRMSCH 79
+
+#define SRST_MMC0 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI0 84
+#define SRST_WDT 86
+#define SRST_SARADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_P 89
+#define SRST_DDRCTRL 90
+#define SRST_DDRCTRL_P 91
+
+#define SRST_HDMI_P 96
+#define SRST_VIO_BUS_H 99
+#define SRST_UTMI0 103
+#define SRST_UTMI1 104
+#define SRST_USBPOR 105
+
+#define SRST_VCODEC_A 112
+#define SRST_VCODEC_H 113
+#define SRST_VIO1_A 114
+#define SRST_HEVC 115
+#define SRST_VCODEC_NIU_A 116
+#define SRST_LCDC1_A 117
+#define SRST_LCDC1_H 118
+#define SRST_LCDC1_D 119
+#define SRST_GPU 120
+#define SRST_GPU_NIU_A 122
+
+#define SRST_DBG_P 131
+
+#endif
--- /dev/null
+/*
+ * Synopsys HSDK SDP CGU clock driver dts bindings
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
+#define __DT_BINDINGS_CLK_HSDK_CGU_H_
+
+#define CLK_ARC_PLL 0
+#define CLK_ARC 1
+#define CLK_DDR_PLL 2
+#define CLK_SYS_PLL 3
+#define CLK_SYS_APB 4
+#define CLK_SYS_AXI 5
+#define CLK_SYS_ETH 6
+#define CLK_SYS_USB 7
+#define CLK_SYS_SDIO 8
+#define CLK_SYS_HDMI 9
+#define CLK_SYS_GFX_CORE 10
+#define CLK_SYS_GFX_DMA 11
+#define CLK_SYS_GFX_CFG 12
+#define CLK_SYS_DMAC_CORE 13
+#define CLK_SYS_DMAC_CFG 14
+#define CLK_SYS_SDIO_REF 15
+#define CLK_SYS_SPI_REF 16
+#define CLK_SYS_I2C_REF 17
+#define CLK_SYS_UART_REF 18
+#define CLK_SYS_EBI_REF 19
+#define CLK_TUN_PLL 20
+#define CLK_TUN 21
+#define CLK_HDMI_PLL 22
+#define CLK_HDMI 23
+
+#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
+#define _DT_BINDINGS_GPIO_UNIPHIER_H
+
+#define UNIPHIER_GPIO_LINES_PER_BANK 8
+
+#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
+
+#define UNIPHIER_GPIO_PORT(bank, line) \
+ ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
+
+#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
+
+#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */
#define STM32F7_RCC_APB2_TIM8 1
#define STM32F7_RCC_APB2_USART1 4
#define STM32F7_RCC_APB2_USART6 5
+#define STM32F7_RCC_APB2_SDMMC2 7
#define STM32F7_RCC_APB2_ADC1 8
#define STM32F7_RCC_APB2_ADC2 9
#define STM32F7_RCC_APB2_ADC3 10
--- /dev/null
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2017 Xilinx, Inc.
+ * Author: Chirag Parekh <chirag.parekh@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for IO standards */
+#define IO_STANDARD_LVCMOS33 0
+#define IO_STANDARD_LVCMOS18 1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST 0
+#define SLEW_RATE_SLOW 1
+
+/* Bit values for Pin inputs */
+#define PIN_INPUT_TYPE_CMOS 0
+#define PIN_INPUT_TYPE_SCHMITT 1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77970_PD_CA53_CPU0 5
+#define R8A77970_PD_CA53_CPU1 6
+#define R8A77970_PD_CR7 13
+#define R8A77970_PD_CA53_SCU 21
+#define R8A77970_PD_A2IR0 23
+#define R8A77970_PD_A3IR 24
+#define R8A77970_PD_A2IR1 27
+#define R8A77970_PD_A2IR2 28
+#define R8A77970_PD_A2IR3 29
+#define R8A77970_PD_A2SC0 30
+#define R8A77970_PD_A2SC1 31
+
+/* Always-on power area */
+#define R8A77970_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77995_PD_CA53_CPU0 5
+#define R8A77995_PD_CA53_SCU 21
+
+/* Always-on power area */
+#define R8A77995_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
};
enum efi_locate_search_type {
- all_handles,
- by_register_notify,
- by_protocol
+ ALL_HANDLES,
+ BY_REGISTER_NOTIFY,
+ BY_PROTOCOL
};
struct efi_open_protocol_info_entry {
EFI_TIMER_RELATIVE = 2
};
-#define UINTN size_t
-typedef long INTN;
+#define efi_uintn_t size_t
typedef uint16_t *efi_string_t;
#define EVT_TIMER 0x80000000
/* EFI Boot Services table */
struct efi_boot_services {
struct efi_table_hdr hdr;
- efi_status_t (EFIAPI *raise_tpl)(UINTN new_tpl);
- void (EFIAPI *restore_tpl)(UINTN old_tpl);
+ efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl);
+ void (EFIAPI *restore_tpl)(efi_uintn_t old_tpl);
- efi_status_t (EFIAPI *allocate_pages)(int, int, unsigned long,
+ efi_status_t (EFIAPI *allocate_pages)(int, int, efi_uintn_t,
efi_physical_addr_t *);
- efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, unsigned long);
- efi_status_t (EFIAPI *get_memory_map)(unsigned long *memory_map_size,
- struct efi_mem_desc *desc, unsigned long *key,
- unsigned long *desc_size, u32 *desc_version);
- efi_status_t (EFIAPI *allocate_pool)(int, unsigned long, void **);
+ efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, efi_uintn_t);
+ efi_status_t (EFIAPI *get_memory_map)(efi_uintn_t *memory_map_size,
+ struct efi_mem_desc *desc,
+ efi_uintn_t *key,
+ efi_uintn_t *desc_size,
+ u32 *desc_version);
+ efi_status_t (EFIAPI *allocate_pool)(int, efi_uintn_t, void **);
efi_status_t (EFIAPI *free_pool)(void *);
efi_status_t (EFIAPI *create_event)(uint32_t type,
- UINTN notify_tpl,
+ efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
efi_status_t (EFIAPI *set_timer)(struct efi_event *event,
enum efi_timer_delay type,
uint64_t trigger_time);
- efi_status_t (EFIAPI *wait_for_event)(unsigned long number_of_events,
- struct efi_event **event, size_t *index);
+ efi_status_t (EFIAPI *wait_for_event)(efi_uintn_t number_of_events,
+ struct efi_event **event,
+ efi_uintn_t *index);
efi_status_t (EFIAPI *signal_event)(struct efi_event *event);
efi_status_t (EFIAPI *close_event)(struct efi_event *event);
efi_status_t (EFIAPI *check_event)(struct efi_event *event);
efi_status_t (EFIAPI *locate_handle)(
enum efi_locate_search_type search_type,
const efi_guid_t *protocol, void *search_key,
- unsigned long *buffer_size, efi_handle_t *buffer);
+ efi_uintn_t *buffer_size, efi_handle_t *buffer);
efi_status_t (EFIAPI *locate_device_path)(const efi_guid_t *protocol,
struct efi_device_path **device_path,
efi_handle_t *device);
efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle,
const efi_guid_t *protocol,
struct efi_open_protocol_info_entry **entry_buffer,
- unsigned long *entry_count);
+ efi_uintn_t *entry_count);
efi_status_t (EFIAPI *protocols_per_handle)(efi_handle_t handle,
efi_guid_t ***protocol_buffer,
- unsigned long *protocols_buffer_count);
+ efi_uintn_t *protocols_buffer_count);
efi_status_t (EFIAPI *locate_handle_buffer) (
enum efi_locate_search_type search_type,
const efi_guid_t *protocol, void *search_key,
- unsigned long *no_handles, efi_handle_t **buffer);
+ efi_uintn_t *no_handles, efi_handle_t **buffer);
efi_status_t (EFIAPI *locate_protocol)(const efi_guid_t *protocol,
void *registration, void **protocol_interface);
efi_status_t (EFIAPI *install_multiple_protocol_interfaces)(
struct efi_simple_text_output_protocol *std_err;
struct efi_runtime_services *runtime;
struct efi_boot_services *boottime;
- unsigned long nr_tables;
+ efi_uintn_t nr_tables;
struct efi_configuration_table *tables;
};
struct efi_gop
{
efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number,
- unsigned long *size_of_info,
+ efi_uintn_t *size_of_info,
struct efi_gop_mode_info **info);
efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number);
efi_status_t (EFIAPI *blt)(struct efi_gop *this, void *buffer,
- unsigned long operation, unsigned long sx,
- unsigned long sy, unsigned long dx,
- unsigned long dy, unsigned long width,
- unsigned long height, unsigned long delta);
+ u32 operation, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta);
struct efi_gop_mode *mode;
};
* SPDX-License-Identifier: GPL-2.0+
*/
+#ifndef _EFI_LOADER_H
+#define _EFI_LOADER_H 1
+
#include <common.h>
#include <part_efi.h>
#include <efi_api.h>
extern struct efi_runtime_services efi_runtime_services;
extern struct efi_system_table systab;
-extern const struct efi_simple_text_output_protocol efi_con_out;
+extern struct efi_simple_text_output_protocol efi_con_out;
extern struct efi_simple_input_interface efi_con_in;
-extern const struct efi_console_control_protocol efi_console_control;
+extern struct efi_console_control_protocol efi_console_control;
extern const struct efi_device_path_to_text_protocol efi_device_path_to_text;
uint16_t *efi_dp_str(struct efi_device_path *dp);
* interface (usually a struct with callback functions), this struct maps the
* protocol GUID to the respective protocol interface */
struct efi_handler {
+ /* Link to the list of protocols of a handle */
+ struct list_head link;
const efi_guid_t *guid;
void *protocol_interface;
};
struct efi_object {
/* Every UEFI object is part of a global object list */
struct list_head link;
- /* We support up to 16 "protocols" an object can be accessed through */
- struct efi_handler protocols[16];
+ /* The list of protocols */
+ struct list_head protocols;
/* The object spawner can either use this for data or as identifier */
void *handle;
};
-#define EFI_PROTOCOL_OBJECT(_guid, _protocol) (struct efi_object){ \
- .protocols = {{ \
- .guid = &(_guid), \
- .protocol_interface = (void *)(_protocol), \
- }}, \
- .handle = (void *)(_protocol), \
-}
-
/**
* struct efi_event
*
*/
struct efi_event {
uint32_t type;
- UINTN notify_tpl;
+ efi_uintn_t notify_tpl;
void (EFIAPI *notify_function)(struct efi_event *event, void *context);
void *notify_context;
u64 trigger_next;
int efi_gop_register(void);
/* Called by bootefi to make the network interface available */
int efi_net_register(void);
+/* Called by bootefi to make the watchdog available */
+int efi_watchdog_register(void);
/* Called by bootefi to make SMBIOS tables available */
void efi_smbios_register(void);
/* Called by networking code to memorize the dhcp ack package */
void efi_net_set_dhcp_ack(void *pkt, int len);
+/* Called by efi_set_watchdog_timer to reset the timer */
+efi_status_t efi_set_watchdog(unsigned long timeout);
/* Called from places to check whether a timer expired */
void efi_timer_check(void);
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
/* Call this to set the current device name */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
+/* Add a new object to the object list. */
+void efi_add_handle(struct efi_object *obj);
+/* Create handle */
+efi_status_t efi_create_handle(void **handle);
+/* Delete handle */
+void efi_delete_handle(struct efi_object *obj);
+/* Call this to validate a handle and find the EFI object for it */
+struct efi_object *efi_search_obj(const void *handle);
+/* Find a protocol on a handle */
+efi_status_t efi_search_protocol(const void *handle,
+ const efi_guid_t *protocol_guid,
+ struct efi_handler **handler);
+/* Install new protocol on a handle */
+efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+ void *protocol_interface);
+/* Delete protocol from a handle */
+efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+ void *protocol_interface);
+/* Delete all protocols from a handle */
+efi_status_t efi_remove_all_protocols(const void *handle);
/* Call this to create an event */
-efi_status_t efi_create_event(uint32_t type, UINTN notify_tpl,
+efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
/* Generic EFI memory allocator, call this to get memory */
void *efi_alloc(uint64_t len, int memory_type);
/* More specific EFI memory allocator, called by EFI payloads */
-efi_status_t efi_allocate_pages(int type, int memory_type, unsigned long pages,
+efi_status_t efi_allocate_pages(int type, int memory_type, efi_uintn_t pages,
uint64_t *memory);
/* EFI memory free function. */
-efi_status_t efi_free_pages(uint64_t memory, unsigned long pages);
+efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages);
/* EFI memory allocator for small allocations */
-efi_status_t efi_allocate_pool(int pool_type, unsigned long size,
+efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size,
void **buffer);
/* EFI pool memory free function. */
efi_status_t efi_free_pool(void *buffer);
/* Returns the EFI memory map */
-efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
+efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
struct efi_mem_desc *memory_map,
- unsigned long *map_key,
- unsigned long *descriptor_size,
+ efi_uintn_t *map_key,
+ efi_uintn_t *descriptor_size,
uint32_t *descriptor_version);
/* Adds a range into the EFI memory map */
uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
int efi_memory_init(void);
/* Adds new or overrides configuration table entry to the system table */
efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table);
-void efi_setup_loaded_image(struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path);
+/* Sets up a loaded image */
+efi_status_t efi_setup_loaded_image(
+ struct efi_loaded_image *info, struct efi_object *obj,
+ struct efi_device_path *device_path,
+ struct efi_device_path *file_path);
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
void **buffer);
struct efi_device_path *efi_dp_next(const struct efi_device_path *dp);
-int efi_dp_match(struct efi_device_path *a, struct efi_device_path *b);
+int efi_dp_match(const struct efi_device_path *a,
+ const struct efi_device_path *b);
struct efi_object *efi_dp_find_obj(struct efi_device_path *dp,
struct efi_device_path **rem);
unsigned efi_dp_size(const struct efi_device_path *dp);
const char *path) { }
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
-#endif
+#endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */
+
+#endif /* _EFI_LOADER_H */
#include <common.h>
#include <efi.h>
#include <efi_api.h>
+#include <efi_loader.h>
#include <linker_lists.h>
#define EFI_ST_SUCCESS 0
(efi_st_printf("%s(%u):\nERROR: ", __FILE__, __LINE__), \
efi_st_printf(__VA_ARGS__)) \
+/*
+ * Prints a TODO message.
+ *
+ * @... format string followed by fields to print
+ */
+#define efi_st_todo(...) \
+ (efi_st_printf("%s(%u):\nTODO: ", __FILE__, __LINE__), \
+ efi_st_printf(__VA_ARGS__)) \
+
/*
* A test may be setup and executed at boottime,
* it may be setup at boottime and executed at runtime,
*/
int efi_st_memcmp(const void *buf1, const void *buf2, size_t length);
+/*
+ * Compare an u16 string to a char string.
+ *
+ * @buf1: u16 string
+ * @buf2: char string
+ * @return: 0 if both buffers contain the same bytes
+ */
+int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2);
+
/*
* Reads an Unicode character from the input device.
*
* @setup: set up the unit test
* @teardown: tear down the unit test
* @execute: execute the unit test
+ * @on_request: test is only executed on request
*/
struct efi_unit_test {
const char *name;
const struct efi_system_table *systable);
int (*execute)(void);
int (*teardown)(void);
+ bool on_request;
};
/* Declare a new EFI unit test */
static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
#endif
+/**
+ * Record information about a processed loadable in /fit-images (creating
+ * /fit-images if necessary).
+ *
+ * @param blob FDT blob to update
+ * @param index index of this loadable
+ * @param name name of the loadable
+ * @param load_addr address the loadable was loaded to
+ * @param size number of bytes loaded
+ * @param entry_point entry point (if specified, otherwise pass -1)
+ * @param type type (if specified, otherwise pass NULL)
+ * @param os os-type (if specified, otherwise pass NULL)
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+int fdt_record_loadable(void *blob, u32 index, const char *name,
+ uintptr_t load_addr, u32 size, uintptr_t entry_point,
+ const char *type, const char *os);
+
#ifdef CONFIG_PCI
#include <pci.h>
int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
+ COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */
+ COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */
COMPAT_COUNT,
};
int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
+int fpga_is_partial_data(int devnum, size_t img_len);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
- * Author: German Rivera <German.Rivera@freescale.com>
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define __FSL_DPBP_H
/* DPBP Version */
-#define DPBP_VER_MAJOR 2
-#define DPBP_VER_MINOR 2
+#define DPBP_VER_MAJOR 3
+#define DPBP_VER_MINOR 3
/* Command IDs */
-#define DPBP_CMDID_CLOSE 0x800
-#define DPBP_CMDID_OPEN 0x804
-#define DPBP_CMDID_CREATE 0x904
-#define DPBP_CMDID_DESTROY 0x900
-
-#define DPBP_CMDID_ENABLE 0x002
-#define DPBP_CMDID_DISABLE 0x003
-#define DPBP_CMDID_GET_ATTR 0x004
-#define DPBP_CMDID_RESET 0x005
+#define DPBP_CMDID_CLOSE 0x8001
+#define DPBP_CMDID_OPEN 0x8041
+#define DPBP_CMDID_CREATE 0x9041
+#define DPBP_CMDID_DESTROY 0x9841
+#define DPBP_CMDID_GET_API_VERSION 0xa041
+
+#define DPBP_CMDID_ENABLE 0x0021
+#define DPBP_CMDID_DISABLE 0x0031
+#define DPBP_CMDID_GET_ATTR 0x0041
+#define DPBP_CMDID_RESET 0x0051
+#define DPBP_CMDID_IS_ENABLED 0x0061
/* cmd, param, offset, width, type, arg_name */
#define DPBP_CMD_OPEN(cmd, dpbp_id) \
do { \
MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \
MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
- MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
- MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
} while (0)
/* Data Path Buffer Pool API
* Return: '0' on Success; Error code otherwise.
*/
int dpbp_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
const struct dpbp_cfg *cfg,
- uint16_t *token);
+ uint32_t *obj_id);
/**
* dpbp_destroy() - Destroy the DPBP object and release all its resources.
* Return: '0' on Success; error code otherwise.
*/
int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
uint32_t cmd_flags,
- uint16_t token);
+ uint32_t obj_id);
/**
* dpbp_enable() - Enable the DPBP.
* acquire/release operations on buffers
*/
struct dpbp_attr {
- int id;
- /**
- * struct version - Structure representing DPBP version
- * @major: DPBP major version
- * @minor: DPBP minor version
- */
- struct {
- uint16_t major;
- uint16_t minor;
- } version;
+ uint32_t id;
uint16_t bpid;
};
uint16_t token,
struct dpbp_attr *attr);
+/**
+ * dpbp_get_api_version - Retrieve DPBP Major and Minor version info.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: DPBP major version
+ * @minor_ver: DPBP minor version
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpbp_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver);
+
/** @} */
#endif /* __FSL_DPBP_H */
/*
- * Copyright (C) 2013-2015 Freescale Semiconductor
+ * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define _FSL_DPIO_H
/* DPIO Version */
-#define DPIO_VER_MAJOR 3
+#define DPIO_VER_MAJOR 4
#define DPIO_VER_MINOR 2
/* Command IDs */
-#define DPIO_CMDID_CLOSE 0x800
-#define DPIO_CMDID_OPEN 0x803
-#define DPIO_CMDID_CREATE 0x903
-#define DPIO_CMDID_DESTROY 0x900
+#define DPIO_CMDID_CLOSE 0x8001
+#define DPIO_CMDID_OPEN 0x8031
+#define DPIO_CMDID_CREATE 0x9031
+#define DPIO_CMDID_DESTROY 0x9831
+#define DPIO_CMDID_GET_API_VERSION 0xa031
-#define DPIO_CMDID_ENABLE 0x002
-#define DPIO_CMDID_DISABLE 0x003
-#define DPIO_CMDID_GET_ATTR 0x004
-#define DPIO_CMDID_RESET 0x005
+#define DPIO_CMDID_ENABLE 0x0021
+#define DPIO_CMDID_DISABLE 0x0031
+#define DPIO_CMDID_GET_ATTR 0x0041
+#define DPIO_CMDID_RESET 0x0051
/* cmd, param, offset, width, type, arg_name */
#define DPIO_CMD_OPEN(cmd, dpio_id) \
MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\
MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\
MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\
- MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\
- MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\
MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\
} while (0)
*/
int dpio_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
- int dpio_id,
+ uint32_t dpio_id,
uint16_t *token);
/**
/**
* dpio_create() - Create the DPIO object.
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @cfg: Configuration structure
- * @token: Returned token; use in subsequent API calls
+ * @obj_id: Returned obj_id; use in subsequent API calls
*
* Create the DPIO object, allocate required resources and
* perform required initialization.
* Return: '0' on Success; Error code otherwise.
*/
int dpio_create(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
const struct dpio_cfg *cfg,
- uint16_t *token);
+ uint32_t *obj_id);
/**
* dpio_destroy() - Destroy the DPIO object and release all its resources.
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPIO object
+ * @obj_id: Object ID of DPIO
*
* Return: '0' on Success; Error code otherwise
*/
int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
- uint16_t token);
+ uint32_t obj_id);
/**
* dpio_enable() - Enable the DPIO, allow I/O portal operations.
* @qbman_version: QBMAN version
*/
struct dpio_attr {
- int id;
- /**
- * struct version - DPIO version
- * @major: DPIO major version
- * @minor: DPIO minor version
- */
- struct {
- uint16_t major;
- uint16_t minor;
- } version;
+ uint32_t id;
uint64_t qbman_portal_ce_offset;
uint64_t qbman_portal_ci_offset;
uint16_t qbman_portal_id;
uint16_t token,
struct dpio_attr *attr);
+/**
+ * dpio_get_api_version - Retrieve DPIO Major and Minor version info.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: DPIO major version
+ * @minor_ver: DPIO minor version
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpio_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver);
+
#endif /* _FSL_DPIO_H */
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
#define __FSL_DPMAC_H
/* DPMAC Version */
-#define DPMAC_VER_MAJOR 3
+#define DPMAC_VER_MAJOR 4
#define DPMAC_VER_MINOR 2
/* Command IDs */
-#define DPMAC_CMDID_CLOSE 0x800
-#define DPMAC_CMDID_OPEN 0x80c
-#define DPMAC_CMDID_CREATE 0x90c
-#define DPMAC_CMDID_DESTROY 0x900
+#define DPMAC_CMDID_CLOSE 0x8001
+#define DPMAC_CMDID_OPEN 0x80c1
+#define DPMAC_CMDID_CREATE 0x90c1
+#define DPMAC_CMDID_DESTROY 0x98c1
+#define DPMAC_CMDID_GET_API_VERSION 0xa0c1
-#define DPMAC_CMDID_GET_ATTR 0x004
-#define DPMAC_CMDID_RESET 0x005
+#define DPMAC_CMDID_GET_ATTR 0x0041
+#define DPMAC_CMDID_RESET 0x0051
-#define DPMAC_CMDID_MDIO_READ 0x0c0
-#define DPMAC_CMDID_MDIO_WRITE 0x0c1
-#define DPMAC_CMDID_GET_LINK_CFG 0x0c2
-#define DPMAC_CMDID_SET_LINK_STATE 0x0c3
-#define DPMAC_CMDID_GET_COUNTER 0x0c4
+#define DPMAC_CMDID_MDIO_READ 0x0c01
+#define DPMAC_CMDID_MDIO_WRITE 0x0c11
+#define DPMAC_CMDID_GET_LINK_CFG 0x0c21
+#define DPMAC_CMDID_SET_LINK_STATE 0x0c31
+#define DPMAC_CMDID_GET_COUNTER 0x0c41
/* cmd, param, offset, width, type, arg_name */
#define DPMAC_CMD_CREATE(cmd, cfg) \
- MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id)
+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id)
/* cmd, param, offset, width, type, arg_name */
#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
do { \
MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\
MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
- MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
- MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\
MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\
MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
/* cmd, param, offset, width, type, arg_name */
#define DPMAC_CMD_GET_COUNTER(cmd, type) \
- MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type)
+ MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type)
/* cmd, param, offset, width, type, arg_name */
#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
/**
* dpmac_create() - Create the DPMAC object.
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @cfg: Configuration structure
- * @token: Returned token; use in subsequent API calls
+ * @obj_id: Returned obj_id; use in subsequent API calls
*
* Create the DPMAC object, allocate required resources and
* perform required initialization.
* Return: '0' on Success; Error code otherwise.
*/
int dpmac_create(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
const struct dpmac_cfg *cfg,
- uint16_t *token);
+ uint32_t *obj_id);
/**
* dpmac_destroy() - Destroy the DPMAC object and release all its resources.
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPMAC object
+ * @obj_id: DPMAC object id
*
* Return: '0' on Success; error code otherwise.
*/
int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
- uint16_t token);
+ uint32_t obj_id);
/* DPMAC IRQ Index and Events */
enum dpmac_link_type link_type;
enum dpmac_eth_if eth_if;
uint32_t max_rate;
- /**
- * struct version - Structure representing DPMAC version
- * @major: DPMAC major version
- * @minor: DPMAC minor version
- */
- struct {
- uint16_t major;
- uint16_t minor;
- } version;
};
/**
uint16_t token,
enum dpmac_counter type,
uint64_t *counter);
+/**
+ * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: DPMAC major version
+ * @minor_ver: DPMAC minor version
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver);
#endif /* __FSL_DPMAC_H */
/*
- * Copyright (C) 2013-2015 Freescale Semiconductor
+ * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define _FSL_DPNI_H
/* DPNI Version */
-#define DPNI_VER_MAJOR 6
-#define DPNI_VER_MINOR 0
+#define DPNI_VER_MAJOR 7
+#define DPNI_VER_MINOR 3
/* Command IDs */
-#define DPNI_CMDID_OPEN 0x801
-#define DPNI_CMDID_CLOSE 0x800
-#define DPNI_CMDID_CREATE 0x901
-#define DPNI_CMDID_DESTROY 0x900
-
-#define DPNI_CMDID_ENABLE 0x002
-#define DPNI_CMDID_DISABLE 0x003
-#define DPNI_CMDID_GET_ATTR 0x004
-#define DPNI_CMDID_RESET 0x005
-
-#define DPNI_CMDID_SET_POOLS 0x200
-#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201
-#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202
-#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203
-#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204
-#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205
-#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206
-#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B
-
-#define DPNI_CMDID_GET_QDID 0x210
-#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212
-#define DPNI_CMDID_GET_COUNTER 0x213
-#define DPNI_CMDID_SET_COUNTER 0x214
-#define DPNI_CMDID_GET_LINK_STATE 0x215
-#define DPNI_CMDID_SET_LINK_CFG 0x21A
-
-#define DPNI_CMDID_SET_PRIM_MAC 0x224
-#define DPNI_CMDID_GET_PRIM_MAC 0x225
-#define DPNI_CMDID_ADD_MAC_ADDR 0x226
-#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227
-
-#define DPNI_CMDID_SET_TX_FLOW 0x236
-#define DPNI_CMDID_GET_TX_FLOW 0x237
-#define DPNI_CMDID_SET_RX_FLOW 0x238
-#define DPNI_CMDID_GET_RX_FLOW 0x239
-#define DPNI_CMDID_SET_TX_CONF 0x257
-#define DPNI_CMDID_GET_TX_CONF 0x258
+#define DPNI_CMDID_OPEN 0x8011
+#define DPNI_CMDID_CLOSE 0x8001
+#define DPNI_CMDID_CREATE 0x9011
+#define DPNI_CMDID_DESTROY 0x9811
+#define DPNI_CMDID_GET_API_VERSION 0xa011
+
+#define DPNI_CMDID_ENABLE 0x0021
+#define DPNI_CMDID_DISABLE 0x0031
+#define DPNI_CMDID_GET_ATTR 0x0041
+#define DPNI_CMDID_RESET 0x0051
+
+#define DPNI_CMDID_SET_POOLS 0x2002
+#define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651
+#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641
+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1
+
+#define DPNI_CMDID_GET_QDID 0x2101
+#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121
+#define DPNI_CMDID_GET_LINK_STATE 0x2151
+#define DPNI_CMDID_SET_LINK_CFG 0x21A1
+
+#define DPNI_CMDID_SET_PRIM_MAC 0x2241
+#define DPNI_CMDID_GET_PRIM_MAC 0x2251
+#define DPNI_CMDID_ADD_MAC_ADDR 0x2261
+#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271
+
+#define DPNI_CMDID_GET_STATISTICS 0x25D1
+#define DPNI_CMDID_RESET_STATISTICS 0x25E1
+#define DPNI_CMDID_GET_QUEUE 0x25F1
+#define DPNI_CMDID_SET_QUEUE 0x2601
+#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_OPEN(cmd, dpni_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
-#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_PREP_CFG(param, cfg) \
do { \
- MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
- MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
- MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
- MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
- MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
- MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
- MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
- MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
- MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
- MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
- MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
- MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
- MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
- MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
- MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
- MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
- MC_PREP_OP(ext, 4, 0, 16, uint16_t, \
- cfg->ipr_cfg.max_open_frames_ipv4); \
- MC_PREP_OP(ext, 4, 16, 16, uint16_t, \
- cfg->ipr_cfg.max_open_frames_ipv6); \
- MC_PREP_OP(ext, 4, 32, 16, uint16_t, \
- cfg->ipr_cfg.max_reass_frm_size); \
- MC_PREP_OP(ext, 5, 0, 16, uint16_t, \
- cfg->ipr_cfg.min_frag_size_ipv4); \
- MC_PREP_OP(ext, 5, 16, 16, uint16_t, \
- cfg->ipr_cfg.min_frag_size_ipv6); \
+ MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \
+ MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \
+ MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \
+ MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \
+ MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \
+ MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \
+ MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \
} while (0)
-#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_EXT_CFG(param, cfg) \
do { \
- MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
- MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
- MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
- MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
- MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
- MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
- MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
- MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
- MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
- MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
- MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
- MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
- MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
- MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
- MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
- MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
- MC_EXT_OP(ext, 4, 0, 16, uint16_t, \
- cfg->ipr_cfg.max_open_frames_ipv4); \
- MC_EXT_OP(ext, 4, 16, 16, uint16_t, \
- cfg->ipr_cfg.max_open_frames_ipv6); \
- MC_EXT_OP(ext, 4, 32, 16, uint16_t, \
- cfg->ipr_cfg.max_reass_frm_size); \
- MC_EXT_OP(ext, 5, 0, 16, uint16_t, \
- cfg->ipr_cfg.min_frag_size_ipv4); \
- MC_EXT_OP(ext, 5, 16, 16, uint16_t, \
- cfg->ipr_cfg.min_frag_size_ipv6); \
+ MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \
+ MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \
+ MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \
+ MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \
+ MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \
+ MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \
+ MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_CREATE(cmd, cfg) \
do { \
- MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \
- MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \
- MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \
- MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \
- MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \
- MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \
- MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \
- MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \
- MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \
- MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \
- MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \
- MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \
- MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \
- MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
- MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
- MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
- MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
- MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
- MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \
+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \
+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \
+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \
+ MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
} while (0)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_GET_ATTR(cmd, attr) \
- MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova)
-
/* cmd, param, offset, width, type, arg_name */
#define DPNI_RSP_GET_ATTR(cmd, attr) \
do { \
- MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
- MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \
- MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \
- MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \
- MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options); \
- MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \
- MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\
- MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \
- MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \
- MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \
- MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \
- MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \
- MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \
- MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\
- MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\
+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \
+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \
+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \
+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \
+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \
+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \
+ MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \
+ MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \
+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
} while (0)
/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \
-do { \
- MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \
-do { \
- MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
- MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \
-do { \
- MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \
-do { \
- MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
- MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
-do { \
- MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
-} while (0)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
+#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \
do { \
- MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
- MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
- MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
- MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
- MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
- MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
- MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
- MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \
+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \
+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \
+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \
+ MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \
+ MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \
+ MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \
+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \
+ MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \
} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \
MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_GET_COUNTER(cmd, counter) \
- MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_COUNTER(cmd, value) \
- MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \
-do { \
- MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \
- MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \
-} while (0)
-
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \
do { \
MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
} while (0)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \
+#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \
do { \
- MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\
- MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\
- MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\
- MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \
} while (0)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \
- MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
-
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \
+#define DPNI_RSP_GET_QUEUE(cmd, queue) \
do { \
- MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\
- MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\
- MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\
+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \
+ MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \
+ MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \
+ MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \
+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \
+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \
+ MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \
+ MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \
} while (0)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \
+#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \
do { \
- MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
- MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
- MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\
- MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
- MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
- MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \
- MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \
- MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \
- MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
- cfg->flc_cfg.frame_data_size);\
- MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
- cfg->flc_cfg.flow_context_size);\
- MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\
- MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\
- MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \
+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \
+ MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \
+ MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \
+ MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \
+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \
+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \
} while (0)
-/* cmd, param, offset, width, type, arg_name */
-#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \
-do { \
- MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
-} while (0)
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_GET_STATISTICS(cmd, page) \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page)
/* cmd, param, offset, width, type, arg_name */
-#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \
+#define DPNI_RSP_GET_STATISTICS(cmd, stat) \
do { \
- MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \
- MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
- MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \
- MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
- MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \
- MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \
- MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \
- MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \
- MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
- attr->flc_cfg.frame_data_size);\
- MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
- attr->flc_cfg.flow_context_size);\
- MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\
- MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\
-} while (0)
-
-#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \
-do { \
- MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \
- MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \
- cfg->queue_cfg.dest_cfg.dest_type); \
- MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \
- MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
- MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \
- MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \
- MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \
- MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \
- cfg->queue_cfg.tail_drop_threshold); \
- MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
- cfg->queue_cfg.flc_cfg.flc_type); \
- MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
- cfg->queue_cfg.flc_cfg.frame_data_size); \
- MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
- cfg->queue_cfg.flc_cfg.flow_context_size); \
- MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \
- MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \
- cfg->queue_cfg.flc_cfg.flow_context); \
-} while (0)
-
-#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \
- MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
-
-#define DPNI_RSP_GET_TX_CONF(cmd, attr) \
-do { \
- MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \
- attr->queue_attr.dest_cfg.priority); \
- MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \
- attr->queue_attr.dest_cfg.dest_type); \
- MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \
- MC_RSP_OP(cmd, 0, 46, 1, int, \
- attr->queue_attr.order_preservation_en); \
- MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \
- MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \
- MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \
- attr->queue_attr.tail_drop_threshold); \
- MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \
- MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
- attr->queue_attr.flc_cfg.flc_type); \
- MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
- attr->queue_attr.flc_cfg.frame_data_size); \
- MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
- attr->queue_attr.flc_cfg.flow_context_size); \
- MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \
- MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \
- attr->queue_attr.flc_cfg.flow_context); \
+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \
+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \
+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \
+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \
+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \
+ MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \
+ MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \
} while (0)
enum net_prot {
/* Support masking of Flow Steering lookup keys */
#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
+/**
+ * enum dpni_queue_type - Identifies a type of queue targeted by the command
+ * @DPNI_QUEUE_RX: Rx queue
+ * @DPNI_QUEUE_TX: Tx queue
+ * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue
+ * @DPNI_QUEUE_RX_ERR: Rx error queue
+ */
+enum dpni_queue_type {
+ DPNI_QUEUE_RX,
+ DPNI_QUEUE_TX,
+ DPNI_QUEUE_TX_CONFIRM,
+ DPNI_QUEUE_RX_ERR,
+};
+
+struct dpni_cfg {
+ uint8_t mac_addr[6];
+ struct {
+ uint32_t options;
+ uint16_t fs_entries;
+ uint8_t num_queues;
+ uint8_t num_tcs;
+ uint8_t mac_entries;
+ uint8_t vlan_entries;
+ uint8_t qos_entries;
+ } adv;
+};
+
/**
* struct dpni_extended_cfg - Structure representing extended DPNI configuration
* @tc_cfg: TCs configuration
};
/**
- * dpni_prepare_extended_cfg() - function prepare extended parameters
- * @cfg: extended structure
- * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
+ * dpni_prepare_cfg() - function prepare parameters
+ * @cfg: cfg structure
+ * @cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
*
* This function has to be called before dpni_create()
*/
-int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
- uint8_t *ext_cfg_buf);
-
-/**
- * struct dpni_cfg - Structure representing DPNI configuration
- * @mac_addr: Primary MAC address
- * @adv: Advanced parameters; default is all zeros;
- * use this structure to change default settings
- */
-struct dpni_cfg {
- uint8_t mac_addr[6];
- /**
- * struct adv - Advanced parameters
- * @options: Mask of available options; use 'DPNI_OPT_<X>' values
- * @start_hdr: Selects the packet starting header for parsing;
- * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH'
- * @max_senders: Maximum number of different senders; used as the number
- * of dedicated Tx flows; Non-power-of-2 values are rounded
- * up to the next power-of-2 value as hardware demands it;
- * '0' will be treated as '1'
- * @max_tcs: Maximum number of traffic classes (for both Tx and Rx);
- * '0' will e treated as '1'
- * @max_unicast_filters: Maximum number of unicast filters;
- * '0' is treated as '16'
- * @max_multicast_filters: Maximum number of multicast filters;
- * '0' is treated as '64'
- * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in
- * the QoS table; '0' is treated as '64'
- * @max_qos_key_size: Maximum key size for the QoS look-up;
- * '0' is treated as '24' which is enough for IPv4
- * 5-tuple
- * @max_dist_key_size: Maximum key size for the distribution;
- * '0' is treated as '24' which is enough for IPv4 5-tuple
- * @max_policers: Maximum number of policers;
- * should be between '0' and max_tcs
- * @max_congestion_ctrl: Maximum number of congestion control groups
- * (CGs); covers early drop and congestion notification
- * requirements;
- * should be between '0' and ('max_tcs' + 'max_senders')
- * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory
- * filled with the extended configuration by calling
- * dpni_prepare_extended_cfg()
- */
- struct {
- uint32_t options;
- enum net_prot start_hdr;
- uint8_t max_senders;
- uint8_t max_tcs;
- uint8_t max_unicast_filters;
- uint8_t max_multicast_filters;
- uint8_t max_vlan_filters;
- uint8_t max_qos_entries;
- uint8_t max_qos_key_size;
- uint8_t max_dist_key_size;
- uint8_t max_policers;
- uint8_t max_congestion_ctrl;
- uint64_t ext_cfg_iova;
- } adv;
-};
-
+int dpni_prepare_cfg(const struct dpni_cfg *cfg,
+ uint8_t *cfg_buf);
/**
* dpni_create() - Create the DPNI object
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @cfg: Configuration structure
- * @token: Returned token; use in subsequent API calls
+ * @obj_id: Returned obj_id; use in subsequent API calls
*
* Create the DPNI object, allocate required resources and
* perform required initialization.
* Return: '0' on Success; Error code otherwise.
*/
int dpni_create(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
const struct dpni_cfg *cfg,
- uint16_t *token);
+ uint32_t *obj_id);
/**
* dpni_destroy() - Destroy the DPNI object and release all its resources.
* @mc_io: Pointer to MC portal's I/O object
+ * @token: Authentication token.
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
+ * @obj_id: Returned obj_id; use in subsequent API calls
*
* Return: '0' on Success; error code otherwise.
*/
int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint16_t token,
uint32_t cmd_flags,
- uint16_t token);
+ uint32_t obj_id);
/**
* struct dpni_pools_cfg - Structure representing buffer pools configuration
/**
* struct dpni_attr - Structure representing DPNI attributes
- * @id: DPNI object ID
- * @version: DPNI version
- * @start_hdr: Indicates the packet starting header for parsing
* @options: Mask of available options; reflects the value as was given in
* object's creation
- * @max_senders: Maximum number of different senders; used as the number
- * of dedicated Tx flows;
- * @max_tcs: Maximum number of traffic classes (for both Tx and Rx)
+ * @max_num_queues: Number of queues available (for both Tx and Rx)
+ * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx)
+ * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx)
* @max_unicast_filters: Maximum number of unicast filters
* @max_multicast_filters: Maximum number of multicast filters
- * @max_vlan_filters: Maximum number of VLAN filters
+ * @max_vlan_entries: Maximum number of VLAN filters
* @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table
+ * @max_fs_entries: declares the maximum entries in flow steering table
* @max_qos_key_size: Maximum key size for the QoS look-up
- * @max_dist_key_size: Maximum key size for the distribution look-up
- * @max_policers: Maximum number of policers;
- * @max_congestion_ctrl: Maximum number of congestion control groups (CGs);
- * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory;
- * call dpni_extract_extended_cfg() to extract the extended configuration
+ * @max_fs_key_size: Maximum key size for the flow steering
+ * @wriop_version: Indicates revision of WRIOP hardware block
*/
struct dpni_attr {
- int id;
- /**
- * struct version - DPNI version
- * @major: DPNI major version
- * @minor: DPNI minor version
- */
- struct {
- uint16_t major;
- uint16_t minor;
- } version;
- enum net_prot start_hdr;
+ uint32_t id;
uint32_t options;
- uint8_t max_senders;
- uint8_t max_tcs;
- uint8_t max_unicast_filters;
- uint8_t max_multicast_filters;
- uint8_t max_vlan_filters;
+ uint8_t max_num_queues;
+ uint8_t max_num_tcs;
+ uint8_t max_mac_entries;
+ uint8_t max_vlan_entries;
uint8_t max_qos_entries;
+ uint16_t max_fs_entries;
uint8_t max_qos_key_size;
- uint8_t max_dist_key_size;
- uint8_t max_policers;
- uint8_t max_congestion_ctrl;
- uint64_t ext_cfg_iova;
+ uint8_t max_fs_key_size;
+ uint16_t wriop_version;
};
/**
struct dpni_attr *attr);
/**
- * dpni_extract_extended_cfg() - extract the extended parameters
- * @cfg: extended structure
- * @ext_cfg_buf: 256 bytes of DMA-able memory
+ * dpni_extract_cfg() - extract the parameters
+ * @cfg: cfg structure
+ * @cfg_buf: 256 bytes of DMA-able memory
*
* This function has to be called after dpni_get_attributes()
*/
-int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
- const uint8_t *ext_cfg_buf);
+int dpni_extract_cfg(struct dpni_cfg *cfg,
+ const uint8_t *cfg_buf);
/**
* DPNI errors
* @data_tail_room: Data tail room
*/
struct dpni_buffer_layout {
- uint32_t options;
+ uint16_t options;
int pass_timestamp;
int pass_parser_result;
int pass_frame_status;
};
/**
- * dpni_get_rx_buffer_layout() - Retrieve Rx buffer layout attributes.
+ * dpni_get_buffer_layout() - Retrieve buffer layout attributes.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
* @layout: Returns buffer layout attributes
+ * @type: DPNI queue type
*
* Return: '0' on Success; Error code otherwise.
*/
-int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout);
+int dpni_get_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const struct dpni_buffer_layout *layout,
+ enum dpni_queue_type type);
/**
- * dpni_set_rx_buffer_layout() - Set Rx buffer layout configuration.
+ * dpni_set_buffer_layout() - Set buffer layout configuration.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
* @layout: Buffer layout configuration
+ * @type: DPNI queue type
*
* Return: '0' on Success; Error code otherwise.
*
* @warning Allowed only when DPNI is disabled
*/
-int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout);
-
-/**
- * dpni_get_tx_buffer_layout() - Retrieve Tx buffer layout attributes.
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @layout: Returns buffer layout attributes
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout);
-
-/**
- * dpni_set_tx_buffer_layout() - Set Tx buffer layout configuration.
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @layout: Buffer layout configuration
- *
- * Return: '0' on Success; Error code otherwise.
- *
- * @warning Allowed only when DPNI is disabled
- */
-int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout);
-
-/**
- * dpni_get_tx_conf_buffer_layout() - Retrieve Tx confirmation buffer layout
- * attributes.
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @layout: Returns buffer layout attributes
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- struct dpni_buffer_layout *layout);
-
-/**
- * dpni_set_tx_conf_buffer_layout() - Set Tx confirmation buffer layout
- * configuration.
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @layout: Buffer layout configuration
- *
- * Return: '0' on Success; Error code otherwise.
- *
- * @warning Allowed only when DPNI is disabled
- */
-int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- const struct dpni_buffer_layout *layout);
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const struct dpni_buffer_layout *layout,
+ enum dpni_queue_type type);
/**
* dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
uint16_t token,
uint16_t *data_offset);
-/**
- * enum dpni_counter - DPNI counter types
- * @DPNI_CNT_ING_FRAME: Counts ingress frames
- * @DPNI_CNT_ING_BYTE: Counts ingress bytes
- * @DPNI_CNT_ING_FRAME_DROP: Counts ingress frames dropped due to explicit
- * 'drop' setting
- * @DPNI_CNT_ING_FRAME_DISCARD: Counts ingress frames discarded due to errors
- * @DPNI_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
- * @DPNI_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
- * @DPNI_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
- * @DPNI_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
- * @DPNI_CNT_EGR_FRAME: Counts egress frames
- * @DPNI_CNT_EGR_BYTE: Counts egress bytes
- * @DPNI_CNT_EGR_FRAME_DISCARD: Counts egress frames discarded due to errors
- */
-enum dpni_counter {
- DPNI_CNT_ING_FRAME = 0x0,
- DPNI_CNT_ING_BYTE = 0x1,
- DPNI_CNT_ING_FRAME_DROP = 0x2,
- DPNI_CNT_ING_FRAME_DISCARD = 0x3,
- DPNI_CNT_ING_MCAST_FRAME = 0x4,
- DPNI_CNT_ING_MCAST_BYTE = 0x5,
- DPNI_CNT_ING_BCAST_FRAME = 0x6,
- DPNI_CNT_ING_BCAST_BYTES = 0x7,
- DPNI_CNT_EGR_FRAME = 0x8,
- DPNI_CNT_EGR_BYTE = 0x9,
- DPNI_CNT_EGR_FRAME_DISCARD = 0xa
-};
-
-/**
- * dpni_get_counter() - Read a specific DPNI counter
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @counter: The requested counter
- * @value: Returned counter's current value
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_get_counter(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- enum dpni_counter counter,
- uint64_t *value);
-
-/**
- * dpni_set_counter() - Set (or clear) a specific DPNI counter
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @counter: The requested counter
- * @value: New counter value; typically pass '0' for resetting
- * the counter.
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_set_counter(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- enum dpni_counter counter,
- uint64_t value);
-
/* Enable auto-negotiation */
#define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL
/* Enable half-duplex mode */
#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020
/**
- * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration
- * @options: Flags representing the suggested modifications to the Tx flow;
- * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags
- * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx
- * confirmation and error queue; Set to '0' to use the private
- * Tx confirmation and error queue; valid only if
- * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation
- * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options'
- * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable;
- * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options'
- * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable;
- * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options'
- */
-struct dpni_tx_flow_cfg {
- uint32_t options;
- int use_common_tx_conf_queue;
- int l3_chksum_gen;
- int l4_chksum_gen;
-};
-
-/**
- * dpni_set_tx_flow() - Set Tx flow configuration
+ * dpni_get_api_version - Retrieve DPNI Major and Minor version info.
+ *
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @flow_id: Provides (or returns) the sender's flow ID;
- * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate
- * a new flow_id; this ID should be used as the QDBIN argument
- * in enqueue operations
- * @cfg: Tx flow configuration
+ * @major_ver: DPNI major version
+ * @minor_ver: DPNI minor version
*
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_set_tx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t *flow_id,
- const struct dpni_tx_flow_cfg *cfg);
-
-/**
- * struct dpni_tx_flow_attr - Structure representing Tx flow attributes
- * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and
- * error queue; '0' if using private Tx confirmation and error queue
- * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled
- * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled
- */
-struct dpni_tx_flow_attr {
- int use_common_tx_conf_queue;
- int l3_chksum_gen;
- int l4_chksum_gen;
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver);
+
+/**
+ * enum dpni_confirmation_mode - Defines DPNI options supported for Tx
+ * confirmation
+ * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is
+ * an affine Tx Confirmation queue
+ * @DPNI_CONF_SINGLE: All Tx queues are associated with a single Tx
+ * confirmation queue
+ * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated
+ * with proper FD set-up to have buffers release to a Buffer Pool, otherwise
+ * buffers will be leaked.
+ */
+enum dpni_confirmation_mode {
+ DPNI_CONF_AFFINE,
+ DPNI_CONF_SINGLE,
+ DPNI_CONF_DISABLE,
};
-/**
- * dpni_get_tx_flow() - Get Tx flow attributes
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @flow_id: The sender's flow ID, as returned by the
- * dpni_set_tx_flow() function
- * @attr: Returned Tx flow attributes
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_get_tx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- struct dpni_tx_flow_attr *attr);
+struct dpni_tx_confirmation_mode {
+ uint32_t pad;
+ uint8_t confirmation_mode;
+};
/**
- * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration
- * @errors_only: Set to '1' to report back only error frames;
- * Set to '0' to confirm transmission/error for all transmitted frames;
- * @queue_cfg: Queue configuration
+ * struct dpni_queue - Queue structure
+ * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ
+ * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant
+ * for Tx queues.
+ * @flc: FLC value for traffic dequeued from this queue.
+ * @user_context: User data, presented to the user along with any frames
+ * from this queue. Not relevant for Tx queues.
*/
-struct dpni_tx_conf_cfg {
- int errors_only;
- struct dpni_queue_cfg queue_cfg;
+struct dpni_queue {
+ /**
+ * struct destination - Destination structure
+ * @id: ID of the destination, only relevant if DEST_TYPE is > 0.
+ * Identifies either a DPIO or a DPCON object. Not relevant for Tx
+ * queues.
+ * @type: May be one of the following:
+ * 0 - No destination, queue can be manually queried, but won't
+ * push traffic or notifications to a DPIO;
+ * 1 - The destination is DPIO. When traffic becomes available in
+ * the queue a FQDAN (FQ data available notification) will be
+ * generated to selected DPIO;
+ * 2 - The destination is a DPCON. The queue is associated with a
+ * DPCON object for purpose of scheduling between multiple
+ * queues. The DPCON may be independently configured to
+ * generate notifications. Not relevant for Tx queues.
+ * @hold_active: Hold active
+ */
+ struct {
+ uint32_t id;
+ enum dpni_dest type;
+ char hold_active;
+ char stash_ctrl;
+ } destination;
+ uint8_t options;
+ uint32_t fqid;
+ uint16_t qdbin;
+ uint64_t flc;
+ uint64_t user_context;
};
/**
- * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @flow_id: The sender's flow ID, as returned by the
- * dpni_set_tx_flow() function;
- * use 'DPNI_COMMON_TX_CONF' for common tx-conf
- * @cfg: Queue configuration
+ * dpni_set_queue() - Set queue parameters
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @type: Type of queue
+ * @tc: Traffic class, in range 0 to NUM_TCS - 1
+ * @index: Selects the specific queue out of the set allocated for the same
+ * TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @queue: Queue structure
*
- * If either 'DPNI_OPT_TX_CONF_DISABLED' or
- * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
- * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
- * i.e. only serve the common tx-conf-err queue;
- * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported
- * back - successfully transmitted frames are not confirmed. Otherwise, all
- * transmitted frames are sent for confirmation.
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type type,
+ uint8_t tc,
+ uint8_t index,
+ const struct dpni_queue *queue);
+
+/**
+ * dpni_get_queue() - Get queue parameters
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @type: Type of queue
+ * @tc: Traffic class, in range 0 to NUM_TCS - 1
+ * @index: Selects the specific queue out of the set allocated for the same
+ * TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @queue: Queue structure
*
- * Return: '0' on Success; Error code otherwise.
+ * Return: '0' on Success; Error code otherwise.
*/
-int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- const struct dpni_tx_conf_cfg *cfg);
+int dpni_get_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type type,
+ uint8_t tc,
+ uint8_t index,
+ struct dpni_queue *queue);
/**
- * struct dpni_tx_conf_attr - Structure representing Tx conf attributes
- * @errors_only: '1' if only error frames are reported back; '0' if all
- * transmitted frames are confirmed
- * @queue_attr: Queue attributes
+ * dpni_set_tx_confirmation_mode() - Set TX conf mode
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @mode: DPNI confirmation mode type
+ *
+ * Return: '0' on Success; Error code otherwise.
*/
-struct dpni_tx_conf_attr {
- int errors_only;
- struct dpni_queue_attr queue_attr;
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_confirmation_mode mode);
+struct dpni_statistics {
+ /**
+ * Page_0 statistics structure
+ * @ingress_all_frames: Ingress frame count
+ * @ingress_all_bytes: Ingress byte count
+ * @ingress_multicast_frames: Ingress multicast frame count
+ * @ingress_multicast_bytes: Ingress multicast byte count
+ * @ingress_broadcast_frames: Ingress broadcast frame count
+ * @ingress_broadcast_bytes: Ingress broadcast byte count
+ *
+ * Page_1 statistics structure
+ * @egress_all_frames: Egress frame count
+ * @egress_all_bytes: Egress byte count
+ * @egress_multicast_frames: Egress multicast frame count
+ * @egress_multicast_bytes: Egress multicast byte count
+ * @egress_broadcast_frames: Egress broadcast frame count
+ * @egress_broadcast_bytes: Egress broadcast byte count
+ *
+ * Page_2 statistics structure
+ * @ingress_filtered_frames: Ingress filtered frame count
+ * @ingress_discarded_frames: Ingress discarded frame count
+ * @ingress_nobuffer_discards: Ingress discarded frame count due to
+ * lack of buffers.
+ * @egress_discarded_frames: Egress discarded frame count
+ * @egress_confirmed_frames: Egress confirmed frame count
+ */
+
+ uint64_t counter0;
+ uint64_t counter1;
+ uint64_t counter2;
+ uint64_t counter3;
+ uint64_t counter4;
+ uint64_t counter5;
+ uint64_t counter6;
};
/**
- * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes
+ * dpni_get_statistics() - Get DPNI statistics
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
- * @flow_id: The sender's flow ID, as returned by the
- * dpni_set_tx_flow() function;
- * use 'DPNI_COMMON_TX_CONF' for common tx-conf
- * @attr: Returned tx-conf attributes
- *
- * If either 'DPNI_OPT_TX_CONF_DISABLED' or
- * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
- * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
- * i.e. only serve the common tx-conf-err queue;
+ * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS
+ * output. Pages are numbered 0 to 2.
+ * @stat: Structure containing the statistics
*
* Return: '0' on Success; Error code otherwise.
*/
-int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint16_t flow_id,
- struct dpni_tx_conf_attr *attr);
-/**
- * dpni_set_rx_flow() - Set Rx flow configuration
- * @mc_io: Pointer to MC portal's I/O object
- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
- * @token: Token of DPNI object
- * @tc_id: Traffic class selection (0-7);
- * use 'DPNI_ALL_TCS' to set all TCs and all flows
- * @flow_id: Rx flow id within the traffic class; use
- * 'DPNI_ALL_TC_FLOWS' to set all flows within
- * this tc_id; ignored if tc_id is set to
- * 'DPNI_ALL_TCS';
- * @cfg: Rx flow configuration
- *
- * Return: '0' on Success; Error code otherwise.
- */
-int dpni_set_rx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint8_t tc_id,
- uint16_t flow_id,
- const struct dpni_queue_cfg *cfg);
+int dpni_get_statistics(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t page,
+ struct dpni_statistics *stat);
/**
- * dpni_get_rx_flow() - Get Rx flow attributes
+ * dpni_reset_statistics() - Clears DPNI statistics
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPNI object
- * @tc_id: Traffic class selection (0-7)
- * @flow_id: Rx flow id within the traffic class
- * @attr: Returned Rx flow attributes
*
* Return: '0' on Success; Error code otherwise.
*/
-int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
- uint32_t cmd_flags,
- uint16_t token,
- uint8_t tc_id,
- uint16_t flow_id,
- struct dpni_queue_attr *attr);
-
+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
#endif /* _FSL_DPNI_H */
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
- * Author: German Rivera <German.Rivera@freescale.com>
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define _FSL_DPRC_H
/* DPRC Version */
-#define DPRC_VER_MAJOR 5
+#define DPRC_VER_MAJOR 6
#define DPRC_VER_MINOR 1
/* Command IDs */
-#define DPRC_CMDID_CLOSE 0x800
-#define DPRC_CMDID_OPEN 0x805
-#define DPRC_CMDID_CREATE 0x905
-
-#define DPRC_CMDID_GET_ATTR 0x004
-#define DPRC_CMDID_RESET_CONT 0x005
-
-#define DPRC_CMDID_CREATE_CONT 0x151
-#define DPRC_CMDID_DESTROY_CONT 0x152
-#define DPRC_CMDID_GET_CONT_ID 0x830
-#define DPRC_CMDID_GET_OBJ_COUNT 0x159
-#define DPRC_CMDID_GET_OBJ 0x15A
-#define DPRC_CMDID_GET_RES_COUNT 0x15B
-#define DPRC_CMDID_GET_RES_IDS 0x15C
-#define DPRC_CMDID_GET_OBJ_REG 0x15E
-
-#define DPRC_CMDID_CONNECT 0x167
-#define DPRC_CMDID_DISCONNECT 0x168
-#define DPRC_CMDID_GET_CONNECTION 0x16C
+#define DPRC_CMDID_CLOSE 0x8001
+#define DPRC_CMDID_OPEN 0x8051
+#define DPRC_CMDID_CREATE 0x9051
+
+#define DPRC_CMDID_GET_ATTR 0x0041
+#define DPRC_CMDID_RESET_CONT 0x0051
+#define DPRC_CMDID_GET_API_VERSION 0xa051
+
+#define DPRC_CMDID_CREATE_CONT 0x1511
+#define DPRC_CMDID_DESTROY_CONT 0x1521
+#define DPRC_CMDID_GET_CONT_ID 0x8301
+#define DPRC_CMDID_GET_OBJ_COUNT 0x1591
+#define DPRC_CMDID_GET_OBJ 0x15A1
+#define DPRC_CMDID_GET_RES_COUNT 0x15B1
+#define DPRC_CMDID_GET_RES_IDS 0x15C1
+#define DPRC_CMDID_GET_OBJ_REG 0x15E1
+
+#define DPRC_CMDID_CONNECT 0x1671
+#define DPRC_CMDID_DISCONNECT 0x1681
+#define DPRC_CMDID_GET_CONNECTION 0x16C1
/* cmd, param, offset, width, type, arg_name */
#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \
MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \
MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\
MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \
- MC_RSP_OP(cmd, 2, 0, 16, uint16_t, attr->version.major);\
- MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->version.minor);\
} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \
do { \
MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \
- MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \
- MC_CMD_OP(cmd, 1, 32, 16, uint16_t, endpoint2->if_id); \
+ MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \
MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \
MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \
MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \
/* cmd, param, offset, width, type, arg_name */
#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \
do { \
- MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \
- MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
+ MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \
MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \
MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \
uint16_t icid;
int portal_id;
uint64_t options;
- /**
- * struct version - DPRC version
- * @major: DPRC major version
- * @minor: DPRC minor version
- */
- struct {
- uint16_t major;
- uint16_t minor;
- } version;
};
/**
struct dprc_endpoint *endpoint2,
int *state);
+/**
+ * dprc_get_api_version - Retrieve DPRC Major and Minor version info.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: DPRC major version
+ * @minor_ver: DPRC minor version
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dprc_get_api_version(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 *major_ver,
+ u16 *minor_ver);
+
#endif /* _FSL_DPRC_H */
-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
uint64_t params[MC_CMD_NUM_OF_PARAMS];
};
+struct mc_rsp_create {
+ __le32 object_id;
+};
+
+struct mc_rsp_api_ver {
+ __le16 major_ver;
+ __le16 minor_ver;
+};
+
enum mc_cmd_status {
MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */
MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */
#define MC_CMD_FLAG_INTR_DIS 0x01000000
-#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */
-#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */
+#define MC_CMD_HDR_CMDID_O 48 /* Command ID field offset */
+#define MC_CMD_HDR_CMDID_S 16 /* Command ID field size */
#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */
-#define MC_CMD_HDR_TOKEN_O 38 /* Token field offset */
-#define MC_CMD_HDR_TOKEN_S 10 /* Token field size */
+#define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */
+#define MC_CMD_HDR_TOKEN_S 16 /* Token field size */
#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/
#define MC_CMD_HDR_FLAGS_O 0 /* Flags field offset */
#define MC_CMD_HDR_FLAGS_S 32 /* Flags field size*/
-#define MC_CMD_HDR_FLAGS_MASK 0xFF00FF00 /* Command flags mask */
+#define MC_CMD_HDR_FLAGS_MASK 0x0000FFFF /* Command flags mask */
#define MC_CMD_HDR_READ_STATUS(_hdr) \
((enum mc_cmd_status)mc_dec((_hdr), \
#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
(_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
+/* cmd, param, offset, width, type, arg_name */
+#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id)
+
static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
uint32_t cmd_flags,
uint16_t token)
{
- uint64_t hdr;
+ uint64_t hdr = 0;
hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);
hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S,
return status;
}
+/**
+ * mc_read_version - read version of the given cmd
+ *
+ * @cmd: pointer to a filled command
+ * @major_version: major version value for the given cmd
+ * @minor_version: minor version value for the given cmd
+ */
+static inline void mc_cmd_read_api_version(struct mc_command *cmd,
+ u16 *major_ver,
+ u16 *minor_ver)
+{
+ struct mc_rsp_api_ver *rsp_params;
+
+ rsp_params = (struct mc_rsp_api_ver *)cmd->params;
+ *major_ver = le16_to_cpu(rsp_params->major_ver);
+ *minor_ver = le16_to_cpu(rsp_params->minor_ver);
+}
+
#endif /* __FSL_MC_CMD_H */
/*
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
* @struct dpbp_attr: DPBP attribute
*/
struct fsl_dpbp_obj {
+ uint32_t dpbp_id;
uint16_t dpbp_handle;
struct dpbp_attr dpbp_attr;
};
* @struct qbman_swp *sw_portal: SW portal object
*/
struct fsl_dpio_obj {
- int dpio_id;
+ uint32_t dpio_id;
uint16_t dpio_handle;
struct qbman_swp *sw_portal; /** SW portal object */
};
* @struct dpni_buffer_layout: DPNI buffer layout
*/
struct fsl_dpni_obj {
- int dpni_id;
+ uint32_t dpni_id;
uint16_t dpni_handle;
struct dpni_attr dpni_attrs;
struct dpni_buffer_layout buf_layout;
IH_OS_OSE, /* OSE */
IH_OS_PLAN9, /* Plan 9 */
IH_OS_OPENRTOS, /* OpenRTOS */
+ IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
IH_OS_COUNT,
};
/* image node */
#define FIT_DATA_PROP "data"
+#define FIT_DATA_POSITION_PROP "data-position"
#define FIT_DATA_OFFSET_PROP "data-offset"
#define FIT_DATA_SIZE_PROP "data-size"
#define FIT_TIMESTAMP_PROP "timestamp"
int fit_image_get_data(const void *fit, int noffset,
const void **data, size_t *size);
int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset);
+int fit_image_get_data_position(const void *fit, int noffset,
+ int *data_position);
int fit_image_get_data_size(const void *fit, int noffset, int *data_size);
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
#include <asm-generic/bitsperlong.h>
#include <linux/compiler.h>
+#ifdef __KERNEL__
#define BIT(nr) (1UL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
+#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG))
+#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG)
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#endif
/*
* Create a contiguous bitmask starting at bit position @l and ending at
#ifndef __LINUX_MTD_NAND_FSL_UPM
#define __LINUX_MTD_NAND_FSL_UPM
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
#define FSL_UPM_WAIT_RUN_PATTERN 0x1
#define FSL_UPM_WAIT_WRITE_BYTE 0x2
#ifndef __FSMC_NAND_H__
#define __FSMC_NAND_H__
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
struct fsmc_regs {
u32 ctrl; /* 0x00 */
#else
#define MTD_MAX_ECCPOS_ENTRIES_LARGE 680
#endif
+/**
+ * struct mtd_oob_region - oob region definition
+ * @offset: region offset
+ * @length: region length
+ *
+ * This structure describes a region of the OOB area, and is used
+ * to retrieve ECC or free bytes sections.
+ * Each section is defined by an offset within the OOB area and a
+ * length.
+ */
+struct mtd_oob_region {
+ u32 offset;
+ u32 length;
+};
+
+/*
+ * struct mtd_ooblayout_ops - NAND OOB layout operations
+ * @ecc: function returning an ECC region in the OOB area.
+ * Should return -ERANGE if %section exceeds the total number of
+ * ECC sections.
+ * @free: function returning a free region in the OOB area.
+ * Should return -ERANGE if %section exceeds the total number of
+ * free sections.
+ */
+struct mtd_ooblayout_ops {
+ int (*ecc)(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc);
+ int (*free)(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree);
+};
/*
* Internal ECC layout control structure. For historical reasons, there is a
#endif
int index;
+ /* OOB layout description */
+ const struct mtd_ooblayout_ops *ooblayout;
+
/* ECC layout structure pointer - read only! */
struct nand_ecclayout *ecclayout;
int usecount;
};
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc);
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion);
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree);
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd);
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd);
+
+static inline void mtd_set_ooblayout(struct mtd_info *mtd,
+ const struct mtd_ooblayout_ops *ooblayout)
+{
+ mtd->ooblayout = ooblayout;
+}
+
static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
{
return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
/*
- * linux/include/linux/mtd/nand.h
- *
* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
* Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
* Changelog:
* See git changelog.
*/
-#ifndef __LINUX_MTD_NAND_H
-#define __LINUX_MTD_NAND_H
+#ifndef __LINUX_MTD_RAWNAND_H
+#define __LINUX_MTD_RAWNAND_H
#include <config.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/flashchip.h>
#include <linux/mtd/bbm.h>
+#include <asm/cache.h>
struct mtd_info;
struct nand_flash_dev;
struct device_node;
/* Scan and identify a NAND device */
-extern int nand_scan(struct mtd_info *mtd, int max_chips);
+int nand_scan(struct mtd_info *mtd, int max_chips);
/*
* Separate phases of nand_scan(), allowing board driver to intervene
* and override command or ECC setup according to flash type.
*/
-extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
+int nand_scan_ident(struct mtd_info *mtd, int max_chips,
struct nand_flash_dev *table);
-extern int nand_scan_tail(struct mtd_info *mtd);
+int nand_scan_tail(struct mtd_info *mtd);
/* Free resources held by the NAND device */
-extern void nand_release(struct mtd_info *mtd);
+void nand_release(struct mtd_info *mtd);
/* Internal helper for board drivers which need to override command function */
-extern void nand_wait_ready(struct mtd_info *mtd);
+void nand_wait_ready(struct mtd_info *mtd);
/*
* This constant declares the max. oobsize / page, which
#define NAND_STATUS_READY 0x40
#define NAND_STATUS_WP 0x80
+#define NAND_DATA_IFACE_CHECK_ONLY -1
+
/*
* Constants for ECC_MODES
*/
* pages and you want to rely on the default implementation.
*/
#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
+#define NAND_ECC_MAXIMIZE BIT(1)
+/*
+ * If your controller already sends the required NAND commands when
+ * reading or writing a page, then the framework is not supposed to
+ * send READ0 and SEQIN/PAGEPROG respectively.
+ */
+#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
/* Bit mask for flags passed to do_nand_read_ecc */
#define NAND_GET_DEVICE 0x80
*/
#define NAND_NEED_SCRAMBLING 0x00002000
+/* Device needs 3rd row address cycle */
+#define NAND_ROW_ADDR_3 0x00004000
+
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
/* Macros to identify the above */
#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
+#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
/* Non chip related options */
/* This option skips the bbt scan during initialization. */
struct nand_chip *active;
};
+/**
+ * struct nand_ecc_step_info - ECC step information of ECC engine
+ * @stepsize: data bytes per ECC step
+ * @strengths: array of supported strengths
+ * @nstrengths: number of supported strengths
+ */
+struct nand_ecc_step_info {
+ int stepsize;
+ const int *strengths;
+ int nstrengths;
+};
+
+/**
+ * struct nand_ecc_caps - capability of ECC engine
+ * @stepinfos: array of ECC step information
+ * @nstepinfos: number of ECC step information
+ * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
+ */
+struct nand_ecc_caps {
+ const struct nand_ecc_step_info *stepinfos;
+ int nstepinfos;
+ int (*calc_ecc_bytes)(int step_size, int strength);
+};
+
+/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
+#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
+static const int __name##_strengths[] = { __VA_ARGS__ }; \
+static const struct nand_ecc_step_info __name##_stepinfo = { \
+ .stepsize = __step, \
+ .strengths = __name##_strengths, \
+ .nstrengths = ARRAY_SIZE(__name##_strengths), \
+}; \
+static const struct nand_ecc_caps __name = { \
+ .stepinfos = &__name##_stepinfo, \
+ .nstepinfos = 1, \
+ .calc_ecc_bytes = __calc, \
+}
+
/**
* struct nand_ecc_ctrl - Control structure for ECC
* @mode: ECC mode
int page);
};
+static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
+{
+ return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
+}
+
/**
* struct nand_buffers - buffer structure for read/write
* @ecccalc: buffer pointer for calculated ECC, size is oobsize.
ARCH_DMA_MINALIGN)];
};
+/**
+ * struct nand_sdr_timings - SDR NAND chip timings
+ *
+ * This struct defines the timing requirements of a SDR NAND chip.
+ * These information can be found in every NAND datasheets and the timings
+ * meaning are described in the ONFI specifications:
+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
+ * Parameters)
+ *
+ * All these timings are expressed in picoseconds.
+ *
+ * @tBERS_max: Block erase time
+ * @tCCS_min: Change column setup time
+ * @tPROG_max: Page program time
+ * @tR_max: Page read time
+ * @tALH_min: ALE hold time
+ * @tADL_min: ALE to data loading time
+ * @tALS_min: ALE setup time
+ * @tAR_min: ALE to RE# delay
+ * @tCEA_max: CE# access time
+ * @tCEH_min: CE# high hold time
+ * @tCH_min: CE# hold time
+ * @tCHZ_max: CE# high to output hi-Z
+ * @tCLH_min: CLE hold time
+ * @tCLR_min: CLE to RE# delay
+ * @tCLS_min: CLE setup time
+ * @tCOH_min: CE# high to output hold
+ * @tCS_min: CE# setup time
+ * @tDH_min: Data hold time
+ * @tDS_min: Data setup time
+ * @tFEAT_max: Busy time for Set Features and Get Features
+ * @tIR_min: Output hi-Z to RE# low
+ * @tITC_max: Interface and Timing Mode Change time
+ * @tRC_min: RE# cycle time
+ * @tREA_max: RE# access time
+ * @tREH_min: RE# high hold time
+ * @tRHOH_min: RE# high to output hold
+ * @tRHW_min: RE# high to WE# low
+ * @tRHZ_max: RE# high to output hi-Z
+ * @tRLOH_min: RE# low to output hold
+ * @tRP_min: RE# pulse width
+ * @tRR_min: Ready to RE# low (data only)
+ * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
+ * rising edge of R/B#.
+ * @tWB_max: WE# high to SR[6] low
+ * @tWC_min: WE# cycle time
+ * @tWH_min: WE# high hold time
+ * @tWHR_min: WE# high to RE# low
+ * @tWP_min: WE# pulse width
+ * @tWW_min: WP# transition to WE# low
+ */
+struct nand_sdr_timings {
+ u64 tBERS_max;
+ u32 tCCS_min;
+ u64 tPROG_max;
+ u64 tR_max;
+ u32 tALH_min;
+ u32 tADL_min;
+ u32 tALS_min;
+ u32 tAR_min;
+ u32 tCEA_max;
+ u32 tCEH_min;
+ u32 tCH_min;
+ u32 tCHZ_max;
+ u32 tCLH_min;
+ u32 tCLR_min;
+ u32 tCLS_min;
+ u32 tCOH_min;
+ u32 tCS_min;
+ u32 tDH_min;
+ u32 tDS_min;
+ u32 tFEAT_max;
+ u32 tIR_min;
+ u32 tITC_max;
+ u32 tRC_min;
+ u32 tREA_max;
+ u32 tREH_min;
+ u32 tRHOH_min;
+ u32 tRHW_min;
+ u32 tRHZ_max;
+ u32 tRLOH_min;
+ u32 tRP_min;
+ u32 tRR_min;
+ u64 tRST_max;
+ u32 tWB_max;
+ u32 tWC_min;
+ u32 tWH_min;
+ u32 tWHR_min;
+ u32 tWP_min;
+ u32 tWW_min;
+};
+
+/**
+ * enum nand_data_interface_type - NAND interface timing type
+ * @NAND_SDR_IFACE: Single Data Rate interface
+ */
+enum nand_data_interface_type {
+ NAND_SDR_IFACE,
+};
+
+/**
+ * struct nand_data_interface - NAND interface timing
+ * @type: type of the timing
+ * @timings: The timing, type according to @type
+ */
+struct nand_data_interface {
+ enum nand_data_interface_type type;
+ union {
+ struct nand_sdr_timings sdr;
+ } timings;
+};
+
+/**
+ * nand_get_sdr_timings - get SDR timing from data interface
+ * @conf: The data interface
+ */
+static inline const struct nand_sdr_timings *
+nand_get_sdr_timings(const struct nand_data_interface *conf)
+{
+ if (conf->type != NAND_SDR_IFACE)
+ return ERR_PTR(-EINVAL);
+
+ return &conf->timings.sdr;
+}
+
/**
* struct nand_chip - NAND Private Flash Chip Data
* @mtd: MTD device registered to the MTD framework
* setting the read-retry mode. Mostly needed for MLC NAND.
* @ecc: [BOARDSPECIFIC] ECC control structure
* @buffers: buffer structure for read/write
+ * @buf_align: minimum buffer alignment required by a platform
* @hwcontrol: platform-specific hardware control structure
* @erase: [REPLACEABLE] erase function
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* also from the datasheet. It is the recommended ECC step
* size, if known; if unknown, set to zero.
* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
- * either deduced from the datasheet if the NAND
- * chip is not ONFI compliant or set to 0 if it is
- * (an ONFI chip is always configured in mode 0
- * after a NAND reset)
+ * set to the actually used ONFI mode if the chip is
+ * ONFI compliant or deduced from the datasheet if
+ * the NAND chip is not ONFI compliant.
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
* @read_retries: [INTERN] the number of read retry modes supported
* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
+ * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
+ * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
+ * means the configuration should not be applied but
+ * only checked.
* @bbt: [INTERN] bad block table pointer
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
* lookup.
* structure which is shared among multiple independent
* devices.
* @priv: [OPTIONAL] pointer to private chip data
- * @errstat: [OPTIONAL] hardware specific function to perform
- * additional error status checks (determine if errors are
- * correctable).
* @write_page: [REPLACEABLE] High-level page write function
*/
int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
int (*erase)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
- int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
- int status, int page);
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, int data_len, const uint8_t *buf,
- int oob_required, int page, int cached, int raw);
+ int oob_required, int page, int raw);
int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
int feature_addr, uint8_t *subfeature_para);
int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
int feature_addr, uint8_t *subfeature_para);
int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
+ int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf);
+
int chip_delay;
unsigned int options;
int onfi_version;
int jedec_version;
-#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
struct nand_onfi_params onfi_params;
-#endif
struct nand_jedec_params jedec_params;
+ struct nand_data_interface *data_interface;
+
int read_retries;
flstate_t state;
struct nand_ecc_ctrl ecc;
struct nand_buffers *buffers;
+ unsigned long buf_align;
struct nand_hw_control hwcontrol;
uint8_t *bbt;
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
-extern int nand_default_bbt(struct mtd_info *mtd);
-extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
-extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
-extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
-extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+int nand_default_bbt(struct mtd_info *mtd);
+int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
+int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
+int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
+int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
int allowbbt);
-extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
+int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, uint8_t *buf);
/*
return ONFI_TIMING_MODE_UNKNOWN;
return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
}
+#else
+static inline int onfi_feature(struct nand_chip *chip)
+{
+ return 0;
+}
+
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+ return ONFI_TIMING_MODE_UNKNOWN;
+}
+
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+ return ONFI_TIMING_MODE_UNKNOWN;
+}
#endif
+int onfi_init_data_interface(struct nand_chip *chip,
+ struct nand_data_interface *iface,
+ enum nand_data_interface_type type,
+ int timing_mode);
+
/*
* Check if it is a SLC nand.
* The !nand_is_slc() can be used to check the MLC/TLC nand chips.
void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
uint8_t nand_read_byte(struct mtd_info *mtd);
-/*
- * struct nand_sdr_timings - SDR NAND chip timings
- *
- * This struct defines the timing requirements of a SDR NAND chip.
- * These informations can be found in every NAND datasheets and the timings
- * meaning are described in the ONFI specifications:
- * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
- * Parameters)
- *
- * All these timings are expressed in picoseconds.
- */
-
-struct nand_sdr_timings {
- u32 tALH_min;
- u32 tADL_min;
- u32 tALS_min;
- u32 tAR_min;
- u32 tCEA_max;
- u32 tCEH_min;
- u32 tCH_min;
- u32 tCHZ_max;
- u32 tCLH_min;
- u32 tCLR_min;
- u32 tCLS_min;
- u32 tCOH_min;
- u32 tCS_min;
- u32 tDH_min;
- u32 tDS_min;
- u32 tFEAT_max;
- u32 tIR_min;
- u32 tITC_max;
- u32 tRC_min;
- u32 tREA_max;
- u32 tREH_min;
- u32 tRHOH_min;
- u32 tRHW_min;
- u32 tRHZ_max;
- u32 tRLOH_min;
- u32 tRP_min;
- u32 tRR_min;
- u64 tRST_max;
- u32 tWB_max;
- u32 tWC_min;
- u32 tWH_min;
- u32 tWHR_min;
- u32 tWP_min;
- u32 tWW_min;
-};
-
/* get timing characteristics from ONFI timing mode. */
const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
+/* get data interface from ONFI timing mode 0, used after reset. */
+const struct nand_data_interface *nand_get_default_data_interface(void);
int nand_check_erased_ecc_chunk(void *data, int datalen,
void *ecc, int ecclen,
void *extraoob, int extraooblen,
int threshold);
-#endif /* __LINUX_MTD_NAND_H */
+
+int nand_check_ecc_caps(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail);
+
+int nand_match_ecc_req(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail);
+
+int nand_maximize_ecc(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail);
+
+/* Reset and initialize a NAND device */
+int nand_reset(struct nand_chip *chip, int chipnr);
+#endif /* __LINUX_MTD_RAWNAND_H */
--- /dev/null
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LOG_H
+#define __LOG_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/** Log levels supported, ranging from most to least important */
+enum log_level_t {
+ LOGL_EMERG = 0, /*U-Boot is unstable */
+ LOGL_ALERT, /* Action must be taken immediately */
+ LOGL_CRIT, /* Critical conditions */
+ LOGL_ERR, /* Error that prevents something from working */
+ LOGL_WARNING, /* Warning may prevent optimial operation */
+ LOGL_NOTICE, /* Normal but significant condition, printf() */
+ LOGL_INFO, /* General information message */
+ LOGL_DEBUG, /* Basic debug-level message */
+ LOGL_DEBUG_CONTENT, /* Debug message showing full message content */
+ LOGL_DEBUG_IO, /* Debug message showing hardware I/O access */
+
+ LOGL_COUNT,
+ LOGL_FIRST = LOGL_EMERG,
+ LOGL_MAX = LOGL_DEBUG,
+};
+
+/**
+ * Log categories supported. Most of these correspond to uclasses (i.e.
+ * enum uclass_id) but there are also some more generic categories
+ */
+enum log_category_t {
+ LOGC_FIRST = 0, /* First part mirrors UCLASS_... */
+
+ LOGC_NONE = UCLASS_COUNT,
+ LOGC_ARCH,
+ LOGC_BOARD,
+ LOGC_CORE,
+ LOGC_DT,
+
+ LOGC_COUNT,
+ LOGC_END,
+};
+
+/* Helper to cast a uclass ID to a log category */
+static inline int log_uc_cat(enum uclass_id id)
+{
+ return (enum log_category_t)id;
+}
+
+/**
+ * _log() - Internal function to emit a new log record
+ *
+ * @cat: Category of log record (indicating which subsystem generated it)
+ * @level: Level of log record (indicating its severity)
+ * @file: File name of file where log record was generated
+ * @line: Line number in file where log record was generated
+ * @func: Function where log record was generated
+ * @fmt: printf() format string for log record
+ * @...: Optional parameters, according to the format string @fmt
+ * @return 0 if log record was emitted, -ve on error
+ */
+int _log(enum log_category_t cat, enum log_level_t level, const char *file,
+ int line, const char *func, const char *fmt, ...);
+
+/* Define this at the top of a file to add a prefix to debug messages */
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+/* Use a default category if this file does not supply one */
+#ifndef LOG_CATEGORY
+#define LOG_CATEGORY LOGC_NONE
+#endif
+
+/*
+ * This header may be including when CONFIG_LOG is disabled, in which case
+ * CONFIG_LOG_MAX_LEVEL is not defined. Add a check for this.
+ */
+#if CONFIG_IS_ENABLED(LOG)
+#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL)
+#else
+#define _LOG_MAX_LEVEL LOGL_INFO
+#endif
+
+/* Emit a log record if the level is less that the maximum */
+#define log(_cat, _level, _fmt, _args...) ({ \
+ int _l = _level; \
+ if (_l <= _LOG_MAX_LEVEL) \
+ _log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
+ __func__, \
+ pr_fmt(_fmt), ##_args); \
+ })
+
+#ifdef DEBUG
+#define _DEBUG 1
+#else
+#define _DEBUG 0
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define _SPL_BUILD 1
+#else
+#define _SPL_BUILD 0
+#endif
+
+#if !_DEBUG && CONFIG_IS_ENABLED(LOG)
+
+#define debug_cond(cond, fmt, args...) \
+ do { \
+ if (1) \
+ log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \
+ } while (0)
+
+#else /* _DEBUG */
+
+/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...) \
+ do { \
+ if (cond) \
+ printf(pr_fmt(fmt), ##args); \
+ } while (0)
+
+#endif /* _DEBUG */
+
+/* Show a message if DEBUG is defined in a file */
+#define debug(fmt, args...) \
+ debug_cond(_DEBUG, fmt, ##args)
+
+/* Show a message if not in SPL */
+#define warn_non_spl(fmt, args...) \
+ debug_cond(!_SPL_BUILD, fmt, ##args)
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned int line,
+ const char *function);
+#define assert(x) \
+ ({ if (!(x) && _DEBUG) \
+ __assert_fail(#x, __FILE__, __LINE__, __func__); })
+
+/**
+ * struct log_rec - a single log record
+ *
+ * Holds information about a single record in the log
+ *
+ * Members marked as 'not allocated' are stored as pointers and the caller is
+ * responsible for making sure that the data pointed to is not overwritten.
+ * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log
+ * system.
+ *
+ * @cat: Category, representing a uclass or part of U-Boot
+ * @level: Severity level, less severe is higher
+ * @file: Name of file where the log record was generated (not allocated)
+ * @line: Line number where the log record was generated
+ * @func: Function where the log record was generated (not allocated)
+ * @msg: Log message (allocated)
+ */
+struct log_rec {
+ enum log_category_t cat;
+ enum log_level_t level;
+ const char *file;
+ int line;
+ const char *func;
+ const char *msg;
+};
+
+struct log_device;
+
+/**
+ * struct log_driver - a driver which accepts and processes log records
+ *
+ * @name: Name of driver
+ */
+struct log_driver {
+ const char *name;
+ /**
+ * emit() - emit a log record
+ *
+ * Called by the log system to pass a log record to a particular driver
+ * for processing. The filter is checked before calling this function.
+ */
+ int (*emit)(struct log_device *ldev, struct log_rec *rec);
+};
+
+/**
+ * struct log_device - an instance of a log driver
+ *
+ * Since drivers are set up at build-time we need to have a separate device for
+ * the run-time aspects of drivers (currently just a list of filters to apply
+ * to records send to this device).
+ *
+ * @next_filter_num: Seqence number of next filter filter added (0=no filters
+ * yet). This increments with each new filter on the device, but never
+ * decrements
+ * @drv: Pointer to driver for this device
+ * @filter_head: List of filters for this device
+ * @sibling_node: Next device in the list of all devices
+ */
+struct log_device {
+ int next_filter_num;
+ struct log_driver *drv;
+ struct list_head filter_head;
+ struct list_head sibling_node;
+};
+
+enum {
+ LOGF_MAX_CATEGORIES = 5, /* maximum categories per filter */
+};
+
+enum log_filter_flags {
+ LOGFF_HAS_CAT = 1 << 0, /* Filter has a category list */
+};
+
+/**
+ * struct log_filter - criterial to filter out log messages
+ *
+ * @filter_num: Sequence number of this filter. This is returned when adding a
+ * new filter, and must be provided when removing a previously added
+ * filter.
+ * @flags: Flags for this filter (LOGFF_...)
+ * @cat_list: List of categories to allow (terminated by LOGC_none). If empty
+ * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries
+ * can be provided
+ * @max_level: Maximum log level to allow
+ * @file_list: List of files to allow, separated by comma. If NULL then all
+ * files are permitted
+ * @sibling_node: Next filter in the list of filters for this log device
+ */
+struct log_filter {
+ int filter_num;
+ int flags;
+ enum log_category_t cat_list[LOGF_MAX_CATEGORIES];
+ enum log_level_t max_level;
+ const char *file_list;
+ struct list_head sibling_node;
+};
+
+#define LOG_DRIVER(_name) \
+ ll_entry_declare(struct log_driver, _name, log_driver)
+
+/* Handle the 'log test' command */
+int do_log_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+
+/**
+ * log_add_filter() - Add a new filter to a log device
+ *
+ * @drv_name: Driver name to add the filter to (since each driver only has a
+ * single device)
+ * @cat_list: List of categories to allow (terminated by LOGC_none). If empty
+ * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries
+ * can be provided
+ * @max_level: Maximum log level to allow
+ * @file_list: List of files to allow, separated by comma. If NULL then all
+ * files are permitted
+ * @return the sequence number of the new filter (>=0) if the filter was added,
+ * or a -ve value on error
+ */
+int log_add_filter(const char *drv_name, enum log_category_t cat_list[],
+ enum log_level_t max_level, const char *file_list);
+
+/**
+ * log_remove_filter() - Remove a filter from a log device
+ *
+ * @drv_name: Driver name to remove the filter from (since each driver only has
+ * a single device)
+ * @filter_num: Filter number to remove (as returned by log_add_filter())
+ * @return 0 if the filter was removed, -ENOENT if either the driver or the
+ * filter number was not found
+ */
+int log_remove_filter(const char *drv_name, int filter_num);
+
+#if CONFIG_IS_ENABLED(LOG)
+/**
+ * log_init() - Set up the log system ready for use
+ *
+ * @return 0 if OK, -ENOMEM if out of memory
+ */
+int log_init(void);
+#else
+static inline int log_init(void)
+{
+ return 0;
+}
+#endif
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2002-2007
- * Detlev Zundel, dzu@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _LOGBUFF_H
-#define _LOGBUFF_H
-
-#ifdef CONFIG_LOGBUFFER
-
-#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */
-#define LOGBUFF_LEN (16384) /* Must be 16k right now */
-#define LOGBUFF_MASK (LOGBUFF_LEN-1)
-#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
-#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
-
-/* The mapping used here has to be the same as in setup_ext_logbuff ()
- in linux/kernel/printk */
-
-typedef struct {
- union {
- struct {
- unsigned long tag;
- unsigned long start;
- unsigned long con;
- unsigned long end;
- unsigned long chars;
- } v2;
- struct {
- unsigned long dummy;
- unsigned long tag;
- unsigned long start;
- unsigned long size;
- unsigned long chars;
- } v1;
- };
- unsigned char buf[0];
-} logbuff_t;
-
-int drv_logbuff_init (void);
-void logbuff_init_ptrs (void);
-void logbuff_log(char *msg);
-void logbuff_reset (void);
-unsigned long logbuffer_base (void);
-
-#endif /* CONFIG_LOGBUFFER */
-
-#endif /* _LOGBUFF_H */
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
int nand_mtd_to_devnum(struct mtd_info *mtd);
*/
int os_get_filesize(const char *fname, loff_t *size);
+/**
+ * Write a character to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param ch Character to write
+ */
+void os_putc(int ch);
+
+/**
+ * Write a string to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param str String to write (note that \n is not appended)
+ */
+void os_puts(const char *str);
+
/**
* Write the sandbox RAM buffer to a existing file
*
#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
-#define GPT_ENTRY_NUMBERS 128
+#define GPT_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS
#define GPT_ENTRY_SIZE 128
#define PARTITION_SYSTEM_GUID \
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#if defined(CONFIG_POST)
#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS
#ifdef CONFIG_SYS_POST_WORD_ADDR
extern void post_word_store(ulong value);
#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */
-#endif /* defined (CONFIG_POST) || defined(CONFIG_LOGBUFFER) */
+#endif /* defined (CONFIG_POST) */
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_POST
#define SANDBOX_BUCK_DRIVER "sandbox_buck"
#define SANDBOX_OF_BUCK_PREFIX "buck"
-#define SANDBOX_BUCK_COUNT 2
+#define SANDBOX_BUCK_COUNT 3
#define SANDBOX_LDO_COUNT 2
/*
* Sandbox PMIC registers:
#define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V"
#define SANDBOX_BUCK2_DEVNAME "buck2"
#define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V"
+/* BUCK3: for testing fallback regulator prefix matching during bind */
+#define SANDBOX_BUCK3_DEVNAME "no_match_by_nodename"
+#define SANDBOX_BUCK3_PLATNAME "buck_SUPPLY_1.5V"
/* LDO names */
#define SANDBOX_LDO1_DEVNAME "ldo1"
#define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V"
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TPS65910_PMIC_H_
+#define __TPS65910_PMIC_H_
+
+#define TPS65910_I2C_SEL_MASK (0x1 << 4)
+#define TPS65910_VDD_SR_MASK (0x1 << 7)
+#define TPS65910_GAIN_SEL_MASK (0x3 << 6)
+#define TPS65910_VDD_SEL_MASK 0x7f
+#define TPS65910_VDD_SEL_MIN 3
+#define TPS65910_VDD_SEL_MAX 75
+#define TPS65910_SEL_MASK (0x3 << 2)
+#define TPS65910_SUPPLY_STATE_MASK 0x3
+#define TPS65910_SUPPLY_STATE_OFF 0x0
+#define TPS65910_SUPPLY_STATE_ON 0x1
+
+/* i2c registers */
+enum {
+ TPS65910_REG_RTC_SEC = 0x00,
+ TPS65910_REG_RTC_MIN,
+ TPS65910_REG_RTC_HOUR,
+ TPS65910_REG_RTC_DAY,
+ TPS65910_REG_RTC_MONTH,
+ TPS65910_REG_RTC_YEAR,
+ TPS65910_REG_RTC_WEEK,
+ TPS65910_REG_RTC_ALARM_SEC = 0x08,
+ TPS65910_REG_RTC_ALARM_MIN,
+ TPS65910_REG_RTC_ALARM_HOUR,
+ TPS65910_REG_RTC_ALARM_DAY,
+ TPS65910_REG_RTC_ALARM_MONTH,
+ TPS65910_REG_RTC_ALARM_YEAR,
+ TPS65910_REG_RTC_CTRL = 0x10,
+ TPS65910_REG_RTC_STAT,
+ TPS65910_REG_RTC_INT,
+ TPS65910_REG_RTC_COMP_LSB,
+ TPS65910_REG_RTC_COMP_MSB,
+ TPS65910_REG_RTC_RESISTOR_PRG,
+ TPS65910_REG_RTC_RESET_STAT,
+ TPS65910_REG_BACKUP1,
+ TPS65910_REG_BACKUP2,
+ TPS65910_REG_BACKUP3,
+ TPS65910_REG_BACKUP4,
+ TPS65910_REG_BACKUP5,
+ TPS65910_REG_PUADEN,
+ TPS65910_REG_REF,
+ TPS65910_REG_VRTC,
+ TPS65910_REG_VIO = 0x20,
+ TPS65910_REG_VDD1,
+ TPS65910_REG_VDD1_VAL,
+ TPS65910_REG_VDD1_VAL_SR,
+ TPS65910_REG_VDD2,
+ TPS65910_REG_VDD2_VAL,
+ TPS65910_REG_VDD2_VAL_SR,
+ TPS65910_REG_VDD3,
+ TPS65910_REG_VDIG1 = 0x30,
+ TPS65910_REG_VDIG2,
+ TPS65910_REG_VAUX1,
+ TPS65910_REG_VAUX2,
+ TPS65910_REG_VAUX33,
+ TPS65910_REG_VMMC,
+ TPS65910_REG_VPLL,
+ TPS65910_REG_VDAC,
+ TPS65910_REG_THERM,
+ TPS65910_REG_BATTERY_BACKUP_CHARGE,
+ TPS65910_REG_DCDC_CTRL = 0x3e,
+ TPS65910_REG_DEVICE_CTRL,
+ TPS65910_REG_DEVICE_CTRL2,
+ TPS65910_REG_SLEEP_KEEP_LDO_ON,
+ TPS65910_REG_SLEEP_KEEP_RES_ON,
+ TPS65910_REG_SLEEP_SET_LDO_OFF,
+ TPS65910_REG_SLEEP_SET_RES_OFF,
+ TPS65910_REG_EN1_LDO_ASS,
+ TPS65910_REG_EM1_SMPS_ASS,
+ TPS65910_REG_EN2_LDO_ASS,
+ TPS65910_REG_EM2_SMPS_ASS,
+ TPS65910_REG_INT_STAT = 0x50,
+ TPS65910_REG_INT_MASK,
+ TPS65910_REG_INT_STAT2,
+ TPS65910_REG_INT_MASK2,
+ TPS65910_REG_GPIO = 0x60,
+ TPS65910_REG_JTAGREVNUM = 0x80,
+ TPS65910_NUM_REGS
+};
+
+/* chip supplies */
+enum {
+ TPS65910_SUPPLY_VCCIO = 0x00,
+ TPS65910_SUPPLY_VCC1,
+ TPS65910_SUPPLY_VCC2,
+ TPS65910_SUPPLY_VCC3,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_NUM_SUPPLIES
+};
+
+/* regulator unit numbers */
+enum {
+ TPS65910_UNIT_VRTC = 0x00,
+ TPS65910_UNIT_VIO,
+ TPS65910_UNIT_VDD1,
+ TPS65910_UNIT_VDD2,
+ TPS65910_UNIT_VDD3,
+ TPS65910_UNIT_VDIG1,
+ TPS65910_UNIT_VDIG2,
+ TPS65910_UNIT_VPLL,
+ TPS65910_UNIT_VDAC,
+ TPS65910_UNIT_VAUX1,
+ TPS65910_UNIT_VAUX2,
+ TPS65910_UNIT_VAUX33,
+ TPS65910_UNIT_VMMC,
+};
+
+/* platform data */
+struct tps65910_regulator_pdata {
+ u32 supply; /* regulator supply voltage in uV */
+ uint unit; /* unit-address according to DT */
+};
+
+/* driver names */
+#define TPS65910_BUCK_DRIVER "tps65910_buck"
+#define TPS65910_BOOST_DRIVER "tps65910_boost"
+#define TPS65910_LDO_DRIVER "tps65910_ldo"
+
+#endif /* __TPS65910_PMIC_H_ */
EXYNOS5_BOARD_ODROID_XU3_REV01,
EXYNOS5_BOARD_ODROID_XU3_REV02,
EXYNOS5_BOARD_ODROID_XU4_REV01,
+ EXYNOS5_BOARD_ODROID_HC1_REV01,
EXYNOS5_BOARD_ODROID_UNKNOWN,
EXYNOS5_BOARD_COUNT,
bool board_is_generic(void);
bool board_is_odroidxu3(void);
bool board_is_odroidxu4(void);
+bool board_is_odroidhc1(void);
#endif
#ifndef _SPL_H_
#define _SPL_H_
+#include <binman_sym.h>
+
/* Platform-specific defines */
#include <linux/compiler.h>
#include <asm/spl.h>
struct spl_image_info {
const char *name;
u8 os;
- ulong load_addr;
- ulong entry_point;
+ uintptr_t load_addr;
+ uintptr_t entry_point;
+#if CONFIG_IS_ENABLED(LOAD_FIT)
+ void *fdt_addr;
+#endif
u32 size;
u32 flags;
void *arg;
void *buf);
};
+/*
+ * We need to know the position of U-Boot in memory so we can jump to it. We
+ * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
+ * u-boot.img), hence the '_any'. These is no checking here that the correct
+ * image is found. For * example if u-boot.img is used we don't check that
+ * spl_parse_image_header() can parse a valid header.
+ */
+binman_sym_extern(ulong, u_boot_any, pos);
+
/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
int spl_mmc_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
-void bl31_entry(void);
+/**
+ * spl_invoke_atf - boot using an ARM trusted firmware image
+ */
+void spl_invoke_atf(struct spl_image_info *spl_image);
/**
* board_return_to_bootrom - allow for boards to continue with the boot ROM
--- /dev/null
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_RCC_H_
+#define __STM32_RCC_H_
+
+#define AHB_PSC_1 0
+#define AHB_PSC_2 0x8
+#define AHB_PSC_4 0x9
+#define AHB_PSC_8 0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_128 0xD
+#define AHB_PSC_256 0xE
+#define AHB_PSC_512 0xF
+
+#define APB_PSC_1 0
+#define APB_PSC_2 0x4
+#define APB_PSC_4 0x5
+#define APB_PSC_8 0x6
+#define APB_PSC_16 0x7
+
+struct pll_psc {
+ u8 pll_m;
+ u16 pll_n;
+ u8 pll_p;
+ u8 pll_q;
+ u8 ahb_psc;
+ u8 apb1_psc;
+ u8 apb2_psc;
+};
+
+struct stm32_clk_info {
+ struct pll_psc sys_pll_psc;
+ bool has_overdrive;
+ bool v2;
+};
+
+enum soc_family {
+ STM32F4,
+ STM32F7,
+};
+
+struct stm32_rcc_clk {
+ char *drv_name;
+ enum soc_family soc;
+};
+
+struct stm32_rcc_regs {
+ u32 cr; /* RCC clock control */
+ u32 pllcfgr; /* RCC PLL configuration */
+ u32 cfgr; /* RCC clock configuration */
+ u32 cir; /* RCC clock interrupt */
+ u32 ahb1rstr; /* RCC AHB1 peripheral reset */
+ u32 ahb2rstr; /* RCC AHB2 peripheral reset */
+ u32 ahb3rstr; /* RCC AHB3 peripheral reset */
+ u32 rsv0;
+ u32 apb1rstr; /* RCC APB1 peripheral reset */
+ u32 apb2rstr; /* RCC APB2 peripheral reset */
+ u32 rsv1[2];
+ u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
+ u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
+ u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
+ u32 rsv2;
+ u32 apb1enr; /* RCC APB1 peripheral clock enable */
+ u32 apb2enr; /* RCC APB2 peripheral clock enable */
+ u32 rsv3[2];
+ u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
+ u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
+ u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
+ u32 rsv4;
+ u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
+ u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
+ u32 rsv5[2];
+ u32 bdcr; /* RCC Backup domain control */
+ u32 csr; /* RCC clock control & status */
+ u32 rsv6[2];
+ u32 sscgr; /* RCC spread spectrum clock generation */
+ u32 plli2scfgr; /* RCC PLLI2S configuration */
+ /* below registers are only available on STM32F46x and STM32F7 SoCs*/
+ u32 pllsaicfgr; /* PLLSAI configuration */
+ u32 dckcfgr; /* dedicated clocks configuration register */
+ /* Below registers are only available on STM32F7 SoCs */
+ u32 dckcfgr2; /* dedicated clocks configuration register */
+};
+
+#endif /* __STM32_RCC_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TEST_COMPRESSION_H__
+#define __TEST_COMPRESSION_H__
+
+#include <test/test.h>
+
+/* Declare a new compression test */
+#define COMPRESSION_TEST(_name, _flags) \
+ UNIT_TEST(_name, _flags, compression_test)
+
+#endif /* __TEST_ENV_H__ */
#ifndef __TEST_SUITES_H__
#define __TEST_SUITES_H__
+struct unit_test;
+
+/**
+ * cmd_ut_category() - Run a category of unit tests
+ *
+ * @name: Category name
+ * @tests: List of tests to run
+ * @n_ents: Number of tests in @tests
+ * @argc: Argument count provided. Must be <= 1. If this is 1 then all
+ * tests are run, otherwise only the one named @argv[1] is run.
+ * @argv: Arguments: argv[1] is the test to run (if @argc >= 2)
+ * @return 0 if OK, CMD_RET_FAILURE on failure
+ */
+int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents,
+ int argc, char * const argv[]);
+
int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
#endif /* __TEST_SUITES_H__ */
#ifndef __LIN_COMPAT_H__
#define __LIN_COMPAT_H__
+#include <linux/bitops.h>
#include <linux/compat.h>
/* common */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr) \
- DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
#define DECLARE_BITMAP(name, bits) \
unsigned long name[BITS_TO_LONGS(bits)]
config RBTREE
bool
+config BITREVERSE
+ bool "Bit reverse library from Linux"
+
source lib/dhry/Kconfig
menu "Security support"
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <charset.h>
#include <malloc.h>
return dest;
}
+
+uint16_t *utf8_to_utf16(uint16_t *dest, const uint8_t *src, size_t size)
+{
+ while (size--) {
+ int extension_bytes;
+ uint32_t code;
+
+ extension_bytes = 0;
+ if (*src <= 0x7f) {
+ code = *src++;
+ /* Exit on zero byte */
+ if (!code)
+ size = 0;
+ } else if (*src <= 0xbf) {
+ /* Illegal code */
+ code = '?';
+ } else if (*src <= 0xdf) {
+ code = *src++ & 0x1f;
+ extension_bytes = 1;
+ } else if (*src <= 0xef) {
+ code = *src++ & 0x0f;
+ extension_bytes = 2;
+ } else if (*src <= 0xf7) {
+ code = *src++ & 0x07;
+ extension_bytes = 3;
+ } else {
+ /* Illegal code */
+ code = '?';
+ }
+
+ for (; extension_bytes && size; --size, --extension_bytes) {
+ if ((*src & 0xc0) == 0x80) {
+ code <<= 6;
+ code |= *src++ & 0x3f;
+ } else {
+ /* Illegal code */
+ code = '?';
+ ++src;
+ --size;
+ break;
+ }
+ }
+
+ if (code < 0x10000) {
+ *dest++ = code;
+ } else {
+ /*
+ * Simplified expression for
+ * (((code - 0x10000) >> 10) & 0x3ff) | 0xd800
+ */
+ *dest++ = (code >> 10) + 0xd7c0;
+ *dest++ = (code & 0x3ff) | 0xdc00;
+ }
+ }
+ return dest;
+}
struct efi_boot_services *boot = sys_table->boottime;
struct efi_mem_desc *desc;
struct efi_entry_memmap map;
- ulong key, desc_size, size;
+ efi_uintn_t key, desc_size, size;
efi_status_t ret;
u32 version;
int cs32;
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
-CFLAGS_helloworld.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI)
+CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) -Os
ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
always += helloworld.efi
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o
-obj-y += efi_file.o efi_variable.o efi_bootmgr.o
+obj-y += efi_file.o efi_variable.o efi_bootmgr.o efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_DM_VIDEO) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
DECLARE_GLOBAL_DATA_PTR;
/* Task priority level */
-static UINTN efi_tpl = TPL_APPLICATION;
+static efi_uintn_t efi_tpl = TPL_APPLICATION;
/* This list contains all the EFI objects our payload has access to */
LIST_HEAD(efi_obj_list);
event->is_queued = false;
}
-/*
- * Write a debug message for an EPI API service that is not implemented yet.
- *
- * @funcname function that is not yet implemented
- * @return EFI_UNSUPPORTED
- */
-static efi_status_t efi_unsupported(const char *funcname)
-{
- debug("EFI: App called into unimplemented function %s\n", funcname);
- return EFI_EXIT(EFI_UNSUPPORTED);
-}
-
/*
* Raise the task priority level.
*
* @new_tpl new value of the task priority level
* @return old value of the task priority level
*/
-static unsigned long EFIAPI efi_raise_tpl(UINTN new_tpl)
+static unsigned long EFIAPI efi_raise_tpl(efi_uintn_t new_tpl)
{
- UINTN old_tpl = efi_tpl;
+ efi_uintn_t old_tpl = efi_tpl;
EFI_ENTRY("0x%zx", new_tpl);
*
* @old_tpl value of the task priority level to be restored
*/
-static void EFIAPI efi_restore_tpl(UINTN old_tpl)
+static void EFIAPI efi_restore_tpl(efi_uintn_t old_tpl)
{
EFI_ENTRY("0x%zx", old_tpl);
* @return status code
*/
static efi_status_t EFIAPI efi_allocate_pages_ext(int type, int memory_type,
- unsigned long pages,
+ efi_uintn_t pages,
uint64_t *memory)
{
efi_status_t r;
- EFI_ENTRY("%d, %d, 0x%lx, %p", type, memory_type, pages, memory);
+ EFI_ENTRY("%d, %d, 0x%zx, %p", type, memory_type, pages, memory);
r = efi_allocate_pages(type, memory_type, pages, memory);
return EFI_EXIT(r);
}
* @return status code
*/
static efi_status_t EFIAPI efi_free_pages_ext(uint64_t memory,
- unsigned long pages)
+ efi_uintn_t pages)
{
efi_status_t r;
- EFI_ENTRY("%"PRIx64", 0x%lx", memory, pages);
+ EFI_ENTRY("%"PRIx64", 0x%zx", memory, pages);
r = efi_free_pages(memory, pages);
return EFI_EXIT(r);
}
* @return status code
*/
static efi_status_t EFIAPI efi_get_memory_map_ext(
- unsigned long *memory_map_size,
+ efi_uintn_t *memory_map_size,
struct efi_mem_desc *memory_map,
- unsigned long *map_key,
- unsigned long *descriptor_size,
+ efi_uintn_t *map_key,
+ efi_uintn_t *descriptor_size,
uint32_t *descriptor_version)
{
efi_status_t r;
* @return status code
*/
static efi_status_t EFIAPI efi_allocate_pool_ext(int pool_type,
- unsigned long size,
+ efi_uintn_t size,
void **buffer)
{
efi_status_t r;
- EFI_ENTRY("%d, %ld, %p", pool_type, size, buffer);
+ EFI_ENTRY("%d, %zd, %p", pool_type, size, buffer);
r = efi_allocate_pool(pool_type, size, buffer);
return EFI_EXIT(r);
}
return EFI_EXIT(r);
}
-static efi_status_t efi_create_handle(void **handle)
+/*
+ * Add a new object to the object list.
+ *
+ * The protocols list is initialized.
+ * The object handle is set.
+ *
+ * @obj object to be added
+ */
+void efi_add_handle(struct efi_object *obj)
+{
+ if (!obj)
+ return;
+ INIT_LIST_HEAD(&obj->protocols);
+ obj->handle = obj;
+ list_add_tail(&obj->link, &efi_obj_list);
+}
+
+/*
+ * Create handle.
+ *
+ * @handle new handle
+ * @return status code
+ */
+efi_status_t efi_create_handle(void **handle)
{
struct efi_object *obj;
efi_status_t r;
(void **)&obj);
if (r != EFI_SUCCESS)
return r;
- memset(obj, 0, sizeof(struct efi_object));
- obj->handle = obj;
- list_add_tail(&obj->link, &efi_obj_list);
- *handle = obj;
+ efi_add_handle(obj);
+ *handle = obj->handle;
return r;
}
+/*
+ * Find a protocol on a handle.
+ *
+ * @handle handle
+ * @protocol_guid GUID of the protocol
+ * @handler reference to the protocol
+ * @return status code
+ */
+efi_status_t efi_search_protocol(const void *handle,
+ const efi_guid_t *protocol_guid,
+ struct efi_handler **handler)
+{
+ struct efi_object *efiobj;
+ struct list_head *lhandle;
+
+ if (!handle || !protocol_guid)
+ return EFI_INVALID_PARAMETER;
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_INVALID_PARAMETER;
+ list_for_each(lhandle, &efiobj->protocols) {
+ struct efi_handler *protocol;
+
+ protocol = list_entry(lhandle, struct efi_handler, link);
+ if (!guidcmp(protocol->guid, protocol_guid)) {
+ if (handler)
+ *handler = protocol;
+ return EFI_SUCCESS;
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+/*
+ * Delete protocol from a handle.
+ *
+ * @handle handle from which the protocol shall be deleted
+ * @protocol GUID of the protocol to be deleted
+ * @protocol_interface interface of the protocol implementation
+ * @return status code
+ */
+efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+ void *protocol_interface)
+{
+ struct efi_handler *handler;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(handle, protocol, &handler);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (guidcmp(handler->guid, protocol))
+ return EFI_INVALID_PARAMETER;
+ list_del(&handler->link);
+ free(handler);
+ return EFI_SUCCESS;
+}
+
+/*
+ * Delete all protocols from a handle.
+ *
+ * @handle handle from which the protocols shall be deleted
+ * @return status code
+ */
+efi_status_t efi_remove_all_protocols(const void *handle)
+{
+ struct efi_object *efiobj;
+ struct list_head *lhandle;
+ struct list_head *pos;
+
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_INVALID_PARAMETER;
+ list_for_each_safe(lhandle, pos, &efiobj->protocols) {
+ struct efi_handler *protocol;
+ efi_status_t ret;
+
+ protocol = list_entry(lhandle, struct efi_handler, link);
+
+ ret = efi_remove_protocol(handle, protocol->guid,
+ protocol->protocol_interface);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Delete handle.
+ *
+ * @handle handle to delete
+ */
+void efi_delete_handle(struct efi_object *obj)
+{
+ if (!obj)
+ return;
+ efi_remove_all_protocols(obj->handle);
+ list_del(&obj->link);
+ free(obj);
+}
+
/*
* Our event capabilities are very limited. Only a small limited
* number of events is allowed to coexist.
* @event created event
* @return status code
*/
-efi_status_t efi_create_event(uint32_t type, UINTN notify_tpl,
+efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
* @return status code
*/
static efi_status_t EFIAPI efi_create_event_ext(
- uint32_t type, UINTN notify_tpl,
+ uint32_t type, efi_uintn_t notify_tpl,
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
* @index index of the event that was signaled
* @return status code
*/
-static efi_status_t EFIAPI efi_wait_for_event(unsigned long num_events,
+static efi_status_t EFIAPI efi_wait_for_event(efi_uintn_t num_events,
struct efi_event **event,
- size_t *index)
+ efi_uintn_t *index)
{
int i, j;
- EFI_ENTRY("%ld, %p, %p", num_events, event, index);
+ EFI_ENTRY("%zd, %p, %p", num_events, event, index);
/* Check parameters */
if (!num_events || !event)
}
/*
- * Install protocol interface.
+ * Find the internal EFI object for a handle.
*
- * This is the function for internal calls. For the API implementation of the
- * InstallProtocolInterface service see function
- * efi_install_protocol_interface_ext.
+ * @handle handle to find
+ * @return EFI object
+ */
+struct efi_object *efi_search_obj(const void *handle)
+{
+ struct efi_object *efiobj;
+
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ if (efiobj->handle == handle)
+ return efiobj;
+ }
+
+ return NULL;
+}
+
+/*
+ * Install new protocol on a handle.
*
* @handle handle on which the protocol shall be installed
* @protocol GUID of the protocol to be installed
- * @protocol_interface_type type of the interface to be installed,
- * always EFI_NATIVE_INTERFACE
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-static efi_status_t EFIAPI efi_install_protocol_interface(void **handle,
- const efi_guid_t *protocol, int protocol_interface_type,
- void *protocol_interface)
+efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol,
+ void *protocol_interface)
{
- struct list_head *lhandle;
- int i;
- efi_status_t r;
-
- if (!handle || !protocol ||
- protocol_interface_type != EFI_NATIVE_INTERFACE) {
- r = EFI_INVALID_PARAMETER;
- goto out;
- }
-
- /* Create new handle if requested. */
- if (!*handle) {
- r = efi_create_handle(handle);
- if (r != EFI_SUCCESS)
- goto out;
- }
- /* Find object. */
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
-
- if (efiobj->handle != *handle)
- continue;
- /* Check if protocol is already installed on the handle. */
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
-
- if (!handler->guid)
- continue;
- if (!guidcmp(handler->guid, protocol)) {
- r = EFI_INVALID_PARAMETER;
- goto out;
- }
- }
- /* Install protocol in first empty slot. */
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
-
- if (handler->guid)
- continue;
+ struct efi_object *efiobj;
+ struct efi_handler *handler;
+ efi_status_t ret;
- handler->guid = protocol;
- handler->protocol_interface = protocol_interface;
- r = EFI_SUCCESS;
- goto out;
- }
- r = EFI_OUT_OF_RESOURCES;
- goto out;
- }
- r = EFI_INVALID_PARAMETER;
-out:
- return r;
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_INVALID_PARAMETER;
+ ret = efi_search_protocol(handle, protocol, NULL);
+ if (ret != EFI_NOT_FOUND)
+ return EFI_INVALID_PARAMETER;
+ handler = calloc(1, sizeof(struct efi_handler));
+ if (!handler)
+ return EFI_OUT_OF_RESOURCES;
+ handler->guid = protocol;
+ handler->protocol_interface = protocol_interface;
+ list_add_tail(&handler->link, &efiobj->protocols);
+ return EFI_SUCCESS;
}
/*
* @protocol_interface interface of the protocol implementation
* @return status code
*/
-static efi_status_t EFIAPI efi_install_protocol_interface_ext(void **handle,
- const efi_guid_t *protocol, int protocol_interface_type,
- void *protocol_interface)
+static efi_status_t EFIAPI efi_install_protocol_interface(
+ void **handle, const efi_guid_t *protocol,
+ int protocol_interface_type, void *protocol_interface)
{
+ efi_status_t r;
+
EFI_ENTRY("%p, %pUl, %d, %p", handle, protocol, protocol_interface_type,
protocol_interface);
- return EFI_EXIT(efi_install_protocol_interface(handle, protocol,
- protocol_interface_type,
- protocol_interface));
+ if (!handle || !protocol ||
+ protocol_interface_type != EFI_NATIVE_INTERFACE) {
+ r = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* Create new handle if requested. */
+ if (!*handle) {
+ r = efi_create_handle(handle);
+ if (r != EFI_SUCCESS)
+ goto out;
+ debug("%sEFI: new handle %p\n", indent_string(nesting_level),
+ *handle);
+ } else {
+ debug("%sEFI: handle %p\n", indent_string(nesting_level),
+ *handle);
+ }
+ /* Add new protocol */
+ r = efi_add_protocol(*handle, protocol, protocol_interface);
+out:
+ return EFI_EXIT(r);
}
/*
/*
* Uninstall protocol interface.
*
- * This is the function for internal calls. For the API implementation of the
- * UninstallProtocolInterface service see function
- * efi_uninstall_protocol_interface_ext.
+ * This function implements the UninstallProtocolInterface service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
*
* @handle handle from which the protocol shall be removed
* @protocol GUID of the protocol to be removed
* @protocol_interface interface to be removed
* @return status code
*/
-static efi_status_t EFIAPI efi_uninstall_protocol_interface(void *handle,
- const efi_guid_t *protocol, void *protocol_interface)
+static efi_status_t EFIAPI efi_uninstall_protocol_interface(
+ void *handle, const efi_guid_t *protocol,
+ void *protocol_interface)
{
- struct list_head *lhandle;
- int i;
- efi_status_t r = EFI_NOT_FOUND;
+ struct efi_handler *handler;
+ efi_status_t r;
+
+ EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface);
if (!handle || !protocol) {
r = EFI_INVALID_PARAMETER;
goto out;
}
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
-
- if (efiobj->handle != handle)
- continue;
-
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
- const efi_guid_t *hprotocol = handler->guid;
-
- if (!hprotocol)
- continue;
- if (!guidcmp(hprotocol, protocol)) {
- if (handler->protocol_interface) {
- r = EFI_ACCESS_DENIED;
- } else {
- handler->guid = 0;
- r = EFI_SUCCESS;
- }
- goto out;
- }
- }
+ /* Find the protocol on the handle */
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
+ if (handler->protocol_interface) {
+ /* TODO disconnect controllers */
+ r = EFI_ACCESS_DENIED;
+ } else {
+ r = efi_remove_protocol(handle, protocol, protocol_interface);
}
-
out:
- return r;
-}
-
-/*
- * Uninstall protocol interface.
- *
- * This function implements the UninstallProtocolInterface service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @handle handle from which the protocol shall be removed
- * @protocol GUID of the protocol to be removed
- * @protocol_interface interface to be removed
- * @return status code
- */
-static efi_status_t EFIAPI efi_uninstall_protocol_interface_ext(void *handle,
- const efi_guid_t *protocol, void *protocol_interface)
-{
- EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface);
-
- return EFI_EXIT(efi_uninstall_protocol_interface(handle, protocol,
- protocol_interface));
+ return EFI_EXIT(r);
}
/*
const efi_guid_t *protocol, void *search_key,
struct efi_object *efiobj)
{
- int i;
+ efi_status_t ret;
switch (search_type) {
- case all_handles:
+ case ALL_HANDLES:
return 0;
- case by_register_notify:
+ case BY_REGISTER_NOTIFY:
+ /* TODO: RegisterProtocolNotify is not implemented yet */
return -1;
- case by_protocol:
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- const efi_guid_t *guid = efiobj->protocols[i].guid;
- if (guid && !guidcmp(guid, protocol))
- return 0;
- }
+ case BY_PROTOCOL:
+ ret = efi_search_protocol(efiobj->handle, protocol, NULL);
+ return (ret != EFI_SUCCESS);
+ default:
+ /* Invalid search type */
return -1;
}
-
- return -1;
}
/*
static efi_status_t efi_locate_handle(
enum efi_locate_search_type search_type,
const efi_guid_t *protocol, void *search_key,
- unsigned long *buffer_size, efi_handle_t *buffer)
+ efi_uintn_t *buffer_size, efi_handle_t *buffer)
{
- struct list_head *lhandle;
- unsigned long size = 0;
+ struct efi_object *efiobj;
+ efi_uintn_t size = 0;
+
+ /* Check parameters */
+ switch (search_type) {
+ case ALL_HANDLES:
+ break;
+ case BY_REGISTER_NOTIFY:
+ if (!search_key)
+ return EFI_INVALID_PARAMETER;
+ /* RegisterProtocolNotify is not implemented yet */
+ return EFI_UNSUPPORTED;
+ case BY_PROTOCOL:
+ if (!protocol)
+ return EFI_INVALID_PARAMETER;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /*
+ * efi_locate_handle_buffer uses this function for
+ * the calculation of the necessary buffer size.
+ * So do not require a buffer for buffersize == 0.
+ */
+ if (!buffer_size || (*buffer_size && !buffer))
+ return EFI_INVALID_PARAMETER;
/* Count how much space we need */
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
- if (!efi_search(search_type, protocol, search_key, efiobj)) {
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ if (!efi_search(search_type, protocol, search_key, efiobj))
size += sizeof(void*);
- }
}
if (*buffer_size < size) {
return EFI_NOT_FOUND;
/* Then fill the array */
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
- if (!efi_search(search_type, protocol, search_key, efiobj)) {
- *(buffer++) = efiobj->handle;
- }
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ if (!efi_search(search_type, protocol, search_key, efiobj))
+ *buffer++ = efiobj->handle;
}
return EFI_SUCCESS;
static efi_status_t EFIAPI efi_locate_handle_ext(
enum efi_locate_search_type search_type,
const efi_guid_t *protocol, void *search_key,
- unsigned long *buffer_size, efi_handle_t *buffer)
+ efi_uintn_t *buffer_size, efi_handle_t *buffer)
{
EFI_ENTRY("%d, %pUl, %p, %p, %p", search_type, protocol, search_key,
buffer_size, buffer);
buffer_size, buffer));
}
-/*
- * Get the device path and handle of an device implementing a protocol.
- *
- * This function implements the LocateDevicePath service.
- * See the Unified Extensible Firmware Interface (UEFI) specification
- * for details.
- *
- * @protocol GUID of the protocol
- * @device_path device path
- * @device handle of the device
- * @return status code
- */
-static efi_status_t EFIAPI efi_locate_device_path(
- const efi_guid_t *protocol,
- struct efi_device_path **device_path,
- efi_handle_t *device)
-{
- struct efi_object *efiobj;
-
- EFI_ENTRY("%pUl, %p, %p", protocol, device_path, device);
-
- efiobj = efi_dp_find_obj(*device_path, device_path);
- if (!efiobj)
- return EFI_EXIT(EFI_NOT_FOUND);
-
- *device = efiobj->handle;
-
- return EFI_EXIT(EFI_SUCCESS);
-}
-
/* Collapses configuration table entries, removing index i */
static void efi_remove_configuration_table(int i)
{
* @obj internal object associated with the loaded image
* @device_path device path of the loaded image
* @file_path file path of the loaded image
+ * @return status code
*/
-void efi_setup_loaded_image(struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path)
+efi_status_t efi_setup_loaded_image(
+ struct efi_loaded_image *info, struct efi_object *obj,
+ struct efi_device_path *device_path,
+ struct efi_device_path *file_path)
{
+ efi_status_t ret;
+
+ /* Add internal object to object list */
+ efi_add_handle(obj);
+ /* efi_exit() assumes that the handle points to the info */
obj->handle = info;
+ info->file_path = file_path;
+ if (device_path)
+ info->device_handle = efi_dp_find_obj(device_path, NULL);
+
/*
* When asking for the device path interface, return
* bootefi_device_path
*/
- obj->protocols[0].guid = &efi_guid_device_path;
- obj->protocols[0].protocol_interface = device_path;
+ ret = efi_add_protocol(obj->handle, &efi_guid_device_path, device_path);
+ if (ret != EFI_SUCCESS)
+ goto failure;
/*
* When asking for the loaded_image interface, just
* return handle which points to loaded_image_info
*/
- obj->protocols[1].guid = &efi_guid_loaded_image;
- obj->protocols[1].protocol_interface = info;
-
- obj->protocols[2].guid = &efi_guid_console_control;
- obj->protocols[2].protocol_interface = (void *)&efi_console_control;
+ ret = efi_add_protocol(obj->handle, &efi_guid_loaded_image, info);
+ if (ret != EFI_SUCCESS)
+ goto failure;
- obj->protocols[3].guid = &efi_guid_device_path_to_text_protocol;
- obj->protocols[3].protocol_interface =
- (void *)&efi_device_path_to_text;
+ ret = efi_add_protocol(obj->handle, &efi_guid_console_control,
+ (void *)&efi_console_control);
+ if (ret != EFI_SUCCESS)
+ goto failure;
- info->file_path = file_path;
- if (device_path)
- info->device_handle = efi_dp_find_obj(device_path, NULL);
+ ret = efi_add_protocol(obj->handle,
+ &efi_guid_device_path_to_text_protocol,
+ (void *)&efi_device_path_to_text);
+ if (ret != EFI_SUCCESS)
+ goto failure;
- list_add_tail(&obj->link, &efi_obj_list);
+ return ret;
+failure:
+ printf("ERROR: Failure to install protocols for loaded image\n");
+ return ret;
}
/*
{
struct efi_loaded_image *info;
struct efi_object *obj;
+ efi_status_t ret;
EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
if (!source_buffer) {
struct efi_device_path *dp, *fp;
- efi_status_t ret;
ret = efi_load_image_from_path(file_path, &source_buffer);
- if (ret != EFI_SUCCESS) {
- free(info);
- free(obj);
- return EFI_EXIT(ret);
- }
-
+ if (ret != EFI_SUCCESS)
+ goto failure;
/*
* split file_path which contains both the device and
* file parts:
*/
efi_dp_split_file_path(file_path, &dp, &fp);
-
- efi_setup_loaded_image(info, obj, dp, fp);
+ ret = efi_setup_loaded_image(info, obj, dp, fp);
+ if (ret != EFI_SUCCESS)
+ goto failure;
} else {
/* In this case, file_path is the "device" path, ie.
* something like a HARDWARE_DEVICE:MEMORY_MAPPED
*/
- efi_setup_loaded_image(info, obj, file_path, NULL);
+ ret = efi_setup_loaded_image(info, obj, file_path, NULL);
+ if (ret != EFI_SUCCESS)
+ goto failure;
}
-
info->reserved = efi_load_pe(source_buffer, info);
if (!info->reserved) {
- free(info);
- free(obj);
- return EFI_EXIT(EFI_UNSUPPORTED);
+ ret = EFI_UNSUPPORTED;
+ goto failure;
}
-
- *image_handle = info;
-
+ info->system_table = &systab;
+ info->parent_handle = parent_image;
+ *image_handle = obj->handle;
return EFI_EXIT(EFI_SUCCESS);
+failure:
+ free(info);
+ efi_delete_handle(obj);
+ return EFI_EXIT(ret);
}
/*
efi_status_t exit_status, unsigned long exit_data_size,
int16_t *exit_data)
{
+ /*
+ * We require that the handle points to the original loaded
+ * image protocol interface.
+ *
+ * For getting the longjmp address this is safer than locating
+ * the protocol because the protocol may have been reinstalled
+ * pointing to another memory location.
+ *
+ * TODO: We should call the unload procedure of the loaded
+ * image protocol.
+ */
struct efi_loaded_image *loaded_image_info = (void*)image_handle;
EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
panic("EFI application exited");
}
-/*
- * Find the internal EFI object for a handle.
- *
- * @handle handle to find
- * @return EFI object
- */
-static struct efi_object *efi_search_obj(void *handle)
-{
- struct list_head *lhandle;
-
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
- if (efiobj->handle == handle)
- return efiobj;
- }
-
- return NULL;
-}
-
/*
* Unload an EFI image.
*
bootm_disable_interrupts();
/* Give the payload some time to boot */
+ efi_set_watchdog(0);
WATCHDOG_RESET();
return EFI_EXIT(EFI_SUCCESS);
/*
* Reset the watchdog timer.
*
- * This function implements the WatchdogTimer service.
+ * This function implements the SetWatchdogTimer service.
* See the Unified Extensible Firmware Interface (UEFI) specification
* for details.
*
{
EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code,
data_size, watchdog_data);
- return efi_unsupported(__func__);
+ return EFI_EXIT(efi_set_watchdog(timeout));
}
/*
static efi_status_t EFIAPI efi_open_protocol_information(efi_handle_t handle,
const efi_guid_t *protocol,
struct efi_open_protocol_info_entry **entry_buffer,
- unsigned long *entry_count)
+ efi_uintn_t *entry_count)
{
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, entry_buffer,
entry_count);
*/
static efi_status_t EFIAPI efi_protocols_per_handle(void *handle,
efi_guid_t ***protocol_buffer,
- unsigned long *protocol_buffer_count)
+ efi_uintn_t *protocol_buffer_count)
{
unsigned long buffer_size;
struct efi_object *efiobj;
- unsigned long i, j;
- struct list_head *lhandle;
+ struct list_head *protocol_handle;
efi_status_t r;
EFI_ENTRY("%p, %p, %p", handle, protocol_buffer,
*protocol_buffer = NULL;
*protocol_buffer_count = 0;
- list_for_each(lhandle, &efi_obj_list) {
- efiobj = list_entry(lhandle, struct efi_object, link);
- if (efiobj->handle != handle)
- continue;
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
- /* Count protocols */
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- if (efiobj->protocols[i].guid)
- ++*protocol_buffer_count;
- }
- /* Copy guids */
- if (*protocol_buffer_count) {
- buffer_size = sizeof(efi_guid_t *) *
- *protocol_buffer_count;
- r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES,
- buffer_size,
- (void **)protocol_buffer);
- if (r != EFI_SUCCESS)
- return EFI_EXIT(r);
- j = 0;
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); ++i) {
- if (efiobj->protocols[i].guid) {
- (*protocol_buffer)[j] = (void *)
- efiobj->protocols[i].guid;
- ++j;
- }
- }
+ /* Count protocols */
+ list_for_each(protocol_handle, &efiobj->protocols) {
+ ++*protocol_buffer_count;
+ }
+
+ /* Copy guids */
+ if (*protocol_buffer_count) {
+ size_t j = 0;
+
+ buffer_size = sizeof(efi_guid_t *) * *protocol_buffer_count;
+ r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, buffer_size,
+ (void **)protocol_buffer);
+ if (r != EFI_SUCCESS)
+ return EFI_EXIT(r);
+ list_for_each(protocol_handle, &efiobj->protocols) {
+ struct efi_handler *protocol;
+
+ protocol = list_entry(protocol_handle,
+ struct efi_handler, link);
+ (*protocol_buffer)[j] = (void *)protocol->guid;
+ ++j;
}
- break;
}
return EFI_EXIT(EFI_SUCCESS);
static efi_status_t EFIAPI efi_locate_handle_buffer(
enum efi_locate_search_type search_type,
const efi_guid_t *protocol, void *search_key,
- unsigned long *no_handles, efi_handle_t **buffer)
+ efi_uintn_t *no_handles, efi_handle_t **buffer)
{
efi_status_t r;
- unsigned long buffer_size = 0;
+ efi_uintn_t buffer_size = 0;
EFI_ENTRY("%d, %pUl, %p, %p, %p", search_type, protocol, search_key,
no_handles, buffer);
void **protocol_interface)
{
struct list_head *lhandle;
- int i;
+ efi_status_t ret;
EFI_ENTRY("%pUl, %p, %p", protocol, registration, protocol_interface);
if (!protocol || !protocol_interface)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- EFI_PRINT_GUID("protocol", protocol);
-
list_for_each(lhandle, &efi_obj_list) {
struct efi_object *efiobj;
+ struct efi_handler *handler;
efiobj = list_entry(lhandle, struct efi_object, link);
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
-
- if (!handler->guid)
- continue;
- if (!guidcmp(handler->guid, protocol)) {
- *protocol_interface =
- handler->protocol_interface;
- return EFI_EXIT(EFI_SUCCESS);
- }
+
+ ret = efi_search_protocol(efiobj->handle, protocol, &handler);
+ if (ret == EFI_SUCCESS) {
+ *protocol_interface = handler->protocol_interface;
+ return EFI_EXIT(EFI_SUCCESS);
}
}
*protocol_interface = NULL;
return EFI_EXIT(EFI_NOT_FOUND);
}
+/*
+ * Get the device path and handle of an device implementing a protocol.
+ *
+ * This function implements the LocateDevicePath service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @protocol GUID of the protocol
+ * @device_path device path
+ * @device handle of the device
+ * @return status code
+ */
+static efi_status_t EFIAPI efi_locate_device_path(
+ const efi_guid_t *protocol,
+ struct efi_device_path **device_path,
+ efi_handle_t *device)
+{
+ struct efi_device_path *dp;
+ size_t i;
+ struct efi_handler *handler;
+ efi_handle_t *handles;
+ size_t len, len_dp;
+ size_t len_best = 0;
+ efi_uintn_t no_handles;
+ u8 *remainder;
+ efi_status_t ret;
+
+ EFI_ENTRY("%pUl, %p, %p", protocol, device_path, device);
+
+ if (!protocol || !device_path || !*device_path || !device) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* Find end of device path */
+ len = efi_dp_size(*device_path);
+
+ /* Get all handles implementing the protocol */
+ ret = EFI_CALL(efi_locate_handle_buffer(BY_PROTOCOL, protocol, NULL,
+ &no_handles, &handles));
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ for (i = 0; i < no_handles; ++i) {
+ /* Find the device path protocol */
+ ret = efi_search_protocol(handles[i], &efi_guid_device_path,
+ &handler);
+ if (ret != EFI_SUCCESS)
+ continue;
+ dp = (struct efi_device_path *)handler->protocol_interface;
+ len_dp = efi_dp_size(dp);
+ /*
+ * This handle can only be a better fit
+ * if its device path length is longer than the best fit and
+ * if its device path length is shorter of equal the searched
+ * device path.
+ */
+ if (len_dp <= len_best || len_dp > len)
+ continue;
+ /* Check if dp is a subpath of device_path */
+ if (memcmp(*device_path, dp, len_dp))
+ continue;
+ *device = handles[i];
+ len_best = len_dp;
+ }
+ if (len_best) {
+ remainder = (u8 *)*device_path + len_best;
+ *device_path = (struct efi_device_path *)remainder;
+ ret = EFI_SUCCESS;
+ } else {
+ ret = EFI_NOT_FOUND;
+ }
+out:
+ return EFI_EXIT(ret);
+}
+
/*
* Install multiple protocol interfaces.
*
if (!protocol)
break;
protocol_interface = va_arg(argptr, void*);
- r = efi_install_protocol_interface(handle, protocol,
- EFI_NATIVE_INTERFACE,
- protocol_interface);
+ r = EFI_CALL(efi_install_protocol_interface(
+ handle, protocol,
+ EFI_NATIVE_INTERFACE,
+ protocol_interface));
if (r != EFI_SUCCESS)
break;
i++;
if (r == EFI_SUCCESS)
return EFI_EXIT(r);
- /* If an error occured undo all changes. */
+ /* If an error occurred undo all changes. */
va_start(argptr, handle);
for (; i; --i) {
protocol = va_arg(argptr, efi_guid_t*);
protocol_interface = va_arg(argptr, void*);
- efi_uninstall_protocol_interface(handle, protocol,
- protocol_interface);
+ EFI_CALL(efi_uninstall_protocol_interface(handle, protocol,
+ protocol_interface));
}
va_end(argptr);
void *handle, ...)
{
EFI_ENTRY("%p", handle);
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ va_list argptr;
+ const efi_guid_t *protocol;
+ void *protocol_interface;
+ efi_status_t r = EFI_SUCCESS;
+ size_t i = 0;
+
+ if (!handle)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ va_start(argptr, handle);
+ for (;;) {
+ protocol = va_arg(argptr, efi_guid_t*);
+ if (!protocol)
+ break;
+ protocol_interface = va_arg(argptr, void*);
+ r = EFI_CALL(efi_uninstall_protocol_interface(
+ handle, protocol,
+ protocol_interface));
+ if (r != EFI_SUCCESS)
+ break;
+ i++;
+ }
+ va_end(argptr);
+ if (r == EFI_SUCCESS)
+ return EFI_EXIT(r);
+
+ /* If an error occurred undo all changes. */
+ va_start(argptr, handle);
+ for (; i; --i) {
+ protocol = va_arg(argptr, efi_guid_t*);
+ protocol_interface = va_arg(argptr, void*);
+ EFI_CALL(efi_install_protocol_interface(&handle, protocol,
+ EFI_NATIVE_INTERFACE,
+ protocol_interface));
+ }
+ va_end(argptr);
+
+ return EFI_EXIT(r);
}
/*
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
- struct list_head *lhandle;
- int i;
+ struct efi_handler *handler;
efi_status_t r = EFI_INVALID_PARAMETER;
EFI_ENTRY("%p, %pUl, %p, %p, %p, 0x%x", handle, protocol,
goto out;
}
- EFI_PRINT_GUID("protocol", protocol);
-
switch (attributes) {
case EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL:
case EFI_OPEN_PROTOCOL_GET_PROTOCOL:
goto out;
}
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- efiobj = list_entry(lhandle, struct efi_object, link);
-
- if (efiobj->handle != handle)
- continue;
-
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
- const efi_guid_t *hprotocol = handler->guid;
- if (!hprotocol)
- continue;
- if (!guidcmp(hprotocol, protocol)) {
- if (attributes !=
- EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {
- *protocol_interface =
- handler->protocol_interface;
- }
- r = EFI_SUCCESS;
- goto out;
- }
- }
- goto unsupported;
- }
+ r = efi_search_protocol(handle, protocol, &handler);
+ if (r != EFI_SUCCESS)
+ goto out;
-unsupported:
- r = EFI_UNSUPPORTED;
+ if (attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL)
+ *protocol_interface = handler->protocol_interface;
out:
return EFI_EXIT(r);
}
.signal_event = efi_signal_event_ext,
.close_event = efi_close_event,
.check_event = efi_check_event,
- .install_protocol_interface = efi_install_protocol_interface_ext,
+ .install_protocol_interface = efi_install_protocol_interface,
.reinstall_protocol_interface = efi_reinstall_protocol_interface,
- .uninstall_protocol_interface = efi_uninstall_protocol_interface_ext,
+ .uninstall_protocol_interface = efi_uninstall_protocol_interface,
.handle_protocol = efi_handle_protocol,
.reserved = NULL,
.register_protocol_notify = efi_register_protocol_notify,
};
const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
+const efi_guid_t efi_guid_text_output_protocol =
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID;
+const efi_guid_t efi_guid_text_input_protocol =
+ EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID;
#define cESC '\x1b'
#define ESC "\x1b"
return EFI_EXIT(EFI_UNSUPPORTED);
}
-const struct efi_console_control_protocol efi_console_control = {
+struct efi_console_control_protocol efi_console_control = {
.get_mode = efi_cin_get_mode,
.set_mode = efi_cin_set_mode,
.lock_std_in = efi_cin_lock_std_in,
return EFI_EXIT(EFI_SUCCESS);
}
-const struct efi_simple_text_output_protocol efi_con_out = {
+struct efi_simple_text_output_protocol efi_con_out = {
.reset = efi_cout_reset,
.output_string = efi_cout_output_string,
.test_string = efi_cout_test_string,
}
-static struct efi_object efi_console_control_obj =
- EFI_PROTOCOL_OBJECT(efi_guid_console_control, &efi_console_control);
-static struct efi_object efi_console_output_obj =
- EFI_PROTOCOL_OBJECT(EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID, &efi_con_out);
-static struct efi_object efi_console_input_obj =
- EFI_PROTOCOL_OBJECT(EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID, &efi_con_in);
-
/* This gets called from do_bootefi_exec(). */
int efi_console_register(void)
{
efi_status_t r;
+ struct efi_object *efi_console_control_obj;
+ struct efi_object *efi_console_output_obj;
+ struct efi_object *efi_console_input_obj;
- /* Hook up to the device list */
- list_add_tail(&efi_console_control_obj.link, &efi_obj_list);
- list_add_tail(&efi_console_output_obj.link, &efi_obj_list);
- list_add_tail(&efi_console_input_obj.link, &efi_obj_list);
+ /* Create handles */
+ r = efi_create_handle((void **)&efi_console_control_obj);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_add_protocol(efi_console_control_obj->handle,
+ &efi_guid_console_control, &efi_console_control);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_create_handle((void **)&efi_console_output_obj);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_add_protocol(efi_console_output_obj->handle,
+ &efi_guid_text_output_protocol, &efi_con_out);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_create_handle((void **)&efi_console_input_obj);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_add_protocol(efi_console_input_obj->handle,
+ &efi_guid_text_input_protocol, &efi_con_in);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ /* Create console events */
r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK,
efi_key_notify, NULL, &efi_con_in.wait_for_key);
if (r != EFI_SUCCESS) {
if (r != EFI_SUCCESS)
printf("ERROR: Failed to set console timer\n");
return r;
+out_of_memory:
+ printf("ERROR: Out of meemory\n");
+ return r;
}
.guid = U_BOOT_GUID,
};
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+/*
+ * Determine if an MMC device is an SD card.
+ *
+ * @desc block device descriptor
+ * @return true if the device is an SD card
+ */
+static bool is_sd(struct blk_desc *desc)
+{
+ struct mmc *mmc = find_mmc_device(desc->devnum);
+
+ if (!mmc)
+ return false;
+
+ return IS_SD(mmc) != 0U;
+}
+#endif
+
static void *dp_alloc(size_t sz)
{
void *buf;
* representing a device with one representing a file on the device, or
* a device with a parent device.
*/
-int efi_dp_match(struct efi_device_path *a, struct efi_device_path *b)
+int efi_dp_match(const struct efi_device_path *a,
+ const struct efi_device_path *b)
{
while (1) {
int ret;
struct efi_device_path **rem)
{
struct efi_object *efiobj;
+ unsigned int dp_size = efi_dp_size(dp);
list_for_each_entry(efiobj, &efi_obj_list, link) {
- int i;
-
- for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
- struct efi_handler *handler = &efiobj->protocols[i];
- struct efi_device_path *obj_dp;
-
- if (!handler->guid)
- break;
-
- if (guidcmp(handler->guid, &efi_guid_device_path))
- continue;
-
- obj_dp = handler->protocol_interface;
-
- do {
- if (efi_dp_match(dp, obj_dp) == 0) {
- if (rem) {
- *rem = ((void *)dp) +
- efi_dp_size(obj_dp);
- }
+ struct efi_handler *handler;
+ struct efi_device_path *obj_dp;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(efiobj->handle,
+ &efi_guid_device_path, &handler);
+ if (ret != EFI_SUCCESS)
+ continue;
+ obj_dp = handler->protocol_interface;
+
+ do {
+ if (efi_dp_match(dp, obj_dp) == 0) {
+ if (rem) {
+ /*
+ * Allow partial matches, but inform
+ * the caller.
+ */
+ *rem = ((void *)dp) +
+ efi_dp_size(obj_dp);
return efiobj;
+ } else {
+ /* Only return on exact matches */
+ if (efi_dp_size(obj_dp) == dp_size)
+ return efiobj;
}
+ }
- obj_dp = shorten_path(efi_dp_next(obj_dp));
- } while (short_path && obj_dp);
- }
+ obj_dp = shorten_path(efi_dp_next(obj_dp));
+ } while (short_path && obj_dp);
}
return NULL;
{
struct efi_object *efiobj;
- efiobj = find_obj(dp, false, rem);
+ /* Search for an exact match first */
+ efiobj = find_obj(dp, false, NULL);
+ /* Then for a fuzzy match */
+ if (!efiobj)
+ efiobj = find_obj(dp, false, rem);
+
+ /* And now for a fuzzy short match */
if (!efiobj)
efiobj = find_obj(dp, true, rem);
struct blk_desc *desc = mmc_get_blk_desc(mmc);
sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- sddp->dp.sub_type = (desc->if_type == IF_TYPE_MMC) ?
- DEVICE_PATH_SUB_TYPE_MSG_MMC :
- DEVICE_PATH_SUB_TYPE_MSG_SD;
+ sddp->dp.sub_type = is_sd(desc) ?
+ DEVICE_PATH_SUB_TYPE_MSG_SD :
+ DEVICE_PATH_SUB_TYPE_MSG_MMC;
sddp->dp.length = sizeof(*sddp);
sddp->slot_number = dev->seq;
return dpsize;
}
+/*
+ * Create a device path for a block device or one of its partitions.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
{
disk_partition_t info;
* and handling all the different cases like we do for non-
* legacy (ie CONFIG_BLK=y) case. But most important thing
* is just to have a unique device-path for if_type+devnum.
- * So map things to a fictional USB device:
+ * So map things to a fictitious USB device.
*/
struct efi_device_path_usb *udp;
if (desc->part_type == PART_TYPE_ISO) {
struct efi_device_path_cdrom_path *cddp = buf;
- cddp->boot_entry = part - 1;
+ cddp->boot_entry = part;
cddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
cddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_CDROM_PATH;
cddp->dp.length = sizeof(*cddp);
hddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
hddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH;
hddp->dp.length = sizeof(*hddp);
- hddp->partition_number = part - 1;
+ hddp->partition_number = part;
hddp->partition_start = info.start;
hddp->partition_end = info.size;
if (desc->part_type == PART_TYPE_EFI)
hddp->partmap_type = 2;
else
hddp->partmap_type = 1;
- hddp->signature_type = desc->sig_type;
- if (hddp->signature_type != 0)
+
+ switch (desc->sig_type) {
+ case SIG_TYPE_NONE:
+ default:
+ hddp->signature_type = 0;
+ memset(hddp->partition_signature, 0,
+ sizeof(hddp->partition_signature));
+ break;
+ case SIG_TYPE_MBR:
+ hddp->signature_type = 1;
+ memset(hddp->partition_signature, 0,
+ sizeof(hddp->partition_signature));
+ memcpy(hddp->partition_signature, &desc->mbr_sig,
+ sizeof(desc->mbr_sig));
+ break;
+ case SIG_TYPE_GUID:
+ hddp->signature_type = 2;
memcpy(hddp->partition_signature, &desc->guid_sig,
sizeof(hddp->partition_signature));
+ break;
+ }
buf = &hddp[1];
}
#define MAC_OUTPUT_LEN 22
#define UNKNOWN_OUTPUT_LEN 23
+#define MAX_NODE_LEN 512
+#define MAX_PATH_LEN 1024
+
const efi_guid_t efi_guid_device_path_to_text_protocol =
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
+static u16 *efi_str_to_u16(char *str)
+{
+ efi_uintn_t len;
+ u16 *out;
+ efi_status_t ret;
+
+ len = strlen(str) + 1;
+ ret = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, len * sizeof(u16),
+ (void **)&out);
+ if (ret != EFI_SUCCESS)
+ return NULL;
+ ascii2unicode(out, str);
+ out[len - 1] = 0;
+ return out;
+}
+
static char *dp_unknown(char *s, struct efi_device_path *dp)
{
- s += sprintf(s, "/UNKNOWN(%04x,%04x)", dp->type, dp->sub_type);
+ s += sprintf(s, "UNKNOWN(%04x,%04x)", dp->type, dp->sub_type);
return s;
}
case DEVICE_PATH_SUB_TYPE_MEMORY: {
struct efi_device_path_memory *mdp =
(struct efi_device_path_memory *)dp;
- s += sprintf(s, "/MemoryMapped(0x%x,0x%llx,0x%llx)",
+ s += sprintf(s, "MemoryMapped(0x%x,0x%llx,0x%llx)",
mdp->memory_type,
mdp->start_address,
mdp->end_address);
case DEVICE_PATH_SUB_TYPE_VENDOR: {
struct efi_device_path_vendor *vdp =
(struct efi_device_path_vendor *)dp;
- s += sprintf(s, "/VenHw(%pUl)", &vdp->guid);
+ s += sprintf(s, "VenHw(%pUl)", &vdp->guid);
break;
}
default:
case DEVICE_PATH_SUB_TYPE_ACPI_DEVICE: {
struct efi_device_path_acpi_path *adp =
(struct efi_device_path_acpi_path *)dp;
- s += sprintf(s, "/Acpi(PNP%04x", EISA_PNP_NUM(adp->hid));
+ s += sprintf(s, "Acpi(PNP%04x", EISA_PNP_NUM(adp->hid));
if (adp->uid)
s += sprintf(s, ",%d", adp->uid);
s += sprintf(s, ")");
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
struct efi_device_path_usb *udp =
(struct efi_device_path_usb *)dp;
- s += sprintf(s, "/Usb(0x%x,0x%x)", udp->parent_port_number,
+ s += sprintf(s, "USB(0x%x,0x%x)", udp->parent_port_number,
udp->usb_interface);
break;
}
if (mdp->if_type != 0 && mdp->if_type != 1)
break;
- s += sprintf(s, "/MAC(%02x%02x%02x%02x%02x%02x,0x%1x)",
+ s += sprintf(s, "MAC(%02x%02x%02x%02x%02x%02x,0x%1x)",
mdp->mac.addr[0], mdp->mac.addr[1],
mdp->mac.addr[2], mdp->mac.addr[3],
mdp->mac.addr[4], mdp->mac.addr[5],
struct efi_device_path_usb_class *ucdp =
(struct efi_device_path_usb_class *)dp;
- s += sprintf(s, "/USBClass(%x,%x,%x,%x,%x)",
+ s += sprintf(s, "USBClass(%x,%x,%x,%x,%x)",
ucdp->vendor_id, ucdp->product_id,
ucdp->device_class, ucdp->device_subclass,
ucdp->device_protocol);
case DEVICE_PATH_SUB_TYPE_MSG_MMC: {
const char *typename =
(dp->sub_type == DEVICE_PATH_SUB_TYPE_MSG_SD) ?
- "SDCard" : "MMC";
+ "SD" : "eMMC";
struct efi_device_path_sd_mmc_path *sddp =
(struct efi_device_path_sd_mmc_path *)dp;
- s += sprintf(s, "/%s(Slot%u)", typename, sddp->slot_number);
+ s += sprintf(s, "%s(%u)", typename, sddp->slot_number);
break;
}
default:
return s;
}
+/*
+ * Convert a media device path node to text.
+ *
+ * @s output buffer
+ * @dp device path node
+ * @return next unused buffer address
+ */
static char *dp_media(char *s, struct efi_device_path *dp)
{
switch (dp->sub_type) {
struct efi_device_path_hard_drive_path *hddp =
(struct efi_device_path_hard_drive_path *)dp;
void *sig = hddp->partition_signature;
+ u64 start;
+ u64 end;
+
+ /* Copy from packed structure to aligned memory */
+ memcpy(&start, &hddp->partition_start, sizeof(start));
+ memcpy(&end, &hddp->partition_end, sizeof(end));
switch (hddp->signature_type) {
- case SIG_TYPE_MBR:
- s += sprintf(s, "/HD(Part%d,Sig%08x)",
- hddp->partition_number,
- *(uint32_t *)sig);
+ case SIG_TYPE_MBR: {
+ u32 signature;
+
+ memcpy(&signature, sig, sizeof(signature));
+ s += sprintf(
+ s, "HD(%d,MBR,0x%08x,0x%llx,0x%llx)",
+ hddp->partition_number, signature, start, end);
break;
+ }
case SIG_TYPE_GUID:
- s += sprintf(s, "/HD(Part%d,Sig%pUl)",
- hddp->partition_number, sig);
+ s += sprintf(
+ s, "HD(%d,GPT,%pUl,0x%llx,0x%llx)",
+ hddp->partition_number, sig, start, end);
+ break;
default:
- s += sprintf(s, "/HD(Part%d,MBRType=%02x,SigType=%02x)",
- hddp->partition_number, hddp->partmap_type,
- hddp->signature_type);
+ s += sprintf(
+ s, "HD(%d,0x%02x,0,0x%llx,0x%llx)",
+ hddp->partition_number, hddp->partmap_type,
+ start, end);
+ break;
}
break;
case DEVICE_PATH_SUB_TYPE_CDROM_PATH: {
struct efi_device_path_cdrom_path *cddp =
(struct efi_device_path_cdrom_path *)dp;
- s += sprintf(s, "/CDROM(0x%x)", cddp->boot_entry);
+ s += sprintf(s, "CDROM(0x%x)", cddp->boot_entry);
break;
}
case DEVICE_PATH_SUB_TYPE_FILE_PATH: {
struct efi_device_path_file_path *fp =
(struct efi_device_path_file_path *)dp;
int slen = (dp->length - sizeof(*dp)) / 2;
- s += sprintf(s, "/%-*ls", slen, fp->str);
+ if (slen > MAX_NODE_LEN - 2)
+ slen = MAX_NODE_LEN - 2;
+ s += sprintf(s, "%-.*ls", slen, fp->str);
break;
}
default:
return s;
}
-static uint16_t *efi_convert_device_node_to_text(
- struct efi_device_path *dp,
- bool display_only,
- bool allow_shortcuts)
+/*
+ * Converts a single node to a char string.
+ *
+ * @buffer output buffer
+ * @dp device path or node
+ * @return end of string
+ */
+static char *efi_convert_single_device_node_to_text(
+ char *buffer,
+ struct efi_device_path *dp)
{
- unsigned long len;
- efi_status_t r;
- char buf[512]; /* this ought be be big enough for worst case */
- char *str = buf;
- uint16_t *out;
-
- while (dp) {
- switch (dp->type) {
- case DEVICE_PATH_TYPE_HARDWARE_DEVICE:
- str = dp_hardware(str, dp);
- break;
- case DEVICE_PATH_TYPE_ACPI_DEVICE:
- str = dp_acpi(str, dp);
- break;
- case DEVICE_PATH_TYPE_MESSAGING_DEVICE:
- str = dp_msging(str, dp);
- break;
- case DEVICE_PATH_TYPE_MEDIA_DEVICE:
- str = dp_media(str, dp);
- break;
- default:
- str = dp_unknown(str, dp);
- }
+ char *str = buffer;
- dp = efi_dp_next(dp);
+ switch (dp->type) {
+ case DEVICE_PATH_TYPE_HARDWARE_DEVICE:
+ str = dp_hardware(str, dp);
+ break;
+ case DEVICE_PATH_TYPE_ACPI_DEVICE:
+ str = dp_acpi(str, dp);
+ break;
+ case DEVICE_PATH_TYPE_MESSAGING_DEVICE:
+ str = dp_msging(str, dp);
+ break;
+ case DEVICE_PATH_TYPE_MEDIA_DEVICE:
+ str = dp_media(str, dp);
+ break;
+ default:
+ str = dp_unknown(str, dp);
}
- *str++ = '\0';
-
- len = str - buf;
- r = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, 2 * len, (void **)&out);
- if (r != EFI_SUCCESS)
- return NULL;
-
- ascii2unicode(out, buf);
- out[len - 1] = 0;
-
- return out;
+ *str = '\0';
+ return str;
}
-/* helper for debug prints.. efi_free_pool() the result. */
-uint16_t *efi_dp_str(struct efi_device_path *dp)
-{
- return efi_convert_device_node_to_text(dp, true, true);
-}
-
-
-static uint16_t EFIAPI *efi_convert_device_node_to_text_ext(
+/*
+ * This function implements the ConvertDeviceNodeToText service of the
+ * EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * device_node device node to be converted
+ * display_only true if the shorter text represenation shall be used
+ * allow_shortcuts true if shortcut forms may be used
+ * @return text represenation of the device path
+ * NULL if out of memory of device_path is NULL
+ */
+static uint16_t EFIAPI *efi_convert_device_node_to_text(
struct efi_device_path *device_node,
bool display_only,
bool allow_shortcuts)
{
- uint16_t *buffer;
+ char str[MAX_NODE_LEN];
+ uint16_t *text = NULL;
EFI_ENTRY("%p, %d, %d", device_node, display_only, allow_shortcuts);
- buffer = efi_convert_device_node_to_text(device_node, display_only,
- allow_shortcuts);
+ if (!device_node)
+ goto out;
+ efi_convert_single_device_node_to_text(str, device_node);
+
+ text = efi_str_to_u16(str);
+out:
EFI_EXIT(EFI_SUCCESS);
- return buffer;
+ return text;
}
+/*
+ * This function implements the ConvertDevicePathToText service of the
+ * EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * device_path device path to be converted
+ * display_only true if the shorter text represenation shall be used
+ * allow_shortcuts true if shortcut forms may be used
+ * @return text represenation of the device path
+ * NULL if out of memory of device_path is NULL
+ */
static uint16_t EFIAPI *efi_convert_device_path_to_text(
struct efi_device_path *device_path,
bool display_only,
bool allow_shortcuts)
{
- uint16_t *buffer;
+ uint16_t *text = NULL;
+ char buffer[MAX_PATH_LEN];
+ char *str = buffer;
EFI_ENTRY("%p, %d, %d", device_path, display_only, allow_shortcuts);
- /*
- * Our device paths are all of depth one. So its is sufficient to
- * to convert the first node.
- */
- buffer = efi_convert_device_node_to_text(device_path, display_only,
- allow_shortcuts);
+ if (!device_path)
+ goto out;
+ while (device_path &&
+ str + MAX_NODE_LEN < buffer + MAX_PATH_LEN) {
+ *str++ = '/';
+ str = efi_convert_single_device_node_to_text(str, device_path);
+ device_path = efi_dp_next(device_path);
+ }
+
+ text = efi_str_to_u16(buffer);
+out:
EFI_EXIT(EFI_SUCCESS);
- return buffer;
+ return text;
+}
+
+/* helper for debug prints.. efi_free_pool() the result. */
+uint16_t *efi_dp_str(struct efi_device_path *dp)
+{
+ return EFI_CALL(efi_convert_device_path_to_text(dp, true, true));
}
const struct efi_device_path_to_text_protocol efi_device_path_to_text = {
- .convert_device_node_to_text = efi_convert_device_node_to_text_ext,
+ .convert_device_node_to_text = efi_convert_device_node_to_text,
.convert_device_path_to_text = efi_convert_device_path_to_text,
};
return diskobj->volume;
}
+/*
+ * Create a device for a disk
+ *
+ * @name not used
+ * @if_typename interface name for block device
+ * @desc internal block device
+ * @dev_index device index for block device
+ * @offset offset into disk for simple partitions
+ */
static void efi_disk_add_dev(const char *name,
const char *if_typename,
struct blk_desc *desc,
unsigned int part)
{
struct efi_disk_obj *diskobj;
+ efi_status_t ret;
/* Don't add empty devices */
if (!desc->lba)
return;
diskobj = calloc(1, sizeof(*diskobj));
+ if (!diskobj)
+ goto out_of_memory;
+
+ /* Hook up to the device list */
+ efi_add_handle(&diskobj->parent);
/* Fill in object data */
diskobj->dp = efi_dp_from_part(desc, part);
diskobj->part = part;
- diskobj->parent.protocols[0].guid = &efi_block_io_guid;
- diskobj->parent.protocols[0].protocol_interface = &diskobj->ops;
- diskobj->parent.protocols[1].guid = &efi_guid_device_path;
- diskobj->parent.protocols[1].protocol_interface = diskobj->dp;
+ ret = efi_add_protocol(diskobj->parent.handle, &efi_block_io_guid,
+ &diskobj->ops);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
+ ret = efi_add_protocol(diskobj->parent.handle, &efi_guid_device_path,
+ diskobj->dp);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
if (part >= 1) {
diskobj->volume = efi_simple_file_system(desc, part,
diskobj->dp);
- diskobj->parent.protocols[2].guid =
- &efi_simple_file_system_protocol_guid;
- diskobj->parent.protocols[2].protocol_interface =
- diskobj->volume;
+ ret = efi_add_protocol(diskobj->parent.handle,
+ &efi_simple_file_system_protocol_guid,
+ &diskobj->volume);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
}
- diskobj->parent.handle = diskobj;
diskobj->ops = block_io_disk_template;
diskobj->ifname = if_typename;
diskobj->dev_index = dev_index;
diskobj->media.block_size = desc->blksz;
diskobj->media.io_align = desc->blksz;
diskobj->media.last_block = desc->lba - offset;
+ if (part != 0)
+ diskobj->media.logical_partition = 1;
diskobj->ops.media = &diskobj->media;
-
- /* Hook up to the device list */
- list_add_tail(&diskobj->parent.link, &efi_obj_list);
+ return;
+out_of_memory:
+ printf("ERROR: Out of memory\n");
}
-static int efi_disk_create_eltorito(struct blk_desc *desc,
- const char *if_typename,
- int diskid,
- const char *pdevname)
+static int efi_disk_create_partitions(struct blk_desc *desc,
+ const char *if_typename,
+ int diskid,
+ const char *pdevname)
{
int disks = 0;
-#if CONFIG_IS_ENABLED(ISO_PARTITION)
char devname[32] = { 0 }; /* dp->str is u16[32] long */
disk_partition_t info;
int part;
- if (desc->part_type != PART_TYPE_ISO)
- return 0;
-
- /* and devices for each partition: */
+ /* Add devices for each partition */
for (part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
if (part_get_info(desc, part, &info))
continue;
disks++;
}
- /* ... and add block device: */
- efi_disk_add_dev(devname, if_typename, desc, diskid, 0, 0);
-#endif
-
return disks;
}
uclass_next_device_check(&dev)) {
struct blk_desc *desc = dev_get_uclass_platdata(dev);
const char *if_typename = dev->driver->name;
- disk_partition_t info;
- int part;
printf("Scanning disk %s...\n", dev->name);
- /* add devices for each partition: */
- for (part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
- if (part_get_info(desc, part, &info))
- continue;
- efi_disk_add_dev(dev->name, if_typename, desc,
- desc->devnum, 0, part);
- }
-
- /* ... and add block device: */
+ /* Add block device for the full device */
efi_disk_add_dev(dev->name, if_typename, desc,
desc->devnum, 0, 0);
disks++;
- /*
- * El Torito images show up as block devices in an EFI world,
- * so let's create them here
- */
- disks += efi_disk_create_eltorito(desc, if_typename,
- desc->devnum, dev->name);
+ /* Partitions show up as block devices in EFI */
+ disks += efi_disk_create_partitions(desc, if_typename,
+ desc->devnum, dev->name);
}
#else
int i, if_type;
for (i = 0; i < 4; i++) {
struct blk_desc *desc;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
- disk_partition_t info;
- int part;
desc = blk_get_devnum_by_type(if_type, i);
if (!desc)
snprintf(devname, sizeof(devname), "%s%d",
if_typename, i);
- /* add devices for each partition: */
- for (part = 1; part <= MAX_SEARCH_PARTITIONS; part++) {
- if (part_get_info(desc, part, &info))
- continue;
- efi_disk_add_dev(devname, if_typename, desc,
- i, 0, part);
- }
-
- /* ... and add block device: */
+ /* Add block device for the full device */
efi_disk_add_dev(devname, if_typename, desc, i, 0, 0);
disks++;
- /*
- * El Torito images show up as block devices
- * in an EFI world, so let's create them here
- */
- disks += efi_disk_create_eltorito(desc, if_typename,
- i, devname);
+ /* Partitions show up as block devices in EFI */
+ disks += efi_disk_create_partitions(desc, if_typename,
+ i, devname);
}
}
#endif
};
static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
- unsigned long *size_of_info,
+ efi_uintn_t *size_of_info,
struct efi_gop_mode_info **info)
{
struct efi_gop_obj *gopobj;
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
- unsigned long operation, unsigned long sx,
- unsigned long sy, unsigned long dx,
- unsigned long dy, unsigned long width,
- unsigned long height, unsigned long delta)
+efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
+ u32 operation, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
{
struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
int i, j, line_len16, line_len32;
void *fb;
- EFI_ENTRY("%p, %p, %lx, %lx, %lx, %lx, %lx, %lx, %lx, %lx", this,
+ EFI_ENTRY("%p, %p, %u, %zu, %zu, %zu, %zu, %zu, %zu, %zu", this,
buffer, operation, sx, sy, dx, dy, width, height, delta);
if (operation != EFI_BLT_BUFFER_TO_VIDEO)
u32 bpix, col, row;
u64 fb_base, fb_size;
void *fb;
+ efi_status_t ret;
#ifdef CONFIG_DM_VIDEO
struct udevice *vdev;
}
gopobj = calloc(1, sizeof(*gopobj));
+ if (!gopobj) {
+ printf("ERROR: Out of memory\n");
+ return 1;
+ }
+
+ /* Hook up to the device list */
+ efi_add_handle(&gopobj->parent);
/* Fill in object data */
- gopobj->parent.protocols[0].guid = &efi_gop_guid;
- gopobj->parent.protocols[0].protocol_interface = &gopobj->ops;
- gopobj->parent.handle = &gopobj->ops;
+ ret = efi_add_protocol(gopobj->parent.handle, &efi_gop_guid,
+ &gopobj->ops);
+ if (ret != EFI_SUCCESS) {
+ printf("ERROR: Out of memory\n");
+ return 1;
+ }
gopobj->ops.query_mode = gop_query_mode;
gopobj->ops.set_mode = gop_set_mode;
gopobj->ops.blt = gop_blt;
gopobj->bpix = bpix;
gopobj->fb = fb;
- /* Hook up to the device list */
- list_add_tail(&gopobj->parent.link, &efi_obj_list);
-
return 0;
}
}
efi_status_t efi_allocate_pages(int type, int memory_type,
- unsigned long pages, uint64_t *memory)
+ efi_uintn_t pages, uint64_t *memory)
{
u64 len = pages << EFI_PAGE_SHIFT;
efi_status_t r = EFI_SUCCESS;
return NULL;
}
-efi_status_t efi_free_pages(uint64_t memory, unsigned long pages)
+efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
return EFI_NOT_FOUND;
}
-efi_status_t efi_allocate_pool(int pool_type, unsigned long size,
+efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size,
void **buffer)
{
efi_status_t r;
return r;
}
-efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
- struct efi_mem_desc *memory_map,
- unsigned long *map_key,
- unsigned long *descriptor_size,
- uint32_t *descriptor_version)
+efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
+ struct efi_mem_desc *memory_map,
+ efi_uintn_t *map_key,
+ efi_uintn_t *descriptor_size,
+ uint32_t *descriptor_version)
{
- ulong map_size = 0;
+ efi_uintn_t map_size = 0;
int map_entries = 0;
struct list_head *lhandle;
- unsigned long provided_map_size = *memory_map_size;
+ efi_uintn_t provided_map_size = *memory_map_size;
list_for_each(lhandle, &efi_mem)
map_entries++;
/* We only expose the "active" eth device, so one is enough */
netobj = calloc(1, sizeof(*netobj));
+ if (!netobj)
+ goto out_of_memory;
+
+ /* Hook net up to the device list */
+ efi_add_handle(&netobj->parent);
/* Fill in object data */
- netobj->parent.protocols[0].guid = &efi_net_guid;
- netobj->parent.protocols[0].protocol_interface = &netobj->net;
- netobj->parent.protocols[1].guid = &efi_guid_device_path;
- netobj->parent.protocols[1].protocol_interface =
- efi_dp_from_eth();
- netobj->parent.protocols[2].guid = &efi_pxe_guid;
- netobj->parent.protocols[2].protocol_interface = &netobj->pxe;
- netobj->parent.handle = &netobj->net;
+ r = efi_add_protocol(netobj->parent.handle, &efi_net_guid,
+ &netobj->net);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_add_protocol(netobj->parent.handle, &efi_guid_device_path,
+ efi_dp_from_eth());
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
+ r = efi_add_protocol(netobj->parent.handle, &efi_pxe_guid,
+ &netobj->pxe);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
netobj->net.revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
netobj->net.start = efi_net_start;
netobj->net.stop = efi_net_stop;
if (dhcp_ack)
netobj->pxe_mode.dhcp_ack = *dhcp_ack;
- /* Hook net up to the device list */
- list_add_tail(&netobj->parent.link, &efi_obj_list);
-
/*
* Create WaitForPacket event.
*/
}
return 0;
+out_of_memory:
+ printf("ERROR: Out of memory\n");
+ return 1;
}
--- /dev/null
+/*
+ * EFI watchdog
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+
+/* Conversion factor from seconds to multiples of 100ns */
+#define EFI_SECONDS_TO_100NS 10000000ULL
+
+static struct efi_event *watchdog_timer_event;
+
+/*
+ * Reset the system when the watchdog event is notified.
+ *
+ * @event: the watchdog event
+ * @context: not used
+ */
+static void EFIAPI efi_watchdog_timer_notify(struct efi_event *event,
+ void *context)
+{
+ EFI_ENTRY("%p, %p", event, context);
+
+ printf("\nEFI: Watchdog timeout\n");
+ EFI_CALL_VOID(efi_runtime_services.reset_system(EFI_RESET_COLD,
+ EFI_SUCCESS, 0, NULL));
+
+ EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+/*
+ * Reset the watchdog timer.
+ *
+ * This function is used by the SetWatchdogTimer service.
+ *
+ * @timeout: seconds before reset by watchdog
+ * @return: status code
+ */
+efi_status_t efi_set_watchdog(unsigned long timeout)
+{
+ efi_status_t r;
+
+ if (timeout)
+ /* Reset watchdog */
+ r = efi_set_timer(watchdog_timer_event, EFI_TIMER_RELATIVE,
+ EFI_SECONDS_TO_100NS * timeout);
+ else
+ /* Deactivate watchdog */
+ r = efi_set_timer(watchdog_timer_event, EFI_TIMER_STOP, 0);
+ return r;
+}
+
+/*
+ * Initialize the EFI watchdog.
+ *
+ * This function is called by efi_init_obj_list()
+ */
+int efi_watchdog_register(void)
+{
+ efi_status_t r;
+
+ /*
+ * Create a timer event.
+ */
+ r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
+ efi_watchdog_timer_notify, NULL,
+ &watchdog_timer_event);
+ if (r != EFI_SUCCESS) {
+ printf("ERROR: Failed to register watchdog event\n");
+ return r;
+ }
+ /*
+ * The UEFI standard requires that the watchdog timer is set to five
+ * minutes when invoking an EFI boot option.
+ *
+ * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
+ * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
+ */
+ r = efi_set_watchdog(300);
+ if (r != EFI_SUCCESS) {
+ printf("ERROR: Failed to set watchdog timer\n");
+ return r;
+ }
+ return 0;
+}
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * This program demonstrates calling a boottime service.
+ * It writes a greeting and the load options to the console.
*/
#include <common.h>
-#include <part_efi.h>
#include <efi_api.h>
+static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
efi_status_t EFIAPI efi_main(efi_handle_t handle,
struct efi_system_table *systable)
{
struct efi_simple_text_output_protocol *con_out = systable->con_out;
struct efi_boot_services *boottime = systable->boottime;
+ struct efi_loaded_image *loaded_image;
+ efi_status_t ret;
con_out->output_string(con_out, L"Hello, world!\n");
- boottime->exit(handle, 0, 0, NULL);
- return EFI_SUCCESS;
+ /* Get the loaded image protocol */
+ ret = boottime->handle_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image);
+ if (ret != EFI_SUCCESS) {
+ con_out->output_string(con_out,
+ L"Cannot open loaded image protocol\n");
+ goto out;
+ }
+ /* Output the load options */
+ con_out->output_string(con_out, L"Load options: ");
+ if (loaded_image->load_options_size && loaded_image->load_options)
+ con_out->output_string(con_out,
+ (u16 *)loaded_image->load_options);
+ else
+ con_out->output_string(con_out, L"<none>");
+ con_out->output_string(con_out, L"\n");
+
+out:
+ boottime->exit(handle, ret, 0, NULL);
+
+ /* We should never arrive here */
+ return ret;
}
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
-CFLAGS_efi_selftest.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_console.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_console.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_events.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_events.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_exitbootservices.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_exitbootservices.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_snp.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_snp.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_tpl.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_tpl.o := $(CFLAGS_NON_EFI)
-CFLAGS_efi_selftest_util.o := $(CFLAGS_EFI)
-CFLAGS_REMOVE_efi_selftest_util.o := $(CFLAGS_NON_EFI)
-
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
efi_selftest_console.o \
+efi_selftest_devicepath.o \
efi_selftest_events.o \
efi_selftest_exitbootservices.o \
+efi_selftest_gop.o \
+efi_selftest_manageprotocols.o \
efi_selftest_snp.o \
+efi_selftest_textoutput.o \
efi_selftest_tpl.o \
-efi_selftest_util.o
+efi_selftest_util.o \
+efi_selftest_watchdog.o
#include <efi_selftest.h>
#include <vsprintf.h>
+/*
+ * Constants for test step bitmap
+ */
+#define EFI_ST_SETUP 1
+#define EFI_ST_EXECUTE 2
+#define EFI_ST_TEARDOWN 4
+
static const struct efi_system_table *systable;
static const struct efi_boot_services *boottime;
static const struct efi_runtime_services *runtime;
*/
void efi_st_exit_boot_services(void)
{
- unsigned long map_size = 0;
- unsigned long map_key;
- unsigned long desc_size;
+ efi_uintn_t map_size = 0;
+ efi_uintn_t map_key;
+ efi_uintn_t desc_size;
u32 desc_version;
efi_status_t ret;
struct efi_mem_desc *memory_map;
return ret;
}
+/*
+ * Check that a test exists.
+ *
+ * @testname: name of the test
+ * @return: test
+ */
+static struct efi_unit_test *find_test(const u16 *testname)
+{
+ struct efi_unit_test *test;
+
+ for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
+ test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
+ if (!efi_st_strcmp_16_8(testname, test->name))
+ return test;
+ }
+ efi_st_printf("\nTest '%ps' not found\n", testname);
+ return NULL;
+}
+
+/*
+ * List all available tests.
+ */
+static void list_all_tests(void)
+{
+ struct efi_unit_test *test;
+
+ /* List all tests */
+ efi_st_printf("\nAvailable tests:\n");
+ for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
+ test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
+ efi_st_printf("'%s'%s\n", test->name,
+ test->on_request ? " - on request" : "");
+ }
+}
+
+/*
+ * Execute test steps of one phase.
+ *
+ * @testname name of a single selected test or NULL
+ * @phase test phase
+ * @steps steps to execute
+ * failures returns EFI_ST_SUCCESS if all test steps succeeded
+ */
+void efi_st_do_tests(const u16 *testname, unsigned int phase,
+ unsigned int steps, unsigned int *failures)
+{
+ struct efi_unit_test *test;
+
+ for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
+ test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
+ if (testname ?
+ efi_st_strcmp_16_8(testname, test->name) : test->on_request)
+ continue;
+ if (test->phase != phase)
+ continue;
+ if (steps & EFI_ST_SETUP)
+ setup(test, failures);
+ if (steps & EFI_ST_EXECUTE)
+ execute(test, failures);
+ if (steps & EFI_ST_TEARDOWN)
+ teardown(test, failures);
+ }
+}
+
/*
* Execute selftest of the EFI API
*
efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle,
struct efi_system_table *systab)
{
- struct efi_unit_test *test;
unsigned int failures = 0;
+ const u16 *testname = NULL;
+ struct efi_loaded_image *loaded_image;
+ efi_status_t ret;
systable = systab;
boottime = systable->boottime;
con_out = systable->con_out;
con_in = systable->con_in;
- efi_st_printf("\nTesting EFI API implementation\n");
+ ret = boottime->handle_protocol(image_handle, &efi_guid_loaded_image,
+ (void **)&loaded_image);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot open loaded image protocol\n");
+ return ret;
+ }
- efi_st_printf("\nNumber of tests to execute: %u\n",
- ll_entry_count(struct efi_unit_test, efi_unit_test));
+ if (loaded_image->load_options)
+ testname = (u16 *)loaded_image->load_options;
- /* Execute boottime tests */
- for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
- test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
- if (test->phase == EFI_EXECUTE_BEFORE_BOOTTIME_EXIT) {
- setup(test, &failures);
- execute(test, &failures);
- teardown(test, &failures);
+ if (testname) {
+ if (!efi_st_strcmp_16_8(testname, "list") ||
+ !find_test(testname)) {
+ list_all_tests();
+ /*
+ * TODO:
+ * Once the Exit boottime service is correctly
+ * implemented we should call
+ * boottime->exit(image_handle, EFI_SUCCESS, 0, NULL);
+ * here, cf.
+ * https://lists.denx.de/pipermail/u-boot/2017-October/308720.html
+ */
+ return EFI_SUCCESS;
}
}
+ efi_st_printf("\nTesting EFI API implementation\n");
+
+ if (testname)
+ efi_st_printf("\nSelected test: '%ps'\n", testname);
+ else
+ efi_st_printf("\nNumber of tests to execute: %u\n",
+ ll_entry_count(struct efi_unit_test,
+ efi_unit_test));
+
+ /* Execute boottime tests */
+ efi_st_do_tests(testname, EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ EFI_ST_SETUP | EFI_ST_EXECUTE | EFI_ST_TEARDOWN,
+ &failures);
+
/* Execute mixed tests */
- for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
- test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
- if (test->phase == EFI_SETUP_BEFORE_BOOTTIME_EXIT)
- setup(test, &failures);
- }
+ efi_st_do_tests(testname, EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ EFI_ST_SETUP, &failures);
efi_st_exit_boot_services();
- for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
- test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
- if (test->phase == EFI_SETUP_BEFORE_BOOTTIME_EXIT) {
- execute(test, &failures);
- teardown(test, &failures);
- }
- }
+ efi_st_do_tests(testname, EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ EFI_ST_EXECUTE | EFI_ST_TEARDOWN, &failures);
/* Execute runtime tests */
- for (test = ll_entry_start(struct efi_unit_test, efi_unit_test);
- test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) {
- if (test->phase == EFI_SETUP_AFTER_BOOTTIME_EXIT) {
- setup(test, &failures);
- execute(test, &failures);
- teardown(test, &failures);
- }
- }
+ efi_st_do_tests(testname, EFI_SETUP_AFTER_BOOTTIME_EXIT,
+ EFI_ST_SETUP | EFI_ST_EXECUTE | EFI_ST_TEARDOWN,
+ &failures);
/* Give feedback */
efi_st_printf("\nSummary: %u failures\n\n", failures);
const char *c;
u16 *pos = buf;
const char *s;
+ const u16 *u;
va_start(args, fmt);
case 'p':
++c;
switch (*c) {
+ /* MAC address */
case 'm':
mac(va_arg(args, void*), &pos);
break;
+
+ /* u16 string */
+ case 's':
+ u = va_arg(args, u16*);
+ /* Ensure string fits into buffer */
+ for (; *u && pos < buf + 120; ++u)
+ *pos++ = *u;
+ break;
default:
--c;
pointer(va_arg(args, void*), &pos);
--- /dev/null
+/*
+ * efi_selftest_devicepath
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This unit test checks the following protocol services:
+ * DevicePathToText
+ */
+
+#include <efi_selftest.h>
+
+static struct efi_boot_services *boottime;
+
+static efi_handle_t handle1;
+static efi_handle_t handle2;
+static efi_handle_t handle3;
+
+struct interface {
+ void (EFIAPI * inc)(void);
+} interface;
+
+static efi_guid_t guid_device_path = DEVICE_PATH_GUID;
+
+static efi_guid_t guid_device_path_to_text_protocol =
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
+
+static efi_guid_t guid_protocol =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xbb, 0x7d);
+
+static efi_guid_t guid_vendor1 =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xbb, 0xb1);
+
+static efi_guid_t guid_vendor2 =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xbb, 0xa2);
+
+static efi_guid_t guid_vendor3 =
+ EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d,
+ 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xbb, 0xc3);
+
+static u8 *dp1;
+static u8 *dp2;
+static u8 *dp3;
+
+struct efi_device_path_to_text_protocol *device_path_to_text;
+
+/*
+ * Setup unit test.
+ *
+ * Create three handles. Install a new protocol on two of them and
+ * provice device paths.
+ *
+ * handle1
+ * guid interface
+ * handle2
+ * guid interface
+ * handle3
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ struct efi_device_path_vendor vendor_node;
+ struct efi_device_path end_node;
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->locate_protocol(&guid_device_path_to_text_protocol,
+ NULL, (void **)&device_path_to_text);
+ if (ret != EFI_SUCCESS) {
+ device_path_to_text = NULL;
+ efi_st_error(
+ "Device path to text protocol is not available.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA,
+ sizeof(struct efi_device_path_vendor) +
+ sizeof(struct efi_device_path),
+ (void **)&dp1);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, 2 *
+ sizeof(struct efi_device_path_vendor) +
+ sizeof(struct efi_device_path),
+ (void **)&dp2);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, 3 *
+ sizeof(struct efi_device_path_vendor) +
+ sizeof(struct efi_device_path),
+ (void **)&dp3);
+ if (ret != EFI_SUCCESS)
+ goto out_of_memory;
+
+ vendor_node.dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+ vendor_node.dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+ vendor_node.dp.length = sizeof(struct efi_device_path_vendor);
+
+ boottime->copy_mem(&vendor_node.guid, &guid_vendor1,
+ sizeof(efi_guid_t));
+ boottime->copy_mem(dp1, &vendor_node,
+ sizeof(struct efi_device_path_vendor));
+ boottime->copy_mem(dp2, &vendor_node,
+ sizeof(struct efi_device_path_vendor));
+ boottime->copy_mem(dp3, &vendor_node,
+ sizeof(struct efi_device_path_vendor));
+
+ boottime->copy_mem(&vendor_node.guid, &guid_vendor2,
+ sizeof(efi_guid_t));
+ boottime->copy_mem(dp2 + sizeof(struct efi_device_path_vendor),
+ &vendor_node, sizeof(struct efi_device_path_vendor));
+ boottime->copy_mem(dp3 + sizeof(struct efi_device_path_vendor),
+ &vendor_node, sizeof(struct efi_device_path_vendor));
+
+ boottime->copy_mem(&vendor_node.guid, &guid_vendor3,
+ sizeof(efi_guid_t));
+ boottime->copy_mem(dp3 + 2 * sizeof(struct efi_device_path_vendor),
+ &vendor_node, sizeof(struct efi_device_path_vendor));
+
+ end_node.type = DEVICE_PATH_TYPE_END;
+ end_node.sub_type = DEVICE_PATH_SUB_TYPE_END;
+ end_node.length = sizeof(struct efi_device_path);
+ boottime->copy_mem(dp1 + sizeof(struct efi_device_path_vendor),
+ &end_node, sizeof(struct efi_device_path));
+ boottime->copy_mem(dp2 + 2 * sizeof(struct efi_device_path_vendor),
+ &end_node, sizeof(struct efi_device_path));
+ boottime->copy_mem(dp3 + 3 * sizeof(struct efi_device_path_vendor),
+ &end_node, sizeof(struct efi_device_path));
+
+ ret = boottime->install_protocol_interface(&handle1,
+ &guid_device_path,
+ EFI_NATIVE_INTERFACE,
+ dp1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_protocol_interface(&handle1,
+ &guid_protocol,
+ EFI_NATIVE_INTERFACE,
+ &interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_protocol_interface(&handle2,
+ &guid_device_path,
+ EFI_NATIVE_INTERFACE,
+ dp2);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_protocol_interface(&handle2,
+ &guid_protocol,
+ EFI_NATIVE_INTERFACE,
+ &interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_protocol_interface(&handle3,
+ &guid_device_path,
+ EFI_NATIVE_INTERFACE,
+ dp3);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+
+out_of_memory:
+ efi_st_error("Out of memory\n");
+ return EFI_ST_FAILURE;
+}
+
+/*
+ * Tear down unit test.
+ *
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ ret = boottime->uninstall_protocol_interface(&handle1,
+ &guid_device_path,
+ dp1);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ ret = boottime->uninstall_protocol_interface(&handle1,
+ &guid_protocol,
+ &interface);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ ret = boottime->uninstall_protocol_interface(&handle2,
+ &guid_device_path,
+ dp2);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ ret = boottime->uninstall_protocol_interface(&handle2,
+ &guid_protocol,
+ &interface);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ ret = boottime->uninstall_protocol_interface(&handle3,
+ &guid_device_path,
+ dp3);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ if (dp1) {
+ ret = boottime->free_pool(dp1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (dp2) {
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (dp3) {
+ ret = boottime->free_pool(dp3);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ */
+static int execute(void)
+{
+ struct efi_device_path *remaining_dp;
+ void *handle;
+ /*
+ * This device path node ends with the letter 't' of 'u-boot'.
+ * The following '.bin' does not belong to the node but is
+ * helps to test the correct truncation.
+ */
+ struct {
+ struct efi_device_path dp;
+ u16 text[12];
+ } __packed dp_node = {
+ { DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ sizeof(struct efi_device_path) + 12},
+ L"u-boot.bin",
+ };
+ u16 *string;
+ efi_status_t ret;
+ efi_uintn_t i, no_handles;
+ efi_handle_t *handles;
+ struct efi_device_path *dp;
+
+ /* Display all available device paths */
+ ret = boottime->locate_handle_buffer(BY_PROTOCOL,
+ &guid_device_path,
+ NULL, &no_handles, &handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot retrieve device path protocols.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ efi_st_printf("Installed device path protocols:\n");
+ for (i = 0; i < no_handles; ++i) {
+ ret = boottime->open_protocol(handles[i], &guid_device_path,
+ (void **)&dp, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Cannot open device path protocol.\n");
+ return EFI_ST_FAILURE;
+ }
+ string = device_path_to_text->convert_device_path_to_text(
+ dp, true, false);
+ if (!string) {
+ efi_st_error("ConvertDevicePathToText failed\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("%ps\n", string);
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->close_protocol(handles[i], &guid_device_path,
+ NULL, NULL);
+ if (ret != EFI_SUCCESS)
+ efi_st_todo("Cannot close device path protocol.\n");
+ }
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("\n");
+
+ /* Test ConvertDevicePathToText */
+ string = device_path_to_text->convert_device_path_to_text(
+ (struct efi_device_path *)dp2, true, false);
+ if (!string) {
+ efi_st_error("ConvertDevicePathToText failed\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("dp2: %ps\n", string);
+ if (efi_st_strcmp_16_8(
+ string,
+ "/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbb1)/VenHw(dbca4c98-6cb0-694d-0872-819c650cbba2)")
+ ) {
+ efi_st_error("Incorrect text from ConvertDevicePathToText\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Test ConvertDeviceNodeToText */
+ string = device_path_to_text->convert_device_node_to_text(
+ (struct efi_device_path *)&dp_node, true, false);
+ if (!string) {
+ efi_st_error("ConvertDeviceNodeToText failed\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("dp_node: %ps\n", string);
+ ret = boottime->free_pool(string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_strcmp_16_8(string, "u-boot")) {
+ efi_st_error(
+ "Incorrect conversion by ConvertDeviceNodeToText\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Test LocateDevicePath */
+ remaining_dp = (struct efi_device_path *)dp3;
+ ret = boottime->locate_device_path(&guid_protocol, &remaining_dp,
+ &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateDevicePath failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (handle != handle2) {
+ efi_st_error("LocateDevicePath returned wrong handle\n");
+ return EFI_ST_FAILURE;
+ }
+ string = device_path_to_text->convert_device_path_to_text(remaining_dp,
+ true, false);
+ if (!string) {
+ efi_st_error("ConvertDevicePathToText failed\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("remaining device path: %ps\n", string);
+ if (efi_st_strcmp_16_8(string,
+ "/VenHw(dbca4c98-6cb0-694d-0872-819c650cbbc3)")
+ ) {
+ efi_st_error("LocateDevicePath: wrong remaining device path\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(devicepath) = {
+ .name = "device path",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
*/
static int execute(void)
{
- size_t index;
+ efi_uintn_t index;
efi_status_t ret;
/* Set 10 ms timer */
--- /dev/null
+/*
+ * efi_selftest_gop
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Test the graphical output protocol.
+ */
+
+#include <efi_selftest.h>
+
+static struct efi_boot_services *boottime;
+static efi_guid_t efi_gop_guid = EFI_GOP_GUID;
+static struct efi_gop *gop;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->locate_protocol(&efi_gop_guid, NULL, (void **)&gop);
+ if (ret != EFI_SUCCESS) {
+ gop = NULL;
+ efi_st_printf("Graphical output protocol is not available.\n");
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ u32 i, max_mode;
+ efi_uintn_t size;
+ struct efi_gop_mode_info *info;
+
+ if (!gop)
+ return EFI_ST_SUCCESS;
+
+ if (!gop->mode) {
+ efi_st_error("EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE missing\n");
+ return EFI_ST_FAILURE;
+ }
+ max_mode = gop->mode->max_mode;
+ if (!max_mode) {
+ efi_st_error("No graphical mode available\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("Number of available modes: %u\n", max_mode);
+
+ for (i = 0; i < max_mode; ++i) {
+ ret = gop->query_mode(gop, i, &size, &info);
+ if (ret != EFI_SUCCESS) {
+ efi_st_printf("Could not query mode %u\n", i);
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("Mode %u: %u x %u\n",
+ i, info->width, info->height);
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(gop) = {
+ .name = "graphical output",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
--- /dev/null
+/*
+ * efi_selftest_manageprotocols
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This unit test checks the following protocol services:
+ * InstallProtocolInterface, UninstallProtocolInterface,
+ * InstallMultipleProtocolsInterfaces, UninstallMultipleProtocolsInterfaces,
+ * HandleProtocol, ProtocolsPerHandle,
+ * LocateHandle, LocateHandleBuffer.
+ */
+
+#include <efi_selftest.h>
+
+/*
+ * The test currently does not actually call the interface function.
+ * So this is just a dummy structure.
+ */
+struct interface {
+ void (EFIAPI * inc)(void);
+};
+
+static struct efi_boot_services *boottime;
+static efi_guid_t guid1 =
+ EFI_GUID(0x2e7ca819, 0x21d3, 0x0a3a,
+ 0xf7, 0x91, 0x82, 0x1f, 0x7a, 0x83, 0x67, 0xaf);
+static efi_guid_t guid2 =
+ EFI_GUID(0xf909f2bb, 0x90a8, 0x0d77,
+ 0x94, 0x0c, 0x3e, 0xa8, 0xea, 0x38, 0xd6, 0x6f);
+static efi_guid_t guid3 =
+ EFI_GUID(0x06d641a3, 0xf4e7, 0xe0c9,
+ 0xe7, 0x8d, 0x41, 0x2d, 0x72, 0xa6, 0xb1, 0x24);
+static efi_handle_t handle1;
+static efi_handle_t handle2;
+static struct interface interface1;
+static struct interface interface2;
+static struct interface interface3;
+static struct interface interface4;
+
+/*
+ * Find a handle in an array.
+ *
+ * @handle: handle to find
+ * @count: number of entries in the array
+ * @buffer: array to search
+ */
+efi_status_t find_in_buffer(efi_handle_t handle, size_t count,
+ efi_handle_t *buffer)
+{
+ size_t i;
+
+ for (i = 0; i < count; ++i) {
+ if (buffer[i] == handle)
+ return EFI_SUCCESS;
+ }
+ return EFI_NOT_FOUND;
+}
+
+/*
+ * Setup unit test.
+ *
+ * Create two handles and install two out of three protocol interfaces on each
+ * of them:
+ *
+ * handle1
+ * guid1 interface1
+ * guid3 interface3
+ * handle2
+ * guid1 interface4
+ * guid2 interface2
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ boottime = systable->boottime;
+
+ ret = boottime->install_protocol_interface(&handle1, &guid3,
+ EFI_NATIVE_INTERFACE,
+ &interface3);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!handle1) {
+ efi_st_error("InstallProtocolInterface failed to create handle\n");
+ return EFI_ST_FAILURE;
+ }
+ handle = handle1;
+ ret = boottime->install_protocol_interface(&handle1, &guid1,
+ EFI_NATIVE_INTERFACE,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (handle != handle1) {
+ efi_st_error("InstallProtocolInterface failed to use handle\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_multiple_protocol_interfaces(&handle2,
+ &guid1, &interface4, &guid2, &interface2, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallMultipleProtocolInterfaces failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!handle2 || handle1 == handle2) {
+ efi_st_error("InstallMultipleProtocolInterfaces failed to create handle\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ */
+static int teardown(void)
+{
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ */
+static int execute(void)
+{
+ struct interface *interface;
+ efi_status_t ret;
+ efi_handle_t *buffer;
+ size_t buffer_size;
+ efi_uintn_t count = 0;
+ efi_guid_t **prot_buffer;
+ efi_uintn_t prot_count;
+
+ /*
+ * Test HandleProtocol
+ */
+ ret = boottime->handle_protocol(handle1, &guid3, (void **)&interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("HandleProtocol failed to retrieve interface\n");
+ return EFI_ST_FAILURE;
+ }
+ if (interface != &interface3) {
+ efi_st_error("HandleProtocol returned wrong interface\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->handle_protocol(handle1, &guid2, (void **)&interface);
+ if (ret == EFI_SUCCESS) {
+ efi_st_error("HandleProtocol returned not installed interface\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Test LocateHandleBuffer with AllHandles
+ */
+ ret = boottime->locate_handle_buffer(ALL_HANDLES, NULL, NULL,
+ &count, &buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer with AllHandles failed\n");
+ return EFI_ST_FAILURE;
+ }
+ buffer_size = count;
+ ret = find_in_buffer(handle1, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed to locate new handle\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = find_in_buffer(handle2, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed to locate new handle\n");
+ return EFI_ST_FAILURE;
+ }
+ boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+
+ /*
+ * Test error handling in UninstallMultipleProtocols
+ *
+ * Try to uninstall more protocols than there are installed.
+ */
+ ret = boottime->uninstall_multiple_protocol_interfaces(
+ handle2,
+ &guid1, &interface4,
+ &guid2, &interface2,
+ &guid3, &interface3,
+ NULL);
+ if (ret == EFI_SUCCESS) {
+ efi_st_todo("UninstallMultipleProtocolInterfaces did not catch error\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Test LocateHandleBuffer with ByProtocol
+ */
+ count = buffer_size;
+ ret = boottime->locate_handle_buffer(BY_PROTOCOL, &guid1, NULL,
+ &count, &buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed to locate new handles\n");
+ return EFI_ST_FAILURE;
+ }
+ if (count != 2) {
+ efi_st_error("LocateHandleBuffer failed to locate new handles\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = find_in_buffer(handle1, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed to locate new handle\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = find_in_buffer(handle2, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed to locate new handle\n");
+ return EFI_ST_FAILURE;
+ }
+ boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+
+ /*
+ * Test LocateHandle with ByProtocol
+ */
+ count = buffer_size * sizeof(efi_handle_t);
+ ret = boottime->locate_handle(BY_PROTOCOL, &guid1, NULL,
+ &count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandle with ByProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (count / sizeof(efi_handle_t) != 2) {
+ efi_st_error("LocateHandle failed to locate new handles\n");
+ return EFI_ST_FAILURE;
+ }
+ buffer_size = count;
+ ret = find_in_buffer(handle1, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandle failed to locate new handles\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = find_in_buffer(handle2, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandle failed to locate new handles\n");
+ return EFI_ST_FAILURE;
+ }
+ boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+
+ /*
+ * Test LocateProtocol
+ */
+ ret = boottime->locate_protocol(&guid1, NULL, (void **)&interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (interface != &interface1 && interface != &interface4) {
+ efi_st_error("LocateProtocol failed to locate protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Test UninstallMultipleProtocols
+ */
+ ret = boottime->uninstall_multiple_protocol_interfaces(
+ handle2,
+ &guid1, &interface4,
+ &guid2, &interface2,
+ NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_todo("UninstallMultipleProtocolInterfaces failed\n");
+ /* This test is known to fail due to missing implementation */
+ }
+ /*
+ * Check that the protocols are really uninstalled.
+ */
+ count = buffer_size;
+ ret = boottime->locate_handle_buffer(BY_PROTOCOL, &guid1, NULL,
+ &count, &buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("LocateHandleBuffer failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (count != 1) {
+ efi_st_todo("UninstallMultipleProtocolInterfaces failed to uninstall protocols\n");
+ /* This test is known to fail due to missing implementation */
+ }
+ ret = find_in_buffer(handle1, count, buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to locate new handle\n");
+ return EFI_ST_FAILURE;
+ }
+ boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+
+ /*
+ * Test ProtocolsPerHandle
+ */
+ ret = boottime->protocols_per_handle(handle1,
+ &prot_buffer, &prot_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get protocols per handle\n");
+ return EFI_ST_FAILURE;
+ }
+ if (prot_count != 2) {
+ efi_st_error("Failed to get protocols per handle\n");
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(prot_buffer[0], &guid1, 16) &&
+ efi_st_memcmp(prot_buffer[1], &guid1, 16)) {
+ efi_st_error("Failed to get protocols per handle\n");
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(prot_buffer[0], &guid3, 16) &&
+ efi_st_memcmp(prot_buffer[1], &guid3, 16)) {
+ efi_st_error("Failed to get protocols per handle\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Uninstall remaining protocols
+ */
+ ret = boottime->uninstall_protocol_interface(handle1, &guid1,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ /* This test is known to fail due to missing implementation */
+ }
+ ret = boottime->handle_protocol(handle1, &guid1, (void **)&interface);
+ if (ret == EFI_SUCCESS) {
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ /* This test is known to fail due to missing implementation */
+ }
+ ret = boottime->uninstall_protocol_interface(handle1, &guid3,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_todo("UninstallProtocolInterface failed\n");
+ /* This test is known to fail due to missing implementation */
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(protserv) = {
+ .name = "manage protocols",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
{
efi_status_t ret;
struct efi_event *events[2];
- size_t index;
+ efi_uintn_t index;
union {
struct dhcp p;
u8 b[PKTSIZE];
--- /dev/null
+/*
+ * efi_selftest_textoutput
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Test the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.
+ *
+ * The following services are tested:
+ * OutputString, TestString, SetAttribute.
+ */
+
+#include <efi_selftest.h>
+
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ size_t foreground;
+ size_t background;
+ size_t attrib;
+ efi_status_t ret;
+
+ /* SetAttribute */
+ efi_st_printf("\nColor palette\n");
+ for (foreground = 0; foreground < 0x10; ++foreground) {
+ for (background = 0; background < 0x80; background += 0x10) {
+ attrib = foreground | background;
+ con_out->set_attribute(con_out, attrib);
+ efi_st_printf("%p", (void *)attrib);
+ }
+ con_out->set_attribute(con_out, 0);
+ efi_st_printf("\n");
+ }
+ /* TestString */
+ ret = con_out->test_string(con_out,
+ L" !\"#$%&'()*+,-./0-9:;<=>?@A-Z[\\]^_`a-z{|}~\n");
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("TestString failed for ANSI characters\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(textoutput) = {
+ .name = "text output",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .execute = execute,
+};
*/
static int execute(void)
{
- size_t index;
+ efi_uintn_t index;
efi_status_t ret;
- UINTN old_tpl;
+ efi_uintn_t old_tpl;
/* Set 10 ms timer */
notification_count = 0;
++pos1;
++pos2;
}
- return EFI_ST_SUCCESS;
+ return 0;
+}
+
+int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2)
+{
+ for (; *buf1 || *buf2; ++buf1, ++buf2) {
+ if (*buf1 != *buf2)
+ return *buf1 - *buf2;
+ }
+ return 0;
}
--- /dev/null
+/*
+ * efi_selftest_watchdog
+ *
+ * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The 'watchdog timer' unit test checks that the watchdog timer
+ * will not cause a system restart during the timeout period after
+ * a timer reset.
+ *
+ * The 'watchdog reboot' unit test checks that the watchdog timer
+ * actually reboots the system after a timeout. The test is only
+ * executed on explicit request. Use the following commands:
+ *
+ * setenv efi_selftest watchdog reboot
+ * bootefi selftest
+ */
+
+#include <efi_selftest.h>
+
+/*
+ * This is the communication structure for the notification function.
+ */
+struct notify_context {
+ /* Status code returned when resetting watchdog */
+ efi_status_t status;
+ /* Number of invocations of the notification function */
+ unsigned int timer_ticks;
+};
+
+static struct efi_event *event_notify;
+static struct efi_event *event_wait;
+static struct efi_boot_services *boottime;
+static struct notify_context notification_context;
+static bool watchdog_reset;
+
+/*
+ * Notification function, increments the notfication count if parameter
+ * context is provided.
+ *
+ * @event notified event
+ * @context pointer to the timeout
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ struct notify_context *notify_context = context;
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (!notify_context)
+ return;
+
+ /* Reset watchdog timer to one second */
+ ret = boottime->set_watchdog_timer(1, 0, 0, NULL);
+ if (ret != EFI_SUCCESS)
+ notify_context->status = ret;
+ /* Count number of calls */
+ notify_context->timer_ticks++;
+}
+
+/*
+ * Setup unit test.
+ *
+ * Create two timer events.
+ * One with EVT_NOTIFY_SIGNAL, the other with EVT_NOTIFY_WAIT.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ notification_context.status = EFI_SUCCESS;
+ notification_context.timer_ticks = 0;
+ ret = boottime->create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK, notify,
+ (void *)¬ification_context,
+ &event_notify);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->create_event(EVT_TIMER | EVT_NOTIFY_WAIT,
+ TPL_CALLBACK, notify, NULL, &event_wait);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute the test resetting the watchdog in a timely manner. No reboot occurs.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup_timer(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ watchdog_reset = true;
+ return setup(handle, systable);
+}
+
+/*
+ * Execute the test without resetting the watchdog. A system reboot occurs.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup_reboot(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ watchdog_reset = false;
+ return setup(handle, systable);
+}
+
+/*
+ * Tear down unit test.
+ *
+ * Close the events created in setup.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ /* Set the watchdog timer to the five minute default value */
+ ret = boottime->set_watchdog_timer(300, 0, 0, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Setting watchdog timer failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (event_notify) {
+ ret = boottime->close_event(event_notify);
+ event_notify = NULL;
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not close event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (event_wait) {
+ ret = boottime->close_event(event_wait);
+ event_wait = NULL;
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not close event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Run a 600 ms periodic timer that resets the watchdog to one second
+ * on every timer tick.
+ *
+ * Run a 1350 ms single shot timer and check that the 600ms timer has
+ * been called 2 times.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ size_t index;
+ efi_status_t ret;
+
+ /* Set the watchdog timeout to one second */
+ ret = boottime->set_watchdog_timer(1, 0, 0, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Setting watchdog timer failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (watchdog_reset) {
+ /* Set 600 ms timer */
+ ret = boottime->set_timer(event_notify, EFI_TIMER_PERIODIC,
+ 6000000);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not set timer\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ /* Set 1350 ms timer */
+ ret = boottime->set_timer(event_wait, EFI_TIMER_RELATIVE, 13500000);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not set timer\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->wait_for_event(1, &event_wait, &index);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Could not wait for event\n");
+ return EFI_ST_FAILURE;
+ }
+ if (notification_context.status != EFI_SUCCESS) {
+ efi_st_error("Setting watchdog timer failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (notification_context.timer_ticks != 2) {
+ efi_st_error("The timer was called %u times, expected 2.\n",
+ notification_context.timer_ticks);
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(watchdog1) = {
+ .name = "watchdog timer",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup_timer,
+ .execute = execute,
+ .teardown = teardown,
+};
+
+EFI_UNIT_TEST(watchdog2) = {
+ .name = "watchdog reboot",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup_reboot,
+ .execute = execute,
+ .teardown = teardown,
+ .on_request = true,
+};
COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+ COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
+ COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
#if defined(CONFIG_NR_DRAM_BANKS)
int fdtdec_setup_memory_banksize(void)
{
- int bank, ret, mem;
+ int bank, ret, mem, reg = 0;
struct fdt_resource res;
- mem = fdt_path_offset(gd->fdt_blob, "/memory");
+ mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type",
+ "memory", 7);
if (mem < 0) {
debug("%s: Missing /memory node\n", __func__);
return -EINVAL;
}
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
- if (ret == -FDT_ERR_NOTFOUND)
- break;
- if (ret != 0)
+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
+ if (ret == -FDT_ERR_NOTFOUND) {
+ reg = 0;
+ mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
+ "device_type",
+ "memory", 7);
+ if (mem == -FDT_ERR_NOTFOUND)
+ break;
+
+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
+ if (ret == -FDT_ERR_NOTFOUND)
+ break;
+ }
+ if (ret != 0) {
return -EINVAL;
+ }
gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
gd->bd->bi_dram[bank].size =
# endif
# ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
+# ifdef CONFIG_SPL_BUILD
+ gd->fdt_blob = __dtb_dt_spl_begin;
+# else
gd->fdt_blob = __dtb_dt_begin;
+# endif
# elif defined CONFIG_OF_SEPARATE
# ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
# Use upstream code.
obj-y += \
fdt.o \
+ fdt_wip.o \
fdt_strerror.o \
fdt_sw.o \
fdt_empty_tree.o \
# TODO: split out the local modifiction.
obj-y += \
fdt_ro.o \
- fdt_rw.o \
- fdt_wip.o \
+ fdt_rw.o
# U-Boot own file
obj-y += fdt_region.o
#include "libfdt_internal.h"
+#define FDT_MAX_DEPTH 32
+
+static int str_in_list(const char *str, char * const list[], int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ if (!strcmp(list[i], str))
+ return 1;
+
+ return 0;
+}
+
+int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
+ char * const exc_prop[], int exc_prop_count,
+ struct fdt_region region[], int max_regions,
+ char *path, int path_len, int add_string_tab)
+{
+ int stack[FDT_MAX_DEPTH] = { 0 };
+ char *end;
+ int nextoffset = 0;
+ uint32_t tag;
+ int count = 0;
+ int start = -1;
+ int depth = -1;
+ int want = 0;
+ int base = fdt_off_dt_struct(fdt);
+
+ end = path;
+ *end = '\0';
+ do {
+ const struct fdt_property *prop;
+ const char *name;
+ const char *str;
+ int include = 0;
+ int stop_at = 0;
+ int offset;
+ int len;
+
+ offset = nextoffset;
+ tag = fdt_next_tag(fdt, offset, &nextoffset);
+ stop_at = nextoffset;
+
+ switch (tag) {
+ case FDT_PROP:
+ include = want >= 2;
+ stop_at = offset;
+ prop = fdt_get_property_by_offset(fdt, offset, NULL);
+ str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+ if (str_in_list(str, exc_prop, exc_prop_count))
+ include = 0;
+ break;
+
+ case FDT_NOP:
+ include = want >= 2;
+ stop_at = offset;
+ break;
+
+ case FDT_BEGIN_NODE:
+ depth++;
+ if (depth == FDT_MAX_DEPTH)
+ return -FDT_ERR_BADSTRUCTURE;
+ name = fdt_get_name(fdt, offset, &len);
+ if (end - path + 2 + len >= path_len)
+ return -FDT_ERR_NOSPACE;
+ if (end != path + 1)
+ *end++ = '/';
+ strcpy(end, name);
+ end += len;
+ stack[depth] = want;
+ if (want == 1)
+ stop_at = offset;
+ if (str_in_list(path, inc, inc_count))
+ want = 2;
+ else if (want)
+ want--;
+ else
+ stop_at = offset;
+ include = want;
+ break;
+
+ case FDT_END_NODE:
+ include = want;
+ want = stack[depth--];
+ while (end > path && *--end != '/')
+ ;
+ *end = '\0';
+ break;
+
+ case FDT_END:
+ include = 1;
+ break;
+ }
+
+ if (include && start == -1) {
+ /* Should we merge with previous? */
+ if (count && count <= max_regions &&
+ offset == region[count - 1].offset +
+ region[count - 1].size - base)
+ start = region[--count].offset - base;
+ else
+ start = offset;
+ }
+
+ if (!include && start != -1) {
+ if (count < max_regions) {
+ region[count].offset = base + start;
+ region[count].size = stop_at - start;
+ }
+ count++;
+ start = -1;
+ }
+ } while (tag != FDT_END);
+
+ if (nextoffset != fdt_size_dt_struct(fdt))
+ return -FDT_ERR_BADLAYOUT;
+
+ /* Add a region for the END tag and the string table */
+ if (count < max_regions) {
+ region[count].offset = base + start;
+ region[count].size = nextoffset - start;
+ if (add_string_tab)
+ region[count].size += fdt_size_dt_strings(fdt);
+ }
+ count++;
+
+ return count;
+}
+
/**
* fdt_add_region() - Add a new region to our list
* @info: State information
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
- */
-#include <libfdt_env.h>
-
-#ifndef USE_HOSTCC
-#include <fdt.h>
-#include <libfdt.h>
-#else
-#include "fdt_host.h"
-#endif
-
-#include "libfdt_internal.h"
-
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
- const char *name, int namelen,
- uint32_t idx, const void *val,
- int len)
-{
- void *propval;
- int proplen;
-
- propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen,
- &proplen);
- if (!propval)
- return proplen;
-
- if (proplen < (len + idx))
- return -FDT_ERR_NOSPACE;
-
- memcpy((char *)propval + idx, val, len);
- return 0;
-}
-
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
- const void *val, int len)
-{
- const void *propval;
- int proplen;
-
- propval = fdt_getprop(fdt, nodeoffset, name, &proplen);
- if (!propval)
- return proplen;
-
- if (proplen != len)
- return -FDT_ERR_NOSPACE;
-
- return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
- strlen(name), 0,
- val, len);
-}
-
-static void _fdt_nop_region(void *start, int len)
-{
- fdt32_t *p;
-
- for (p = start; (char *)p < ((char *)start + len); p++)
- *p = cpu_to_fdt32(FDT_NOP);
-}
-
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
-{
- struct fdt_property *prop;
- int len;
-
- prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
- if (!prop)
- return len;
-
- _fdt_nop_region(prop, len + sizeof(*prop));
-
- return 0;
-}
-
-int _fdt_node_end_offset(void *fdt, int offset)
-{
- int depth = 0;
-
- while ((offset >= 0) && (depth >= 0))
- offset = fdt_next_node(fdt, offset, &depth);
-
- return offset;
-}
-
-int fdt_nop_node(void *fdt, int nodeoffset)
-{
- int endoffset;
-
- endoffset = _fdt_node_end_offset(fdt, nodeoffset);
- if (endoffset < 0)
- return endoffset;
-
- _fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0),
- endoffset - nodeoffset);
- return 0;
-}
-
-#define FDT_MAX_DEPTH 32
-
-static int str_in_list(const char *str, char * const list[], int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- if (!strcmp(list[i], str))
- return 1;
-
- return 0;
-}
-
-int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
- char * const exc_prop[], int exc_prop_count,
- struct fdt_region region[], int max_regions,
- char *path, int path_len, int add_string_tab)
-{
- int stack[FDT_MAX_DEPTH] = { 0 };
- char *end;
- int nextoffset = 0;
- uint32_t tag;
- int count = 0;
- int start = -1;
- int depth = -1;
- int want = 0;
- int base = fdt_off_dt_struct(fdt);
-
- end = path;
- *end = '\0';
- do {
- const struct fdt_property *prop;
- const char *name;
- const char *str;
- int include = 0;
- int stop_at = 0;
- int offset;
- int len;
-
- offset = nextoffset;
- tag = fdt_next_tag(fdt, offset, &nextoffset);
- stop_at = nextoffset;
-
- switch (tag) {
- case FDT_PROP:
- include = want >= 2;
- stop_at = offset;
- prop = fdt_get_property_by_offset(fdt, offset, NULL);
- str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
- if (str_in_list(str, exc_prop, exc_prop_count))
- include = 0;
- break;
-
- case FDT_NOP:
- include = want >= 2;
- stop_at = offset;
- break;
-
- case FDT_BEGIN_NODE:
- depth++;
- if (depth == FDT_MAX_DEPTH)
- return -FDT_ERR_BADSTRUCTURE;
- name = fdt_get_name(fdt, offset, &len);
- if (end - path + 2 + len >= path_len)
- return -FDT_ERR_NOSPACE;
- if (end != path + 1)
- *end++ = '/';
- strcpy(end, name);
- end += len;
- stack[depth] = want;
- if (want == 1)
- stop_at = offset;
- if (str_in_list(path, inc, inc_count))
- want = 2;
- else if (want)
- want--;
- else
- stop_at = offset;
- include = want;
- break;
-
- case FDT_END_NODE:
- include = want;
- want = stack[depth--];
- while (end > path && *--end != '/')
- ;
- *end = '\0';
- break;
-
- case FDT_END:
- include = 1;
- break;
- }
-
- if (include && start == -1) {
- /* Should we merge with previous? */
- if (count && count <= max_regions &&
- offset == region[count - 1].offset +
- region[count - 1].size - base)
- start = region[--count].offset - base;
- else
- start = offset;
- }
-
- if (!include && start != -1) {
- if (count < max_regions) {
- region[count].offset = base + start;
- region[count].size = stop_at - start;
- }
- count++;
- start = -1;
- }
- } while (tag != FDT_END);
-
- if (nextoffset != fdt_size_dt_struct(fdt))
- return -FDT_ERR_BADLAYOUT;
-
- /* Add a region for the END tag and the string table */
- if (count < max_regions) {
- region[count].offset = base + start;
- region[count].size = nextoffset - start;
- if (add_string_tab)
- region[count].size += fdt_size_dt_strings(fdt);
- }
- count++;
-
- return count;
-}
+#include <linux/libfdt_env.h>
+#include "../../scripts/dtc/libfdt/fdt_wip.c"
#include <asm/gpio.h>
#endif
-#ifdef CONFIG_LOGBUFFER
-#include <logbuff.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define POST_MAX_NUMBER 32
vsprintf(printbuffer, format, args);
va_end(args);
-#ifdef CONFIG_LOGBUFFER
- /* Send to the logbuffer */
- logbuff_log(printbuffer);
-#else
/* Send to the stdout file */
puts(printbuffer);
-#endif
return 0;
}
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
- *
- * Be sure to mark tests to be run before relocation as such with the
- * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
- * logbuffer support is enabled.
*/
#include <common.h>
ld_flags = $(LDFLAGS) $(ldflags-y)
# Try these files in order to find the U-Boot-specific .dtsi include file
-u_boot_dtsi_options = $(wildcard $(dir $<)$(basename $(notdir $<))-u-boot.dtsi) \
+u_boot_dtsi_options = $(strip $(wildcard $(dir $<)$(basename $(notdir $<))-u-boot.dtsi) \
$(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \
$(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \
$(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \
- $(wildcard $(dir $<)u-boot.dtsi)
+ $(wildcard $(dir $<)u-boot.dtsi))
+
+u_boot_dtsi_options_raw = $(warning Automatic .dtsi inclusion: options: \
+ $(dir $<)$(basename $(notdir $<))-u-boot.dtsi \
+ $(dir $<)$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi \
+ $(dir $<)$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi \
+ $(dir $<)$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi \
+ $(dir $<)u-boot.dtsi ... \
+ found: $(if $(u_boot_dtsi_options),"$(u_boot_dtsi_options)",nothing!))
# Uncomment for debugging
-# $(warning u_boot_dtsi_options: $(u_boot_dtsi_options))
+# This shows all the files that were considered and the one that we chose.
+# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
# We use the first match
-u_boot_dtsi = $(notdir $(firstword $(u_boot_dtsi_options)))
+u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
+ $(notdir $(firstword $(u_boot_dtsi_options))))
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
endif
ifdef CONFIG_ARCH_ZYNQMP
-MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \
+ -n $(srctree)/$(CONFIG_PMUFW_INIT_FILE)
endif
spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
@bss_size_str=$(shell $(NM) $< | awk 'BEGIN {size = 0} /__bss_size/ {size = $$1} END {print "ibase=16; " toupper(size)}' | bc); \
dd if=/dev/zero of=$@ bs=1 count=$${bss_size_str} 2>/dev/null;
-# Pass the original device tree file through fdtgrep twice. The first pass
-# removes any unwanted nodes (i.e. those which don't have the
-# 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second
-# pass removes various unused properties from the remaining nodes.
-# The output is typically a much smaller device tree file.
-ifeq ($(CONFIG_TPL_BUILD),y)
-fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl
-else
-fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl
-endif
-quiet_cmd_fdtgrep = FDTGREP $@
- cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \
- -n /chosen -n /config -O dtb | \
- $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
- $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS)))
-
-$(obj)/$(SPL_BIN).dtb: dts/dt.dtb $(objtree)/tools/fdtgrep FORCE
- $(call if_changed,fdtgrep)
+$(obj)/$(SPL_BIN).dtb: dts/dt-spl.dtb FORCE
+ $(call if_changed,copy)
pythonpath = PYTHONPATH=scripts/dtc/pylibfdt
ifndef CONFIG_SPL_DM
CONFIG_DM_SERIAL=
CONFIG_DM_GPIO=
-CONIFG_DM_I2C=
+CONFIG_DM_I2C=
CONFIG_DM_SPI=
CONFIG_DM_SPI_FLASH=
endif
CONFIG_AEMIF_CNTRL_BASE
CONFIG_ALTERA_SPI_IDLE_VAL
CONFIG_ALTIVEC
-CONFIG_ALT_LB_ADDR
CONFIG_ALU
CONFIG_AM335X_LCD
CONFIG_AM335X_USB0
CONFIG_AP_SH4A_4A
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_CPU_INIT
-CONFIG_ARCH_CSB226
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
-CONFIG_ARCH_INNOKOM
CONFIG_ARCH_KIRKWOOD
-CONFIG_ARCH_LUBBOCK
CONFIG_ARCH_MAP_SYSMEM
CONFIG_ARCH_OMAP4
CONFIG_ARCH_ORION5X
-CONFIG_ARCH_PLEB
-CONFIG_ARCH_PXA_CERF
-CONFIG_ARCH_PXA_IDP
CONFIG_ARCH_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
CONFIG_ARCH_TEGRA
CONFIG_ARM_DCC
CONFIG_ARM_FREQ
CONFIG_ARM_GIC_BASE_ADDRESS
-CONFIG_ARM_PL180_MMCI
CONFIG_ARM_PL180_MMCI_BASE
CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
CONFIG_ARM_THUMB
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
CONFIG_ATAPI
-CONFIG_ATA_ACPI
CONFIG_ATI
CONFIG_ATI_RADEON_FB
CONFIG_ATM
CONFIG_BOOGER
CONFIG_BOOM
CONFIG_BOOTBLOCK
-CONFIG_BOOTCOMMAND
CONFIG_BOOTCOUNT_ALEN
CONFIG_BOOTCOUNT_AM33XX
CONFIG_BOOTCOUNT_ENV
CONFIG_CPU_SH_TYPE_R
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
-CONFIG_CP_CLK_FREQ
CONFIG_CQSPI_DECODER
CONFIG_CQSPI_REF_CLK
CONFIG_CRC32
CONFIG_DWC2_UTMI_WIDTH
CONFIG_DWCDDR21MCTL
CONFIG_DWCDDR21MCTL_BASE
-CONFIG_DWC_AHSATA
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
CONFIG_DW_ALTDESCRIPTOR
CONFIG_FSL_QIXIS
CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
CONFIG_FSL_QIXIS_V2
-CONFIG_FSL_SATA
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SDRAM_TYPE
CONFIG_FTRTC010_BASE
CONFIG_FTRTC010_EXTCLK
CONFIG_FTRTC010_PCLK
-CONFIG_FTSDC010
CONFIG_FTSDC010_BASE
CONFIG_FTSDC010_BASE_LIST
CONFIG_FTSDC010_NUMBER
CONFIG_LG4573
CONFIG_LG4573_BUS
CONFIG_LG4573_CS
-CONFIG_LIBATA
CONFIG_LIB_HW_RAND
CONFIG_LIB_UUID
CONFIG_LINUX
CONFIG_LOADADDR
CONFIG_LOADCMD
CONFIG_LOADS_ECHO
-CONFIG_LOGBUFFER
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
CONFIG_LOW_MCFCLK
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_MTD_ECC_SOFT
-CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
CONFIG_MTD_NAND_ECC_SMC
CONFIG_MTD_NAND_MUSEUM_IDS
CONFIG_MTD_NAND_VERIFY_WRITE
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
-CONFIG_MVSATA_IDE
CONFIG_MVSATA_IDE_USE_PORT0
CONFIG_MVSATA_IDE_USE_PORT1
CONFIG_MV_ETH_RXQ
CONFIG_MV_I2C_NUM
CONFIG_MV_I2C_REG
CONFIG_MX23
-CONFIG_MX25
CONFIG_MX25_CLK32
CONFIG_MX25_HCLK_FREQ
CONFIG_MX27
CONFIG_NAND_CS_INIT
CONFIG_NAND_DATA_REG
CONFIG_NAND_DAVINCI
-CONFIG_NAND_DENALI_ECC_SIZE
CONFIG_NAND_ECC_BCH
CONFIG_NAND_ENV_DST
CONFIG_NAND_FSL_ELBC
CONFIG_RAMDISK_BOOT
CONFIG_RAM_BOOT
CONFIG_RAM_BOOT_PHYS
-CONFIG_RCAR_BOARD_STRING
CONFIG_RD_LVL
CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
CONFIG_RUN_FROM_IRAM_ONLY
CONFIG_RX_DESCR_NUM
CONFIG_S32V234
-CONFIG_S3D2_CLK_FREQ
-CONFIG_S3D4_CLK_FREQ
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110
CONFIG_SAR_REG
CONFIG_SATA1
CONFIG_SATA2
-CONFIG_SATA_MV
-CONFIG_SATA_SIL
-CONFIG_SATA_SIL3114
CONFIG_SATA_ULI5288
CONFIG_SBC8349
CONFIG_SBC8548
CONFIG_SCIF_A
CONFIG_SCIF_EXT_CLOCK
CONFIG_SCIF_USE_EXT_CLK
-CONFIG_SCSI_AHCI
CONFIG_SCSI_AHCI_PLAT
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_STACKBASE
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STATIC_BOARD_REV
-CONFIG_STATIC_RELA
CONFIG_STD_DEVICES_SETTINGS
CONFIG_STM32F4DISCOVERY
CONFIG_STM32_FLASH
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
CONFIG_SUNXI_AHCI
-CONFIG_SUNXI_EMAC
CONFIG_SUNXI_GPIO
CONFIG_SUNXI_MAX_FB_SIZE
CONFIG_SUNXI_USB_PHYS
CONFIG_SYS_BOARD_OMAP3_HA
CONFIG_SYS_BOARD_VERSION
CONFIG_SYS_BOOK3E_HV
-CONFIG_SYS_BOOTCOUNT_ADDR
CONFIG_SYS_BOOTCOUNT_BE
CONFIG_SYS_BOOTCOUNT_LE
CONFIG_SYS_BOOTCOUNT_SINGLEWORD
CONFIG_SYS_POST_MEMORY
CONFIG_SYS_POST_MEM_REGIONS
CONFIG_SYS_POST_OCM
-CONFIG_SYS_POST_PREREL
CONFIG_SYS_POST_RTC
CONFIG_SYS_POST_SPR
CONFIG_SYS_POST_SYSMON
CONFIG_ZYNQ_SDHCI1
CONFIG_ZYNQ_SDHCI_MAX_FREQ
CONFIG_ZYNQ_SDHCI_MIN_FREQ
-CONFIG_ZYNQ_SERIAL
CONFIG_eTSEC_MDIO_BUS
obj-$(CONFIG_SANDBOX) += compression.o
obj-$(CONFIG_SANDBOX) += print_ut.o
obj-$(CONFIG_UT_TIME) += time_ut.o
+obj-$(CONFIG_$(SPL_)LOG) += log/
#include <common.h>
#include <command.h>
#include <test/suites.h>
+#include <test/test.h>
static int do_ut_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents,
+ int argc, char * const argv[])
+{
+ struct unit_test_state uts = { .fail_count = 0 };
+ struct unit_test *test;
+
+ if (argc == 1)
+ printf("Running %d %s tests\n", n_ents, name);
+
+ for (test = tests; test < tests + n_ents; test++) {
+ if (argc > 1 && strcmp(argv[1], test->name))
+ continue;
+ printf("Test: %s\n", test->name);
+
+ uts.start = mallinfo();
+
+ test->func(&uts);
+ }
+
+ printf("Failures: %d\n", uts.fail_count);
+
+ return uts.fail_count ? CMD_RET_FAILURE : 0;
+}
+
static cmd_tbl_t cmd_ut_sub[] = {
U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""),
#if defined(CONFIG_UT_DM)
#ifdef CONFIG_UT_TIME
U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""),
#endif
+#ifdef CONFIG_SANDBOX
+ U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression,
+ "", ""),
+#endif
};
static int do_ut_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#ifdef CONFIG_UT_TIME
"ut time - Very basic test of time functions\n"
+#endif
+#ifdef CONFIG_SANDBOX
+ "ut compression - Test compressors and bootm decompression\n"
#endif
;
#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#define DEBUG
-
#include <common.h>
#include <bootm.h>
#include <command.h>
#include <lzma/LzmaTools.h>
#include <linux/lzo.h>
+#include <test/compression.h>
+#include <test/suites.h>
+#include <test/ut.h>
static const char plain[] =
"I am a highly compressable bit of text.\n"
#define TEST_BUFFER_SIZE 512
-typedef int (*mutate_func)(void *, unsigned long, void *, unsigned long,
- unsigned long *);
+typedef int (*mutate_func)(struct unit_test_state *uts, void *, unsigned long,
+ void *, unsigned long, unsigned long *);
-static int compress_using_gzip(void *in, unsigned long in_size,
+static int compress_using_gzip(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
return ret;
}
-static int uncompress_using_gzip(void *in, unsigned long in_size,
+static int uncompress_using_gzip(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
return ret;
}
-static int compress_using_bzip2(void *in, unsigned long in_size,
+static int compress_using_bzip2(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
/* There is no bzip2 compression in u-boot, so fake it. */
- assert(in_size == strlen(plain));
- assert(memcmp(plain, in, in_size) == 0);
+ ut_asserteq(in_size, strlen(plain));
+ ut_asserteq(0, memcmp(plain, in, in_size));
if (bzip2_compressed_size > out_max)
return -1;
return 0;
}
-static int uncompress_using_bzip2(void *in, unsigned long in_size,
+static int uncompress_using_bzip2(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
return (ret != BZ_OK);
}
-static int compress_using_lzma(void *in, unsigned long in_size,
+static int compress_using_lzma(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
/* There is no lzma compression in u-boot, so fake it. */
- assert(in_size == strlen(plain));
- assert(memcmp(plain, in, in_size) == 0);
+ ut_asserteq(in_size, strlen(plain));
+ ut_asserteq(0, memcmp(plain, in, in_size));
if (lzma_compressed_size > out_max)
return -1;
return 0;
}
-static int uncompress_using_lzma(void *in, unsigned long in_size,
+static int uncompress_using_lzma(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
return (ret != SZ_OK);
}
-static int compress_using_lzo(void *in, unsigned long in_size,
+static int compress_using_lzo(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
/* There is no lzo compression in u-boot, so fake it. */
- assert(in_size == strlen(plain));
- assert(memcmp(plain, in, in_size) == 0);
+ ut_asserteq(in_size, strlen(plain));
+ ut_asserteq(0, memcmp(plain, in, in_size));
if (lzo_compressed_size > out_max)
return -1;
return 0;
}
-static int uncompress_using_lzo(void *in, unsigned long in_size,
+static int uncompress_using_lzo(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
return (ret != LZO_E_OK);
}
-static int compress_using_lz4(void *in, unsigned long in_size,
+static int compress_using_lz4(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
/* There is no lz4 compression in u-boot, so fake it. */
- assert(in_size == strlen(plain));
- assert(memcmp(plain, in, in_size) == 0);
+ ut_asserteq(in_size, strlen(plain));
+ ut_asserteq(0, memcmp(plain, in, in_size));
if (lz4_compressed_size > out_max)
return -1;
return 0;
}
-static int uncompress_using_lz4(void *in, unsigned long in_size,
+static int uncompress_using_lz4(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
goto out; \
}
-static int run_test(char *name, mutate_func compress, mutate_func uncompress)
-{
- ulong orig_size, compressed_size, uncompressed_size;
+struct buf_state {
+ ulong orig_size;
+ ulong compressed_size;
+ ulong uncompressed_size;
void *orig_buf;
- void *compressed_buf = NULL;
- void *uncompressed_buf = NULL;
- void *compare_buf = NULL;
+ void *compressed_buf;
+ void *uncompressed_buf;
+ void *compare_buf;
+};
+
+static int run_test_internal(struct unit_test_state *uts, char *name,
+ mutate_func compress, mutate_func uncompress,
+ struct buf_state *buf)
+{
int ret;
- printf(" testing %s ...\n", name);
-
- orig_buf = (void *)plain;
- orig_size = strlen(orig_buf); /* Trailing NULL not included. */
- errcheck(orig_size > 0);
-
- compressed_size = uncompressed_size = TEST_BUFFER_SIZE;
- compressed_buf = malloc(compressed_size);
- errcheck(compressed_buf != NULL);
- uncompressed_buf = malloc(uncompressed_size);
- errcheck(uncompressed_buf != NULL);
- compare_buf = malloc(uncompressed_size);
- errcheck(compare_buf != NULL);
-
/* Compress works as expected. */
- printf("\torig_size:%lu\n", orig_size);
- memset(compressed_buf, 'A', TEST_BUFFER_SIZE);
- errcheck(compress(orig_buf, orig_size,
- compressed_buf, compressed_size,
- &compressed_size) == 0);
- printf("\tcompressed_size:%lu\n", compressed_size);
- errcheck(compressed_size > 0);
- errcheck(compressed_size < orig_size);
- errcheck(((char *)compressed_buf)[compressed_size-1] != 'A');
- errcheck(((char *)compressed_buf)[compressed_size] == 'A');
+ printf("\torig_size:%lu\n", buf->orig_size);
+ memset(buf->compressed_buf, 'A', TEST_BUFFER_SIZE);
+ errcheck(compress(uts, buf->orig_buf, buf->orig_size,
+ buf->compressed_buf, buf->compressed_size,
+ &buf->compressed_size) == 0);
+ printf("\tcompressed_size:%lu\n", buf->compressed_size);
+ errcheck(buf->compressed_size > 0);
+ errcheck(buf->compressed_size < buf->orig_size);
+ errcheck(((char *)buf->compressed_buf)[buf->compressed_size - 1] !=
+ 'A');
+ errcheck(((char *)buf->compressed_buf)[buf->compressed_size] == 'A');
/* Uncompresses with space remaining. */
- errcheck(uncompress(compressed_buf, compressed_size,
- uncompressed_buf, uncompressed_size,
- &uncompressed_size) == 0);
- printf("\tuncompressed_size:%lu\n", uncompressed_size);
- errcheck(uncompressed_size == orig_size);
- errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0);
+ errcheck(uncompress(uts, buf->compressed_buf, buf->compressed_size,
+ buf->uncompressed_buf, buf->uncompressed_size,
+ &buf->uncompressed_size) == 0);
+ printf("\tuncompressed_size:%lu\n", buf->uncompressed_size);
+ errcheck(buf->uncompressed_size == buf->orig_size);
+ errcheck(memcmp(buf->orig_buf, buf->uncompressed_buf,
+ buf->orig_size) == 0);
/* Uncompresses with exactly the right size output buffer. */
- memset(uncompressed_buf, 'A', TEST_BUFFER_SIZE);
- errcheck(uncompress(compressed_buf, compressed_size,
- uncompressed_buf, orig_size,
- &uncompressed_size) == 0);
- errcheck(uncompressed_size == orig_size);
- errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0);
- errcheck(((char *)uncompressed_buf)[orig_size] == 'A');
+ memset(buf->uncompressed_buf, 'A', TEST_BUFFER_SIZE);
+ errcheck(uncompress(uts, buf->compressed_buf, buf->compressed_size,
+ buf->uncompressed_buf, buf->orig_size,
+ &buf->uncompressed_size) == 0);
+ errcheck(buf->uncompressed_size == buf->orig_size);
+ errcheck(memcmp(buf->orig_buf, buf->uncompressed_buf,
+ buf->orig_size) == 0);
+ errcheck(((char *)buf->uncompressed_buf)[buf->orig_size] == 'A');
/* Make sure compression does not over-run. */
- memset(compare_buf, 'A', TEST_BUFFER_SIZE);
- ret = compress(orig_buf, orig_size,
- compare_buf, compressed_size - 1,
+ memset(buf->compare_buf, 'A', TEST_BUFFER_SIZE);
+ ret = compress(uts, buf->orig_buf, buf->orig_size,
+ buf->compare_buf, buf->compressed_size - 1,
NULL);
- errcheck(((char *)compare_buf)[compressed_size] == 'A');
+ errcheck(((char *)buf->compare_buf)[buf->compressed_size] == 'A');
errcheck(ret != 0);
printf("\tcompress does not overrun\n");
/* Make sure decompression does not over-run. */
- memset(compare_buf, 'A', TEST_BUFFER_SIZE);
- ret = uncompress(compressed_buf, compressed_size,
- compare_buf, uncompressed_size - 1,
+ memset(buf->compare_buf, 'A', TEST_BUFFER_SIZE);
+ ret = uncompress(uts, buf->compressed_buf, buf->compressed_size,
+ buf->compare_buf, buf->uncompressed_size - 1,
NULL);
- errcheck(((char *)compare_buf)[uncompressed_size - 1] == 'A');
+ errcheck(((char *)buf->compare_buf)[buf->uncompressed_size - 1] == 'A');
errcheck(ret != 0);
printf("\tuncompress does not overrun\n");
/* Got here, everything is fine. */
ret = 0;
+out:
+ return ret;
+}
+
+static int run_test(struct unit_test_state *uts, char *name,
+ mutate_func compress, mutate_func uncompress)
+{
+ struct buf_state sbuf, *buf = &sbuf;
+ int ret;
+
+ printf(" testing %s ...\n", name);
+
+ buf->orig_buf = (void *)plain;
+ buf->orig_size = strlen(buf->orig_buf); /* Trailing NUL not included */
+ errcheck(buf->orig_size > 0);
+
+ buf->compressed_size = TEST_BUFFER_SIZE;
+ buf->uncompressed_size = TEST_BUFFER_SIZE;
+ buf->compressed_buf = malloc(buf->compressed_size);
+ errcheck(buf->compressed_buf);
+ buf->uncompressed_buf = malloc(buf->uncompressed_size);
+ errcheck(buf->uncompressed_buf);
+ buf->compare_buf = malloc(buf->uncompressed_size);
+ errcheck(buf->compare_buf);
+
+ ret = run_test_internal(uts, name, compress, uncompress, buf);
out:
printf(" %s: %s\n", name, ret == 0 ? "ok" : "FAILED");
- free(compare_buf);
- free(uncompressed_buf);
- free(compressed_buf);
+ free(buf->compare_buf);
+ free(buf->uncompressed_buf);
+ free(buf->compressed_buf);
return ret;
}
-static int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+static int compression_test_gzip(struct unit_test_state *uts)
{
- int err = 0;
+ return run_test(uts, "gzip", compress_using_gzip,
+ uncompress_using_gzip);
+}
+COMPRESSION_TEST(compression_test_gzip, 0);
+
+static int compression_test_bzip2(struct unit_test_state *uts)
+{
+ return run_test(uts, "bzip2", compress_using_bzip2,
+ uncompress_using_bzip2);
+}
+COMPRESSION_TEST(compression_test_bzip2, 0);
- err += run_test("gzip", compress_using_gzip, uncompress_using_gzip);
- err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2);
- err += run_test("lzma", compress_using_lzma, uncompress_using_lzma);
- err += run_test("lzo", compress_using_lzo, uncompress_using_lzo);
- err += run_test("lz4", compress_using_lz4, uncompress_using_lz4);
+static int compression_test_lzma(struct unit_test_state *uts)
+{
+ return run_test(uts, "lzma", compress_using_lzma,
+ uncompress_using_lzma);
+}
+COMPRESSION_TEST(compression_test_lzma, 0);
- printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED");
+static int compression_test_lzo(struct unit_test_state *uts)
+{
+ return run_test(uts, "lzo", compress_using_lzo, uncompress_using_lzo);
+}
+COMPRESSION_TEST(compression_test_lzo, 0);
- return err;
+static int compression_test_lz4(struct unit_test_state *uts)
+{
+ return run_test(uts, "lz4", compress_using_lz4, uncompress_using_lz4);
}
+COMPRESSION_TEST(compression_test_lz4, 0);
-static int compress_using_none(void *in, unsigned long in_size,
+static int compress_using_none(struct unit_test_state *uts,
+ void *in, unsigned long in_size,
void *out, unsigned long out_max,
unsigned long *out_size)
{
* @compress: Our function to compress data
* @return 0 if OK, non-zero on failure
*/
-static int run_bootm_test(int comp_type, mutate_func compress)
+static int run_bootm_test(struct unit_test_state *uts, int comp_type,
+ mutate_func compress)
{
ulong compress_size = 1024;
void *compress_buff;
printf("Testing: %s\n", genimg_get_comp_name(comp_type));
compress_buff = map_sysmem(image_start, 0);
unc_len = strlen(plain);
- compress((void *)plain, unc_len, compress_buff, compress_size,
+ compress(uts, (void *)plain, unc_len, compress_buff, compress_size,
&compress_size);
err = bootm_decomp_image(comp_type, load_addr, image_start,
IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
compress_buff, compress_size, unc_len,
&load_end);
- if (err)
- return err;
+ ut_assertok(err);
err = bootm_decomp_image(comp_type, load_addr, image_start,
IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
compress_buff, compress_size, unc_len - 1,
&load_end);
- if (!err)
- return -EINVAL;
+ ut_assert(err);
/* We can't detect corruption when not decompressing */
if (comp_type == IH_COMP_NONE)
IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
compress_buff, compress_size, 0x10000,
&load_end);
- if (!err)
- return -EINVAL;
+ ut_assert(err);
return 0;
}
-static int do_ut_image_decomp(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+static int compression_test_bootm_gzip(struct unit_test_state *uts)
{
- int err = 0;
+ return run_bootm_test(uts, IH_COMP_GZIP, compress_using_gzip);
+}
+COMPRESSION_TEST(compression_test_bootm_gzip, 0);
+
+static int compression_test_bootm_bzip2(struct unit_test_state *uts)
+{
+ return run_bootm_test(uts, IH_COMP_BZIP2, compress_using_bzip2);
+}
+COMPRESSION_TEST(compression_test_bootm_bzip2, 0);
- err = run_bootm_test(IH_COMP_GZIP, compress_using_gzip);
- err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2);
- err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma);
- err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo);
- err |= run_bootm_test(IH_COMP_LZ4, compress_using_lz4);
- err |= run_bootm_test(IH_COMP_NONE, compress_using_none);
+static int compression_test_bootm_lzma(struct unit_test_state *uts)
+{
+ return run_bootm_test(uts, IH_COMP_LZMA, compress_using_lzma);
+}
+COMPRESSION_TEST(compression_test_bootm_lzma, 0);
- printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED");
+static int compression_test_bootm_lzo(struct unit_test_state *uts)
+{
+ return run_bootm_test(uts, IH_COMP_LZO, compress_using_lzo);
+}
+COMPRESSION_TEST(compression_test_bootm_lzo, 0);
- return 0;
+static int compression_test_bootm_lz4(struct unit_test_state *uts)
+{
+ return run_bootm_test(uts, IH_COMP_LZ4, compress_using_lz4);
}
+COMPRESSION_TEST(compression_test_bootm_lz4, 0);
-U_BOOT_CMD(
- ut_compression, 5, 1, do_ut_compression,
- "Basic test of compressors: gzip bzip2 lzma lzo", ""
-);
+static int compression_test_bootm_none(struct unit_test_state *uts)
+{
+ return run_bootm_test(uts, IH_COMP_NONE, compress_using_none);
+}
+COMPRESSION_TEST(compression_test_bootm_none, 0);
-U_BOOT_CMD(
- ut_image_decomp, 5, 1, do_ut_image_decomp,
- "Basic test of bootm decompression", ""
-);
+int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct unit_test *tests = ll_entry_start(struct unit_test,
+ compression_test);
+ const int n_ents = ll_entry_count(struct unit_test, compression_test);
+
+ return cmd_ut_category("compression", tests, n_ents, argc, argv);
+}
enum {
BUCK1,
BUCK2,
+ BUCK3,
LDO1,
LDO2,
OUTPUT_COUNT,
/* devname, platname */
{ SANDBOX_BUCK1_DEVNAME, SANDBOX_BUCK1_PLATNAME },
{ SANDBOX_BUCK2_DEVNAME, SANDBOX_BUCK2_PLATNAME },
+ { SANDBOX_BUCK3_DEVNAME, SANDBOX_BUCK3_PLATNAME },
{ SANDBOX_LDO1_DEVNAME, SANDBOX_LDO1_PLATNAME},
{ SANDBOX_LDO2_DEVNAME, SANDBOX_LDO2_PLATNAME},
};
{
struct unit_test *tests = ll_entry_start(struct unit_test, env_test);
const int n_ents = ll_entry_count(struct unit_test, env_test);
- struct unit_test_state uts = { .fail_count = 0 };
- struct unit_test *test;
- if (argc == 1)
- printf("Running %d environment tests\n", n_ents);
-
- for (test = tests; test < tests + n_ents; test++) {
- if (argc > 1 && strcmp(argv[1], test->name))
- continue;
- printf("Test: %s\n", test->name);
-
- uts.start = mallinfo();
-
- test->func(&uts);
- }
-
- printf("Failures: %d\n", uts.fail_count);
-
- return uts.fail_count ? CMD_RET_FAILURE : 0;
+ return cmd_ut_category("environment", tests, n_ents, argc, argv);
}
--- /dev/null
+#
+# Copyright (c) 2017 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_LOG_TEST) += log_test.o
--- /dev/null
+/*
+ * Logging support test program
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/* emit some sample log records in different ways, for testing */
+static int log_run(enum uclass_id cat, const char *file)
+{
+ int i;
+
+ debug("debug\n");
+ for (i = LOGL_FIRST; i < LOGL_COUNT; i++) {
+ log(cat, i, "log %d\n", i);
+ _log(log_uc_cat(cat), i, file, 100 + i, "func", "_log %d\n",
+ i);
+ }
+
+ return 0;
+}
+
+static int log_test(int testnum)
+{
+ int ret;
+
+ printf("test %d\n", testnum);
+ switch (testnum) {
+ case 0: {
+ /* Check a category filter using the first category */
+ enum log_category_t cat_list[] = {
+ log_uc_cat(UCLASS_MMC), log_uc_cat(UCLASS_SPI),
+ LOGC_NONE, LOGC_END
+ };
+
+ ret = log_add_filter("console", cat_list, LOGL_MAX, NULL);
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_MMC, "file");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 1: {
+ /* Check a category filter using the second category */
+ enum log_category_t cat_list[] = {
+ log_uc_cat(UCLASS_MMC), log_uc_cat(UCLASS_SPI), LOGC_END
+ };
+
+ ret = log_add_filter("console", cat_list, LOGL_MAX, NULL);
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 2: {
+ /* Check a category filter that should block log entries */
+ enum log_category_t cat_list[] = {
+ log_uc_cat(UCLASS_MMC), LOGC_NONE, LOGC_END
+ };
+
+ ret = log_add_filter("console", cat_list, LOGL_MAX, NULL);
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 3: {
+ /* Check a passing file filter */
+ ret = log_add_filter("console", NULL, LOGL_MAX, "file");
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 4: {
+ /* Check a failing file filter */
+ ret = log_add_filter("console", NULL, LOGL_MAX, "file");
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file2");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 5: {
+ /* Check a passing file filter (second in list) */
+ ret = log_add_filter("console", NULL, LOGL_MAX, "file,file2");
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file2");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 6: {
+ /* Check a passing file filter */
+ ret = log_add_filter("console", NULL, LOGL_MAX,
+ "file,file2,log/log_test.c");
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file2");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 7: {
+ /* Check a log level filter */
+ ret = log_add_filter("console", NULL, LOGL_WARNING, NULL);
+ if (ret < 0)
+ return ret;
+ log_run(UCLASS_SPI, "file");
+ ret = log_remove_filter("console", ret);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 8: {
+ /* Check two filters, one of which passes everything */
+ int filt1, filt2;
+
+ ret = log_add_filter("console", NULL, LOGL_WARNING, NULL);
+ if (ret < 0)
+ return ret;
+ filt1 = ret;
+ ret = log_add_filter("console", NULL, LOGL_MAX, NULL);
+ if (ret < 0)
+ return ret;
+ filt2 = ret;
+ log_run(UCLASS_SPI, "file");
+ ret = log_remove_filter("console", filt1);
+ if (ret < 0)
+ return ret;
+ ret = log_remove_filter("console", filt2);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ case 9: {
+ /* Check three filters, which together pass everything */
+ int filt1, filt2, filt3;
+
+ ret = log_add_filter("console", NULL, LOGL_MAX, "file)");
+ if (ret < 0)
+ return ret;
+ filt1 = ret;
+ ret = log_add_filter("console", NULL, LOGL_MAX, "file2");
+ if (ret < 0)
+ return ret;
+ filt2 = ret;
+ ret = log_add_filter("console", NULL, LOGL_MAX,
+ "log/log_test.c");
+ if (ret < 0)
+ return ret;
+ filt3 = ret;
+ log_run(UCLASS_SPI, "file2");
+ ret = log_remove_filter("console", filt1);
+ if (ret < 0)
+ return ret;
+ ret = log_remove_filter("console", filt2);
+ if (ret < 0)
+ return ret;
+ ret = log_remove_filter("console", filt3);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_LOG_TEST
+int do_log_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int testnum = 0;
+ int ret;
+
+ if (argc > 1)
+ testnum = simple_strtoul(argv[1], NULL, 10);
+
+ ret = log_test(testnum);
+ if (ret)
+ printf("Test failure (err=%d)\n", ret);
+
+ return ret ? CMD_RET_FAILURE : 0;
+}
+#endif
#include <test/ut.h>
#include <test/overlay.h>
+#include <test/suites.h>
/* 4k ought to be enough for anybody */
#define FDT_COPY_SIZE (4 * SZ_1K)
overlay_test);
const int n_ents = ll_entry_count(struct unit_test, overlay_test);
struct unit_test_state *uts;
- struct unit_test *test;
void *fdt_base = &__dtb_test_fdt_base_begin;
void *fdt_overlay = &__dtb_test_fdt_overlay_begin;
void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin;
/* Apply the stacked overlay */
ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_stacked_copy));
- if (argc == 1)
- printf("Running %d environment tests\n", n_ents);
-
- for (test = tests; test < tests + n_ents; test++) {
- if (argc > 1 && strcmp(argv[1], test->name))
- continue;
- printf("Test: %s\n", test->name);
-
- uts->start = mallinfo();
-
- test->func(uts);
- }
-
- printf("Failures: %d\n", uts->fail_count);
- if (!uts->fail_count)
- ret = 0;
- else
- ret = CMD_RET_FAILURE;
+ ret = cmd_ut_category("overlay", tests, n_ents, argc, argv);
free(fdt_overlay_stacked_copy);
err3:
import u_boot_console_exec_attach
console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
-re_ut_test_list = re.compile(r'_u_boot_list_2_(dm|env)_test_2_\1_test_(.*)\s*$')
+re_ut_test_list = re.compile(r'_u_boot_list_2_(.*)_test_2_\1_test_(.*)\s*$')
def generate_ut_subtest(metafunc, fixture_name):
"""Provide parametrization for a ut_subtest fixture.
"""
Note: This test relies on boardenv_* containing configuration values to define
-which the network environment available for testing. Without this, the parts
+which network environment is available for testing. Without this, the parts
that rely on network will be automatically skipped.
For example:
output = u_boot_console.run_command('bootefi %x' % addr)
expected_text = 'Hello, world'
assert expected_text in output
+ expected_text = '## Application terminated, r = 0'
+ assert expected_text in output
@pytest.mark.buildconfigspec('cmd_bootefi_hello')
def test_efi_helloworld_builtin(u_boot_console):
-# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
# Copyright (c) 2017, Heinrich Schuchardt <xypron.glpk@gmx.de>
#
# SPDX-License-Identifier: GPL-2.0
Run bootefi selftest
"""
+ u_boot_console.run_command(cmd='setenv efi_selftest')
u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
if m != 0:
if m != 0:
raise Exception('Reset failed during the EFI selftest')
u_boot_console.restart_uboot();
+
+@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
+def test_efi_selftest_watchdog_reboot(u_boot_console):
+ u_boot_console.run_command(cmd='setenv efi_selftest list')
+ output = u_boot_console.run_command('bootefi selftest')
+ assert '\'watchdog reboot\'' in output
+ u_boot_console.run_command(cmd='setenv efi_selftest watchdog reboot')
+ u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ m = u_boot_console.p.expect(['resetting', 'U-Boot'])
+ if m != 0:
+ raise Exception('Reset failed in \'watchdog reboot\' test')
+ u_boot_console.restart_uboot();
Nothing.
"""
- state_test_env.u_boot_console.run_command('setenv %s "%s"' % (var, value))
+ bc = state_test_env.u_boot_console.config.buildconfig
+ if bc.get('config_hush_parser', None):
+ quote = '"'
+ else:
+ quote = ''
+ if ' ' in value:
+ pytest.skip('Space in variable value on non-Hush shell')
+
+ state_test_env.u_boot_console.run_command(
+ 'setenv %s %s%s%s' % (var, quote, value, quote))
state_test_env.env[var] = value
def validate_empty(state_test_env, var):
cmd = ('sgdisk', '-U', '375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '--new=1:2048:2560', '-c 1:part1', persistent)
+ # part1 offset 1MB size 1MB
+ cmd = ('sgdisk', '--new=1:2048:4095', '-c 1:part1', persistent)
+ # part2 offset 2MB size 1.5MB
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '--new=2:4096:4608', '-c 2:part2', persistent)
+ cmd = ('sgdisk', '--new=2:4096:7167', '-c 2:part2', persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
cmd = ('sgdisk', '-l', persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
output = u_boot_console.run_command('gpt read host 0')
- assert 'Start 1MiB, size 0MiB' in output
+ assert 'Start 1MiB, size 1MiB' in output
assert 'Block size 512, name part1' in output
- assert 'Start 2MiB, size 0MiB' in output
+ assert 'Start 2MiB, size 1MiB' in output
assert 'Block size 512, name part2' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "part1"' in output
- assert '0x00001000 0x00001200 "part2"' in output
+ assert '0x00000800 0x00000fff "part1"' in output
+ assert '0x00001000 0x00001bff "part2"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
output = u_boot_console.run_command('gpt read host 0')
assert 'name second' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
u_boot_console.run_command('gpt swap host 0 first second')
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "second"' in output
- assert '0x00001000 0x00001200 "first"' in output
+ assert '0x00000800 0x00000fff "second"' in output
+ assert '0x00001000 0x00001bff "first"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
assert 'Writing GPT: success!' in output
output = u_boot_console.run_command('part list host 0')
assert '0x00000022 0x00001fde "all"' in output
- output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=0x100000,size=0x40200;name=second,start=0x200000,size=0x40200;"')
+ output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
assert 'Writing GPT: success!' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
output = u_boot_console.run_command('gpt guid host 0')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
--- /dev/null
+# Copyright (c) 2016, Google Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# U-Boot Verified Boot Test
+
+"""
+This tests U-Boot logging. It uses the 'log test' command with various options
+and checks that the output is correct.
+"""
+
+import pytest
+
+LOGL_FIRST, LOGL_WARNING, LOGL_INFO = (0, 4, 6)
+
+@pytest.mark.buildconfigspec('log')
+def test_log(u_boot_console):
+ """Test that U-Boot logging works correctly."""
+ def check_log_entries(lines, mask, max_level=LOGL_INFO):
+ """Check that the expected log records appear in the output
+
+ Args:
+ lines: iterator containing lines to check
+ mask: bit mask to select which lines to check for:
+ bit 0: standard log line
+ bit 1: _log line
+ max_level: maximum log level to expect in the output
+ """
+ for i in range(max_level):
+ if mask & 1:
+ assert 'log %d' % i == lines.next()
+ if mask & 3:
+ assert '_log %d' % i == lines.next()
+
+ def run_test(testnum):
+ """Run a particular test number (the 'log test' command)
+
+ Args:
+ testnum: Test number to run
+ Returns:
+ iterator containing the lines output from the command
+ """
+
+ with cons.log.section('basic'):
+ output = u_boot_console.run_command('log test %d' % testnum)
+ split = output.replace('\r', '').splitlines()
+ lines = iter(split)
+ assert 'test %d' % testnum == lines.next()
+ return lines
+
+ def test0():
+ lines = run_test(0)
+ check_log_entries(lines, 3)
+
+ def test1():
+ lines = run_test(1)
+ check_log_entries(lines, 3)
+
+ def test2():
+ lines = run_test(2)
+
+ def test3():
+ lines = run_test(3)
+ check_log_entries(lines, 2)
+
+ def test4():
+ lines = run_test(4)
+ assert next(lines, None) == None
+
+ def test5():
+ lines = run_test(5)
+ check_log_entries(lines, 2)
+
+ def test6():
+ lines = run_test(6)
+ check_log_entries(lines, 3)
+
+ def test7():
+ lines = run_test(7)
+ check_log_entries(lines, 3, LOGL_WARNING)
+
+ def test8():
+ lines = run_test(8)
+ check_log_entries(lines, 3)
+
+ def test9():
+ lines = run_test(9)
+ check_log_entries(lines, 3)
+
+ # TODO(sjg@chromium.org): Consider structuring this as separate tests
+ cons = u_boot_console
+ test0()
+ test1()
+ test2()
+ test3()
+ test4()
+ test5()
+ test6()
+ test7()
+ test8()
+ test9()
import pytest
import time
+"""
+Note: This test doesn't rely on boardenv_* configuration values but they can
+change test behavior.
+
+# Setup env__sleep_accurate to False if time is not accurate on your platform
+env__sleep_accurate = False
+
+"""
+
def test_sleep(u_boot_console):
"""Test the sleep command, and validate that it sleeps for approximately
the correct amount of time."""
+ sleep_skip = u_boot_console.config.env.get('env__sleep_accurate', True)
+ if not sleep_skip:
+ pytest.skip('sleep is not accurate')
+
if u_boot_console.config.buildconfig.get('config_cmd_misc', 'n') != 'y':
pytest.skip('sleep command not supported')
# 3s isn't too long, but is enough to cross a few second boundaries.
-#!/bin/sh
+#!/bin/bash
+
+run_test() {
+ $@
+ [ $? -ne 0 ] && result=$((result+1))
+}
+
+result=0
# Run all tests that the standard sandbox build can support
-./test/py/test.py --bd sandbox --build
+run_test ./test/py/test.py --bd sandbox --build
# Run tests which require sandbox_spl
-./test/py/test.py --bd sandbox_spl --build -k test/py/tests/test_ofplatdata.py
+run_test ./test/py/test.py --bd sandbox_spl --build -k \
+ test/py/tests/test_ofplatdata.py
# Run tests for the flat DT version of sandbox
./test/py/test.py --bd sandbox_flattree --build
+
+if [ $result == 0 ]; then
+ echo "Tests passed!"
+else
+ echo "Tests FAILED"
+ exit 1
+fi
# The following files are synced with upstream DTC.
# Use synced versions from scripts/dtc/libfdt/.
-LIBFDT_SRCS_SYNCED := fdt.c fdt_sw.c fdt_strerror.c fdt_empty_tree.c \
+LIBFDT_SRCS_SYNCED := fdt.c fdt_wip.c fdt_sw.c fdt_strerror.c fdt_empty_tree.c \
fdt_addresses.c fdt_overlay.c
# The following files are locally modified for U-Boot (unfotunately).
# Use U-Boot own versions from lib/libfdt/.
-LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_wip.c fdt_rw.c fdt_region.c
+LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_rw.c fdt_region.c
LIBFDT_OBJS := $(addprefix libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_SYNCED))) \
$(addprefix lib/libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_UNSYNCED)))
Binman has a few other options which you can see by running 'binman -h'.
+Enabling binman for a board
+---------------------------
+
+At present binman is invoked from a rule in the main Makefile. Typically you
+will have a rule like:
+
+ifneq ($(CONFIG_ARCH_<something>),)
+u-boot-<your_suffix>.bin: <input_file_1> <input_file_2> checkbinman FORCE
+ $(call if_changed,binman)
+endif
+
+This assumes that u-boot-<your_suffix>.bin is a target, and is the final file
+that you need to produce. You can make it a target by adding it to ALL-y
+either in the main Makefile or in a config.mk file in your arch subdirectory.
+
+Once binman is executed it will pick up its instructions from a device-tree
+file, typically <soc>-u-boot.dtsi, where <soc> is your CONFIG_SYS_SOC value.
+You can use other, more specific CONFIG options - see 'Automatic .dtsi
+inclusion' below.
+
+
Image description format
------------------------
an entry containing a hash of the contents of some other entries. At this
stage the position and size of entries should not be adjusted.
+6. WriteEntryInfo()
+
7. BuildImage() - builds the image and writes it to a file. This is the final
step.
the 'warning' line in scripts/Makefile.lib to see what it has found:
# Uncomment for debugging
- # $(warning binman_dtsi_options: $(binman_dtsi_options))
+ # This shows all the files that were considered and the one that we chose.
+ # u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
+
+
+Access to binman entry positions at run time
+--------------------------------------------
+
+Binman assembles images and determines where each entry is placed in the image.
+This information may be useful to U-Boot at run time. For example, in SPL it
+is useful to be able to find the location of U-Boot so that it can be executed
+when SPL is finished.
+
+Binman allows you to declare symbols in the SPL image which are filled in
+with their correct values during the build. For example:
+
+ binman_sym_declare(ulong, u_boot_any, pos);
+
+declares a ulong value which will be assigned to the position of any U-Boot
+image (u-boot.bin, u-boot.img, u-boot-nodtb.bin) that is present in the image.
+You can access this value with something like:
+
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
+Thus u_boot_pos will be set to the position of U-Boot in memory, assuming that
+the whole image has been loaded, or is available in flash. You can then jump to
+that address to start U-Boot.
+
+At present this feature is only supported in SPL. In principle it is possible
+to fill in such symbols in U-Boot proper, as well.
Code coverage
Some ideas:
- Fill out the device tree to include the final position and size of each
- entry (since the input file may not always specify these)
+ entry (since the input file may not always specify these). See also
+ 'Access to binman entry positions at run time' above
- Use of-platdata to make the information available to code that is unable
to use device tree (such as a very small SPL image)
- Write an image map to a text file
"""See README for more information"""
+import glob
import os
import sys
import traceback
import command
import control
-def RunTests():
+def RunTests(debug):
"""Run the functional tests and any embedded doctests"""
+ import elf_test
import entry_test
import fdt_test
- import func_test
+ import ftest
+ import image_test
import test
import doctest
suite.run(result)
sys.argv = [sys.argv[0]]
- for module in (func_test.TestFunctional, fdt_test.TestFdt,
- entry_test.TestEntry):
+ if debug:
+ sys.argv.append('-D')
+
+ # Run the entry tests first ,since these need to be the first to import the
+ # 'entry' module.
+ suite = unittest.TestLoader().loadTestsFromTestCase(entry_test.TestEntry)
+ suite.run(result)
+ for module in (ftest.TestFunctional, fdt_test.TestFdt, elf_test.TestElf,
+ image_test.TestImage):
suite = unittest.TestLoader().loadTestsFromTestCase(module)
suite.run(result)
for test, err in result.errors:
print test.id(), err
for test, err in result.failures:
- print err
+ print err, result.failures
+ if result.errors or result.failures:
+ print 'binman tests FAILED'
+ return 1
+ return 0
def RunTestCoverage():
"""Run the tests and check that we get 100% coverage"""
# This uses the build output from sandbox_spl to get _libfdt.so
- cmd = ('PYTHONPATH=%s/sandbox_spl/tools coverage run '
+ cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools coverage run '
'--include "tools/binman/*.py" --omit "*test*,*binman.py" '
'tools/binman/binman.py -t' % options.build_dir)
os.system(cmd)
stdout = command.Output('coverage', 'report')
- coverage = stdout.splitlines()[-1].split(' ')[-1]
+ lines = stdout.splitlines()
+
+ test_set= set([os.path.basename(line.split()[0])
+ for line in lines if '/etype/' in line])
+ glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
+ all_set = set([os.path.basename(item) for item in glob_list])
+ missing_list = all_set
+ missing_list.difference_update(test_set)
+ missing_list.remove('_testing.py')
+ coverage = lines[-1].split(' ')[-1]
+ ok = True
+ if missing_list:
+ print 'Missing tests for %s' % (', '.join(missing_list))
+ ok = False
if coverage != '100%':
print stdout
print "Type 'coverage html' to get a report in htmlcov/index.html"
- raise ValueError('Coverage error: %s, but should be 100%%' % coverage)
-
+ print 'Coverage error: %s, but should be 100%%' % coverage
+ ok = False
+ if not ok:
+ raise ValueError('Test coverage failure')
def RunBinman(options, args):
"""Main entry point to binman once arguments are parsed
sys.tracebacklimit = 0
if options.test:
- RunTests()
+ ret_code = RunTests(options.debug)
elif options.test_coverage:
RunTestCoverage()
import tools
import command
+import elf
import fdt
import fdt_util
from image import Image
try:
tout.Init(options.verbosity)
+ elf.debug = options.debug
try:
tools.SetInputDirs(options.indir)
tools.PrepareOutputDir(options.outdir, options.preserve)
image.CheckSize()
image.CheckEntries()
image.ProcessEntryContents()
+ image.WriteSymbols()
image.BuildImage()
finally:
tools.FinaliseOutputDir()
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Handle various things related to ELF images
+#
+
+from collections import namedtuple, OrderedDict
+import command
+import os
+import re
+import struct
+
+import tools
+
+# This is enabled from control.py
+debug = False
+
+Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak'])
+
+
+def GetSymbols(fname, patterns):
+ """Get the symbols from an ELF file
+
+ Args:
+ fname: Filename of the ELF file to read
+ patterns: List of regex patterns to search for, each a string
+
+ Returns:
+ None, if the file does not exist, or Dict:
+ key: Name of symbol
+ value: Hex value of symbol
+ """
+ stdout = command.Output('objdump', '-t', fname, raise_on_error=False)
+ lines = stdout.splitlines()
+ if patterns:
+ re_syms = re.compile('|'.join(patterns))
+ else:
+ re_syms = None
+ syms = {}
+ syms_started = False
+ for line in lines:
+ if not line or not syms_started:
+ if 'SYMBOL TABLE' in line:
+ syms_started = True
+ line = None # Otherwise code coverage complains about 'continue'
+ continue
+ if re_syms and not re_syms.search(line):
+ continue
+
+ space_pos = line.find(' ')
+ value, rest = line[:space_pos], line[space_pos + 1:]
+ flags = rest[:7]
+ parts = rest[7:].split()
+ section, size = parts[:2]
+ if len(parts) > 2:
+ name = parts[2]
+ syms[name] = Symbol(section, int(value, 16), int(size,16),
+ flags[1] == 'w')
+ return syms
+
+def GetSymbolAddress(fname, sym_name):
+ """Get a value of a symbol from an ELF file
+
+ Args:
+ fname: Filename of the ELF file to read
+ patterns: List of regex patterns to search for, each a string
+
+ Returns:
+ Symbol value (as an integer) or None if not found
+ """
+ syms = GetSymbols(fname, [sym_name])
+ sym = syms.get(sym_name)
+ if not sym:
+ return None
+ return sym.address
+
+def LookupAndWriteSymbols(elf_fname, entry, image):
+ """Replace all symbols in an entry with their correct values
+
+ The entry contents is updated so that values for referenced symbols will be
+ visible at run time. This is done by finding out the symbols positions in
+ the entry (using the ELF file) and replacing them with values from binman's
+ data structures.
+
+ Args:
+ elf_fname: Filename of ELF image containing the symbol information for
+ entry
+ entry: Entry to process
+ image: Image which can be used to lookup symbol values
+ """
+ fname = tools.GetInputFilename(elf_fname)
+ syms = GetSymbols(fname, ['image', 'binman'])
+ if not syms:
+ return
+ base = syms.get('__image_copy_start')
+ if not base:
+ return
+ for name, sym in syms.iteritems():
+ if name.startswith('_binman'):
+ msg = ("Image '%s': Symbol '%s'\n in entry '%s'" %
+ (image.GetPath(), name, entry.GetPath()))
+ offset = sym.address - base.address
+ if offset < 0 or offset + sym.size > entry.contents_size:
+ raise ValueError('%s has offset %x (size %x) but the contents '
+ 'size is %x' % (entry.GetPath(), offset,
+ sym.size, entry.contents_size))
+ if sym.size == 4:
+ pack_string = '<I'
+ elif sym.size == 8:
+ pack_string = '<Q'
+ else:
+ raise ValueError('%s has size %d: only 4 and 8 are supported' %
+ (msg, sym.size))
+
+ # Look up the symbol in our entry tables.
+ value = image.LookupSymbol(name, sym.weak, msg)
+ if value is not None:
+ value += base.address
+ else:
+ value = -1
+ pack_string = pack_string.lower()
+ value_bytes = struct.pack(pack_string, value)
+ if debug:
+ print('%s:\n insert %s, offset %x, value %x, length %d' %
+ (msg, name, offset, value, len(value_bytes)))
+ entry.data = (entry.data[:offset] + value_bytes +
+ entry.data[offset + sym.size:])
--- /dev/null
+#
+# Copyright (c) 2017 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the elf module
+
+from contextlib import contextmanager
+import os
+import sys
+import unittest
+
+try:
+ from StringIO import StringIO
+except ImportError:
+ from io import StringIO
+
+import elf
+
+binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+
+# Use this to suppress stdout/stderr output:
+# with capture_sys_output() as (stdout, stderr)
+# ...do something...
+@contextmanager
+def capture_sys_output():
+ capture_out, capture_err = StringIO(), StringIO()
+ old_out, old_err = sys.stdout, sys.stderr
+ try:
+ sys.stdout, sys.stderr = capture_out, capture_err
+ yield capture_out, capture_err
+ finally:
+ sys.stdout, sys.stderr = old_out, old_err
+
+
+class FakeEntry:
+ def __init__(self, contents_size):
+ self.contents_size = contents_size
+ self.data = 'a' * contents_size
+
+ def GetPath(self):
+ return 'entry_path'
+
+class FakeImage:
+ def __init__(self, sym_value=1):
+ self.sym_value = sym_value
+
+ def GetPath(self):
+ return 'image_path'
+
+ def LookupSymbol(self, name, weak, msg):
+ return self.sym_value
+
+class TestElf(unittest.TestCase):
+ def testAllSymbols(self):
+ fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
+ syms = elf.GetSymbols(fname, [])
+ self.assertIn('.ucode', syms)
+
+ def testRegexSymbols(self):
+ fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
+ syms = elf.GetSymbols(fname, ['ucode'])
+ self.assertIn('.ucode', syms)
+ syms = elf.GetSymbols(fname, ['missing'])
+ self.assertNotIn('.ucode', syms)
+ syms = elf.GetSymbols(fname, ['missing', 'ucode'])
+ self.assertIn('.ucode', syms)
+
+ def testMissingFile(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols('missing-file', entry, image)
+ self.assertIn("Filename 'missing-file' not found in input path",
+ str(e.exception))
+
+ def testOutsideFile(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertIn('entry_path has offset 4 (size 8) but the contents size '
+ 'is a', str(e.exception))
+
+ def testMissingImageStart(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_bad')
+ self.assertEqual(elf.LookupAndWriteSymbols(elf_fname, entry, image),
+ None)
+
+ def testBadSymbolSize(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_size')
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertIn('has size 1: only 4 and 8 are supported',
+ str(e.exception))
+
+ def testNoValue(self):
+ entry = FakeEntry(20)
+ image = FakeImage(sym_value=None)
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertEqual(chr(255) * 16 + 'a' * 4, entry.data)
+
+ def testDebug(self):
+ elf.debug = True
+ entry = FakeEntry(20)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ with capture_sys_output() as (stdout, stderr):
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ elf.debug = False
+ self.assertTrue(len(stdout.getvalue()) > 0)
+
+
+if __name__ == '__main__':
+ unittest.main()
# Test for the Entry class
import collections
+import os
+import sys
import unittest
-import entry
+import fdt
+import fdt_util
+import tools
class TestEntry(unittest.TestCase):
+ def GetNode(self):
+ binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+ tools.PrepareOutputDir(None)
+ fname = fdt_util.EnsureCompiled(
+ os.path.join(binman_dir,('test/05_simple.dts')))
+ dtb = fdt.FdtScan(fname)
+ return dtb.GetNode('/binman/u-boot')
+
+ def test1EntryNoImportLib(self):
+ """Test that we can import Entry subclassess successfully"""
+
+ sys.modules['importlib'] = None
+ global entry
+ import entry
+ entry.Entry.Create(None, self.GetNode(), 'u-boot')
+
+ def test2EntryImportLib(self):
+ del sys.modules['importlib']
+ global entry
+ reload(entry)
+ entry.Entry.Create(None, self.GetNode(), 'u-boot-spl')
+ tools._RemoveOutputDir()
+ del entry
+
def testEntryContents(self):
"""Test the Entry bass class"""
+ import entry
base_entry = entry.Entry(None, None, None, read_node=False)
self.assertEqual(True, base_entry.ObtainContents())
def testUnknownEntry(self):
"""Test that unknown entry types are detected"""
+ import entry
Node = collections.namedtuple('Node', ['name', 'path'])
node = Node('invalid-name', 'invalid-path')
with self.assertRaises(ValueError) as e:
entry.Entry.Create(None, node, node.name)
self.assertIn("Unknown entry type 'invalid-name' in node "
"'invalid-path'", str(e.exception))
+
+
+if __name__ == "__main__":
+ unittest.main()
def ProcessContents(self):
pass
+
+ def WriteSymbols(self, image):
+ """Write symbol values into binary files for access at run time
+
+ Args:
+ image: Image containing the entry
+ """
+ pass
# Entry-type module for spl/u-boot-spl.bin
#
+import elf
+
from entry import Entry
from blob import Entry_blob
class Entry_u_boot_spl(Entry_blob):
def __init__(self, image, etype, node):
Entry_blob.__init__(self, image, etype, node)
+ self.elf_fname = 'spl/u-boot-spl'
def GetDefaultFilename(self):
return 'spl/u-boot-spl.bin'
+
+ def WriteSymbols(self, image):
+ elf.LookupAndWriteSymbols(self.elf_fname, self, image)
#
import command
+import elf
from entry import Entry
from blob import Entry_blob
import tools
def ObtainContents(self):
fname = tools.GetInputFilename('spl/u-boot-spl')
- args = [['nm', fname], ['grep', '__bss_size']]
- out = command.RunPipe(args, capture=True).stdout.splitlines()
- bss_size = int(out[0].split()[0], 16)
+ bss_size = elf.GetSymbolAddress(fname, '__bss_size')
+ if not bss_size:
+ self.Raise('Expected __bss_size symbol in spl/u-boot-spl')
self.data = chr(0) * bss_size
self.contents_size = bss_size
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot device tree
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl_dtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl.dtb'
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for 'u-boot-nodtb.bin'
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl_nodtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl-nodtb.bin'
self.elf_fname = 'spl/u-boot-spl'
def GetDefaultFilename(self):
- return 'spl/u-boot-spl.bin'
+ return 'spl/u-boot-spl-nodtb.bin'
def ObtainContents(self):
# If the image does not need microcode, there is nothing to do
ucode_dest_entry = self.image.FindEntryType('u-boot-with-ucode-ptr')
- if ucode_dest_entry and not ucode_dest_entry.target_pos:
- self.data = ''
- return True
-
- # Handle microcode in SPL image as well
- ucode_dest_entry = self.image.FindEntryType('u-boot-spl-with-ucode-ptr')
- if ucode_dest_entry and not ucode_dest_entry.target_pos:
+ ucode_dest_entry_spl = self.image.FindEntryType(
+ 'u-boot-spl-with-ucode-ptr')
+ if ((not ucode_dest_entry or not ucode_dest_entry.target_pos) and
+ (not ucode_dest_entry_spl or not ucode_dest_entry_spl.target_pos)):
self.data = ''
return True
import struct
import command
+import elf
from entry import Entry
from blob import Entry_blob
import fdt_util
def ObtainContents(self):
# Figure out where to put the microcode pointer
fname = tools.GetInputFilename(self.elf_fname)
- args = [['nm', fname], ['grep', '-w', '_dt_ucode_base_size']]
- out = (command.RunPipe(args, capture=True, raise_on_error=False).
- stdout.splitlines())
- if len(out) == 1:
- self.target_pos = int(out[0].split()[0], 16)
+ sym = elf.GetSymbolAddress(fname, '_dt_ucode_base_size')
+ if sym:
+ self.target_pos = sym
elif not fdt_util.GetBool(self._node, 'optional-ucode'):
self.Raise('Cannot locate _dt_ucode_base_size symbol in u-boot')
import cmdline
import command
import control
-import entry
+import elf
import fdt
import fdt_util
import tools
import tout
# Contents of test files, corresponding to different entry types
-U_BOOT_DATA = '1234'
-U_BOOT_IMG_DATA = 'img'
-U_BOOT_SPL_DATA = '567'
-BLOB_DATA = '89'
-ME_DATA = '0abcd'
-VGA_DATA = 'vga'
-U_BOOT_DTB_DATA = 'udtb'
-X86_START16_DATA = 'start16'
-U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
-FSP_DATA = 'fsp'
-CMC_DATA = 'cmc'
-VBT_DATA = 'vbt'
+U_BOOT_DATA = '1234'
+U_BOOT_IMG_DATA = 'img'
+U_BOOT_SPL_DATA = '56780123456789abcde'
+BLOB_DATA = '89'
+ME_DATA = '0abcd'
+VGA_DATA = 'vga'
+U_BOOT_DTB_DATA = 'udtb'
+U_BOOT_SPL_DTB_DATA = 'spldtb'
+X86_START16_DATA = 'start16'
+X86_START16_SPL_DATA = 'start16spl'
+U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
+U_BOOT_SPL_NODTB_DATA = 'splnodtb with microcode pointer somewhere in here'
+FSP_DATA = 'fsp'
+CMC_DATA = 'cmc'
+VBT_DATA = 'vbt'
+MRC_DATA = 'mrc'
class TestFunctional(unittest.TestCase):
"""Functional tests for binman
"""
@classmethod
def setUpClass(self):
+ global entry
+ import entry
+
# Handle the case where argv[0] is 'python'
self._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
self._binman_pathname = os.path.join(self._binman_dir, 'binman')
TestFunctional._MakeInputFile('me.bin', ME_DATA)
TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-spl.dtb', U_BOOT_SPL_DTB_DATA)
TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin',
+ X86_START16_SPL_DATA)
TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-spl-nodtb.bin',
+ U_BOOT_SPL_NODTB_DATA)
TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
+ TestFunctional._MakeInputFile('mrc.bin', MRC_DATA)
self._output_setup = False
# ELF file with a '_dt_ucode_base_size' symbol
Returns:
Return value (0 for success)
"""
- (options, args) = cmdline.ParseArgs(list(args))
+ args = list(args)
+ if '-D' in sys.argv:
+ args = args + ['-D']
+ (options, args) = cmdline.ParseArgs(args)
options.pager = 'binman-invalid-pager'
options.build_dir = self._indir
# options.verbosity = tout.DEBUG
return control.Binman(options, args)
- def _DoTestFile(self, fname):
+ def _DoTestFile(self, fname, debug=False):
"""Run binman with a given test file
Args:
fname: Device tree source filename to use (e.g. 05_simple.dts)
"""
- return self._DoBinman('-p', '-I', self._indir,
- '-d', self.TestFile(fname))
+ args = ['-p', '-I', self._indir, '-d', self.TestFile(fname)]
+ if debug:
+ args.append('-D')
+ return self._DoBinman(*args)
def _SetupDtb(self, fname, outfile='u-boot.dtb'):
"""Set up a new test device-tree file
self.assertEqual(0, len(result.stderr))
self.assertEqual(0, result.return_code)
- # Not yet available.
def testBoard(self):
"""Test that we can run it with a specific board"""
self._SetupDtb('05_simple.dts', 'sandbox/u-boot.dtb')
data = self._DoReadFile('05_simple.dts')
self.assertEqual(U_BOOT_DATA, data)
+ def testSimpleDebug(self):
+ """Test a simple binman run with debugging enabled"""
+ data = self._DoTestFile('05_simple.dts', debug=True)
+
def testDual(self):
"""Test that we can handle creating two images
def testImagePadByte(self):
"""Test that the image pad byte can be specified"""
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
data = self._DoReadFile('21_image_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 9) + U_BOOT_DATA, data)
+ self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 1) + U_BOOT_DATA, data)
def testImageName(self):
"""Test that image files can be named"""
def testPackSorted(self):
"""Test that entries can be sorted"""
data = self._DoReadFile('24_sorted.dts')
- self.assertEqual(chr(0) * 5 + U_BOOT_SPL_DATA + chr(0) * 2 +
+ self.assertEqual(chr(0) * 1 + U_BOOT_SPL_DATA + chr(0) * 2 +
U_BOOT_DATA, data)
def testPackZeroPosition(self):
with self.assertRaises(ValueError) as e:
self._DoTestFile('28_pack_4gb_outside.dts')
self.assertIn("Node '/binman/u-boot': Position 0x0 (0) is outside "
- "the image starting at 0xfffffff0 (4294967280)",
+ "the image starting at 0xffffffe0 (4294967264)",
str(e.exception))
def testPackX86Rom(self):
"""Test that a basic x86 ROM can be created"""
data = self._DoReadFile('29_x86-rom.dts')
- self.assertEqual(U_BOOT_DATA + chr(0) * 3 + U_BOOT_SPL_DATA +
- chr(0) * 6, data)
+ self.assertEqual(U_BOOT_DATA + chr(0) * 7 + U_BOOT_SPL_DATA +
+ chr(0) * 2, data)
def testPackX86RomMeNoDesc(self):
"""Test that an invalid Intel descriptor entry is detected"""
data = self._DoReadFile('33_x86-start16.dts')
self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)])
- def testPackUbootMicrocode(self):
- """Test that x86 microcode can be handled correctly
-
- We expect to see the following in the image, in order:
- u-boot-nodtb.bin with a microcode pointer inserted at the correct
- place
- u-boot.dtb with the microcode removed
- the microcode
- """
- data = self._DoReadFile('34_x86_ucode.dts', True)
+ def _RunMicrocodeTest(self, dts_fname, nodtb_data):
+ data = self._DoReadFile(dts_fname, True)
# Now check the device tree has no microcode
- second = data[len(U_BOOT_NODTB_DATA):]
+ second = data[len(nodtb_data):]
fname = tools.GetOutputFilename('test.dtb')
with open(fname, 'wb') as fd:
fd.write(second)
# Check that the microcode appears immediately after the Fdt
# This matches the concatenation of the data properties in
- # the /microcode/update@xxx nodes in x86_ucode.dts.
+ # the /microcode/update@xxx nodes in 34_x86_ucode.dts.
ucode_data = struct.pack('>4L', 0x12345678, 0x12345679, 0xabcd0000,
0x78235609)
self.assertEqual(ucode_data, third[:len(ucode_data)])
- ucode_pos = len(U_BOOT_NODTB_DATA) + fdt_len
+ ucode_pos = len(nodtb_data) + fdt_len
# Check that the microcode pointer was inserted. It should match the
# expected position and size
pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
len(ucode_data))
- first = data[:len(U_BOOT_NODTB_DATA)]
+ first = data[:len(nodtb_data)]
+ return first, pos_and_size
+
+ def testPackUbootMicrocode(self):
+ """Test that x86 microcode can be handled correctly
+
+ We expect to see the following in the image, in order:
+ u-boot-nodtb.bin with a microcode pointer inserted at the correct
+ place
+ u-boot.dtb with the microcode removed
+ the microcode
+ """
+ first, pos_and_size = self._RunMicrocodeTest('34_x86_ucode.dts',
+ U_BOOT_NODTB_DATA)
self.assertEqual('nodtb with microcode' + pos_and_size +
' somewhere in here', first)
"""Test that an image with a VBT binary can be created"""
data = self._DoReadFile('46_intel-vbt.dts')
self.assertEqual(VBT_DATA, data[:len(VBT_DATA)])
+
+ def testSplBssPad(self):
+ """Test that we can pad SPL's BSS with zeros"""
+ # ELF file with a '__bss_size' symbol
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ data = self._DoReadFile('47_spl_bss_pad.dts')
+ self.assertEqual(U_BOOT_SPL_DATA + (chr(0) * 10) + U_BOOT_DATA, data)
+
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('47_spl_bss_pad.dts')
+ self.assertIn('Expected __bss_size symbol in spl/u-boot-spl',
+ str(e.exception))
+
+ def testPackStart16Spl(self):
+ """Test that an image with an x86 start16 region can be created"""
+ data = self._DoReadFile('48_x86-start16-spl.dts')
+ self.assertEqual(X86_START16_SPL_DATA, data[:len(X86_START16_SPL_DATA)])
+
+ def testPackUbootSplMicrocode(self):
+ """Test that x86 microcode can be handled correctly in SPL
+
+ We expect to see the following in the image, in order:
+ u-boot-spl-nodtb.bin with a microcode pointer inserted at the
+ correct place
+ u-boot.dtb with the microcode removed
+ the microcode
+ """
+ # ELF file with a '_dt_ucode_base_size' symbol
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ first, pos_and_size = self._RunMicrocodeTest('49_x86_ucode_spl.dts',
+ U_BOOT_SPL_NODTB_DATA)
+ self.assertEqual('splnodtb with microc' + pos_and_size +
+ 'ter somewhere in here', first)
+
+ def testPackMrc(self):
+ """Test that an image with an MRC binary can be created"""
+ data = self._DoReadFile('50_intel_mrc.dts')
+ self.assertEqual(MRC_DATA, data[:len(MRC_DATA)])
+
+ def testSplDtb(self):
+ """Test that an image with spl/u-boot-spl.dtb can be created"""
+ data = self._DoReadFile('51_u_boot_spl_dtb.dts')
+ self.assertEqual(U_BOOT_SPL_DTB_DATA, data[:len(U_BOOT_SPL_DTB_DATA)])
+
+ def testSplNoDtb(self):
+ """Test that an image with spl/u-boot-spl-nodtb.bin can be created"""
+ data = self._DoReadFile('52_u_boot_spl_nodtb.dts')
+ self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)])
+
+ def testSymbols(self):
+ """Test binman can assign symbols embedded in U-Boot"""
+ elf_fname = self.TestFile('u_boot_binman_syms')
+ syms = elf.GetSymbols(elf_fname, ['binman', 'image'])
+ addr = elf.GetSymbolAddress(elf_fname, '__image_copy_start')
+ self.assertEqual(syms['_binman_u_boot_spl_prop_pos'].address, addr)
+
+ with open(self.TestFile('u_boot_binman_syms')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ data = self._DoReadFile('53_symbols.dts')
+ sym_values = struct.pack('<LQL', 0x24 + 0, 0x24 + 24, 0x24 + 20)
+ expected = (sym_values + U_BOOT_SPL_DATA[16:] + chr(0xff) +
+ U_BOOT_DATA +
+ sym_values + U_BOOT_SPL_DATA[16:])
+ self.assertEqual(expected, data)
+
+
+if __name__ == "__main__":
+ unittest.main()
# Class for an image, the output of binman
#
+from __future__ import print_function
+
from collections import OrderedDict
from operator import attrgetter
+import re
+import sys
-import entry
-from entry import Entry
import fdt_util
import tools
address.
_entries: OrderedDict() of entries
"""
- def __init__(self, name, node):
+ def __init__(self, name, node, test=False):
+ global entry
+ global Entry
+ import entry
+ from entry import Entry
+
self._node = node
self._name = name
self._size = None
self._end_4gb = False
self._entries = OrderedDict()
- self._ReadNode()
- self._ReadEntries()
+ if not test:
+ self._ReadNode()
+ self._ReadEntries()
def _ReadNode(self):
"""Read properties from the image node"""
"""
raise ValueError("Image '%s': %s" % (self._node.path, msg))
+ def GetPath(self):
+ """Get the path of an image (in the FDT)
+
+ Returns:
+ Full path of the node for this image
+ """
+ return self._node.path
+
def _ReadEntries(self):
for node in self._node.subnodes:
self._entries[node.name] = Entry.Create(self, node)
for entry in self._entries.values():
entry.ProcessContents()
+ def WriteSymbols(self):
+ """Write symbol values into binary files for access at run time"""
+ for entry in self._entries.values():
+ entry.WriteSymbols(self)
+
def BuildImage(self):
"""Write the image to a file"""
fname = tools.GetOutputFilename(self._filename)
data = entry.GetData()
fd.seek(self._pad_before + entry.pos - self._skip_at_start)
fd.write(data)
+
+ def LookupSymbol(self, sym_name, optional, msg):
+ """Look up a symbol in an ELF file
+
+ Looks up a symbol in an ELF file. Only entry types which come from an
+ ELF image can be used by this function.
+
+ At present the only entry property supported is pos.
+
+ Args:
+ sym_name: Symbol name in the ELF file to look up in the format
+ _binman_<entry>_prop_<property> where <entry> is the name of
+ the entry and <property> is the property to find (e.g.
+ _binman_u_boot_prop_pos). As a special case, you can append
+ _any to <entry> to have it search for any matching entry. E.g.
+ _binman_u_boot_any_prop_pos will match entries called u-boot,
+ u-boot-img and u-boot-nodtb)
+ optional: True if the symbol is optional. If False this function
+ will raise if the symbol is not found
+ msg: Message to display if an error occurs
+
+ Returns:
+ Value that should be assigned to that symbol, or None if it was
+ optional and not found
+
+ Raises:
+ ValueError if the symbol is invalid or not found, or references a
+ property which is not supported
+ """
+ m = re.match(r'^_binman_(\w+)_prop_(\w+)$', sym_name)
+ if not m:
+ raise ValueError("%s: Symbol '%s' has invalid format" %
+ (msg, sym_name))
+ entry_name, prop_name = m.groups()
+ entry_name = entry_name.replace('_', '-')
+ entry = self._entries.get(entry_name)
+ if not entry:
+ if entry_name.endswith('-any'):
+ root = entry_name[:-4]
+ for name in self._entries:
+ if name.startswith(root):
+ rest = name[len(root):]
+ if rest in ['', '-img', '-nodtb']:
+ entry = self._entries[name]
+ if not entry:
+ err = ("%s: Entry '%s' not found in list (%s)" %
+ (msg, entry_name, ','.join(self._entries.keys())))
+ if optional:
+ print('Warning: %s' % err, file=sys.stderr)
+ return None
+ raise ValueError(err)
+ if prop_name == 'pos':
+ return entry.pos
+ else:
+ raise ValueError("%s: No such property '%s'" % (msg, prop_name))
--- /dev/null
+#
+# Copyright (c) 2017 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the image module
+
+import unittest
+
+from image import Image
+from elf_test import capture_sys_output
+
+class TestImage(unittest.TestCase):
+ def testInvalidFormat(self):
+ image = Image('name', 'node', test=True)
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_something_prop_', False, 'msg')
+ self.assertIn(
+ "msg: Symbol '_binman_something_prop_' has invalid format",
+ str(e.exception))
+
+ def testMissingSymbol(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {}
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_type_prop_pname', False, 'msg')
+ self.assertIn("msg: Entry 'type' not found in list ()",
+ str(e.exception))
+
+ def testMissingSymbolOptional(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {}
+ with capture_sys_output() as (stdout, stderr):
+ val = image.LookupSymbol('_binman_type_prop_pname', True, 'msg')
+ self.assertEqual(val, None)
+ self.assertEqual("Warning: msg: Entry 'type' not found in list ()\n",
+ stderr.getvalue())
+ self.assertEqual('', stdout.getvalue())
+
+ def testBadProperty(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {'u-boot': 1}
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_u_boot_prop_bad', False, 'msg')
+ self.assertIn("msg: No such property 'bad", str(e.exception))
};
u-boot {
- pos = <12>;
+ pos = <20>;
};
};
};
binman {
sort-by-pos;
u-boot {
- pos = <10>;
+ pos = <22>;
};
u-boot-spl {
- pos = <5>;
+ pos = <1>;
};
};
};
binman {
sort-by-pos;
end-at-4gb;
- size = <16>;
+ size = <32>;
u-boot {
pos = <0>;
};
u-boot-spl {
- pos = <0xfffffff7>;
+ pos = <0xffffffeb>;
};
};
};
binman {
sort-by-pos;
end-at-4gb;
- size = <16>;
+ size = <32>;
u-boot {
- pos = <0xfffffff0>;
+ pos = <0xffffffe0>;
};
u-boot-spl {
- pos = <0xfffffff7>;
+ pos = <0xffffffeb>;
};
};
};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-spl {
+ };
+
+ u-boot-spl-bss-pad {
+ };
+
+ u-boot {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ x86-start16-spl {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-spl-with-ucode-ptr {
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ intel-mrc {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ u-boot-spl-dtb {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-spl-nodtb {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+
+ u-boot {
+ pos = <20>;
+ };
+
+ u-boot-spl2 {
+ type = "u-boot-spl";
+ };
+ };
+};
--- /dev/null
+#
+# Builds test programs
+#
+# Copyright (C) 2017 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CFLAGS := -march=i386 -m32 -nostdlib -I ../../../include
+
+LDS_UCODE := -T u_boot_ucode_ptr.lds
+LDS_BINMAN := -T u_boot_binman_syms.lds
+LDS_BINMAN_BAD := -T u_boot_binman_syms_bad.lds
+
+TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \
+ u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \
+ u_boot_binman_syms_size
+
+all: $(TARGETS)
+
+u_boot_no_ucode_ptr: CFLAGS += $(LDS_UCODE)
+u_boot_no_ucode_ptr: u_boot_no_ucode_ptr.c
+
+u_boot_ucode_ptr: CFLAGS += $(LDS_UCODE)
+u_boot_ucode_ptr: u_boot_ucode_ptr.c
+
+bss_data: CFLAGS += bss_data.lds
+bss_data: bss_data.c
+
+u_boot_binman_syms.bin: u_boot_binman_syms
+ objcopy -O binary $< -R .note.gnu.build-id $@
+
+u_boot_binman_syms: CFLAGS += $(LDS_BINMAN)
+u_boot_binman_syms: u_boot_binman_syms.c
+
+u_boot_binman_syms_bad: CFLAGS += $(LDS_BINMAN_BAD)
+u_boot_binman_syms_bad: u_boot_binman_syms_bad.c
+
+u_boot_binman_syms_size: CFLAGS += $(LDS_BINMAN)
+u_boot_binman_syms_size: u_boot_binman_syms_size.c
+
+clean:
+ rm -f $(TARGETS)
+
+help:
+ @echo "Makefile for binman test programs"
+ @echo
+ @echo "Intended for use on x86 hosts"
+ @echo
+ @echo "Targets:"
+ @echo
+ @echo -e "\thelp - Print help (this is it!)"
+ @echo -e "\tall - Builds test programs (default targget)"
+ @echo -e "\tclean - Delete output files"
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create a _dt_ucode_base_size symbol which can be read
+ * by binutils. This is used by binman tests.
+ */
+
+int bss_data[10];
+int __bss_size = sizeof(bss_data);
+
+int main()
+{
+ bss_data[2] = 2;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0xfffffdf0;
+ _start = .;
+ __bss_size = 10;
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create some binman symbols. This is used by binman tests.
+ */
+
+#define CONFIG_BINMAN
+#include <binman_sym.h>
+
+binman_sym_declare(unsigned long, u_boot_spl, pos);
+binman_sym_declare(unsigned long long, u_boot_spl2, pos);
+binman_sym_declare(unsigned long, u_boot_any, pos);
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
+}
--- /dev/null
+u_boot_binman_syms.c
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create some binman symbols. This is used by binman tests.
+ */
+
+#define CONFIG_BINMAN
+#include <binman_sym.h>
+
+binman_sym_declare(char, u_boot_spl, pos);
*
* Simple program to create a bad _dt_ucode_base_size symbol to create an
* error when it is used. This is used by binman tests.
- *
- * Build with:
- * cc -march=i386 -m32 -o u_boot_no_ucode_ptr -T u_boot_ucode_ptr.lds \
- -nostdlib u_boot_no_ucode_ptr.c
*/
static unsigned long not__dt_ucode_base_size[2]
* SPDX-License-Identifier: GPL-2.0+
*
* Simple program to create a _dt_ucode_base_size symbol which can be read
- * by 'nm'. This is used by binman tests.
- *
- * Build with:
- * cc -march=i386 -m32 -o u_boot_ucode_ptr -T u_boot_ucode_ptr.lds -nostdlib \
- u_boot_ucode_ptr.c
+ * by binutils. This is used by binman tests.
*/
static unsigned long _dt_ucode_base_size[2]
import terminal
import toolchain
-def RunTests():
+def RunTests(skip_net_tests):
import func_test
import test
import doctest
suite.run(result)
sys.argv = [sys.argv[0]]
+ if skip_net_tests:
+ test.use_network = False
for module in (test.TestBuild, func_test.TestFunctional):
suite = unittest.TestLoader().loadTestsFromTestCase(module)
suite.run(result)
# Run our meagre tests
if options.test:
- RunTests()
+ RunTests(options.skip_net_tests)
# Build selected commits for selected boards
else:
default=False, help='Show a build summary')
parser.add_option('-S', '--show-sizes', action='store_true',
default=False, help='Show image size variation in summary')
+ parser.add_option('--skip-net-tests', action='store_true', default=False,
+ help='Skip tests which need the network')
parser.add_option('--step', type='int',
default=1, help='Only build every n commits (0=just first and last)')
parser.add_option('-t', '--test', action='store_true', dest='test',
import terminal
import toolchain
+use_network = True
+
settings_data = '''
# Buildman settings file
['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0', ''],
['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''],
['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''],
+ ['Active', 'powerpc', 'mpc83xx', '', 'Tester', 'PowerPC board 2', 'board3', ''],
['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''],
]
def testBoardSingle(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['sandbox']),
- {'all': 1, 'sandbox': 1})
+ {'all': ['board4'], 'sandbox': ['board4']})
def testBoardArch(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['arm']),
- {'all': 2, 'arm': 2})
+ {'all': ['board0', 'board1'],
+ 'arm': ['board0', 'board1']})
def testBoardArchSingle(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['arm sandbox']),
- {'all': 3, 'arm': 2, 'sandbox' : 1})
+ {'sandbox': ['board4'],
+ 'all': ['board0', 'board1', 'board4'],
+ 'arm': ['board0', 'board1']})
+
def testBoardArchSingleMultiWord(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['arm', 'sandbox']),
- {'all': 3, 'arm': 2, 'sandbox' : 1})
+ {'sandbox': ['board4'], 'all': ['board0', 'board1', 'board4'], 'arm': ['board0', 'board1']})
def testBoardSingleAnd(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['Tester & arm']),
- {'all': 2, 'Tester&arm': 2})
+ {'Tester&arm': ['board0', 'board1'], 'all': ['board0', 'board1']})
def testBoardTwoAnd(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['Tester', '&', 'arm',
'Tester' '&', 'powerpc',
'sandbox']),
- {'all': 5, 'Tester&powerpc': 2, 'Tester&arm': 2,
- 'sandbox' : 1})
+ {'sandbox': ['board4'],
+ 'all': ['board0', 'board1', 'board2', 'board3',
+ 'board4'],
+ 'Tester&powerpc': ['board2', 'board3'],
+ 'Tester&arm': ['board0', 'board1']})
def testBoardAll(self):
"""Test single board selection"""
- self.assertEqual(self.boards.SelectBoards([]), {'all': 5})
+ self.assertEqual(self.boards.SelectBoards([]),
+ {'all': ['board0', 'board1', 'board2', 'board3',
+ 'board4']})
def testBoardRegularExpression(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['T.*r&^Po']),
- {'T.*r&^Po': 2, 'all': 2})
+ {'all': ['board2', 'board3'],
+ 'T.*r&^Po': ['board2', 'board3']})
def testBoardDuplicate(self):
"""Test single board selection"""
self.assertEqual(self.boards.SelectBoards(['sandbox sandbox',
'sandbox']),
- {'all': 1, 'sandbox': 1})
+ {'all': ['board4'], 'sandbox': ['board4']})
def CheckDirs(self, build, dirname):
self.assertEqual('base%s' % dirname, build._GetOutputDir(1))
self.assertEqual('base%s/fred' % dirname,
def testToolchainDownload(self):
"""Test that we can download toolchains"""
- self.assertEqual('https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_arm-unknown-linux-gnueabi.tar.xz',
- self.toolchains.LocateArchUrl('arm'))
+ if use_network:
+ self.assertEqual('https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_arm-unknown-linux-gnueabi.tar.xz',
+ self.toolchains.LocateArchUrl('arm'))
if __name__ == "__main__":
search_list = []
for path in search_paths:
search_list.extend(['-i', path])
- args = ['-I', 'dts', '-o', dtb_output, '-O', 'dtb']
+ args = ['-I', 'dts', '-o', dtb_output, '-O', 'dtb',
+ '-W', 'no-unit_address_vs_reg']
args.extend(search_list)
args.append(dts_input)
command.Run('dtc', *args)
our_path = os.path.dirname(os.path.realpath(__file__))
+HEADER = '''/*
+ * DO NOT MODIFY
+ *
+ * This file was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <stdbool.h>
+#include <libfdt.h>'''
+
+C_HEADER = '''/*
+ * DO NOT MODIFY
+ *
+ * This file was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+'''
+
+
def get_dtb_file(dts_fname):
"""Compile a .dts file to a .dtb
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
lines = infile.read().splitlines()
- self.assertEqual(['#include <stdbool.h>', '#include <libfdt.h>'], lines)
+ self.assertEqual(HEADER.splitlines(), lines)
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
lines = infile.read().splitlines()
- self.assertEqual(['#include <common.h>', '#include <dm.h>',
- '#include <dt-structs.h>', ''], lines)
+ self.assertEqual(C_HEADER.splitlines() + [''], lines)
def test_simple(self):
"""Test output from some simple nodes with various types of data"""
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_sandbox_i2c_test {
};
struct dtd_sandbox_pmic_test {
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_sandbox_spl_test dtv_spl_test = {
\t.bytearray\t\t= {0x6, 0x0, 0x0},
\t.byteval\t\t= 0x5,
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_source {
\tstruct phandle_2_arg clocks[4];
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_target dtv_phandle_target = {
\t.intval\t\t\t= 0x0,
};
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_compat1 {
\tfdt32_t\t\tintval;
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_compat1 dtv_spl_test = {
\t.intval\t\t\t= 0x1,
};
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_test1 {
\tfdt64_t\t\treg[2];
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_test1 dtv_test1 = {
\t.reg\t\t\t= {0x1234, 0x5678},
};
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_test1 {
\tfdt32_t\t\treg[2];
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_test1 dtv_test1 = {
\t.reg\t\t\t= {0x1234, 0x5678},
};
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_test1 {
\tfdt64_t\t\treg[2];
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_test1 dtv_test1 = {
\t.reg\t\t\t= {0x123400000000, 0x5678},
};
dtb_platdata.run_steps(['struct'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <stdbool.h>
-#include <libfdt.h>
+ self.assertEqual(HEADER + '''
struct dtd_test1 {
\tfdt64_t\t\treg[2];
};
dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
with open(output) as infile:
data = infile.read()
- self.assertEqual('''#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
+ self.assertEqual(C_HEADER + '''
static struct dtd_test1 dtv_test1 = {
\t.reg\t\t\t= {0x1234, 0x567800000000},
};
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <unistd.h>
+#include <dirent.h>
#ifdef MTD_OLD
# include <stdint.h>
# include <mtd/mtd-user.h>
#endif
+#include <mtd/ubi-user.h>
+
#include "fw_env_private.h"
#include "fw_env.h"
ulong erase_size; /* device erase size */
ulong env_sectors; /* number of environment sectors */
uint8_t mtd_type; /* type of the MTD device */
+ int is_ubi; /* set if we use UBI volume */
};
static struct envdev_s envdevices[2] =
#define DEVESIZE(i) envdevices[(i)].erase_size
#define ENVSECTORS(i) envdevices[(i)].env_sectors
#define DEVTYPE(i) envdevices[(i)].mtd_type
+#define IS_UBI(i) envdevices[(i)].is_ubi
#define CUR_ENVSIZE ENVSIZE(dev_current)
#define DEFAULT_ENV_INSTANCE_STATIC
#include <env_default.h>
+#define UBI_DEV_START "/dev/ubi"
+#define UBI_SYSFS "/sys/class/ubi"
+#define UBI_VOL_NAME_PATT "ubi%d_%d"
+
+static int is_ubi_devname(const char *devname)
+{
+ return !strncmp(devname, UBI_DEV_START, sizeof(UBI_DEV_START) - 1);
+}
+
+static int ubi_check_volume_sysfs_name(const char *volume_sysfs_name,
+ const char *volname)
+{
+ char path[256];
+ FILE *file;
+ char *name;
+ int ret;
+
+ strcpy(path, UBI_SYSFS "/");
+ strcat(path, volume_sysfs_name);
+ strcat(path, "/name");
+
+ file = fopen(path, "r");
+ if (!file)
+ return -1;
+
+ ret = fscanf(file, "%ms", &name);
+ fclose(file);
+ if (ret <= 0 || !name) {
+ fprintf(stderr,
+ "Failed to read from file %s, ret = %d, name = %s\n",
+ path, ret, name);
+ return -1;
+ }
+
+ if (!strcmp(name, volname)) {
+ free(name);
+ return 0;
+ }
+ free(name);
+
+ return -1;
+}
+
+static int ubi_get_volnum_by_name(int devnum, const char *volname)
+{
+ DIR *sysfs_ubi;
+ struct dirent *dirent;
+ int ret;
+ int tmp_devnum;
+ int volnum;
+
+ sysfs_ubi = opendir(UBI_SYSFS);
+ if (!sysfs_ubi)
+ return -1;
+
+#ifdef DEBUG
+ fprintf(stderr, "Looking for volume name \"%s\"\n", volname);
+#endif
+
+ while (1) {
+ dirent = readdir(sysfs_ubi);
+ if (!dirent)
+ return -1;
+
+ ret = sscanf(dirent->d_name, UBI_VOL_NAME_PATT,
+ &tmp_devnum, &volnum);
+ if (ret == 2 && devnum == tmp_devnum) {
+ if (ubi_check_volume_sysfs_name(dirent->d_name,
+ volname) == 0)
+ return volnum;
+ }
+ }
+
+ return -1;
+}
+
+static int ubi_get_devnum_by_devname(const char *devname)
+{
+ int devnum;
+ int ret;
+
+ ret = sscanf(devname + sizeof(UBI_DEV_START) - 1, "%d", &devnum);
+ if (ret != 1)
+ return -1;
+
+ return devnum;
+}
+
+static const char *ubi_get_volume_devname(const char *devname,
+ const char *volname)
+{
+ char *volume_devname;
+ int volnum;
+ int devnum;
+ int ret;
+
+ devnum = ubi_get_devnum_by_devname(devname);
+ if (devnum < 0)
+ return NULL;
+
+ volnum = ubi_get_volnum_by_name(devnum, volname);
+ if (volnum < 0)
+ return NULL;
+
+ ret = asprintf(&volume_devname, "%s_%d", devname, volnum);
+ if (ret < 0)
+ return NULL;
+
+#ifdef DEBUG
+ fprintf(stderr, "Found ubi volume \"%s:%s\" -> %s\n",
+ devname, volname, volume_devname);
+#endif
+
+ return volume_devname;
+}
+
+static void ubi_check_dev(unsigned int dev_id)
+{
+ char *devname = (char *)DEVNAME(dev_id);
+ char *pname;
+ const char *volname = NULL;
+ const char *volume_devname;
+
+ if (!is_ubi_devname(DEVNAME(dev_id)))
+ return;
+
+ IS_UBI(dev_id) = 1;
+
+ for (pname = devname; *pname != '\0'; pname++) {
+ if (*pname == ':') {
+ *pname = '\0';
+ volname = pname + 1;
+ break;
+ }
+ }
+
+ if (volname) {
+ /* Let's find real volume device name */
+ volume_devname = ubi_get_volume_devname(devname, volname);
+ if (!volume_devname) {
+ fprintf(stderr, "Didn't found ubi volume \"%s\"\n",
+ volname);
+ return;
+ }
+
+ free(devname);
+ DEVNAME(dev_id) = volume_devname;
+ }
+}
+
+static int ubi_update_start(int fd, int64_t bytes)
+{
+ if (ioctl(fd, UBI_IOCVOLUP, &bytes))
+ return -1;
+ return 0;
+}
+
+static int ubi_read(int fd, void *buf, size_t count)
+{
+ ssize_t ret;
+
+ while (count > 0) {
+ ret = read(fd, buf, count);
+ if (ret > 0) {
+ count -= ret;
+ buf += ret;
+
+ continue;
+ }
+
+ if (ret == 0) {
+ /*
+ * Happens in case of too short volume data size. If we
+ * return error status we will fail it will be treated
+ * as UBI device error.
+ *
+ * Leave catching this error to CRC check.
+ */
+ fprintf(stderr, "Warning: end of data on ubi volume\n");
+ return 0;
+ } else if (errno == EBADF) {
+ /*
+ * Happens in case of corrupted volume. The same as
+ * above, we cannot return error now, as we will still
+ * be able to successfully write environment later.
+ */
+ fprintf(stderr, "Warning: corrupted volume?\n");
+ return 0;
+ } else if (errno == EINTR) {
+ continue;
+ }
+
+ fprintf(stderr, "Cannot read %u bytes from ubi volume, %s\n",
+ (unsigned int)count, strerror(errno));
+ return -1;
+ }
+
+ return 0;
+}
+
+static int ubi_write(int fd, const void *buf, size_t count)
+{
+ ssize_t ret;
+
+ while (count > 0) {
+ ret = write(fd, buf, count);
+ if (ret <= 0) {
+ if (ret < 0 && errno == EINTR)
+ continue;
+
+ fprintf(stderr, "Cannot write %u bytes to ubi volume\n",
+ (unsigned int)count);
+ return -1;
+ }
+
+ count -= ret;
+ buf += ret;
+ }
+
+ return 0;
+}
+
static int flash_io (int mode);
static int parse_config(struct env_opts *opts);
DEVOFFSET (dev_target), DEVNAME (dev_target));
#endif
+ if (IS_UBI(dev_target)) {
+ if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0)
+ return 0;
+ return ubi_write(fd_target, environment.image, CUR_ENVSIZE);
+ }
+
rc = flash_write_buf(dev_target, fd_target, environment.image,
CUR_ENVSIZE);
if (rc < 0)
{
int rc;
+ if (IS_UBI(dev_current)) {
+ DEVTYPE(dev_current) = MTD_ABSENT;
+
+ return ubi_read(fd, environment.image, CUR_ENVSIZE);
+ }
+
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
DEVTYPE(!dev_current) == MTD_UBIVOLUME) {
environment.flag_scheme = FLAG_INCREMENTAL;
} else if (DEVTYPE(dev_current) == MTD_ABSENT &&
- DEVTYPE(!dev_current) == MTD_ABSENT) {
+ DEVTYPE(!dev_current) == MTD_ABSENT &&
+ IS_UBI(dev_current) == IS_UBI(!dev_current)) {
environment.flag_scheme = FLAG_INCREMENTAL;
} else {
fprintf (stderr, "Incompatible flash types!\n");
static int check_device_config(int dev)
{
struct stat st;
+ int32_t lnum = 0;
int fd, rc = 0;
+ /* Fills in IS_UBI(), converts DEVNAME() with ubi volume name */
+ ubi_check_dev(dev);
+
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
goto err;
}
- if (S_ISCHR(st.st_mode)) {
+ if (IS_UBI(dev)) {
+ rc = ioctl(fd, UBI_IOCEBISMAP, &lnum);
+ if (rc < 0) {
+ fprintf(stderr, "Cannot get UBI information for %s\n",
+ DEVNAME(dev));
+ goto err;
+ }
+ } else if (S_ISCHR(st.st_mode)) {
struct mtd_info_user mtdinfo;
rc = ioctl(fd, MEMGETINFO, &mtdinfo);
if (rc < 0) {
# VFAT example
#/boot/uboot.env 0x0000 0x4000
+
+# UBI volume
+#/dev/ubi0_0 0x0 0x1f000 0x1f000
+#/dev/ubi0_1 0x0 0x1f000 0x1f000
+
+# UBI volume by name
+#/dev/ubi0:env 0x0 0x1f000 0x1f000
+#/dev/ubi0:env-redund 0x0 0x1f000 0x1f000
--- /dev/null
+#include "fdt_host.h"
+#include "../scripts/dtc/libfdt/fdt_wip.c"
#include "gpheader.h"
#include "omapimage.h"
+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
/* Header size is CH header rounded up to 512 bytes plus GP header */
#define OMAP_CH_HDR_SIZE 512
#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE)
do_swap32 = 1;
int swapped = 0;
uint32_t *data = (uint32_t *)ptr;
+ const off_t size_in_words =
+ DIV_ROUND_UP(sbuf->st_size, sizeof(uint32_t));
- while (swapped <= (sbuf->st_size / sizeof(uint32_t))) {
+ while (swapped < size_in_words) {
*data = cpu_to_be32(*data);
swapped++;
data++;
os.remove(expname)
def GetData(self, data_type):
- data='''
-From 4924887af52713cabea78420eff03badea8f0035 Mon Sep 17 00:00:00 2001
+ data='''From 4924887af52713cabea78420eff03badea8f0035 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 7 Apr 2011 10:14:41 -0700
Subject: [PATCH 1/4] Add microsecond boot time measurement
%s
---
README | 11 ++++++++
+ MAINTAINERS | 3 ++
common/bootstage.c | 50 ++++++++++++++++++++++++++++++++++++
include/bootstage.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++
include/common.h | 8 ++++++
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
+diff --git a/MAINTAINERS b/MAINTAINERS
+index b167b028ec..beb7dc634f 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -474,3 +474,8 @@ S: Maintained
+ T: git git://git.denx.de/u-boot.git
+ F: *
+ F: */
++
++BOOTSTAGE
++M: Simon Glass <sjg@chromium.org>
++L: u-boot@lists.denx.de
++F: common/bootstage.c
diff --git a/common/bootstage.c b/common/bootstage.c
new file mode 100644
index 0000000..2234c87
--- /dev/null
+++ b/common/bootstage.c
-@@ -0,0 +1,39 @@
+@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
-+
+/*
+ * This module records the progress of boot and arbitrary commands, and
+ * permits accurate timestamping of each. The records can optionally be
+
+#include <common.h>
+
-+
+struct bootstage_record {
-+ uint32_t time_us;
++ u32 time_us;
+ const char *name;
+};
+
+static struct bootstage_record record[BOOTSTAGE_COUNT];
+
-+uint32_t bootstage_mark(enum bootstage_id id, const char *name)
++u32 bootstage_mark(enum bootstage_id id, const char *name)
+{
+ struct bootstage_record *rec = &record[id];
+
+ /* Only record the first event for each */
+%sif (!rec->name) {
-+ rec->time_us = (uint32_t)timer_get_us();
++ rec->time_us = (u32)timer_get_us();
+ rec->name = name;
+ }
+ if (!rec->name &&
+ %ssomething_else) {
-+ rec->time_us = (uint32_t)timer_get_us();
++ rec->time_us = (u32)timer_get_us();
+ rec->name = name;
+ }
+%sreturn rec->time_us;
self.assertEqual(result.errors, 0)
self.assertEqual(result.warnings, 0)
self.assertEqual(result.checks, 0)
- self.assertEqual(result.lines, 56)
+ self.assertEqual(result.lines, 62)
os.remove(inf)
def testNoSignoff(self):
self.assertEqual(result.errors, 1)
self.assertEqual(result.warnings, 0)
self.assertEqual(result.checks, 0)
- self.assertEqual(result.lines, 56)
+ self.assertEqual(result.lines, 62)
os.remove(inf)
def testSpaces(self):
inf = self.SetupData('spaces')
result = checkpatch.CheckPatch(inf)
self.assertEqual(result.ok, False)
- self.assertEqual(len(result.problems), 2)
+ self.assertEqual(len(result.problems), 3)
self.assertEqual(result.errors, 0)
- self.assertEqual(result.warnings, 2)
+ self.assertEqual(result.warnings, 3)
self.assertEqual(result.checks, 0)
- self.assertEqual(result.lines, 56)
+ self.assertEqual(result.lines, 62)
os.remove(inf)
def testIndent(self):
self.assertEqual(result.errors, 0)
self.assertEqual(result.warnings, 0)
self.assertEqual(result.checks, 1)
- self.assertEqual(result.lines, 56)
+ self.assertEqual(result.lines, 62)
os.remove(inf)
* @spl_hdr: Boot ROM requires a 4-bytes spl header
* @spl_size: Spl size(include extra 4-bytes spl header)
* @spl_rc4: RC4 encode the SPL binary (same key as header)
- * @spl_boot0: A new-style (ARM_SOC_BOOT0_HOOK) image that should
- * have the boot magic (e.g. 'RK33') written to its first
- * word.
*/
struct spl_info {
const char *spl_hdr;
const uint32_t spl_size;
const bool spl_rc4;
- const bool spl_boot0;
};
static struct spl_info spl_infos[] = {
- { "rk3036", "RK30", 0x1000, false, false },
- { "rk3128", "RK31", 0x1800, false, false },
- { "rk3188", "RK31", 0x8000 - 0x800, true, false },
- { "rk322x", "RK32", 0x8000 - 0x1000, false, false },
- { "rk3288", "RK32", 0x8000, false, false },
- { "rk3328", "RK32", 0x8000 - 0x1000, false, false },
- { "rk3368", "RK33", 0x8000 - 0x1000, false, true },
- { "rk3399", "RK33", 0x30000 - 0x2000, false, true },
- { "rv1108", "RK11", 0x1800, false, false},
+ { "rk3036", "RK30", 0x1000, false },
+ { "rk3128", "RK31", 0x1800, false },
+ { "rk3188", "RK31", 0x8000 - 0x800, true },
+ { "rk322x", "RK32", 0x8000 - 0x1000, false },
+ { "rk3288", "RK32", 0x8000, false },
+ { "rk3328", "RK32", 0x8000 - 0x1000, false },
+ { "rk3368", "RK33", 0x8000 - 0x1000, false },
+ { "rk3399", "RK33", 0x30000 - 0x2000, false },
+ { "rv1108", "RK11", 0x1800, false },
};
static unsigned char rc4_key[16] = {
return info->spl_rc4;
}
-bool rkcommon_spl_is_boot0(struct image_tool_params *params)
-{
- struct spl_info *info = rkcommon_get_spl_info(params->imagename);
-
- /*
- * info would not be NULL, because of we checked params before.
- */
- return info->spl_boot0;
-}
-
static void rkcommon_set_header0(void *buf, uint file_size,
struct image_tool_params *params)
{
* have the first 4 bytes reserved for the spl_name). Reserving
* these 4 bytes is done using the BOOT0_HOOK infrastructure.
*
- * Depending on this, the header is either 0x800 (if this is a
- * 'boot0'-style payload, which has reserved 4 bytes at the
- * beginning for the 'spl_name' and expects us to overwrite
- * its first 4 bytes) or 0x804 bytes in length.
+ * The header is always at 0x800 (as we now use a payload
+ * prepadded using the boot0 hook for all targets): the first
+ * 4 bytes of these images can safely be overwritten using the
+ * boot magic.
*/
- if (rkcommon_spl_is_boot0(params))
- tparams->header_size = RK_SPL_HDR_START;
- else
- tparams->header_size = RK_SPL_HDR_START + 4;
+ tparams->header_size = RK_SPL_HDR_START;
/* Allocate, clear and install the header */
tparams->hdr = malloc(tparams->header_size);
*
* The following Boot Header format/structures and values are defined in the
* following documents:
- * * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ * * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4)
*
* Expected Header Size = 0x9C0
* Forced as 'little' endian, 32-bit words
};
static struct zynqmp_header zynqmpimage_header;
+static void *dynamic_header;
+static FILE *fpmu;
static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
{
printf("Image Size : %lu bytes (%lu bytes packed)\n",
(unsigned long)le32_to_cpu(zynqhdr->image_size),
(unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+
+ if (zynqhdr->pfw_image_length)
+ printf("PMUFW Size : %lu bytes (%lu bytes packed)\n",
+ (unsigned long)le32_to_cpu(zynqhdr->pfw_image_length),
+ (unsigned long)le32_to_cpu(
+ zynqhdr->total_pfw_image_length));
+
printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
le32_to_cpu(zynqhdr->register_init[i].address),
le32_to_cpu(zynqhdr->register_init[i].data));
}
+
+ free(dynamic_header);
}
static int zynqmpimage_check_params(struct image_tool_params *params)
return EXIT_FAILURE;
}
+static uint32_t fsize(FILE *fp)
+{
+ int size, ret, origin;
+
+ origin = ftell(fp);
+ if (origin < 0) {
+ fprintf(stderr, "Incorrect file size\n");
+ fclose(fp);
+ exit(2);
+ }
+
+ ret = fseek(fp, 0L, SEEK_END);
+ if (ret) {
+ fprintf(stderr, "Incorrect file SEEK_END\n");
+ fclose(fp);
+ exit(3);
+ }
+
+ size = ftell(fp);
+ if (size < 0) {
+ fprintf(stderr, "Incorrect file size\n");
+ fclose(fp);
+ exit(4);
+ }
+
+ /* going back */
+ ret = fseek(fp, origin, SEEK_SET);
+ if (ret) {
+ fprintf(stderr, "Incorrect file SEEK_SET to %d\n", origin);
+ fclose(fp);
+ exit(3);
+ }
+
+ return size;
+}
+
+static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr,
+ const char *filename)
+{
+ uint32_t size;
+
+ /* Setup PMU fw size */
+ zynqhdr->pfw_image_length = fsize(fpmu);
+ zynqhdr->total_pfw_image_length = zynqhdr->pfw_image_length;
+
+ zynqhdr->image_size -= zynqhdr->pfw_image_length;
+ zynqhdr->image_stored_size -= zynqhdr->total_pfw_image_length;
+
+ /* Read the whole PMUFW to the header */
+ size = fread(&zynqhdr->__reserved4[66], 1,
+ zynqhdr->pfw_image_length, fpmu);
+ if (size != zynqhdr->pfw_image_length) {
+ fprintf(stderr, "Cannot read PMUFW file: %s\n", filename);
+ fclose(fpmu);
+ exit(1);
+ }
+
+ fclose(fpmu);
+}
+
static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
const char *filename)
{
if (params->eflag)
zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+ /* PMUFW */
+ if (fpmu)
+ zynqmpimage_pmufw(zynqhdr, params->imagename);
+
/* User can pass in text file with init list */
if (strlen(params->imagename2))
zynqmpimage_parse_initparams(zynqhdr, params->imagename2);
zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
}
+static int zynqmpimage_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ struct stat path_stat;
+ char *filename = params->imagename;
+ int err;
+
+ /* Handle static case without PMUFW */
+ tparams->header_size = sizeof(struct zynqmp_header);
+ tparams->hdr = (void *)&zynqmpimage_header;
+
+ /* PMUFW name is passed via params->imagename */
+ if (strlen(filename) == 0)
+ return EXIT_SUCCESS;
+
+ fpmu = fopen(filename, "r");
+ if (!fpmu) {
+ fprintf(stderr, "Cannot open PMUFW file: %s\n", filename);
+ return EXIT_FAILURE;
+ }
+
+ err = fstat(fileno(fpmu), &path_stat);
+ if (err) {
+ fclose(fpmu);
+ fpmu = NULL;
+ return EXIT_FAILURE;
+ }
+
+ if (!S_ISREG(path_stat.st_mode)) {
+ fclose(fpmu);
+ fpmu = NULL;
+ return EXIT_FAILURE;
+ }
+
+ /* Increase header size by PMUFW file size */
+ tparams->header_size += fsize(fpmu);
+
+ /* Allocate buffer with space for PMUFW */
+ dynamic_header = calloc(1, tparams->header_size);
+ tparams->hdr = dynamic_header;
+
+ return EXIT_SUCCESS;
+}
+
U_BOOT_IMAGE_TYPE(
zynqmpimage,
"Xilinx ZynqMP Boot Image support",
NULL,
zynqmpimage_check_image_types,
NULL,
- NULL
+ zynqmpimage_vrec_header
);
projects / people / ms / u-boot.git / commitdiff
